CN116895641A

CN116895641A - Semiconductor device module and signal distribution assembly

Info

Publication number: CN116895641A
Application number: CN202310354495.7A
Authority: CN
Inventors: 刘勇; 杨清
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2022-04-06
Filing date: 2023-04-03
Publication date: 2023-10-17
Also published as: EP4258346A1; US20230326876A1

Abstract

In some aspects, the technology described herein relates to a semiconductor device module and a signal distribution assembly configured to conduct signals in the semiconductor device module, the signal distribution assembly comprising: a metal layer having: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and comprising: a base portion; a first post extending from the base portion; and a second post extending from the base portion. The metal layer may be pre-molded using a molding compound disposed on the second side of the metal layer, wherein respective surfaces of the first and second pillars are exposed through the molding compound, and/or the metal layer is capable of coupling with a thermally conductive insulator (e.g., ceramic) layer.

Description

Semiconductor device module and signal distribution assembly

Technical Field

The present specification relates to semiconductor device modules (semiconductor device assemblies, semiconductor device module assemblies, etc.). More particularly, the present description relates to semiconductor device modules having improved thermal performance and reduced mechanical stress.

Background

Semiconductor device assemblies such as assemblies including power semiconductor devices such as power transistors (e.g., insulated Gate Bipolar Transistors (IGBTs), power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), etc.) may be implemented using multiple semiconductor die, one or more substrates (e.g., directly bonded metal substrates), and electrical interconnects such as bond wires, conductive spacers, and conductive clips, as well as molding compounds (e.g., epoxy molding compounds) that act as sealants to protect other components of the associated device assemblies.

For example, such power transistor devices may be used to implement an electrical inverter for use in an Electric Vehicle (EV) and/or a hybrid-electric vehicle (HEV). However, current implementations of semiconductor device assemblies including such power transistors (e.g., in combination with Fast Recovery Diodes (FRDs)) have certain drawbacks. For example, current implementations may only allow cooling of the component on a single side of the component (e.g., by attaching a heat sink). This can lead to and/or exacerbate stresses between components within such assemblies, such as tensile stress and strain energy on the included semiconductor die, which can damage (e.g., crack) those semiconductor die. As the power requirements and associated operating temperatures of such devices increase, the event of such damage will also increase.

Disclosure of Invention

In some aspects, the technology described herein relates to a semiconductor device module comprising: a substrate, a first semiconductor die, a second semiconductor die, and a signal distribution assembly. The substrate comprises: a first ceramic layer and a first metal layer disposed on a first surface of the substrate. The first side of the first semiconductor die is coupled to the first metal layer. The first side of the second semiconductor die is coupled to the first metal layer. The signal distribution assembly includes a second metal layer having: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and comprising: a base portion, a first column and a second column. The first pillar extends from the base portion, the first pillar being coupled with a second side of the first semiconductor die, the second side being opposite the first side of the first semiconductor die. The second post extends from the base portion, the second post is coupled with a second side of the second semiconductor die, the second side is opposite the first side of the second semiconductor die, and the signal distribution assembly electrically couples the first semiconductor die with the second semiconductor die.

In some aspects, the technology described herein relates to a semiconductor device module further comprising a second ceramic layer coupled with the first side of the second metal layer.

In some aspects, the techniques described herein relate to a semiconductor device module in which the second ceramic layer is a thermally conductive ceramic layer coupled with the first side of the second metal layer via a thermally conductive epoxy adhesive.

In some aspects, the technology described herein relates to a semiconductor device module, wherein: the signal distribution assembly is pre-molded and includes a molding compound disposed on the second side of the second metal layer; a surface of the first pillar coupled to the first semiconductor die is exposed through the molding compound; and a surface of the second pillar coupled to the second semiconductor die is exposed through the molding compound.

In some aspects, the technology described herein relates to a semiconductor device module, further comprising: an insulator layer, a first surface of the insulator layer coupled to the first side of the second metal layer; and a third metal layer coupled to a second surface of the insulator layer, the second surface being opposite the first surface of the insulator layer.

In some aspects, the technology described herein relates to a semiconductor device module wherein the insulator layer is electrically insulating and thermally conductive.

In some aspects, the technology described herein relates to a semiconductor device module, wherein: the second metal layer has an overall thickness of less than 1 millimeter (mm); and the first cylinder and the second cylinder have the same height of less than 0.5 mm.

In some aspects, the technology described herein relates to a semiconductor device module wherein the same height is less than 0.2mm.

In some aspects, the technology described herein relates to a semiconductor device module, wherein: the base portion is a first base portion; the first base portion, the first pillar, and the second pillar are included in a first portion of the second metal layer; and the second metal layer further includes a second portion having: a second base portion; and a third pillar extending from the second base portion, the third pillar coupled with the second side of the first semiconductor die.

In some aspects, the technology described herein relates to a semiconductor device module, wherein: the first semiconductor die is one of an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Silicon Field Effect Transistor (MOSFET); the second semiconductor die is a Fast Recovery Diode (FRD); and the first pillar is coupled with one of an emitter terminal of the IGBT or a source terminal of the MOSFET; the second column is coupled to the cathode of the FRD; and the third pillar is coupled to the gate terminal of the IGBT or to the gate terminal of the MOSFET.

In some aspects, the techniques described herein relate to a semiconductor device module in which the first portion of the second metal layer further includes a fourth post extending from the first base portion, the fourth post coupled with a signal terminal of a leadframe of the semiconductor device module, the signal terminal being an emitter signal terminal or a source signal terminal.

In some aspects, the techniques described herein relate to a semiconductor device module in which the first portion of the second metal layer includes a fourth pillar extending from the first base portion, the fourth pillar coupled with a thermal sense signal pin of a leadframe of the semiconductor device module.

In some aspects, the techniques described herein relate to a semiconductor device module in which the second portion of the second metal layer includes a fourth pillar extending from the second base portion, the fourth pillar coupled with a gate signal pin of a leadframe of the semiconductor device module.

In some aspects, the technology described herein relates to a semiconductor device module, wherein: the signal distribution assembly is pre-molded and includes a molding compound disposed on the second side of the second metal layer; a surface of the first pillar coupled to the first semiconductor die is exposed through the molding compound; a surface of the second pillar coupled to the second semiconductor die is exposed through the molding compound; and a surface of the third pillar coupled with the gate terminal of the IGBT or the gate terminal of the MOSFET is exposed through the molding compound.

In some aspects, the technology described herein relates to a semiconductor device module, wherein: the first base portion of the second metal layer is coupled with a signal terminal of a leadframe of the semiconductor device module, the signal terminal being an emitter signal terminal or a source signal terminal; the first base portion of the second metal layer is further coupled with a thermal sense signal pin of the leadframe; and the second base portion of the second metal layer is coupled with a gate signal pin of the leadframe.

In some aspects, the technology described herein relates to a signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly comprising: metal layer, molding compound and heat conductive ceramic layer. The metal layer has: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and comprising: a base portion, a first column and a second column. The first post extends from the base portion and the second post extends from the base portion. The molding compound is disposed on the second side of the metal layer, and an upper surface of the first pillar and an upper surface of the second pillar are exposed through the molding compound. The thermally conductive ceramic layer is coupled to the first side of the metal layer, the thermally conductive ceramic layer being coupled to the first side of the metal layer via a thermally conductive epoxy adhesive.

In some aspects, the technology described herein relates to a signal distribution assembly, wherein: the base portion is a first base portion; the first base portion, the first post, and the second post are included in a first portion of the metal layer; and the metal layer further includes a second portion having: a second base portion; and a third cylinder extending from the second base portion, an upper surface of the third cylinder being exposed through the molding compound.

In some aspects, the technology described herein relates to a signal distribution assembly, wherein: the first portion of the metal layer further comprises: a fourth cylinder extending from the first base portion, an upper surface of the fourth cylinder being exposed through the molding compound; and a fifth cylinder extending from the first base portion, an upper surface of the fourth cylinder being exposed through the molding compound; and the second portion of the metal layer further includes a sixth pillar extending from the second base portion, an upper surface of the sixth pillar exposed through the molding compound.

In some aspects, the technology described herein relates to a signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly comprising: a first metal layer, a thermally conductive insulator layer, and a second metal layer. The first metal layer has: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and comprising: a base portion, a first column and a second column. The first post extends from the base portion and the second post extends from the base portion. The first surface of the thermally conductive insulator layer is coupled with the first side of the first metal layer. The second metal layer is coupled to a second surface of the thermally conductive insulator layer, the second surface being opposite the first surface of the thermally conductive insulator layer.

In some aspects, the technology described herein relates to a signal distribution assembly, wherein: the base portion is a first base portion; the first base portion, the first pillar, and the second pillar are included in a first portion of the first metal layer; and the first metal layer further includes a second portion having: a second base portion; and a third post extending from the second base portion.

Drawings

Fig. 1A is a schematic diagram schematically illustrating a side view of a signal distribution assembly.

Fig. 1B is a schematic diagram illustrating a plan view (e.g., bottom side plan view) of a signal distribution portion of the assembly of fig. 1A.

Fig. 1C is a schematic diagram illustrating a side view of the signal distribution portion of fig. 1B.

Fig. 1D is a schematic diagram illustrating the signal distribution portion of fig. 1B after pre-molding.

Fig. 1E is a schematic diagram showing a plan view (e.g., bottom side plan view) of another signal distribution portion of a signal distribution assembly.

Fig. 1F is a schematic diagram showing the signal distribution portion of fig. 1B after pre-molding.

Fig. 2A is a schematic diagram illustrating a side view of another signal distribution assembly.

Fig. 2B is a schematic diagram illustrating a plan view (e.g., bottom side plan view) of the signal distribution assembly of fig. 2A.

Fig. 2C is a schematic diagram illustrating a plan view (e.g., bottom side plan view) of another signal distribution assembly.

Fig. 3 is a schematic diagram illustrating a portion of a method for producing a semiconductor device module including the pre-molded signal distribution assembly of fig. 1D.

Fig. 4 is a schematic diagram illustrating a portion of a method for producing a semiconductor device module including the pre-molded signal distribution assembly of fig. 1F.

Fig. 5A is a side view of a semiconductor device module including a signal distribution assembly (such as the assembly of fig. 1A).

Fig. 5B is an enlarged view of a portion of the semiconductor device module of fig. 5A.

Fig. 6A is a side view of a semiconductor device module including a signal distribution assembly (such as the assembly of fig. 2A).

Fig. 6B is an enlarged view of a portion of the semiconductor device module of fig. 6A.

Fig. 7 is a flow chart illustrating a method for producing a semiconductor device module including a signal distribution assembly (such as the assembly of fig. 1A or fig. 2A).

In the drawings, which are not necessarily drawn to scale, like reference numerals may indicate like and/or analogous components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example and not by way of limitation, various implementations discussed in the present disclosure. Reference characters shown in one drawing may not be repeated for identical and/or similar elements in the associated drawings. Repeated reference characters among the multiple figures may not be discussed specifically with respect to each of the figures, but rather provide context for use between related views. In addition, not all similar elements in the drawings are specifically referenced with a reference numeral when multiple instances of the element are illustrated.

Detailed Description

The present disclosure relates to implementations of semiconductor device assemblies including signal distribution assemblies (e.g., electrical interconnect appliances or structures) that may improve thermal performance and reduce mechanical stress in such assemblies (e.g., power transistor assemblies). For example, in some implementations, the power transistor assembly may include a pre-molded electrical interconnect structure or signal distribution assembly, wherein contact surfaces (of portions of the conductive pillars for contacting the semiconductor die and/or leadframe) are exposed through molding compound for pre-molding the structure. The pre-molded structure may then be coupled with the thermally conductive ceramic layer (e.g., using a thermally conductive adhesive such as epoxy). Such implementations may be referred to as Substrate Bonded Ceramic (SBC) components.

In some implementations, a signal distribution assembly having a metal-insulator-metal (MIM) stack structure, which may be referred to as a MIM assembly, may be used. In contrast to SBC assemblies, MIM assemblies may not include molding compound, e.g., may not be pre-molded. Such signal distribution structures (e.g., SBC structures and/or MIM structures) as shown in semiconductor device assemblies described herein may improve thermal performance (reduce thermal resistance) by allowing for double sided cooling, which increases (e.g., may approximately double increase) heat dissipation area compared to current device assemblies with single sided cooling. Implementations described herein may also achieve shorter thermal (and electrical) conduction paths (e.g., by partially eliminating the use of conductive spacers), which also improve thermal performance (e.g., reduce thermal resistance) and improve mechanical performance (e.g., reduce mechanical stress on the semiconductor die stress), as well as improve solder joint reliability due to the mechanical flexibility of the disclosed SBC and MIM structures. The methods described herein may reduce thermal resistance (e.g., junction-to-shell and/or junction-to-slot thermal resistance) by 19% to 36% as compared to current implementations of power transistor assemblies used in, for example, electric Vehicle (EV) and/or Hybrid Electric Vehicle (HEV) electrical inverter applications. Furthermore, the methods described herein may reduce die tensile stress by 10% to 13% compared to current methods, which may reduce the occurrence of die cracking, and may also improve die top pad reliability by 19% to 40%, for example, as a result of reducing die top strain density.

Fig. 1A is a schematic diagram schematically illustrating a side view of a signal distribution assembly 100. The example of fig. 1A may be referred to as an SBC structure, such as described above. As shown in fig. 1A, signal distribution assembly 100 includes a pre-molded signal distribution assembly 110, a ceramic layer 120, and an adhesive 130. The pre-molded signal distribution assembly 110 may include a metal layer 112 and a molding compound 114 for the pre-molded metal layer 112. The metal layer 112 shown in fig. 1A is for illustration (and context) purposes. In some implementations, the metal layer 112 may not be visible in the view shown in fig. 1A because it is obscured by the molding compound 114.

In this example, the molding compound 114 may provide mechanical stability to the metal layer 112 (which may be less than 1 millimeter thick) while still allowing sufficient mechanical flexibility to reduce the occurrence of stresses within the associated semiconductor device assembly including the signal distribution assembly 100. As some examples, ceramic layer 120 may be a thermally conductive and electrically insulating layer, such as alumina (Al ₂ O ₃ ) Aluminum nitride (AlN), silicon nitride Si ₃ N ₄ Or resins such as polyimide. Adhesive agent130 may be used to couple the ceramic layer 120 to the pre-molded signal distribution assembly 110. In some examples, as one example, the adhesive 130 may be a thermally and electrically conductive epoxy, such as a silver filled epoxy. In other implementations, the adhesive 130 may be a thermally conductive but electrically insulating adhesive material, such as a thermal interface material.

Fig. 1B is a schematic diagram illustrating a plan view (e.g., bottom side plan view) of a signal distribution portion (e.g., metal layer 112) of the assembly 100 of fig. 1A. As shown in fig. 1B, in this example, metal layer 112 includes a base portion 140, pillars 142, pillars 144, pillars 146, and pillars 148, wherein each of pillars 142-148 extends away from base portion 140 (e.g., out of the page), such as further illustrated at least in fig. 1C.

As can be seen from a comparison of fig. 1A and 1B, the portion of the metal layer 112 shown in fig. 1A (e.g., the portion exposed via the molding compound 114) corresponds to the pillars 148. In some implementations, the metal layer 112 may be formed from a metal sheet, where etching or other processes may be performed on the metal sheet to form the base portion 140 and the pillars 142-148. In some implementations, the metal layer 112 may be formed using one or more deposition processes and/or sputtering processes. In some implementations, the metal layer 112 may be formed of copper, aluminum-copper, copper-molybdenum, and/or one or more other conductive materials. In this example, the metal layer 112 is monolithic. In other words, base portion 140 and posts 142-148 are included in a unitary structure, which may eliminate the use of conductive spacers and thus reduce reliability problems associated with such spacers.

Fig. 1C is a schematic diagram illustrating a side view of the metal layer 112 of fig. 1B. In this example, the metal layer 112 is viewed along the direction V1 shown in fig. 1B. In the view shown in fig. 1C, post 144, post 146, and post 148 are shown extending away from base portion 140. As also shown in fig. 1C, the metal layer 112 has a first side S1 and a second side S2. In this example, side S1 is planar, which facilitates coupling (e.g., using adhesive 130) pre-molded signal distribution assembly 110 with ceramic layer 120 to create signal distribution assembly 100. Further, in this example, side S2 is non-planar, with posts 142-148 extending away from base portion 140.

Fig. 1D is a schematic diagram illustrating a plan view of the metal layer 112 of fig. 1B after being pre-molded with a molding compound 114 and attaching a ceramic layer 120 to form the pre-molded signal distribution assembly 100 of fig. 1A. In an exemplary implementation, the metal layer 112 may be placed (and/or formed) in a molding jig, and then a transfer molding process (or other molding encapsulation process) may be performed to apply the molding compound 114 to the side S2 of the metal layer 112. As shown in FIG. 1D, after this molding process, the corresponding upper surfaces of pillars 142-148 are exposed through molding compound 114, for example, using a film-assisted molding technique. In some implementations, these upper surfaces may be exposed by controlling the volume of molding compound 114 applied to the side S2 of the metal layer 112 such that the upper surfaces of the pillars are not encapsulated in the molding compound 114. In other implementations, a grinding process may be performed to expose the upper surfaces of the pillars 142-148 via the molding compound 114 after the molding process.

In an exemplary implementation, the signal distribution assembly 100 may be included in a power transistor device assembly including a power transistor such as an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Fast Recovery Diode (FRD). Depending on the particular implementation, the power transistors and/or FRDs may be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any suitable semiconductor material. In some implementations, the exposed surfaces of pillars 142 and 144 can be coupled with a power transistor (e.g., with a collector terminal of an IGBT or a source terminal of a MOSFET). In addition, the exposed surface of pillars 146 may be coupled with the cathode terminal of the FRD such that metal layer 112 electrically couples the power transistor (emitter or source) with the FRD (cathode). Still further, posts 148 may be coupled with signal pads (signal terminals, signal leads, etc.) of a leadframe included in a corresponding power transistor assembly. An example of this is shown in fig. 3.

In some implementations, the arrangement of posts on the base portion 140, as well as the shape and size of the base portion 140, may vary. As an example, in some implementations, a single column (e.g., a larger column) may replace columns 142 and 144.

Fig. 1E is a schematic diagram of a plan view (e.g., bottom side plan view) showing another signal distribution portion (e.g., metal layer 112 a) of the SBC structure. As shown in fig. 1E, similar to metal layer 112 of fig. 1A-1D, metal layer 112a includes (e.g., monolithically) base portion 150, pillars 152, pillars 154, pillars 156, pillars 158, and pillars 159, wherein each of pillars 152-159 extends away from base portion 150 (e.g., out of the page), similar to pillars 142-148 of metal layer 112. The metal layer 112a also includes a base portion 160, pillars 162, and pillars 164 that are physically and electrically separate from the base portion 150 and pillars 152-159, and may also be monolithic. That is, as shown in FIG. 1E, base portion 150 and pillars 152-159 are included in a first portion of metal layer 112a, while base portion 160 and pillars 162-164 are included in a second portion of metal layer 112 a.

Fig. 1F is a schematic diagram illustrating the metal layer 112a of fig. 1E after a ceramic layer, such as ceramic layer 120, is pre-molded and attached with molding compound 114a to form a signal distribution assembly 100 (e.g., SBC structure) similar to the signal distribution assembly 100 of fig. 1A. In an exemplary implementation, the metal layer 112a may be placed (and/or formed) in a molding jig, and then a transfer molding process (or other molding encapsulation process) may be performed to apply the molding compound 114a to the sides of the metal layer 112 including the pillars 152-159 and the pillars 162-164 (e.g., using film-assisted molding to cover the visible portions of the base portion 150 and the base portion 160, for example). As shown in FIG. 1F, after the molding process, the respective upper surfaces of pillars 152-159 and pillars 162-164 are exposed through molding compound 114 a. In some implementations, these upper surfaces may be exposed by controlling the volume of molding compound 114a applied such that the upper surfaces are not encapsulated in molding compound 114 a. In other implementations, a grinding process may be performed to expose the upper surfaces of pillars 152-159 and pillars 162-164 via molding compound 114a after the molding process.

In an exemplary implementation, the signal distribution assembly 100a may be included in a power transistor device assembly including a power transistor such as an IGBT or MOSFET and an FRD. Depending on the particular implementation, the power transistors and/or diodes may be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any suitable semiconductor material. In an exemplary implementation, the exposed surfaces of pillars 152 and 154 may be coupled with a power transistor (e.g., with the collector terminal of an IGBT or the source terminal of a MOSFET). Further, the pillars 156 may be coupled with a cathode terminal of the FRD, and the metal layer 112a may electrically couple the power transistor (emitter or source) with the FRD (cathode). Still further, posts 158 may be coupled with signal pads (signal terminals, signal leads, etc.) of a leadframe included in a corresponding power transistor assembly, and posts 159 may be coupled with thermally sensed signal pins of the leadframe. In addition, pillars 162 may be coupled with gate terminals of corresponding power transistor semiconductor die, and pillars 164 may be coupled with gate signal pins of a leadframe. An example of this is shown in fig. 4.

In some implementations, the arrangement of the respective posts on base portion 150 and base portion 160, as well as the respective shapes and sizes of base portion 150 and base portion 160, may vary. As an example, in some implementations, the base portion 160 may be a straight metal trace, and may include additional corners or bends to route gate signals from corresponding signal pins of an associated leadframe to gate pads on a semiconductor die including an associated power transistor, as appropriate for a particular implementation.

Fig. 2A is a schematic diagram schematically illustrating a side view of signal distribution assembly 200. The example of fig. 2A may be referred to as a MIM structure, such as described above. As shown in fig. 2A, signal distribution assembly 200 includes a metal layer 210, a metal layer 220, and an insulator layer 230. In some implementations, the metal layer 210 and the metal layer 220 may be coupled to respective sides of the insulator layer 230 using Active Metal Brazing (AMB), sintering, plating, and the like. In contrast to the pre-molded signal distribution assembly 110 and the metal layer 112, the metal layer 210 does not include pre-molding. In this example, structural support for 210 (and metal layer 220) is provided by insulator layer 230 while still allowing sufficient mechanical flexibility to reduce the phase comprising signal distribution assembly 200The occurrence of stresses within the associated semiconductor device assembly. As some examples, insulator layer 230 may be a thermally conductive and electrically insulating layer, such as tetraethyl orthosilicate (TEOS), may be a thermally conductive and electrically insulating layer, such as aluminum oxide (Al ₂ O ₃ ) Aluminum nitride (AlN), silicon nitride Si ₃ N ₄ Silicon dioxide (SiO) ₂ ) Resins such as polyimide or epoxy.

In this example, with further reference to fig. 2B, fig. 2A is a schematic diagram illustrating a side view of signal distribution assembly 200 viewed along direction V2 shown in fig. 2B. In the view shown in fig. 2A, the post 244 and post 246 are shown extending away from the base portion 240. As also shown in fig. 2A, the metal layer 210 has a first side S3 and a second side S3. In this example, side S3 is planar, which may facilitate coupling metal layer 210 with insulator layer 230. Further, in this example, side S4 of metal layer 210 is non-planar, with columns 242 and 248 extending away from base portion 240 (e.g., extending the paper in fig. 2B) (as shown in fig. 2B).

Fig. 2B is a schematic diagram illustrating a plan view (e.g., bottom side plan view) of the signal distribution assembly 200 of fig. 2A. As shown in fig. 2B, in this example, side S4 of metal layer 210 includes a base portion 240 and pillars 242-246, wherein each of pillars 242-246 extends away from base portion 240 (e.g., out of the page).

In some implementations, the metal layer 210 may be formed from a metal sheet, where etching or other processes may be performed on the metal sheet to form the base portion 240 and the pillars 242-246. In some implementations, the metal layer 210 may be formed using one or more deposition processes and/or sputtering processes. In some implementations, the metal layer 210 may be formed of copper, aluminum-copper, copper-molybdenum, and/or one or more other conductive materials. In this example, the metal layer 210 is monolithic. In other words, the base portion 240 and the posts 242-246 are included in a unitary structure, which may eliminate the use of conductive spacers and thus reduce reliability problems associated with such spacers.

In an exemplary implementation, the signal distribution assembly 200 may be included in a power transistor device assembly including a power transistor such as an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Fast Recovery Diode (FRD). Depending on the particular implementation, the power transistors and/or FRDs may be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any suitable semiconductor material. In some implementations, respective upper surfaces (e.g., the surfaces shown in fig. 2B) of pillars 242 and 244 can be coupled with a power transistor (e.g., with a collector terminal of an IGBT or a source terminal of a MOSFET). Further, an upper surface of the pillars 246 (e.g., the surface shown in fig. 2B) may be coupled with the cathode terminal of the FRD such that the metal layer 210 electrically couples the power transistor (emitter or source) with the FRD (cathode). Still further, the base portion 240 may be coupled with signal pads (signal terminals, signal leads, etc.) of a leadframe included in a corresponding power transistor assembly, for example, near the edge 248. This example is similar to the implementation of fig. 3.

In some implementations, the arrangement of posts on the base portion 240 and the shape and size of the base portion 240 may vary. As an example, in some implementations, a single column (e.g., a larger column) may replace columns 242 and 244, and/or the size and shape of base layer 240 may vary.

Fig. 2C is a schematic diagram illustrating a plan view (e.g., bottom side plan view) of another signal distribution assembly 200 a. As shown in fig. 2C, metal layer 210a (which is similar to and may be implemented in place of metal layer 210 of fig. 2A and 2B) includes a base portion 250, pillars 252, pillars 254, and pillars 256, wherein each of the pillars 252-256 extends away from base portion 250 (e.g., out of the page). Metal layer 210a also includes a base portion 260 and pillars 262 that are physically and electrically separated from base portion 250 and pillars 252-256. That is, as shown in FIG. 2C, base portion 250 and pillars 252-256 are included in a first portion of metal layer 210, while base portion 260 and pillars 262 are included in a second portion of metal layer 210 a.

In an exemplary implementation, the signal distribution assembly 200a may be included in a power transistor device assembly including a power transistor such as an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Fast Recovery Diode (FRD). Depending on the particular implementation, the power transistors and/or FRDs may be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any suitable semiconductor material. In some implementations, respective upper surfaces (e.g., the surfaces shown in fig. 2C) of pillars 252 and 254 can be coupled with a power transistor (e.g., with the collector terminal of an IGBT or the source terminal of a MOSFET). Further, an upper surface of the pillars 256 (e.g., the surface shown in fig. 2C) may be coupled with the cathode terminal of the FRD such that the metal layer 210a electrically couples the power transistor (emitter or source) with the FRD (cathode). Still further, the base portion 250 may be coupled with signal pads (signal terminals, signal leads, etc.) of a leadframe included in a corresponding power transistor assembly, for example, near edge 258, and may also be coupled with thermal sensing signal pins of the leadframe, for example, near edge 259. In addition, pillars 262 can be coupled with gate terminals of corresponding power transistor semiconductor die, and base portions 260 (e.g., near edges 264) can be coupled with gate signal pins of a leadframe. This example is similar to the implementation shown in fig. 4.

In some implementations, the arrangement of the respective posts on the base portion 250 and the base portion 260, as well as the respective shapes and sizes of the base portion 250 and the base portion 260, may vary. As an example, in some implementations, the base portion 260 may not be a straight metal trace, but may include corners or bends to route gate signals from corresponding signal pins of an associated leadframe to gate pads on a semiconductor die including an associated power transistor.

Fig. 3 is a flow chart illustrating a portion of a method for producing a semiconductor device module 300 that includes the signal distribution assembly 100 of fig. 1D. A similar flow may be used to produce a semiconductor device module using signal distribution assembly 200 of fig. 2A and 2B in place of signal distribution assembly 100. For brevity, this flow (e.g., flow for signal distribution component 200) is not shown here.

In this example, referring first to the left-hand portion of fig. 3, the semiconductor device module 300 may include a substrate 310, which may be a DBM substrate. The substrate 310 may include a top metal layer 312, which may be a copper layer or other metal layer. As shown in fig. 3, semiconductor die 320 and semiconductor die 330 may be coupled with top metal layer 312 of substrate 310, for example, via a solder reflow process, a sintering process, or other suitable process. Blade signal terminals 374 (of the leadframe) may also be coupled with top metal layer 312 using the same process operations (soldering, sintering, etc.) used to attach semiconductor die 320 and semiconductor die 330 to top metal layer 312.

In this example, semiconductor die 320 may include a power transistor, such as an IGBT or MOSFET, and semiconductor die 330 may include an FRD. In this example, top metal layer 312 of substrate 310 and blade signal terminal 374 are electrically coupled with either the collector terminal (for the IGBT included in semiconductor die 320) or the drain terminal (for the MOSFET included in semiconductor die 320) and the anode for the FRD included in semiconductor die 330. That is, the top metal layer 312 electrically couples both the power transistor (collector or drain) and the FRD (anode) with the blade signal terminal 374.

As further shown in fig. 3, a solder printing or dispensing operation may be performed to form solder portions 342, 344, and 346, which correspond to posts 142-146, respectively, of signal distribution assembly 100. That is, the signal distribution assembly 100 may be flipped over and placed over the solder sections 342-346 such that the posts 142-146 are aligned with their respective solder sections. In addition, posts 148 of signal distribution assembly 100 may be aligned with corresponding solder portions (not shown in fig. 3) disposed on blade terminals 348 (of the lead frame). A solder reflow process may then be performed to couple signal distribution assembly 100 to semiconductor die 320, semiconductor die 330, and blade terminals 348 (via the respective pillars of signal distribution assembly 100).

As also shown in fig. 3, the leadframe of semiconductor device module 300 may further include a signal pin 370 (e.g., a gate signal pin) and a signal pin 372 (e.g., a thermal sense signal pin), which may be coupled with semiconductor die 320 via wire bond 370a and wire bond 372a, respectively.

Fig. 4 is a flow chart illustrating a portion of a method for producing a semiconductor device module 400 that includes the signal distribution assembly 100a of fig. 1F. A similar flow may be used to produce a semiconductor device module using signal distribution assembly 200a of fig. 2C in place of signal distribution assembly 100 a. For brevity, this flow (e.g., flow for signal distribution component 200 a) is not shown here.

In this example, referring first to the left portion of fig. 4, the semiconductor device module 400 may include a substrate 410, which may be a DBM substrate. The substrate 410 may include a top metal layer 412, which may be a copper layer or other metal layer. As shown in fig. 4, semiconductor die 420 and semiconductor die 430 may be coupled with top metal layer 412 of substrate 410, for example, via a solder reflow process, a sintering process, or other suitable process. Blade signal terminals 474 (of the leadframe) may also be coupled with top metal layer 412 using the same process operations (soldering, sintering, etc.) used to attach semiconductor die 420 and semiconductor die 430 to top metal layer 412.

In this example, semiconductor die 420 may include a power transistor, such as an IGBT or MOSFET, and semiconductor die 430 may include an FRD. In this example, top metal layer 412 of substrate 410 and blade signal terminal 474 are electrically coupled with either a collector terminal (for the IGBT included in semiconductor die 420) or a drain terminal (for the MOSFET included in semiconductor die 420) and an anode for the FRD included in semiconductor die 430. That is, top metal layer 412 electrically couples both the power transistor (collector or drain) and the FRD (anode) to blade signal terminal 474.

As further shown in fig. 4, a solder printing or dispensing operation may be performed to form solder portion 452, solder portion 454, solder portion 456, and solder portion 462, which correspond to posts 152, 154, 156, and 162, respectively, of signal distribution assembly 100 a. That is, the signal distribution assembly 100a may be flipped over and placed over the solder sections 452, 454, 456, and 462 such that the posts 152, 154, 156, and 162 are aligned with their respective solder sections. Further, posts 158 of signal distribution assembly 100a may be aligned with corresponding solder portions (not shown in fig. 4) disposed on blade terminals 448. Still further, posts 159 and 164 of signal distribution assembly 100a may be aligned with corresponding solder portions (not shown in fig. 4) disposed on signal pins 472 (e.g., thermal sense signal pins) and signal pins 472 (e.g., gate signal pins) of the lead frame. A solder reflow process may then be performed to couple the signal distribution assembly 100a to the semiconductor die 420, the semiconductor die 430, the paddle terminals 448, the signal pins 472, and the signal pins 470 (via the respective pillars of the signal distribution assembly 100 a). In this implementation, wire bonds 370a and 372a are replaced with signal routing implemented in signal distribution assembly 100a, as compared to the implementation of fig. 3.

Fig. 5A is a side view (e.g., cross-sectional view) of a semiconductor device module 500 that includes a signal distribution assembly (SBC structure), such as signal distribution assembly 100 of fig. 1A and 1D. That is, for purposes of illustration, the semiconductor device module 500 is described as including the signal distribution assembly 100, although other signal distribution assembly implementations may be included. In this example, semiconductor device module 500 includes substrate 510 (e.g., a DBM substrate), signal distribution assembly 100, semiconductor die 520 (e.g., including a power transistor), and semiconductor die 530 (e.g., including a FRD). Dashed line 500a in fig. 5A defines illustration 500a, an enlarged view of which is shown in fig. 5B. That is, the illustration 500a includes an arrangement of elements for the semiconductor device module 500 corresponding to the semiconductor die 530 (where the stack associated with the semiconductor die 520 would be the same or similar).

Referring to fig. 5B, an enlarged view of the insert 500a shown in fig. 5A is shown, the substrate 510 including a metal layer 512 (e.g., a top metal layer), a ceramic layer 514, and a metal layer 516 (e.g., a bottom metal layer), which may be used for bottom side cooling of the semiconductor device module 500. As also shown in fig. 5B, and as described above, the signal distribution assembly 100 includes a metal layer 112, a molding compound 114, a ceramic layer 120 (which may be used for top side cooling of the semiconductor device module 500), and an adhesive 130. In the example of insert 500a, the base portion 140 and pillars 146 of the metal layer 112 are shown. As shown in fig. 5B, semiconductor die 530 is coupled with metal layer 512 of substrate 510 using layer 532, which may be a solder layer or a sintered layer. As further shown in fig. 5B, the pillars 146 are coupled with the semiconductor die 530 using a layer 534, which may be a solder layer or a sintered layer.

In a particular non-limiting example, the elements of the semiconductor device module 500 shown in fig. 5B may have a thickness along line T1, as specified below. Of course, in other implementations, other thicknesses may be used and the following discussion is provided by way of example and for purposes of illustration. For clarity, an exemplary thickness (along line T1) of each of the elements shown in fig. 5B is generally listed from the top of semiconductor device module 500 to the bottom of semiconductor device module 500.

In this example, for signal distribution assembly 100, ceramic layer 120 may have a thickness of about 0.32mm, adhesive 130 may have a thickness of about 0.05mm, and metal layer 112 may have an overall thickness of about 0.70mm (e.g., less than 1 mm). For metal layer 112, base portion 140 may have a thickness of about 0.35mm and pillars 146 may have a thickness (height from base portion 140) of about 0.35mm, e.g., both less than 0.5mm. It should be noted that other pillars of metal layer 112 may have the same height. Further, in this example, the molding compound 114 of the signal distribution assembly 100 may have a thickness of about 0.35mm (or a thickness that is about the same as the height of the post 146, or a thickness that is slightly less than the height of the post) such that the post 146 is exposed through 114.

Still further, in this example, layer 534 can have a thickness of about 0.05mm, semiconductor die 530 can have a thickness of about 0.087mm, and layer 532 can have a thickness of about 0.05 mm. For the substrate 510 in this example, the metal layer 512 may have a thickness of about 0.8mm, the ceramic layer 514 may have a thickness of about 0.32mm, and the metal layer 516 may have a thickness of about 0.2 mm.

Fig. 6A is a side view (e.g., cross-sectional view) of a semiconductor device module 600 including a signal distribution assembly (MIM structure), such as signal distribution assembly 200 of fig. 2A and 2B. That is, for purposes of illustration, the semiconductor device module 600 is described as including the signal distribution assembly 200, although other signal distribution assembly implementations may be included. In this example, semiconductor device module 600 includes substrate 610 (e.g., a DBM substrate), signal distribution assembly 200, semiconductor die 620 (e.g., including power transistors), and semiconductor die 630 (e.g., including FRDs). Dashed line 600a in fig. 6A defines illustration 600a, an enlarged view of which is shown in fig. 6B. That is, the illustration 600a includes an arrangement of elements for the semiconductor device module 600 corresponding to the semiconductor die 620 (where the stack associated with the semiconductor die 620 would be the same or similar).

Referring to fig. 6B, an enlarged view of the insert 600a shown in fig. 6A is shown, the substrate 610 including a metal layer 612 (e.g., a top metal layer), a ceramic layer 614, and a metal layer 616 (e.g., a bottom metal layer), which may be used for bottom side cooling of the semiconductor device module 600. As also shown in fig. 6B, and as described above, signal distribution assembly 200 includes metal layer 210, insulator layer 230, and metal layer 220 (which may be used for top side cooling of semiconductor device module 600). In the example of illustration 600a, the base portion 240 and the pillars 242 of the metal layer 210 are shown. As shown in fig. 6B, semiconductor die 620 is coupled with metal layer 612 of substrate 610 using layer 622, which may be a solder layer or a sintered layer. As further shown in fig. 6B, the pillars 242 are coupled with the semiconductor die 620 using a layer 624, which may be a solder layer or a sintered layer.

In a particular non-limiting example, the elements of the semiconductor device module 600 shown in fig. 6B may have a thickness along line T2, as specified below. Of course, in other implementations, other thicknesses may be used and the following discussion is provided by way of example and for purposes of illustration. For clarity, an exemplary thickness (along line T2) of each of the elements shown in fig. 6B is generally listed from the top of semiconductor device module 600 to the bottom of semiconductor device module 600.

In this example, for signal distribution assembly 200, metal layer 220 may have a thickness of about 0.62mm, and insulator layer 230 may have a thickness of about 0.05 mm. Further, the metal layer 210 may have an overall thickness of about 0.80mm (e.g., less than 1 mm). For metal layer 210, base portion 240 may have a thickness of about 0.62mm and posts 242 may have a thickness (height from base portion 140) of about 0.18 mm. It should be noted that other pillars of metal layer 210 may have the same height.

Still further, in this example, layer 624 can have a thickness of about 0.05mm, semiconductor die 620 can have a thickness of about 0.087mm, and layer 622 can have a thickness of about 0.05 mm. For the substrate 610 in this example, the metal layer 612 may have a thickness of about 0.8mm, the ceramic layer 614 may have a thickness of about 0.32mm, and the metal layer 616 may have a thickness of about 0.4 mm.

Fig. 7 is a flow chart illustrating a method 700 for producing a semiconductor device module including a signal distribution assembly (such as the assembly of fig. 1A or 2A). In method 700, block 710 includes fabricating or providing a signal distribution component, such as an SBC structure or a MIM structure, such as those described herein with respect to fig. 1A-2C. At block 720, method 700 includes coupling a power transistor (e.g., a collector terminal of an IGBT or a drain terminal of a MOSFET), an FRD (e.g., an anode terminal), and one or more leadframe portions to a substrate, such as on a metal layer of a DBM substrate as in the examples of fig. 3 and 4. At block 730, if the signal distribution component does not include gates and/or thermal sensing signal routing and/or associated conductive posts, the method 700 includes forming respective wirebonds to provide electrical connection from respective signal terminals (signal pins, etc.) of the lead frame to the gate terminals and/or thermal sensing terminals (e.g., on a surface of the power transistor semiconductor die). At block 740, method 700 includes coupling the signal distribution component of block 710 to the semiconductor die and to one or more corresponding portions of the leadframe. In some implementations, the operations at block 720 may be accomplished with a first solder and the operations at block 740 may be accomplished with a second solder, where the second solder has a melting point lower than the melting point of the first solder, e.g., to prevent unwanted reflow of the solder used at block 720. In some implementations, the operations at blocks 720 and 740 may include sintering operations, such as silver sintering. At block 750, the method 700 includes packaging the resulting semiconductor device assembly in a molding compound, wherein a surface of the signal distribution structure is exposed through a first surface of the molding compound and a surface of the substrate of block 720 is exposed through a second surface of the molding compound.

It will be understood that in the foregoing description, when an element such as a layer, region or substrate is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on …, directly connected to …, or directly coupled to … may not be used throughout the detailed description, elements shown as directly on, directly connected to, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to describe exemplary relationships described in the specification or illustrated in the accompanying drawings.

As used in this specification, the singular forms may include the plural unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above …, above …, above …, below …, below …, below …, below …, at the top of …, at the bottom of …, etc.) are intended to encompass different orientations of the device in use or operation. In some implementations, relative terms above … and below … may include vertically above … and vertically below …, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. For example, features illustrated with respect to one embodiment may be included in other embodiments as appropriate. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the detailed description. It is understood that these modifications and variations are presented by way of example only, and not limitation, and that various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. Implementations described herein may include various combinations and/or sub-combinations of the functions, components, and/or features of different implementations described.

Claims

1. A semiconductor device module, comprising: a substrate, a first semiconductor die, a second semiconductor die and a signal distribution assembly,

the substrate includes a first ceramic layer and a first metal layer disposed on a first surface of the substrate;

A first side of the first semiconductor die is coupled to the first metal layer;

a first side of the second semiconductor die is coupled to the first metal layer; and

the signal distribution assembly includes a second metal layer having a first side and a second side;

the first side of the second metal layer is planar;

the second side of the second metal layer is opposite the first side of the second metal layer, the second side of the second metal layer being non-planar and comprising:

a base portion;

a first pillar extending from the base portion, the first pillar coupled with a second side of the first semiconductor die opposite the first side of the first semiconductor die; and

a second post extending from the base portion, the second post being coupled with a second side of the second semiconductor die opposite the first side of the second semiconductor die, the signal distribution assembly electrically coupling the first semiconductor die with the second semiconductor die.

2. The semiconductor device module of claim 1, further comprising:

an insulator layer, a first surface of the insulator layer coupled with the first side of the second metal layer via a thermally conductive epoxy adhesive; and

a third metal layer coupled to a second surface of the insulator layer, the second surface being opposite the first surface of the insulator layer,

the insulator layer is electrically insulating and thermally conductive.

3. The semiconductor device module of claim 1, wherein:

the second metal layer has an overall thickness of less than 1 millimeter; and is also provided with

The first and second columns have the same height of less than 0.5 millimeters.

4. The semiconductor device module of claim 1, wherein:

the base portion is a first base portion;

the first base portion, the first pillar, and the second pillar are included in a first portion of the second metal layer; and is also provided with

The second metal layer further includes a second portion having:

a second base portion; and

a third pillar extending from the second base portion, the third pillar coupled with the second side of the first semiconductor die.

5. The semiconductor device module of claim 4, wherein:

the first semiconductor die is one of an insulated gate bipolar transistor IGBT or a metal oxide silicon field effect transistor MOSFET;

the second semiconductor die is a fast recovery diode, FRD; and is also provided with

The first pillar is coupled with an emitter terminal of the IGBT or a source terminal of the MOSFET;

the second column is coupled to the cathode of the FRD; and is also provided with

The third pillar is coupled with a gate terminal of the IGBT or with a gate terminal of the MOSFET.

6. The semiconductor device module of claim 5, wherein:

the first portion of the second metal layer further includes a fourth pillar extending from the first base portion, the fourth pillar coupled with a signal terminal of a leadframe of the semiconductor device module, the signal terminal being an emitter signal terminal or a source signal terminal;

the first portion of the second metal layer includes a fifth pillar extending from the first base portion, the fifth pillar coupled with a thermal sense signal pin of a leadframe of the semiconductor device module; and is also provided with

The second portion of the second metal layer includes a sixth pillar extending from the second base portion, the sixth pillar coupled with a gate signal pin of a leadframe of the semiconductor device module.

7. The semiconductor device module of claim 5, wherein:

the first base portion of the second metal layer is coupled with a signal terminal of a leadframe of the semiconductor device module, the signal terminal being an emitter signal terminal or a source signal terminal;

the first base portion of the second metal layer is further coupled with a thermal sense signal pin of the leadframe; and is also provided with

The second base portion of the second metal layer is coupled with a gate signal pin of the leadframe.

8. The semiconductor device module of claim 4, wherein:

the signal distribution assembly is pre-molded and includes a molding compound disposed on the second side of the second metal layer;

a surface of the first pillar coupled to the first semiconductor die is exposed through the molding compound;

a surface of the second pillar coupled to the second semiconductor die is exposed through the molding compound; and is also provided with

A surface of the third pillar coupled to the first semiconductor die is exposed through the molding compound.

9. A signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly comprising: a metal layer, a molding compound and a heat-conducting ceramic layer,

the metal layer has a first side and a second side;

the first side of the metal layer is planar;

the second side of the metal layer is opposite the first side of the metal layer, the second side of the metal layer being non-planar and comprising: a base portion, a first post extending from the base portion, and a second post extending from the base portion;

the molding compound is disposed on the second side of the metal layer, and an upper surface of the first cylinder and an upper surface of the second cylinder are exposed through the molding compound;

the thermally conductive ceramic layer is coupled with the first side of the metal layer, the thermally conductive ceramic layer being coupled with the first side of the metal layer via a thermally conductive epoxy adhesive.

10. The signal distribution assembly of claim 9, wherein:

the base portion is a first base portion;

The first base portion, the first post, and the second post are included in a first portion of the metal layer; and is also provided with

The metal layer further includes a second portion having a second base portion and a third pillar,

the third cylinder extending from the second base portion, an upper surface of the third cylinder being exposed through the molding compound;

the first portion of the metal layer further includes fourth and fifth pillars,

the fourth cylinder extending from the first base portion, an upper surface of the fourth cylinder being exposed through the molding compound;

the fifth cylinder extending from the first base portion, an upper surface of the fourth cylinder being exposed through the molding compound; and is also provided with

The second portion of the metal layer further includes a sixth pillar extending from the second base portion, an upper surface of the sixth pillar exposed through the molding compound.

11. A signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly comprising: a first metal layer, a thermally conductive insulator layer and a second metal layer,

the first metal layer has a first side and a second side,

The first side of the first metal layer is planar;

the second side of the first metal layer is opposite the first side of the first metal layer, the second side of the first metal layer being non-planar and comprising: a base portion, a first post extending from the base portion, and a second post extending from the base portion;

a first surface of the thermally conductive insulator layer is coupled with a first side of the first metal layer;

the second metal layer is coupled to a second surface of the thermal conductive insulator layer opposite the first surface of the thermal conductive insulator layer.

12. The signal distribution assembly of claim 11, wherein:

the base portion is a first base portion;

the first base portion, the first pillar, and the second pillar are included in a first portion of the first metal layer; and is also provided with

The first metal layer also includes a second portion having a second base portion and a third pillar extending from the second base portion.