CN116895634A - Semiconductor chip architecture and method for manufacturing the same - Google Patents

Semiconductor chip architecture and method for manufacturing the same Download PDF

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Publication number
CN116895634A
CN116895634A CN202310369604.2A CN202310369604A CN116895634A CN 116895634 A CN116895634 A CN 116895634A CN 202310369604 A CN202310369604 A CN 202310369604A CN 116895634 A CN116895634 A CN 116895634A
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China
Prior art keywords
wafer
layer
semiconductor chip
pattern
gate
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CN202310369604.2A
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Chinese (zh)
Inventor
咸富铉
洪炳鹤
郑明勋
洪元赫
李昇映
徐康一
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from US17/887,203 external-priority patent/US20230326858A1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN116895634A publication Critical patent/CN116895634A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor chip architecture and a method of manufacturing the same are provided, the semiconductor chip architecture comprising: a wafer; a front end of line (FEOL) layer on the first side of the wafer, the FEOL layer comprising a semiconductor device on the first side of the wafer, shallow Trench Isolation (STI) structures in the wafer, and an interlayer dielectric (ILD) structure on the semiconductor device and the wafer; a process line middle of the line (MOL) layer provided on the FEOL layer, the MOL layer including a contact and a via connected to the contact; an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction; and a power rail penetrating the wafer from a second side of the wafer opposite the first side, wherein the via extends in a vertical direction through the ILD structure, the STI structure, and the wafer to contact the power rail.

Description

Semiconductor chip architecture and method for manufacturing the same
Technical Field
Example embodiments of the present disclosure relate to an inverted High Aspect Ratio Contact (HARC) structure included in a semiconductor chip architecture and a method of manufacturing the same.
Background
As the size of transistors included in semiconductor chip architectures has decreased, multi-stack semiconductor chips are being developed to vertically stack a plurality of transistors in a compact size within a limited area. To implement multi-stack semiconductor chip architectures, such as three-dimensional (3D) stacked semiconductor chip architectures or backside power rail semiconductor chip architectures, high Aspect Ratio Contact (HARC) structures are required. However, in HARC structure manufacturing processes, it may be difficult to align, for example, the HARC via and the contact structure. Misalignment caused between the HARC via and the contact structure may lead to reduced performance of the semiconductor chip architecture.
The information disclosed in this background section is already known to the inventors before implementing an embodiment of the application or is technical information obtained during the course of implementing an embodiment. It may therefore contain information that does not constitute prior art known to the public.
Disclosure of Invention
One or more example embodiments provide an inverted High Aspect Ratio Contact (HARC) structure included in a semiconductor chip architecture and a method of manufacturing the same.
According to an aspect of the example embodiments, there is provided a semiconductor chip architecture including: a wafer; a front end of line (FEOL) layer on the first side of the wafer, the FEOL layer comprising a semiconductor device on the first side of the wafer, shallow Trench Isolation (STI) structures in the wafer, and an interlayer dielectric (ILD) structure on the semiconductor device and the wafer; a process line middle of the line (MOL) layer provided on the FEOL layer, the MOL layer including contacts and vias connected to the contacts; an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction; a power rail penetrates the wafer from a second side of the wafer opposite the first side, wherein a via extends in a vertical direction through the ILD structure, the STI structure, and the wafer to contact the power rail.
According to another aspect of the example embodiments, there is provided a semiconductor chip architecture comprising: a wafer; a front end of line (FEOL) layer on the first side of the wafer, the FEOL layer including semiconductor devices on the first side of the wafer, shallow Trench Isolation (STI) structures in the wafer, and ILD structures on the semiconductor devices and the wafer; a process line middle of the line (MOL) layer provided on the FEOL layer, the MOL layer including a contact and a via connected to the contact; a gate polygonal cutting pattern on a first side of the wafer and adjacent to the via in a horizontal direction; a power rail penetrates the wafer from a second side of the wafer opposite the first side, wherein a via extends in a vertical direction through the ILD structure, the STI structure, and the wafer to contact the power rail.
According to another aspect of the example embodiments, there is provided a method of manufacturing a semiconductor chip architecture, the method comprising: forming a wafer including an oxide layer; forming a semiconductor device on a first side of a wafer; forming an ILD structure over the semiconductor device and the wafer; patterning the ILD structure based on a self-aligned contact (SAC) pattern comprising a first pattern and a second pattern; etching the ILD structure and the wafer to oxide layer level based on the first pattern to form a first trench, and etching the ILD structure to semiconductor device level based on the second pattern to form a second trench based on the SAC pattern; filling the first trench and the second trench with at least one metal material to form a via and a contact, respectively; and forming a power rail penetrating the wafer from a second side of the wafer opposite the first side such that the power rail contacts the via.
Drawings
The above and/or other aspects, features and advantages of example embodiments of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings in which:
fig. 1 shows a perspective view of a backside power distribution network (BSPDN) semiconductor chip architecture according to an example embodiment;
FIGS. 2A, 2B and 2C illustrate a method of fabricating a HARC via structure in a semiconductor chip architecture;
FIG. 3A shows a plan view of a semiconductor chip architecture;
FIG. 3B illustrates a plan view of a semiconductor chip architecture including the HARC via structure of FIG. 2B;
fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H illustrate a method of fabricating a BSPDN semiconductor chip architecture including HARC via structures according to an example embodiment;
fig. 5A, 5B, and 5C illustrate a method of fabricating HARC via structures in a semiconductor chip architecture according to another example embodiment;
fig. 6A, 6B, and 6C illustrate a method of fabricating HARC via structures in a semiconductor chip architecture according to another example embodiment;
fig. 7A shows a plan view of a self-aligned contact (SAC) pattern in the semiconductor chip architecture in fig. 4D;
FIG. 7B illustrates a plan view of a self-aligned contact (SAC) pattern in a semiconductor chip architecture including the HARC via structure of FIG. 5B;
FIG. 7C illustrates a plan view of a self-aligned contact (SAC) pattern in a semiconductor chip architecture including the HARC via structure of FIG. 6B;
FIG. 8 illustrates a flowchart of a method of manufacturing a BSPDN semiconductor chip architecture including a HARC via structure, according to an example embodiment;
FIG. 9 illustrates a flowchart of a method of forming a HARC via structure in a semiconductor chip architecture, according to another example embodiment;
FIG. 10 illustrates a flowchart of a method of forming a HARC via structure in a semiconductor chip architecture, according to yet another example embodiment;
FIG. 11 illustrates a semiconductor architecture that may include a semiconductor chip architecture according to an example embodiment; and
fig. 12 shows a schematic block diagram of an electronic system according to an example embodiment.
Detailed Description
The example embodiments described herein are examples, and thus, the present disclosure is not limited thereto, and may be implemented in various other forms. Each example embodiment provided in the following description does not preclude the association with one or more features of another example or another example embodiment also provided or not provided herein but consistent with the present disclosure. For example, even if what is described in a particular example or example embodiment is not described in a different example or example embodiment thereof, such what is understood to be related to or combined with the different example or embodiment unless mentioned otherwise in the description thereof.
Moreover, it should be understood that all descriptions of principles, aspects, examples, and example embodiments are intended to cover structural and functional equivalents thereof. Furthermore, it should be understood that such equivalents include not only currently known equivalents but also equivalents developed in the future, i.e., all means for performing the same function, regardless of structure.
It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as "an element") of a semiconductor device is referred to as being "above," "over," "under," "below," "beneath," "connected to" or "coupled to" another element of the semiconductor device, it can be directly above, over, under, beneath, directly connected to or coupled to the other element, or intervening elements may be present. In contrast, when an element of a semiconductor device is referred to as being "directly above," "directly over," "directly on," "directly under," "directly connected to," or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like numbers refer to like elements throughout the disclosure.
For ease of description, spatially relative terms such as "above … …," "above … …," "above … …," "below … …," "below … …," "below … …," "lower," "top" and "bottom" may be used herein to describe one element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the drawings is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "under … …" may include both above and below orientations. The semiconductor device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, a phrase such as "at least one of … …" when following a column of elements, modifies the entire column of elements rather than modifying individual elements in the list. For example, the expression "at least one of a, b and c" should be understood to include a only a, b only, c only, both a and b, both a and c, both b and c, or all of a, b and c. Here, when the term "same" is used to compare the dimensions of two or more elements, the term may cover "substantially the same" dimensions.
It will be understood that, although the terms "first," "second," "third," "fourth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.
It will also be understood that, even if a particular step or operation of manufacturing an apparatus or structure is described as being performed later than another step or operation, that step or operation may be performed earlier than another step or operation unless the other step or operation is described as being performed before the step or operation.
The example embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of example embodiments (and intermediate structures). Thus, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted regions. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure. Moreover, in the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
For brevity, general elements of a semiconductor device may or may not be described in detail herein.
Embodiments will be described in detail below with reference to the accompanying drawings. The embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto.
Fig. 1 shows a perspective view of a backside power distribution network (BSPDN) semiconductor chip architecture according to an example embodiment.
As shown in fig. 1, the BSPDN semiconductor chip architecture 1 may include a wafer 100, a signal routing layer 200a provided on a first side (front side) of the wafer 100, and a Power Distribution Network (PDN) layer 200b provided on a second side (back side) of the wafer 100 opposite the first side.
The wafer 100 may include, for example, a silicon (Si) substrate, a glass substrate, a sapphire substrate, etc., without being limited thereto. As shown in fig. 1, the wafer 100 may be a circular panel, but the shape of the wafer 100 is not limited thereto. For example, the wafer 100 may be a quadrilateral panel. Wafer 100 may include a single layer or multiple layers.
The BSPDN semiconductor chip architecture 1 according to the present embodiment can reduce wiring congestion and reduce the size of BSPDN semiconductor chips by removing PDN from the first side of the wafer 100. Thus, a more simplified PDN layer 200b may be provided on the second side of the wafer 100.
It should be appreciated that, although the signal routing layer 200a and the PDN layer 200b are respectively separated by the wafer 100 to have a space therebetween in fig. 1, at least one of the two layers may be bonded to the wafer 100 or otherwise integrated with the wafer 100, or one or more intervening layers may be provided therebetween, according to an embodiment.
Fig. 2A and 2B illustrate a method of fabricating a High Aspect Ratio Contact (HARC) via structure in a semiconductor chip architecture.
Referring to fig. 2A, the method may include providing a device substrate (wafer) 1100. The device substrate 1100 may be formed of a semiconductor material, such as silicon (Si), or may be part of a silicon-on-insulator (SOI) substrate, without being limited thereto. The device substrate 1100 may include an oxide layer 1110 including an oxide material.
Shallow Trench Isolation (STI) structures 1120 may be formed in the device substrate 1100. The STI structures 1120 may extend horizontally in the D2 direction and be spaced apart from each other horizontally in the D1 direction, and may include silicon oxide (SiO) or silicon nitride (SiN), without being limited thereto. The semiconductor device 1130 may be formed on a first side of the device substrate 1100 and may be isolated from each other in the D1 direction by the STI structure 1120. The semiconductor device 1130 may include a transistor. Each transistor may include an epitaxial layer (which may be a source/drain region), a fin forming a channel structure, and a gate structure, but is not limited thereto. The transistors described below may be one or more finfets, nanowire transistors, nanoplatelet transistors, or the like.
An interlayer dielectric (ILD) structure 1140 may be formed over the STI structure 1120 and the semiconductor device 1130. ILD structure 1140 may be formed on the exposed surfaces of STI structure 1120 and the exposed surfaces of semiconductor device 1130. In addition, a nitride spacer layer 1111 may be formed between the semiconductor device 1130 and the ILD structure 1140 and between the STI structure 1120 and the device substrate 1100.
As shown in fig. 2A, the first trenches may be formed in the vertical direction (negative D3 direction) by etching ILD structure 1140, nitride spacer layer 1111, STI structure 1120, and device substrate 1100 to the level of oxide layer 1110. The first trench may be filled with a metallic material such as, for example, tungsten (W) or cobalt (Co) to form HARC via 1116.HARC via 1116 may be formed adjacent to semiconductor device 1130 and extends vertically from the level of the upper surface of nitride spacer layer 1111 or the first side (upper surface) of semiconductor device 1130 to the level of oxide layer 1110, e.g., the upper surface of oxide layer 1110.
Referring to fig. 2B, one or more second trenches may be formed by etching one or more nitride spacer layers 1111 and HARC vias 1116 to a level of an upper surface of the semiconductor device 1130. The second trench may be filled with a metal material such as, for example, tungsten (W) or cobalt (Co) to form an active-on-gate contact 1115.
The active-gate upper contact 1115 may directly contact the upper surface of one or more semiconductor devices 1130 and the upper surface of HARC via 1116. The active-on-gate contact 1115 and HARC via 1116 may be structures included in a process line Middle (MOL) layer of a semiconductor chip architecture, but are not limited thereto.
Further, as shown in fig. 2C, a back end of line (BEOL) layer including a power rail for distributing power may be provided on the second side of the device substrate 1100.
For example, referring to fig. 2C, the system of fig. 2B is flipped over and a carrier wafer 1100' may be provided. The carrier wafer 1100' may comprise silicon. A first BEOL layer 1190 may be formed on the carrier wafer 1100'. BEOL contact structures 1170 may be formed on the first BEOL layer 1190 and ILD structures 1180 may be formed adjacent to the BEOL contact structures 1170 and between the first BEOL layer 1190 and the ILD structures 1140.
The semiconductor chip architecture shown in fig. 2B may be flipped over and attached to ILD structure 1180 such that active-on-gate contact 1115 contacts ILD structure 1180 and BEOL contact structure 1170.
The device substrate 1100 may be etched to the nitride spacer layer 1111 to expose the STI structures 1120, HARC vias 1116 and semiconductor devices 1130. The upper and side surfaces of the STI structure 1120, the upper and side surfaces of the HARC via 1116, and the upper surface of the semiconductor device 1130 may be exposed. Here, the upper surface of the STI structure 1120 refers to the bottom surface thereof in fig. 2B, the upper surface of the HARC via 1116 refers to the bottom surface thereof in fig. 2B, and the upper surface of the semiconductor device 1130 refers to the bottom surface thereof in fig. 2B.
Referring to fig. 2C, ILD structure 1140' is provided over STI structure 1120, HARC via 1116 and semiconductor device 1130. ILD structure 1140' may be patterned and etched to form trenches exposing the upper surfaces of HARC vias 1116. The trenches may be filled with a metallic material to form the backside power rails 1210. The backside power rail 1210 may contact the upper surface of the HARC via 1116. The backside power rail 1210 may be, for example, a Through Silicon Via (TSV) or a Buried Power Rail (BPR). In addition, the back side power rail 1210 may include copper (Cu), co, W, molybdenum (Mo), or ruthenium (Ru), but is not limited thereto. A second BEOL layer 1190 'may be provided on the ILD structure 1140' and connected to the backside power rail 1210. The semiconductor chip architecture in fig. 2C may be referred to as BSPDN semiconductor chip architecture 10, corresponding to the cross-sectional view of I-I' in fig. 1.
The active-gate upper contact 1115 and HARC via 1116 may connect the semiconductor device 1130 to a buried power rail provided from a second side of the device substrate 1100. HARC via 1116 may be connected through device substrate 1100 to a buried power rail extending from a second side of device substrate 1100.
Referring to fig. 2A and 2B, since trenches for HARC via 1116 and active-gate upper contact 1115 are separately etched based on a hole etching process, it may be difficult to properly align HARC via 1116 and active-gate upper contact 1115 or to secure a process margin. In addition, deep contact surface damage may occur.
Fig. 3A shows a plan view of a semiconductor chip architecture, and fig. 3B shows a plan view of a semiconductor chip architecture including the HARC via structure in fig. 2B.
Fig. 3A illustrates that the semiconductor chip architecture may include a semiconductor device 1130 and an ILD structure 1140. The semiconductor device 1130 may include a gate structure 1117 and a spacer layer 1112 provided on a side surface of the gate structure 1117.
Referring to fig. 3B, as shown in part I of the semiconductor chip architecture, circular regions corresponding to HARC vias 1116 are patterned between the spacer layers 1112 of adjacent gate structures 1117 to form HARC vias 1116, and elliptical regions corresponding to active-on-gate contacts 1115 are patterned between the spacer layers 1112 of adjacent gate structures 1117 to form active-on-gate contacts 1115.
However, due to the approximately 20nm width between the spacer layers 1112 of adjacent gate structures 1117, it may be difficult to align and etch the elliptical areas corresponding to the active-on-gate contacts 1115 with the circular areas corresponding to the HARC vias 1116. In addition, deep contact surface damage may occur in forming trenches for HARC via 1116 and active-gate upper contact 1115, and manufacturing costs may increase.
Fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H illustrate a method of fabricating a BSPDN semiconductor chip architecture including HARC via structures according to an example embodiment.
Referring to fig. 4A, the method may include providing a device substrate (wafer) 100. Hereinafter, the wafer 100 may be referred to as a device substrate 100. The device substrate 100 may be formed of a semiconductor material (e.g., si), or may be a part of an SOI substrate, without being limited thereto. The device substrate 100 may include an oxide layer 110 comprising an oxide material.
STI structures 120 may be formed in the device substrate 100. The STI structures 120 may extend horizontally in the D2 direction and be spaced apart from each other in the D1 direction, and may include SiO or SiN, without being limited thereto. The semiconductor devices 130 may be formed on a first side of the device substrate 100 and may be isolated from each other in the D1 direction by the STI structures 120. The semiconductor device 130 may include a transistor. Each transistor may include an epitaxial layer (which may be a source/drain region), a fin forming a channel structure, and a gate structure surrounding the fin, but is not limited thereto. Here, the semiconductor device 130 may refer to a front end of line (FEOL) layer including source/drain regions, fins, and gate structures. The transistors described below may be one or more finfets, nanowire transistors, nanoplatelet transistors, or the like.
Referring to fig. 4B, ILD structure 140 may be formed over STI structure 120 and semiconductor device 130. ILD structure 140 may be formed on exposed surfaces of STI structures 120 and exposed surfaces of semiconductor device 130. In addition, a nitride spacer layer 111 may be formed between the semiconductor device 130 and the ILD structure 140 and between the STI structure 120 and the device substrate 100.
Referring to fig. 4C, ILD structure 140 may be etched to form a horizontal trench extending to the upper surface of device substrate 100 (which corresponds to the upper surface of STI structure 120), which may be filled with a material such as, for example, siN, silicon carbon nitride (SiCN), ion doped carbon, etc., to form insulating layer 112. The insulating layer 112 may be formed adjacent to the semiconductor device 130 in a horizontal direction.
Referring to fig. 4D, a reverse contact structure pattern is printed on ILD structure 140 as a line-type self-aligned contact (SAC). The linear SAC pattern includes a first region, which corresponds to HARC via 116, formed based on insulating layer 112 and first spacer layer 123 (as described in more detail below in fig. 7A), and a second region, which corresponds to two active-gate upper contacts 115. ILD structure 140 and device substrate 100 are etched to the level of the upper surface of oxide layer 110 based on the first region to form trench 114 corresponding to HARC via 116. ILD structure 140 and one or more nitride spacer layers 111 are etched to the level of the upper surface of semiconductor device 130 based on a second region included in the same pattern to form trenches 113 corresponding to two active-gate upper contacts 115 based on a linear SAC pattern. Trenches 114 and 113 may be formed by separate etching processes.
Referring to fig. 4E, trenches 114 and 113 may be filled with a metallic material (such as, for example, W or Co) to form HARC via 116 and active-gate upper contact 115.HARC via 116 and active-gate upper contact 115 may be integrally formed.
HARC via 116 and active-gate upper contact 115 contact one or more semiconductor devices 130, the HARC via 116 extending to the level of the upper surface of the oxide layer in device substrate 100. The active-gate upper contact 115 and HARC via 116 may be structures included in a mid-line of process (MOL) layer of a semiconductor chip architecture, but are not limited thereto.
Referring to fig. 4F, the system of fig. 4E is flipped over to provide a carrier wafer 100'. The carrier wafer 100' may comprise silicon. The first BEOL layer 190 may be formed on the carrier wafer 100'. BEOL contact structures 170 may be formed on the first BEOL layer 190 and ILD structures 180 may be formed adjacent to the BEOL contact structures 170 and between the first BEOL layer 190 and the ILD structures 140.
The semiconductor chip architecture shown in fig. 4E may be flipped over and attached to ILD structure 180 such that active-gate-on-contact 115 contacts ILD structure 180 and BEOL contact structure 170.
Referring to fig. 4G, the device substrate 100 may be etched to the nitride spacer layer 111 to expose the HARC via 116 and the semiconductor device 130. The upper and side surfaces of HARC via 116 and the upper surface of semiconductor device 130 may be exposed. Here, the upper surface of HARC via 116 refers to its bottom surface in fig. 4E, and the upper surface of semiconductor device 130 refers to its bottom surface in fig. 4E.
Referring to fig. 4H, ILD structure 140' is provided over STI structure 120, HARC via 116 and semiconductor device 130. ILD structure 140' may be patterned and etched to form trenches exposing the upper surfaces of HARC via 116. The trenches may be filled with a metal material to form the backside power rail 210. The backside power rail 210 may contact the upper surface of the HARC path 116. The backside power rail 210 may be, for example, a Through Silicon Via (TSV) or a Buried Power Rail (BPR). In addition, the back side power rail 210 may include copper (Cu), co, W, molybdenum (Mo), or ruthenium (Ru), but is not limited thereto. A second BEOL layer 190 'may be provided on ILD structure 140' and connected to backside power rail 210. The semiconductor chip architecture in fig. 4H may be referred to as BSPDN semiconductor chip architecture 10, corresponding to the cross-sectional view of I-I' in fig. 1.
Fig. 5A, 5B, and 5C illustrate a method of fabricating HARC via structures in a semiconductor chip architecture according to another example embodiment.
Referring to fig. 5A, ILD structure 140 may be etched based on second spacer layer 121 to form a horizontal trench extending to the upper surface of device substrate 100 (which corresponds to the upper surface of STI structure 120), which may be filled with a material (such as, for example, siN, siCN, ion-doped carbon, etc.) to form insulating layer 112'. The insulating layer 112' may be formed adjacent to the semiconductor device 130.
Referring to fig. 5B, the reverse contact structure pattern is printed as a line-type self-aligned contact (SAC). The linear SAC pattern includes a first region, which corresponds to HARC via 116', formed based on insulating layer 112' and first spacer layer 123 (as described in more detail below in fig. 7B), and a second region, which corresponds to two active-on-gate contacts 115'. ILD structure 140 and device substrate 100 are etched to a level of the upper surface of oxide layer 110 based on the first region to form trenches 114 'corresponding to HARC vias 116', ILD layer 140 and one or more nitride spacer layers 111 are etched to a level of the upper surface of semiconductor device 130 based on the second region to form trenches 113 'corresponding to two active-gate upper contacts 115' based on a line-SAC pattern. Trenches 114 'and 113' may be formed by separate etching processes.
Referring to fig. 5C, trenches 114 'and 113' may be filled with a metal material (such as, for example, W or Co) to form HARC via 116 'and active-on-gate contact 115'. HARC via 116 'and active-gate upper contact 115' may be integrally formed.
HARC via 116' and active-gate upper contact 115' contact semiconductor device 130, HARC via 116' extending to the level of the upper surface of the oxide layer in device substrate 100. The active-gate upper contact 115 'and HARC via 116' may be structures included in a mid-line of process (MOL) layer of a semiconductor chip architecture, but are not limited thereto.
HARC via 116' and active-gate upper contact 115' may contact semiconductor device 130 and HARC via 116' may contact buried power rail 210 as shown in fig. 4H.
Fig. 6A, 6B, and 6C illustrate a method of fabricating HARC via structures in a semiconductor chip architecture according to another example embodiment.
Referring to fig. 6A, a gate polygon cutting pattern 117' may be formed adjacent to the semiconductor device 130. As described in more detail in fig. 7C, the gate polygonal cutting pattern 117' extends horizontally in the D2 direction perpendicular to the D1 direction, and the gate structure 117 and the first spacer layer 123 extend in the D1 direction.
Based on the gate polygon cut pattern 117', a linear SAC pattern is provided on a first region corresponding to the HARC via 116 "and a second region corresponding to the two active-on-gate contacts 115".
Referring to fig. 6B, ILD structure 140 and device substrate 100 are etched to a level of the upper surface of oxide layer 110 based on the first region formed according to gate polygon cut pattern 117' and first spacer layer 123 to form trench 114 "corresponding to HARC via 116". ILD layer 140 and one or more nitride spacer layers 111 are etched to the level of the upper surface of semiconductor device 130 based on the second region to form trenches 113 "corresponding to the two active-gate upper contacts 115" based on a linear SAC pattern. Trench 114 "and trench 113" may be formed by separate etching processes.
Referring to fig. 6C, trenches 114 "and 113" may be filled with a metal material (such as, for example, W or Co) to form HARC via 116 "and active-on-gate contact 115". HARC via 116 "and active-gate upper contact 115" may be integrally formed.
HARC via 116 "and active-gate upper contact 115" may contact semiconductor device 130, and HARC via 116 "may contact buried power rail 210, as shown in fig. 4H.
Fig. 7A shows a plan view of a self-aligned contact (SAC) pattern in the semiconductor chip architecture including HARC vias in fig. 4E.
Referring to fig. 7A, the semiconductor chip architecture includes ILD structure 140 and semiconductor device 130. The semiconductor device 130 includes a gate structure 117 and a first spacer layer 123, the first spacer layer 123 being provided on a side surface of the gate structure 117 extending horizontally in the D1 direction.
As shown in part a of the semiconductor chip architecture, a first pattern 119 corresponding to the HARC via 116 is patterned, and then a second pattern 118 is patterned. The first pattern 119 is patterned based on the first spacer layer 123 and the insulating layer 112. The second pattern 118 is patterned based on an area larger than an area corresponding to the active-gate upper contact 115, and includes a first spacer layer 123 provided on a side surface of the gate structure 117.
ILD structure 140 and device substrate 100 are etched to the level of the upper surface of oxide layer 110 based on the linear SAC pattern comprising first pattern 119 corresponding to HARC via 116 to form trench 114 corresponding to HARC via 116. ILD structure 140 and one or more nitride spacer layers 111 are etched to the level of the upper surface of semiconductor device 130 based on the linear SAC pattern comprising second pattern 118 to form trenches 113 corresponding to two active-gate upper contacts 115. Trenches 114 and 113 may be etched separately.
Trenches 114 and 113 may be filled with a metal material to form HARC via 116 and active-gate upper contact 115.
Accordingly, alignment between the active-gate upper contact 115 to the HARC via 116 may be improved and a process margin may be ensured based on the linear SAC pattern. In addition, deep contact surface damage can be avoided.
Fig. 7B shows a plan view of a self-aligned contact (SAC) pattern in a semiconductor chip architecture including HARC via in fig. 5C.
Referring to fig. 7B, the semiconductor chip architecture includes ILD structure 140 and semiconductor device 130. The semiconductor device 130 includes a gate structure 117 and a first spacer layer 123, the first spacer layer 123 being provided on a side surface of the gate structure 117 extending in the D1 direction. Further, the semiconductor chip architecture includes a second spacer layer 121 extending in a D2 direction perpendicular to the gate structure 117 and the first spacer layer 123.
As shown in part B of the semiconductor chip architecture, a first pattern 119 'corresponding to the HARC via 116 is patterned, and then a second pattern 118' is patterned. The first pattern 119 'is patterned based on the first spacer layer 123, the insulating layer 112', and the second spacer layer 121. The second pattern 118 'is patterned based on a larger area than an area corresponding to the active-gate upper contact 115' and includes a first spacer layer 123 provided on a side surface of the gate structure 117.
ILD structure 140 and device substrate 100 are etched to the level of the upper surface of oxide layer 110 based on the linear SAC pattern including first pattern 119 'corresponding to HARC via 116' to form trench 114 'corresponding to HARC via 116'. ILD structure 140 and one or more nitride spacer layers 111 are etched to the level of the upper surface of semiconductor device 130 based on the linear SAC pattern comprising second pattern 118' to form trenches 113' corresponding to two active-gate upper contacts 115'. Trenches 114 'and 113' may be etched separately.
Trenches 114 'and 113' may be filled with a metal material to form HARC via 116 'and active-gate upper contact 115'.
Thus, alignment between the active-gate upper contact 115 'to the HARC via 116' may be improved and process margin may be ensured based on the linear SAC pattern. In addition, deep contact surface damage can be avoided.
Fig. 7C shows a plan view of a self-aligned contact (SAC) pattern in a semiconductor chip architecture including HARC vias in fig. 6B.
Referring to fig. 7C, the semiconductor chip architecture includes ILD structure 140 and semiconductor device 130. The semiconductor device 130 includes a gate structure 117 and a first spacer layer 123 provided on a side surface of the gate structure 117. In addition, the semiconductor chip architecture includes a gate polygonal cutting pattern 117' extending horizontally in a D1 direction perpendicular to the gate structure 117 and the first spacer layer 123.
As shown in part C of the semiconductor chip architecture, the pattern 118 "including the first spacer layer 123 is etched to form HARC vias 116" based on the first spacer layer 123 and the gate polygonal cutting pattern 117' and to form active-on-gate contacts 115 "based on the linear SAC pattern. Pattern 118 "is larger than the area corresponding to active-on-gate contact 115" and HARC via 116 "and includes a first spacer layer 123 provided on a side surface of gate structure 117.
ILD structure 140 and device substrate 100 are etched to the level of the upper surface of oxide layer 110 based on gate polygon cut pattern 117' and first spacer layer 123 to form trenches 114 "corresponding to HARC vias 116". ILD structure 140 and one or more nitride spacer layers 111 are etched to the level of the upper surface of semiconductor device 130 based on the linear SAC pattern including pattern 118 "to form trenches 113" corresponding to the two active-gate upper contacts 115". Trenches 114 "and 113" may be etched separately.
Trenches 114 "and 113" may be filled with a metal material to form HARC via 116 "and active-gate upper contact 115".
Thus, the alignment between the active-gate contact 115 "to HARC via 116" may be improved and deep contact surface damage may be avoided. Further, since reverse patterning of the region corresponding to HARC via 116″ is not required in the example embodiment according to fig. 7C, the manufacturing process may be simplified and the cost may be reduced.
Fig. 8 shows a flowchart of a method of manufacturing a semiconductor chip architecture including HARC vias, according to an example embodiment.
In operation S110, a front end of line (FEOL) layer of a semiconductor chip architecture is formed. The FEOL layer includes a device substrate including an oxide layer, an STI structure provided in the device substrate, a semiconductor device provided on an upper surface of the device substrate, and an ILD structure provided on the semiconductor device and the STI structure.
In operation S120, a first trench is etched in the ILD structure to a level of an upper surface of the STI structure, and an insulating material is filled in the first trench to form an insulating layer.
In operation S130, the ILD structure, the nitride spacer layer, the STI structure, and the device substrate are etched to a level of an upper surface of the oxide layer based on a line-type SAC pattern including a first pattern corresponding to the HARC via, which is formed based on the insulating layer and the first spacer layer, to form a second trench.
In operation S140, the ILD structure and the one or more nitride spacer layers are etched to a level of an upper surface of the semiconductor device based on the linear SAC pattern including the second pattern to form a third trench corresponding to the contact on the two active-gates.
In operation S150, the second trench is filled with a metal material to form a High Aspect Ratio Contact (HARC) via and the third trench is filled with a metal material to form an active-on-gate contact.
Fig. 9 shows a flowchart of a method of manufacturing HARC via structures in a semiconductor chip architecture according to another example embodiment.
In operation S210, a front end of line (FEOL) layer of a semiconductor chip architecture is formed. The FEOL layer includes a device substrate including an oxide layer, an STI structure provided in the device substrate, a semiconductor device provided on a first side of the device substrate, and an ILD structure provided on the semiconductor device and the STI structure.
In operation S220, a first trench is etched in the ILD structure to a level of an upper surface of the STI structure, and an insulating material is filled in the first trench to form an insulating layer.
In operation S230, the ILD structure, the nitride spacer layer, the STI structure, and the device substrate are etched to a level of an upper surface of the oxide layer to form a second trench based on a line-type SAC pattern including a first pattern corresponding to the HARC via, which is formed based on the insulating layer, the first spacer layer, and the second spacer layer.
In operation S240, the ILD structure and the one or more nitride spacer layers are etched to a level of an upper surface of the semiconductor device based on the linear SAC pattern including the second pattern to form a third trench corresponding to the contact on the two active-gates.
In operation S250, the second trench is filled with a metal material to form a High Aspect Ratio Contact (HARC) via and the third trench is filled with a metal material to form an active-on-gate contact.
Fig. 10 shows a flowchart of a method of manufacturing a semiconductor chip architecture including HARC vias according to yet another example embodiment.
In operation S310, a front end of line (FEOL) layer of a semiconductor chip architecture is formed. The FEOL layer includes a device substrate including an oxide layer, an STI structure provided in the device substrate, a semiconductor device provided on a first side of the device substrate, and an ILD structure provided on the semiconductor device and the STI structure.
In operation 320, a reverse contact structure pattern is printed on the ILD structure as a line-type self-aligned contact (SAC) pattern based on the gate polygon cut pattern and the spacer layer provided on the side surface of the gate structure.
In operation S330, the ILD structure, the nitride spacer layer, the STI structure, and the device substrate are etched to a level of an upper surface of the oxide layer based on a line-type SAC pattern including a first pattern corresponding to the HARC via, to form a second trench, the first pattern being formed based on the gate polygon cut pattern and the first spacer layer.
In operation S340, the ILD structure and the one or more nitride spacer layers are etched to a level of an upper surface of the semiconductor device based on the linear SAC pattern including the second pattern to form a third trench corresponding to the contact on the two active-gates.
In operation S350, the second trench is filled with a metal material to form a High Aspect Ratio Contact (HARC) via and the third trench is filled with a metal material to form an active-on-gate contact.
Fig. 11 illustrates a semiconductor architecture that may include a semiconductor chip architecture according to an example embodiment.
Referring to fig. 11, a semiconductor package 2000 according to an embodiment may include a processor 2200 and a semiconductor device 2300 mounted on a substrate 2100. The processor 2200 and/or the semiconductor device 2300 may include one or more of the semiconductor chip architectures described in the above embodiments.
Fig. 12 shows a schematic block diagram of an electronic system according to an example embodiment.
Referring to fig. 12, an electronic system 3000 according to an embodiment may include a microprocessor 3100, a memory 3200, and a user interface 3300 in data communication using a bus 3400. The microprocessor 3100 may include a Central Processing Unit (CPU) or an Application Processor (AP). Electronic system 3000 may also include Random Access Memory (RAM) 3500 in direct communication with microprocessor 3100. The microprocessor 3100 and/or RAM 3500 may be implemented in a single module or package. User interface 3300 may be used to input data to electronic system 3000 or output data from electronic system 3000. For example, user interface 3300 may include, without limitation, a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a Liquid Crystal Display (LCD), a micro Light Emitting Device (LED), an Organic Light Emitting Diode (OLED) device, an active matrix light emitting diode (AMOLED) device, a printer, a lighting device, or various other input/output devices. The memory 3200 may store operation codes of the microprocessor 3100, data processed by the microprocessor 3100, or data received from external devices. The memory 3200 may include a memory controller, a hard disk, or a Solid State Drive (SSD).
At least the microprocessor 3100, memory 3200, and/or RAM 3500 in the electronic system 3000 may include a semiconductor chip architecture as described in the above embodiments.
It should be understood that the embodiments described herein should be considered in descriptive sense only and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments.
Although the embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.

Claims (20)

1. A semiconductor chip architecture, comprising:
a wafer;
a process line front end layer on a first side of the wafer, the process line front end layer comprising a semiconductor device on the first side of the wafer, a shallow trench isolation structure in the wafer, and an interlayer dielectric structure on the semiconductor device and the wafer;
a process line middle layer provided on the process line front end layer, the process line middle layer including contacts and vias connected to the contacts;
An insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction; and
a power rail penetrating the wafer from a second side of the wafer opposite the first side,
wherein the via extends in a vertical direction through the interlayer dielectric structure, the shallow trench isolation structure, and the wafer to contact the power rail.
2. The semiconductor chip architecture of claim 1, wherein the via is a High Aspect Ratio Contact (HARC) via penetrating the interlayer dielectric structure and the wafer in the vertical direction to contact the power rail.
3. The semiconductor chip architecture of claim 1, wherein the insulating layer extends in the vertical direction from a level of the upper surface of the contact to an upper surface of the shallow trench isolation structure and directly contacts a side surface of the via in the horizontal direction.
4. The semiconductor chip architecture of claim 1, wherein the semiconductor device comprises a gate structure and a first spacer layer provided on a side surface of the gate structure, and
wherein the contact is provided between the first spacer layers located between adjacent gate structures.
5. The semiconductor chip architecture of claim 4, further comprising a second spacer layer extending in a direction perpendicular to the direction in which the first spacer layer extends,
wherein the via is immediately adjacent to the second spacer layer in the horizontal direction.
6. The semiconductor chip architecture of claim 3, wherein the insulating layer comprises one of silicon nitride (SiN), silicon carbonitride (SiCN), and ion doped carbon (C).
7. A semiconductor chip architecture, comprising:
a wafer;
a process line front end layer on a first side of the wafer, the process line front end layer comprising semiconductor devices on the first side of the wafer, shallow trench isolation structures in the wafer, and an interlayer dielectric structure;
a process line middle layer provided on the process line front end layer, the process line middle layer including contacts and vias connected to the contacts;
a gate polygonal cutting pattern on the first side of the wafer and adjacent to the via in a horizontal direction; and
a power rail penetrating the wafer from a second side of the wafer opposite the first side,
wherein the via extends in a vertical direction through the interlayer dielectric structure, the shallow trench isolation structure, and the wafer to contact the power rail.
8. The semiconductor chip architecture of claim 7, wherein the via is a High Aspect Ratio Contact (HARC) via penetrating the interlayer dielectric structure and the wafer in the vertical direction to contact the power rail.
9. The semiconductor chip architecture of claim 7, wherein the semiconductor device comprises a gate structure and a spacer layer directly on a side surface of the gate structure,
wherein the contacts are provided between the spacer layers located between adjacent gate structures.
10. The semiconductor chip architecture of claim 9, wherein the gate polygon cut pattern extends in a direction perpendicular to a direction in which the gate structure extends and is directly adjacent to the via in the horizontal direction.
11. The semiconductor chip architecture of claim 7, wherein the contacts and the vias comprise one of tungsten (W) and cobalt (Co).
12. A method of fabricating a semiconductor chip architecture, the method comprising:
forming a wafer including an oxide layer;
forming a semiconductor device on a first side of the wafer;
forming an interlayer dielectric structure on the semiconductor device and the wafer;
Patterning the interlayer dielectric structure based on a self-aligned contact pattern including a first pattern and a second pattern;
etching the interlayer dielectric structure and the wafer to the level of the oxide layer based on the first pattern to form a first trench, and etching the interlayer dielectric structure to the level of the semiconductor device based on the second pattern to form a second trench based on the self-aligned contact pattern;
filling the first trench and the second trench with at least one metal material to form a via and a contact, respectively; and
a power rail is formed through the wafer from a second side of the wafer opposite the first side such that the power rail contacts the via.
13. The method of claim 12, further comprising:
etching the interlayer dielectric structure to a level of the first side of the wafer to form a third trench prior to etching the first trench;
the third trench is filled with an insulating material to form an insulating layer.
14. The method of claim 13, wherein the first trench is etched based on the first pattern formed based on the insulating layer and a first spacer layer provided directly on a side surface of a gate structure, and
Wherein the via is formed adjacent to the insulating layer.
15. The method of claim 14, wherein the second trench is etched based on the second pattern formed based on the first spacer layer and the first trench.
16. The method of claim 13, wherein the first trench is etched based on the first pattern formed based on the insulating layer, a first spacer layer provided on a side surface of a gate structure, and a second spacer layer extending horizontally in a direction perpendicular to a direction in which the first spacer layer extends.
17. The method of claim 12, further comprising:
a gate polygon cutting pattern is formed, which extends in a direction perpendicular to a direction in which the gate structures extend and between the gate structures.
18. The method of claim 17, wherein the first trench is etched based on the first pattern formed based on the gate polygon cut pattern and a first spacer layer provided directly on a side surface of the gate structure.
19. The method of claim 18, wherein the second trench is etched based on the second pattern formed based on the first spacer layer and the first trench.
20. The method of claim 18, wherein the via is formed directly adjacent to the gate polygon cut pattern.
CN202310369604.2A 2022-04-11 2023-04-07 Semiconductor chip architecture and method for manufacturing the same Pending CN116895634A (en)

Applications Claiming Priority (4)

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US63/329,720 2022-04-11
US17/887,203 US20230326858A1 (en) 2022-04-11 2022-08-12 Reversed high aspect ratio contact (harc) structure and process
US17/887,203 2022-08-12
KR10-2023-0019532 2023-02-14

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