CN116894412B - On-demand loading method for constructing SystemVerilog object multilayer structure, electronic equipment and medium - Google Patents
On-demand loading method for constructing SystemVerilog object multilayer structure, electronic equipment and medium Download PDFInfo
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- CN116894412B CN116894412B CN202310892683.5A CN202310892683A CN116894412B CN 116894412 B CN116894412 B CN 116894412B CN 202310892683 A CN202310892683 A CN 202310892683A CN 116894412 B CN116894412 B CN 116894412B
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- 238000011068 loading method Methods 0.000 title claims abstract description 36
- 238000010276 construction Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000012795 verification Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 3
- 230000008569 process Effects 0.000 abstract description 12
- 230000006870 function Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000012360 testing method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of chips, in particular to an on-demand loading method, electronic equipment and medium for constructing a multi-layer structure of a SystemVerilog object, wherein the method comprises the following steps of S1, acquiring a construction data type and a construction keyword corresponding to data to be constructed of an SV sub-class object, taking a layer corresponding to the SV sub-class object in the multi-layer structure as a current layer, and executing S2; step S2, judging whether corresponding cache data exist in the memory, if yes, executing step S4, otherwise, executing step S3; step S3, loading all data corresponding to the constructed data type in the current hierarchy and caching the data into a memory; step S4, matching is carried out based on the construction keywords, if the matching is successful, the target data is returned, the process is ended, and otherwise, the step S5 is executed; and S5, taking the parent class corresponding to the current hierarchy as the current hierarchy, and returning to the step S2. The invention reduces the majority of data modeling time and memory occupation.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to an on-demand loading method, an electronic device, and a medium for constructing a multilayer structure of a SystemVerilog object.
Background
The construction tool for chip design and verification needs to perform data modeling on class objects of SystemVerilog (SV for short), and if the class has a parent class, the object also needs to load related data for generating the parent class and store the related data in an object data space. The parent class may also have its own parent class, thus forming a multi-level data structure. In the case of large number of levels, and complex data contents of some levels, it takes a lot of time and memory to perform complete data modeling on the multi-level data structure. Therefore, how to realize light and rapid on-demand loading under the condition of ensuring the data required by matching and reduce most of the data modeling time and memory occupation becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide an on-demand loading method, electronic equipment and medium for constructing a system Verilog object multilayer structure, which reduce most of data modeling time and memory occupation.
According to a first aspect of the present invention, there is provided an on-demand loading method for building a multilayer structure of a SystemVerilog object, comprising:
step S1, obtaining a construction data type and a construction keyword corresponding to data to be constructed of a SystemVerilog sub-class object, taking a level corresponding to the SystemVerilog sub-class object in a multi-layer structure as a current level, and executing step S2;
step S2, judging whether cache data corresponding to the built data type in the current hierarchy exists in the memory, if so, executing step S4, otherwise, executing step S3;
step S3, loading all data corresponding to the constructed data type in the current level, and caching the data in a memory to generate cached data corresponding to the constructed data type in the current level;
step S4, matching is carried out in the cache data corresponding to the construction data type of the current level based on the construction keywords, if matching is successful, the target data corresponding to the construction keywords is returned, the flow is ended, and otherwise, the step S5 is executed;
and step S5, taking the parent class corresponding to the current level as the current level, and returning to the step S2.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the on-demand loading method, the electronic equipment and the medium for constructing the SystemVerilog object multilayer structure can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
according to the invention, dynamic layered loading can be dynamically realized according to actual data construction requirements, and loaded data is cached, so that light and rapid on-demand loading is realized under the condition of ensuring matching of the required data, most of data modeling time and memory occupation are reduced, and further, the efficiency of chip design and verification is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of an on-demand loading method for constructing a multilayer structure of a SystemVerilog object according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides an on-demand loading method for constructing a multi-layer structure of a SystemVerilog object, which is shown in FIG. 1 and comprises the following steps:
step S1, obtaining a construction data type and a construction keyword corresponding to data to be constructed of the SystemVerilog sub-class object, and executing step S2 by taking a level corresponding to the SystemVerilog sub-class object in the multi-layer structure as a current level.
It should be noted that a class is an abstract concept of things that have common characteristics to a class, and is essentially a data type, and an instance of a class is called an object. A new class is built on top of an existing class for enabling multiplexing of codes. Existing classes are called "base classes" or "parent classes", and newly created classes are called "derived classes" or "child classes". When the data modeling is required to be carried out on the SystemVerilog sub-class object, firstly, the construction data type and the construction key word corresponding to the data to be constructed of the SystemVerilog sub-class object are acquired, namely, the real data construction requirement is acquired, and the data of the sub-class and the parent class of the sub-class are not directly loaded, so that the lightweight and rapid on-demand loading is realized. The child, parent of the parent, etc. form a multi-layered structure.
The construction data types corresponding to the data to be constructed of the SystemVerilog sub-class objects comprise variables, parameters, routines and ranges. Routines function similarly to functions, but are more meaningful. A routine is a collection of functional interfaces or services that a certain system provides externally. Such as the API of the operating system, services, etc., are routines; standard functions and library functions provided by Delphi or C++ Builder, etc. are also routines. Range refers to variables that are not simple data types such as common int, logic.
And S2, judging whether cache data corresponding to the built data type in the current hierarchy exists in the memory, if so, executing the step S4, otherwise, executing the step S3.
It should be noted that, each data type of each level only needs to be loaded once, and is not deleted after first use, but is cached, and then can be directly used in the subsequent data construction process, so that the data construction efficiency is improved.
And step S3, loading all data corresponding to the constructed data type in the current level, and caching the data in the memory to generate cached data corresponding to the constructed data type in the current level.
If step S3 is entered, it is explained that the data corresponding to the constructed data type in the current hierarchy is loaded for the first time, after the first time, all the data corresponding to the constructed data type in the current hierarchy is cached in the memory, and then if the data corresponding to the constructed data type corresponding to the hierarchy is needed to be used again in the data construction process, the data is directly invoked in the cache without repeated loading.
And step S4, matching is carried out in the cache data corresponding to the construction data type of the current level based on the construction key, if matching is successful, the target data corresponding to the construction key is returned, the process is ended, and otherwise, the step S5 is executed.
It should be noted that, all data corresponding to a certain data type corresponding to a hierarchy is cached in the cache, but only a part of data may be needed in the actual data construction process, so that matching is needed in the cache data corresponding to the constructed data type of the current hierarchy based on the construction key, the corresponding target data is retrieved and obtained, and the SystemVerilog sub-class object is constructed based on the target data.
And step S5, taking the parent class corresponding to the current level as the current level, and returning to the step S2.
It can be understood that when the data corresponding to the child class can meet the data construction requirement, the data of the parent class is not required to be loaded, and when the data of the current child class is insufficient to meet the data construction requirement, the data of the corresponding data type in the parent class is required to be loaded, and not all the data of the parent class is required to be loaded.
According to the method provided by the embodiment of the invention, dynamic layered loading can be dynamically realized according to actual data construction requirements, the loaded data is cached, light and rapid on-demand loading is realized under the condition of ensuring matching of the required data, most of data modeling time and memory occupation are reduced, and further the efficiency of chip design and verification is improved. It should be noted that under most conditions, the modeling requirement can be met without recording and loading data of all parent classes, but under a small number of extreme conditions, the invention can acquire the target data after loading data of all parent classes, so that the invention can shorten the time of most data modeling and memory occupation.
As an embodiment, the memory caches the multi-layer structure of the SystemVerilog subclass object according to a preset data structure, where the preset data structure includes { a } 1 ,A 2 ,…,A n ,…,A N },A n An= (a) for the n-th level of cache data n 1 ,A n 2 ,A n 3 ,A n 4 ) Wherein A is n 1 For variable type data segment of the nth hierarchy, A n 2 For the n-th level of parameter type data segment, A n 3 For the nth level of routine data segment, A n 4 For the range data segment of the nth hierarchy, A n 1 ,A n 2 ,A n 3 ,A n 4 And (3) initially, carrying out blank, and subsequently loading corresponding data in the corresponding data segment according to specific data construction requirements and filling the corresponding data segment. In the prior art, { A }, is required to be once 1 ,A 2 ,…,A n ,…,A N All data corresponding to the data in the data segment are loaded, and the data segment is loaded and stored when which piece of data is needed according to the dynamic loading requirement, and is not deleted after being loaded, so that the data segment is used in the subsequent data construction process. According to the invention, through setting the preset data structure, in the process of data construction, the data types are distinguished to load the data, the data contents are distinguished to store the data, the loading on demand is realized, the loading content is reduced, the data loading speed is improved, and the memory occupation is reduced.
As an embodiment, the step S2 includes:
step S21, searching the cache data of the current level in the memory.
When the target data is acquired, the cache data of the current level in the memory is searched first to judge whether the target data is loaded or not, so that repeated loading is avoided, and meanwhile, the acquisition efficiency of the target data can be improved.
Step S22, if the data segment corresponding to the constructed data type in the cache data of the current level is empty, determining that the cache data corresponding to the constructed data type in the current level does not exist in the memory, otherwise, determining that the cache data corresponding to the constructed data type in the current level exists in the memory.
The embodiment of the invention caches the data based on the hierarchical segmented data structure, and is also convenient for searching the subsequent target data.
As an embodiment, the step S3 includes:
step S31, loading all data corresponding to the constructed data type in the current hierarchy.
It should be noted that, when loading data, all data corresponding to the type of the constructed data in the current hierarchy is loaded, that is, the data is loaded according to the type of the data, and then the loaded and cached data is searched for obtaining the target data. All types of data are willing to be directly stored in the database, and the types can be intuitively distinguished, so that the method and the device are set for loading the type of a certain layer of the level, not only ensure the accuracy of target data acquisition, but also reduce the data loading content and the memory occupation. For example, if the data with each level data type as a variable needs to be loaded, all the variable data corresponding to the level needs to be loaded and cached in the data segment corresponding to the level corresponding to the data structure.
And step S32, determining a corresponding data segment to be stored in the SystemVerilog sub-class object multi-layer structure in a memory based on the current hierarchy and the constructed data type.
Corresponding data segments are set for different data types in the preset data structure, so that when the data needs to be cached and loaded, the corresponding data segments are locked first, and the corresponding data segments to be stored in the system Verilog sub-object multi-layer structure are determined.
And step S33, all data corresponding to the constructed data type in the current hierarchy are cached in the data segment to be stored.
It can be understood that the loaded data is stored in a layered and segmented manner according to a preset data structure, so that the subsequent target data can be conveniently searched.
As an embodiment, in the chip verification scenario, the SystemVerilog sub-class object is a SystemVerilog sub-class object instantiated in the chip verification platform. The code of the test platform can adopt classes to reduce the multiplexing of the code, and because the code amount of the test platform is very large, a plurality of father stages can be involved in the middle, but when modeling the sub-class objects, only a small block of attributes can be needed, if all the attributes are loaded, the time is very consuming, and a lot of memory space is consumed. Based on the method and the device, the cache is only required to be loaded based on the data which needs to be concerned, so that the target data can be acquired more quickly and accurately.
According to the embodiment of the invention, through the on-demand loading mode, the correct matching of the data is ensured, the number of levels required to be loaded in the data modeling process is reduced, and the improvement is more remarkable under the complex design. Compared with the traditional modeling mode, the first loading speed is greatly improved, and the quick matching can be performed through the cache mode under the condition that data is acquired for a certain object for many times, so that the modeling time is greatly reduced, a large amount of memory space is saved, the memory threshold of a debugging tool is reduced, and the performance of the debugging tool is greatly improved, and the debugging efficiency is improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (6)
1. An on-demand loading method for constructing a multilayer structure of a SystemVerilog object is characterized by comprising the following steps:
step S1, obtaining a construction data type and a construction keyword corresponding to data to be constructed of a SystemVerilog sub-class object, taking a level corresponding to the SystemVerilog sub-class object in a multi-layer structure as a current level, and executing step S2;
step S2, judging whether cache data corresponding to the built data type in the current hierarchy exists in the memory, if so, executing step S4, otherwise, executing step S3;
the step S2 includes:
step S21, searching the cache data of the current level in the memory;
step S22, if the data segment corresponding to the constructed data type in the cache data of the current level is empty, determining that the cache data corresponding to the constructed data type in the current level does not exist in the memory, otherwise, determining that the cache data corresponding to the constructed data type in the current level exists in the memory;
step S3, loading all data corresponding to the constructed data type in the current level, and caching the data in a memory to generate cached data corresponding to the constructed data type in the current level;
the step S3 includes:
step S31, loading all data corresponding to the constructed data type in the current hierarchy;
step S32, determining corresponding data segments to be stored in the SystemVerilog sub-class object multi-layer structure in a memory based on the current hierarchy and the constructed data type;
step S33, all data corresponding to the constructed data type in the current level are cached in the data segment to be stored;
step S4, matching is carried out in the cache data corresponding to the construction data type of the current level based on the construction keywords, if matching is successful, the target data corresponding to the construction keywords is returned, the flow is ended, and otherwise, the step S5 is executed;
and step S5, taking the parent class corresponding to the current level as the current level, and returning to the step S2.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the construction data types corresponding to the data to be constructed of the SystemVerilog sub-class objects comprise variables, parameters, routines and ranges.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the memory caches a multi-layer structure of SystemVerilog sub-class objects according to a preset data structure, wherein the preset data structure comprises { A } 1 ,A 2 ,…,A n ,…,A N },A n An= (a) for the n-th level of cache data n 1 ,A n 2 ,A n 3 ,A n 4 ) Wherein A is n 1 For variable type data segment of the nth hierarchy, A n 2 For the n-th level of parameter type data segment, A n 3 For the nth level of routine data segment, A n 4 Number of ranges for the nth levelAccording to section A n 1 ,A n 2 ,A n 3 ,A n 4 Initially empty.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the SystemVerilog sub-class object is a SystemVerilog sub-class object instantiated in a chip verification platform.
5. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-4.
6. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-4.
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| CN113971019A (en) * | 2021-10-19 | 2022-01-25 | 深圳市元征科技股份有限公司 | Data type creating method, device, server and medium |
| CN116136952A (en) * | 2023-02-09 | 2023-05-19 | 之江实验室 | Simulation test method and device for components |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7934194B2 (en) * | 2006-10-17 | 2011-04-26 | The Mathworks, Inc. | User-defined hierarchies of user-defined classes of graphical objects in a graphical modeling environment |
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| US5493680A (en) * | 1992-07-06 | 1996-02-20 | National Business Machines Corporation | Method for creating an object subclass with selective inheritance |
| CN110989939A (en) * | 2019-12-16 | 2020-04-10 | 中国银行股份有限公司 | Data cache processing method, device and equipment and cache component |
| CN111984829A (en) * | 2020-07-08 | 2020-11-24 | 福建亿能达信息技术股份有限公司 | Vue-based tree asynchronous loading method, device, equipment and medium |
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