CN116893854B

CN116893854B - Method, device, equipment and storage medium for detecting conflict of instruction resources

Info

Publication number: CN116893854B
Application number: CN202311166405.8A
Authority: CN
Inventors: 颜开; 田骅; 肖冉; 蒋荣琳
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2023-09-11
Filing date: 2023-09-11
Publication date: 2023-11-14
Anticipated expiration: 2043-09-11
Also published as: CN116893854A

Abstract

The application discloses a method, a device, equipment and a storage medium for detecting conflict of instruction resources, and relates to the technical field of chips. The method comprises the following steps: acquiring a resource description table, wherein the resource description table comprises a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions respectively; creating a first resource reservation table; in response to the fact that a plurality of groups of hardware resources exist for the ith compiling instruction and meet the resource occupation condition, the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table writes the resource occupation information corresponding to the plurality of groups of hardware resources into the first resource reservation table to obtain a second resource reservation table corresponding to the plurality of groups of hardware resources; for the writing process, in response to the existence of conflict reservation tables in the plurality of second resource reservation tables, deleting the conflict reservation tables from the plurality of second resource reservation tables, wherein the conflict reservation tables have resource conflicts with hardware resource information corresponding to the (i+k) th compiling instruction, so that the instruction scheduling efficiency can be improved.

Description

Method, device, equipment and storage medium for detecting conflict of instruction resources

Technical Field

The present application relates to the field of chip technologies, and in particular, to a method, an apparatus, a device, and a storage medium for detecting collision of instruction resources.

Background

Artificial intelligence (Artificial Intelligence, AI) chips often use very long instruction set (Very Long Instruction Word, VLIW) architecture as an infrastructure, where the hardware responsible functions in many conventional chips are simplified or directly transferred to a compiler for implementation in order to achieve large-scale control of arithmetic units and power consumption. While compilers can become more complex, there is more opportunity for deeper optimization of code at the software level. The instruction scheduling is an important optimization stage, the transmitting sequence of the instructions can be reordered, the parallelism of instruction execution is improved, and the total time required by operator execution is reduced.

In the related art, a table scheduling algorithm is adopted to realize instruction scheduling optimization, in the process, a reserved table (Reservation Table, RT) is generally adopted to perform conflict detection, the reserved table can intuitively describe instruction resource occupation, and the instruction resource occupation can be generated by using automation tools based on hardware documents, so that the complexity is low.

However, in the above method, the reservation table is used to perform conflict detection, and when there are multiple sets of resources in one instruction, selecting the instruction by using a greedy algorithm may make instruction scheduling miss many possible opportunities when analyzing the available instruction, and the scheduling efficiency of instruction scheduling is low.

Disclosure of Invention

The embodiment of the application provides a conflict detection method, device and equipment for instruction resources and a storage medium, which can improve the scheduling efficiency of instruction scheduling. The technical scheme is as follows.

In one aspect, a method for detecting conflict of instruction resources is provided, the method comprising:

acquiring a resource description table, wherein the resource description table comprises a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions respectively, and the hardware resource information comprises at least one group of hardware resources capable of being used for completing the compiling instructions;

creating a first resource reservation table, wherein the first resource reservation table is used for recording the occupation condition of hardware resources of the plurality of compiling instructions;

for the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, in response to the fact that a plurality of groups of hardware resources exist for the ith compiling instruction and meet resource occupation conditions, writing the resource occupation information corresponding to the plurality of groups of hardware resources into the first resource reservation table to obtain a second resource reservation table corresponding to the plurality of groups of hardware resources, wherein i is a positive integer, and the resource occupation conditions are used for indicating that hardware resources required for completing the compiling instruction are unoccupied;

And aiming at the writing process of hardware resource information corresponding to the ith+k compiling instruction in a plurality of second resource reservation tables, deleting the conflict reservation table from the plurality of second resource reservation tables in response to the existence of the conflict reservation table in the plurality of second resource reservation tables, wherein the conflict reservation table has resource conflict with the hardware resource information corresponding to the ith+k compiling instruction, and k is a positive integer.

In another aspect, there is provided a collision detection apparatus of instruction resources, the apparatus including:

the system comprises an acquisition module, a resource description table and a processing module, wherein the acquisition module is used for acquiring a resource description table, the resource description table comprises a plurality of compiling instructions and hardware resource information respectively corresponding to the compiling instructions, and the hardware resource information comprises at least one group of hardware resources capable of being used for completing the compiling instructions;

the processing module is used for creating a first resource reservation table, and the first resource reservation table is used for recording the occupation condition of hardware resources of the plurality of compiling instructions;

the processing module is further configured to, in response to a writing process of hardware resource information of the plurality of compiling instructions in the first resource reservation table, write resource occupation information corresponding to each of the plurality of groups of hardware resources into the first resource reservation table in response to a fact that a plurality of groups of hardware resources exist for an ith compiling instruction, where i is a positive integer, and the resource occupation condition is used to indicate that hardware resources required for completing the compiling instruction are unoccupied;

The processing module is further configured to, for a writing process of hardware resource information corresponding to the i+k compiling instruction in a plurality of second resource reservation tables, delete a conflict reservation table from the plurality of second resource reservation tables in response to the existence of the conflict reservation table in the plurality of second resource reservation tables, where the conflict reservation table has a resource conflict with the hardware resource information corresponding to the i+k compiling instruction, and k is a positive integer.

In another aspect, a computer device is provided, where the computer device includes a processor and a memory, where the memory stores at least one instruction, at least one program, a set of codes, or a set of instructions, where the at least one instruction, the at least one program, the set of codes, or the set of instructions are loaded and executed by the processor to implement a method for collision detection of an instruction resource according to any of the embodiments of the present application described above.

In another aspect, a computer readable storage medium is provided, where at least one instruction, at least one program, a set of codes, or a set of instructions is stored, where the at least one instruction, the at least one program, the set of codes, or the set of instructions are loaded and executed by a processor to implement a method for conflict detection of an instruction resource according to any one of the embodiments of the present application.

In another aspect, a computer program product or computer program is provided, the computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the collision detection method of the instruction resource according to any one of the above embodiments.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

by acquiring a resource description table, the resource description table comprises a plurality of compiling instructions and hardware resource information respectively corresponding to the compiling instructions, the hardware resource information comprises at least one group of hardware resources capable of being used for completing the compiling instructions, a first resource reservation table is created, the first resource reservation table is used for recording the hardware resource occupation condition of the plurality of compiling instructions, the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table is performed, a plurality of groups of hardware resources meeting the resource occupation condition is performed for the ith compiling instruction, the resource occupation information respectively corresponding to the plurality of groups of hardware resources is written in the first resource reservation table, a second resource reservation table respectively corresponding to the plurality of groups of hardware resources is obtained, i is a positive integer, the resource occupation condition is used for indicating that hardware resources required for completing the compiling instructions are not occupied, the writing process of the hardware resource information corresponding to the ith+k compiling instructions in the plurality of second resource reservation tables is performed, the conflict reservation table is used for deleting the conflict reservation table from the plurality of second resource reservation tables, and the hardware resources corresponding to the ith+k compiling instructions are the positive integer. By maintaining a plurality of reserved tables for compiled instructions with a plurality of groups of hardware resources, more selectable opportunities exist in instruction scheduling when available instructions are analyzed, different resource scenes can be compared more comprehensively in the conflict detection process of the instruction resources, optimal results are selected from a plurality of resources, and scheduling efficiency of instruction scheduling is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of reservation table-based instruction resource conflict detection in accordance with an exemplary embodiment of the present application;

FIG. 2 is a schematic illustration of an implementation environment provided by an exemplary embodiment of the present application;

FIG. 3 is a flowchart of a method for conflict detection of instruction resources provided by an exemplary embodiment of the present application;

FIG. 4 is a representation of a resource description intent provided by an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a write process provided by an exemplary embodiment of the present application;

FIG. 6 is a schematic diagram of a multi-reservation table writing process provided by an exemplary embodiment of the present application;

FIG. 7 is a diagram illustrating the deletion of a conflict reservation table in accordance with one exemplary embodiment of the present application;

fig. 8 is a flowchart of a second resource reservation table generation method provided in an exemplary embodiment of the present application;

FIG. 9 is a flowchart of a method for conflict reservation table deletion provided in one exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of instruction execution cycle adjustment provided by an exemplary embodiment of the present application;

FIG. 11 is a flowchart of a method for parsing a resource description table provided by an exemplary embodiment of the present application;

FIG. 12 is a timing occupancy representation provided by one example embodiment of the present application;

FIG. 13 is a diagram of instruction resource conflict detection provided by an exemplary embodiment of the present application;

FIG. 14 is a performance contrast representation of an intent provided by an exemplary embodiment of the present application;

FIG. 15 is a schematic diagram of a parsing flow for a resource description table provided by an exemplary embodiment of the present application;

FIG. 16 is a schematic diagram of a timing occupancy summary provided in an exemplary embodiment of the application;

FIG. 17 is a schematic diagram of a resource conflict detection procedure provided by an exemplary embodiment of the present application;

FIG. 18 is a block diagram of a conflict detection apparatus for instruction resources provided in an exemplary embodiment of the present application;

FIG. 19 is a block diagram of a conflict detection apparatus module for instruction resources provided by an exemplary embodiment of the present application;

fig. 20 is a block diagram of a terminal according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

It should be understood that, although the terms first, second, etc. may be used in this disclosure to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.

AI chips often use VLIW architecture as an infrastructure, where in order to achieve control of large-scale arithmetic units and power consumption, the functions responsible for hardware in many conventional chips are simplified or directly transferred to a compiler for implementation. While compilers can become more complex, there is more opportunity for deeper optimization of code at the software level. The instruction scheduling is an important optimization stage, the transmitting sequence of the instructions can be reordered, the parallelism of instruction execution is improved, and the total time required by operator execution is reduced. In the related art, a table scheduling algorithm is adopted to realize instruction scheduling optimization, in the process, a reserved table is generally adopted to perform conflict detection, the reserved table can intuitively describe instruction resource occupation, and the instruction resource occupation can be generated by using automatic tools based on hardware documents, so that the complexity is low. However, in the above method, the reservation table is used to perform conflict detection, and when there are multiple sets of resources in one instruction, selecting the instruction by using a greedy algorithm may make instruction scheduling miss many possible opportunities when analyzing the available instruction, and the scheduling efficiency of instruction scheduling is low.

In some embodiments, instruction scheduling may reorder the order of the instructions transmitted, in the actual instruction scheduling process, the device constructs a directed acyclic graph (Directed Acyclic Graph, DAG) according to the input instruction sequence, the DAG is used to represent the dependency between instructions, and the priority topology ordering is performed according to the DAG; determining an instruction which can be transmitted in a current instruction execution period and performing conflict detection on instruction resources, putting the instruction which meets the transmission condition into a first list, wherein the first list comprises all the instructions which can be transmitted currently in practice, and continuously adjusting the current instruction execution period until the instruction which can be used is determined if the instruction which meets the transmission condition does not exist, wherein the transmission condition is that the resource conflict exists between the instruction which can be transmitted and the transmitted instruction; and performing sequential adjustment according to the instructions in the first list, namely moving the instruction determined to be transmitted in the current instruction execution period to the back of the last scheduled instruction until all the instructions are adjusted, and completing the instruction scheduling process. The conflict detection process of the instruction resources is used for determining the resource occupation condition of a plurality of compiled instructions in the execution process.

For illustration, a hardware device is determined, and the hardware device supports transmitting a plurality of instructions in a same cycle (cycle), and instruction a, instruction B, instruction C,3 instructions and 6 corresponding hardware resources are taken as examples for description, and please refer to the following table 1 for the instruction resource occupation condition:

Table 1 instruction resource occupancy table

As shown in table 1, the resource group is used to indicate how many corresponding hardware resource combinations are available for each instruction, for example, instruction a corresponds to two sets of hardware resources, wherein if instruction a adopts resource group 1, it is required to occupy hardware resource 0a in cycle (cycle) 0, occupy hardware resource 0b in cycle1, and occupy hardware resource 0c in cycle2 during execution of instruction a. The cycle is used to indicate a unit time in the instruction execution process, for example, cycle0 is used to indicate the 1 st instruction execution cycle in the instruction execution process. It should be noted that, the resource groups are independent of each other, for example, the resource group 1 may be used to execute the instruction a, or the resource group 2 may be used to execute the instruction a, but the resource group 1 and the resource group 2 are not miscible, and if the instruction a is executed while occupying 0a in cycle0, then 1b in cycle1 may not be occupied. The binary representation corresponding to the 6 hardware resources is shown in table 2.

TABLE 2 binary representation of resources

Since the resource conflict detection is performed based on the instruction resource description, the instruction resource description format is introduced first, taking the underlying virtual machine (Low Level Virtual Machine, LLVM) as an example, the LLVM generates an instruction resource description table based on the resource occupation situation indicated in the above table 1, analyzes the resources occupied by the compiling instruction in each stage, the occupation time and the time interval to the next resource for each compiling instruction, and when there are a plurality of resource groups corresponding to the compiling instruction, connects the different hardware resources occupied in the same stage with "|", and describes the instruction resources as the structure shown in the following table 3:

Table 3 instruction resource description table

As shown in table 3, the occupation of hardware resources during completing an instruction is described in conjunction with instruction resources, occupation time of each resource, and interval time to next instruction, where a stage refers to an execution stage of the instruction, for example, instruction a occupies 1 cycle using resource 0a in stage 0, and the interval time from resource 0a to next resource is 1 cycle, that is, instruction a occupies 0a in 1 st cycle, that is, cycle0, occupies 0b in 2 nd cycle, that is, cycle1, where cycle0 corresponds to stage 0, and indicates the time occupied by 1 st execution stage, and so on. However, the resource description format shown in table 3 cannot describe multiple sets of hardware resources required to be occupied by an instruction, and when one instruction has multiple sets of hardware resources, the description format cannot accurately describe the instruction resources, for example, as shown in table 3, instruction a needs to occupy hardware resources 0a or 1a in cycle0 and needs to occupy hardware resources 0b or 1b in cycle1, based on the description format, four kinds of resource occupation situations of 0a+1b, 0a+0b, 1a+1b and 1a+0b can be generated in cycle0 and cycle1 by instruction a, however, according to table 1, it can be known that only 0a+0b or 1a+1b accords with the actual resource occupation situation.

The instruction resource description table provided by table 3 is used for detecting conflict of instruction resources, and it is assumed that in the instruction scheduling process, instruction C, instruction B, instruction a and instruction C need to be scheduled according to the order from high priority to low priority, please refer to fig. 1, fig. 1 is a schematic diagram for detecting conflict of instruction resources based on a reservation table, as shown in fig. 1, a solid rectangular box in the drawing is a reservation table, a dotted rectangular box is used for indicating an instruction execution period, a number before a colon in the reservation table is used for identifying the instruction execution period, a binary number after the colon is used for indicating occupied hardware resources, a number marked in an underlined form before the colon is used for identifying the current instruction execution period, a number marked in italic after the colon is used for identifying the resources occupied by the inserted instruction, and a number marked in bold after the colon is used for identifying the resources with conflicts. As shown in fig. 1, the resource conflict detection process for scheduling instruction C, instruction B, instruction a, instruction C using a reservation table includes the following steps:

1) Creating a reservation table and initializing the reservation table data to 0:000000, inserting the hardware resources required to be occupied by the instruction C from the current instruction execution cycle0, namely occupying the hardware resources 0b (000010) in the cycle0, occupying the hardware resources 0C (000100) in the cycle1, and occupying the hardware resources 0C (000100) in the cycle2, so as to obtain an updated reservation table;

2) Inserting the hardware resource occupied by the instruction B from the current instruction execution cycle0, and adjusting the current instruction execution cycle to be cycle1 because the hardware resource 0c occupied by the instruction B in the cycles 1 and 2 conflicts with the hardware resource occupied by the cycles 1 and 2 in the reserved table; inserting the hardware resource required to occupy by the instruction B from the current instruction execution cycle1, and adjusting the current instruction execution cycle to be cycle2 because the hardware resource 0c required to occupy by the instruction B in cycle2 still has resource conflict with the hardware resource required to occupy by cycle2 in the reserved table; inserting the hardware resources occupied by the instruction B from the current instruction execution cycle2, wherein the hardware resources are respectively occupied by cycle2 (000001), cycle3 (000100), and cycle4 (000100);

3) Inserting the hardware resources required to be occupied by the instruction A from the current instruction execution cycle2, wherein the instruction A has a resource group 1 and a resource group 2, detecting the resource conflict according to the order of the priority from high to low for the resource group 1 and the resource group 2, selecting to occupy the hardware resource 1a at the cycle2 (001000) because the hardware resource 0a required by the instruction A has the resource conflict with the 0a occupied by the cycle2 in the reservation table, selecting to occupy the hardware resource 0b at the cycle3 (000010) because the hardware resource 0b required by the instruction A does not have the resource conflict with the 0c occupied by the cycle3 in the reservation table, and selecting to occupy the hardware resource 1c at the cycle4 (100000) because the hardware resource 0c required by the instruction A has the resource conflict with the 0c occupied by the cycle4 in the reservation table;

4) The hardware resources occupied by the instruction A are inserted from the current instruction execution period cycle2, and the current instruction execution period is adjusted to be cycle3 because the resources 1 and the resources group 2 corresponding to the instruction A have resource conflict with the hardware resources in the reserved table from cycle 2; reinserting the hardware resources occupied by the instruction A from the current instruction execution period cycle3, wherein the resource group 1 and the resource group 2 corresponding to the instruction A have no resource conflict with the hardware resources in the reservation table, and the updated reservation table is obtained by only maintaining 1 reservation table, selecting the resource group 1 according to the priority of the resource group, occupying the hardware resource 0a (000001) at cycle3, occupying the hardware resource 0b (000010) at cycle4 and occupying the hardware resource 0c (000100) at cycle5;

5) The hardware resources occupied by the instruction C are inserted from the current instruction execution cycle3, and the resource group 1 corresponding to the instruction C has resource conflict with the hardware resources in the reserved table from cycle3, so that the current instruction execution cycle is adjusted to cycle4; reinserting the hardware resources occupied by the instruction C from the current instruction execution cycle4, and adjusting the current instruction execution cycle to cycle5 because the resource group 1 corresponding to the instruction C still has resource conflict with the hardware resources in the reserved table from cycle4; reinsertion of the hardware resources occupied by instruction C from the current instruction execution cycle5, occupies hardware resources 0b (000010) at cycle5, occupies hardware resources 0C (000100) at cycle6, occupies hardware resources 0C (000100) at cycle7, and obtains an updated reservation table.

In the above-mentioned conflict detection process of instruction resources, when the hardware resources required to be occupied by the instruction a are reinserted from the current instruction execution cycle3 in step 4, although the resource occupation information corresponding to the resource group 1 and the resource group 2 of the instruction a can be inserted into the reservation table, since only 1 reservation table is maintained, the greedy algorithm is used to select the instruction to make the instruction schedule miss the instruction group 2 to complete the instruction a scheme when the available instruction is analyzed, based on this, when the hardware resources required to be occupied by the instruction C are inserted in step 5, the detection of 2 consecutive cycles has resource conflicts, resulting in 2 cycle stalls, so that the instruction schedule scheme determined based on the above-mentioned conflict detection scheme is easy to miss more instruction schedule opportunities, and is easy to cause more cycle stalls, so that the scheduling efficiency of the instruction schedule is lower.

The method for detecting the conflict of the instruction resources provided by the embodiment of the application comprises the steps of obtaining a resource description table, wherein the resource description table comprises a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions respectively, the hardware resource information comprises at least one group of hardware resources which can be used for completing the compiling instructions, creating a first resource reservation table, the first resource reservation table is used for recording the hardware resource occupation condition of the plurality of compiling instructions, aiming at the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, writing a plurality of groups of hardware resource occupation information corresponding to the hardware resources respectively into the first resource reservation table in response to the existence of a plurality of groups of hardware resource occupation conditions aiming at the ith compiling instruction, obtaining a second resource reservation table corresponding to the plurality of groups of hardware resources respectively, i is a positive integer, wherein the resource occupation conditions are used for indicating the hardware resource unoccupied required for completing the compiling instructions, aiming at the writing process of the hardware resource information corresponding to the ith compiling instruction in the plurality of second resource reservation tables, responding to the conflict reservation table exists in the plurality of second resource reservation tables, and the conflict reservation table is deleted from the plurality of second resource reservation table, and the conflict reservation table is a positive integer which is the conflict reserved for the hardware resource. By maintaining a plurality of reserved tables for compiled instructions with a plurality of groups of hardware resources, more selectable opportunities exist in instruction scheduling when available instructions are analyzed, different resource scenes can be compared more comprehensively in the conflict detection process of the instruction resources, optimal results are selected from a plurality of resources, and scheduling efficiency of instruction scheduling is improved.

First, an environment in which the present application is implemented will be described. Referring to fig. 2, a schematic diagram of an implementation environment provided by an exemplary embodiment of the present application is shown, where the implementation environment includes: and a terminal 210.

In some embodiments, the terminal 210 executes the object program using an AI chip, the terminal 210 is provided with a machine learning model 211 and an AI compiler 212, the AI compiler 212 adopts a classical front-end and back-end structure, and the AI compiler 212 is used to connect the machine learning model 211 with the AI chip.

In some embodiments, the machine learning model 211 is read by the AI compiler 212, first, model analysis is performed at the front end to obtain advanced intermediate representation (Intermediate Representation, IR), then optimization independent of target hardware, such as arithmetic reduction, operator fusion, etc., is performed, and the optimized advanced IR is output; then, target related optimization of the back end is entered, such as dedicated instruction mapping, memory allocation, access delay hiding and the like, and related low-level IR is output; finally, entering a code generation stage of the back end, and finally generating a target program which can run on the AI chip.

In some embodiments, AI chips often use VLIW architecture as an infrastructure, where in order to achieve control of large-scale arithmetic units and power consumption, the functions responsible for hardware in many conventional chips are simplified or directly transferred to a compiler for implementation. While the AI compiler 212 may become more complex, there may be more opportunities for deeper optimization of the code at the software level. The instruction scheduling is an important optimization stage, the transmitting sequence of the instructions can be reordered, the parallelism of instruction execution is improved, and the total time required by operator execution is reduced. In some embodiments, the terminal 210 obtains a resource description table, where the resource description table includes a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions respectively, and the hardware resource information includes at least one set of hardware resources that can be used for completing the compiling instructions; creating a first resource reservation table, wherein the first resource reservation table is used for recording the occupation condition of hardware resources of a plurality of compiling instructions; in response to the fact that a plurality of groups of hardware resources meet resource occupation conditions for an ith compiling instruction in a writing process of hardware resource information of a plurality of compiling instructions in a first resource reservation table, writing the resource occupation information corresponding to the plurality of groups of hardware resources into the first resource reservation table to obtain a second resource reservation table corresponding to the plurality of groups of hardware resources respectively, wherein i is a positive integer, and the resource occupation conditions are used for indicating that hardware resources required for completing the compiling instructions are unoccupied; aiming at the writing process of hardware resource information corresponding to the ith+k compiling instruction in a plurality of second resource reservation tables, in response to the existence of conflict reservation tables in the plurality of second resource reservation tables, deleting the conflict reservation tables from the plurality of second resource reservation tables, wherein the conflict reservation tables and the hardware resource information corresponding to the ith+k compiling instruction have resource conflicts, and k is a positive integer.

The above terminal is optional, and the terminal may be a desktop computer, a laptop portable computer, a mobile phone, a tablet computer, an electronic book reader, a dynamic image expert compression standard audio layer 3 (Moving Picture Experts Group Audio Layer III, MP 3) player, a dynamic image expert compression standard audio layer 4 (Moving Picture Experts Group Audio Layer IV, MP 4) play, a smart television, a smart car, or other terminal devices in various forms, which are not limited in this embodiment of the present application.

In some embodiments, the terminal may also be a server.

It should be noted that the server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server that provides cloud services, cloud security, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, a content distribution network (Content Delivery Network, CDN), and basic cloud computing services such as big data and an artificial intelligence platform.

Cloud Technology (Cloud Technology) refers to a hosting Technology that unifies serial resources such as hardware, software, network and the like in a wide area network or a local area network to realize calculation, storage, processing and sharing of data.

In some embodiments, the servers described above may also be implemented as nodes in a blockchain system.

It should be noted that, the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals related to the present application are all authorized by the user or are fully authorized by the parties, and the collection, use and processing of the related data need to comply with the relevant laws and regulations and standards of the relevant region. For example, the present application relates to that compiling instructions, hardware resource information, etc. are obtained under the condition of full authorization.

Referring to fig. 3, a flowchart of a method for detecting collision of command resources according to an exemplary embodiment of the present application is shown, where the method may be executed by a terminal, may be executed by a server, or may be executed by the terminal and the server together, and the embodiment of the present application is described by using the method executed by the terminal as an example, as shown in fig. 3, and the method includes the following steps:

step 310, a resource description table is obtained.

The resource description table comprises a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions respectively, and the hardware resource information comprises at least one group of hardware resources which can be used for completing the compiling instructions.

In some embodiments, the resource description table is stored in the terminal memory.

Taking the example of the resource description table stored in the terminal memory as an example, the resource description table is stored in the terminal memory in the form of a structure body.

Alternatively, the hardware resource information in the resource description table may be stored as a whole in one structure, or may be stored in a distributed manner in structures corresponding to a plurality of compiled instructions, respectively.

Taking the explanation of the case where the hardware resource information in the resource description table is stored in the structures corresponding to the plurality of compiling instructions in a distributed manner, the acquisition of the resource description table may be implemented by reading the hardware resource information corresponding to the compiling instructions from the plurality of structures, respectively.

Illustratively, each set of hardware resources of each compiling instruction corresponds to a structure body, then the structure body stores hardware resource information corresponding to the set of hardware resources, and assuming that the resource description table includes hardware resource information corresponding to a compiling instruction a, a compiling instruction B and a compiling instruction C, the compiling instruction a corresponds to a structure body a for storing the hardware resource information corresponding to the resource group 1, and a structure body B for storing the hardware resource information corresponding to the resource group 2, the compiling instruction B corresponds to a structure body C for storing the hardware resource information, the compiling instruction C corresponds to a structure body d for storing the hardware resource information, and the resource description table is obtained by reading the structure body a, the structure body B, the structure body C and the structure body d from the terminal memory, and reading the hardware resource information corresponding to the compiling instruction A, B, C.

In some embodiments, the resource description table is used to describe a possible occupation of instruction resources, which is used to indicate at least one set of hardware resources that can be used to complete a compiled instruction.

In some embodiments, the hardware resource information of the resource description table includes an instruction name, a stage identifier, at least one group of resources, an occupied time, and a time interval to a next resource. The instruction name is used for indicating a compiled instruction corresponding to the hardware resource, the stage identification is used for indicating an instruction execution stage corresponding to the hardware resource, the occupied time is used for indicating the number of instruction execution cycles required by the hardware resource in the corresponding instruction execution stage, the time interval from the next resource is used for indicating the number of instruction execution cycles required between the current instruction execution stage and the next instruction execution stage, and the instruction execution cycle is used for indicating the unit time in the instruction execution process.

For illustration, taking the instruction resource occupation situation shown in the above table 1 as an example, please refer to fig. 4, fig. 4 is a schematic illustration of resource description provided by an exemplary embodiment of the present application, as shown in fig. 4, the resource description table 400 includes a resource group 410 corresponding to the instruction a and a resource group 420 corresponding to the instruction a, a resource group 430 corresponding to the instruction B and the instruction C, a resource group 440 corresponding to the instruction C, the resource group 410 includes hardware resources 0a, 0B and 0C required by the instruction a, the resource group 420 includes hardware resources 1a, 1B and 1C required by the instruction a, the resource group 430 includes hardware resources 0a, 0C and 0C required by the instruction B, and the resource group 440 includes hardware resources 0B, 0C and 0C required by the instruction C, where the partition words are used to distinguish different resource groups when a single compiled instruction corresponds to multiple groups of hardware resources. Taking the resource group 1 as an example for the instruction a, the instruction execution stage 0 of the instruction a needs to occupy the hardware resource 0a, the occupying time is 1 cycle, the time interval between the instruction execution stage 0 and the instruction execution stage 1 is 1 cycle, the instruction execution stage 1 of the instruction a needs to occupy the hardware resource 0b, the occupying time is 1 cycle, the time interval between the instruction execution stage 1 and the instruction execution stage 2 is 1 cycle, the instruction execution stage 2 of the instruction a needs to occupy the hardware resource 0c, the occupying time is 1 cycle, and the time interval between the instruction execution stage 2 and the instruction execution stage 0 of the next instruction is 1 cycle. That is, during execution of instruction A, hardware resource 0a is occupied by the 1 st cycle, hardware resource 0b is occupied by the 2 nd cycle, and hardware resource 0c is occupied by the 3 rd cycle.

It should be noted that, the above-mentioned resource description table is merely an example, the implementation form of the resource description table is not limited by the present application, the resource description table adopted in the embodiment of the present application is different from the hybrid description manner of two sets of hardware resources for the instruction a in table 3, the resource description table adopted in the embodiment of the present application may describe multiple sets of hardware resources corresponding to a single compiling instruction independently and clearly, for example, the partition word is used to distinguish the resource set 1 from the resource set 2, and the distinguishing manner between different resource sets is not limited by the present application.

Step 320, a first resource reservation table is created.

The first resource reservation table is used for recording the occupation condition of hardware resources of a plurality of compiling instructions.

In some embodiments, the above-mentioned hardware resource occupation situation refers to an actual resource occupation situation of the compiled instruction in the execution process.

In some embodiments, the first reservation table is stored in a terminal memory.

The first reservation table is stored in the terminal memory in the form of an array.

Alternatively, the first reservation table may be stored in a heap, stack, queue, linked list, or the like, which is not limited in this disclosure.

In some embodiments, creating the first resource reservation table is implemented as creating an array for storing the first resource reservation table.

Illustratively, in response to the first resource reservation table being created, a first array for storing the first resource reservation table is created in the terminal memory, and in response to the new hardware resource occupation situation being written in the first resource reservation table, the data content corresponding to the updated hardware resource occupation situation is updated into the first array, so that the latest first reservation table is stored in the terminal memory in an array form in real time.

Alternatively, one array may be used to store a single resource reservation table, and may also be used to store multiple resource reservation tables.

In some embodiments, the first resource reservation table created is a null table.

In some embodiments, the compiled instruction corresponds to a plurality of instruction execution stages, and the compiled instruction sequentially occupies corresponding hardware resources in an order corresponding to the plurality of instruction execution stages. In some embodiments, in the collision detection process of the instruction resources, resource occupation information corresponding to hardware resources respectively occupied by the compiling instruction in a plurality of instruction execution stages is written in the first resource reservation table based on occupation conditions of the instruction resources.

In some embodiments, when there are 1 first resource reservation tables, the writing process of the hardware resource information for the plurality of compiling instructions in the first resource reservation tables includes the following two cases:

first kindIn response to the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, writing the resource occupation information corresponding to the hardware resource into the first resource reservation table from the current instruction execution period to obtain a fourth resource reservation table, wherein the resource occupation condition corresponding to the current instruction execution period is met by the hardware resource of the compiling instructions;

second kindIn response to the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, the method responds to the current instruction execution cycle and the first instruction execution cycle of the hardware resource of the compiling instructionsAnd when the resource conflict exists in the resource reservation table, updating the next instruction execution period of the current instruction execution period into the current instruction execution period until the hardware resources of the compiled instruction meet the resource occupation condition corresponding to the current instruction execution period, and writing the resource occupation information corresponding to the hardware resources into the first resource reservation table from the current instruction execution period to obtain a fifth resource reservation table.

In some embodiments, the resource occupancy condition includes a hardware resource corresponding to the compiled instruction, and there is no resource conflict with the first reservation table from an instruction execution cycle in which the compiled instruction starts to execute.

For illustration, it is assumed that the first reservation table records that the hardware resources occupied by cycle0 are 0a, the hardware resources occupied by cycle1 are 0b, and the hardware resources occupied by cycle2 are 0c, and if the instruction execution period for starting to execute the instruction a is cycle0, and the hardware resources required by the instruction a in cycles 0, 1, and 2 are 0a, 0b, and 0c, respectively, then the hardware resources corresponding to the instruction a have resource conflict with the first reservation table.

Illustratively, taking the writing process of the hardware resource information of the compiled instruction in the resource description table as shown in fig. 4 as an example, it is assumed that the resource conflict detection is performed by the execution sequence of the instruction C and the instruction B, please refer to fig. 5, fig. 5 is a schematic diagram of the writing process provided in an exemplary embodiment of the present application, and as shown in fig. 5, the first reservation table 510 is created as an empty table, and the data of the first reservation table 510 is initialized as 0:000000, for indicating that the current instruction execution cycle is cycle0, and no hardware resource is occupied; in response to the hardware resource for the compiled instruction C meeting the resource occupation condition corresponding to the cycle0 of the current instruction execution cycle, writing the resource occupation information corresponding to the hardware resource into the first resource reservation table 510 from the current instruction execution cycle to obtain a fourth resource reservation table 520, where the fourth resource reservation table 520 is used to indicate that the hardware resource 0b is occupied at the cycle0 (000010), the hardware resource 0C is occupied at the cycle1 (000100), and the hardware resource 0C is occupied at the cycle2 (000100); in response to the hardware resource for the compiled instruction B having a resource conflict with the fourth resource reservation table 520 in the current instruction execution cycle0, the next instruction execution cycle1 of the current instruction execution cycle0 is updated to be the current instruction execution cycle until the hardware resource for the compiled instruction B meets the resource occupation condition corresponding to the current instruction execution cycle2, the resource occupation information corresponding to the hardware resource is written into the first resource reservation table from the current instruction execution cycle2 to obtain a fifth resource reservation table 530, where the fifth resource reservation table 530 is used to indicate that the hardware resource 0B is occupied in cycle0 (000010), the hardware resource 0c is occupied in cycle1 (000100), the hardware resource 0c is occupied in cycle2 (000100) and the hardware resource 0a (000001), the hardware resource 0c is occupied in cycle3 (000100), and the hardware resource 0c is occupied in cycle4 (000100).

Step 330, for the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, in response to the fact that a plurality of groups of hardware resources exist for the ith compiling instruction and meet the resource occupation condition, writing the resource occupation information corresponding to the plurality of groups of hardware resources into the first resource reservation table, and obtaining the second resource reservation table corresponding to the plurality of groups of hardware resources.

Wherein i is a positive integer, and the resource occupation condition is used for indicating that hardware resources required for completing compiling the instruction are unoccupied.

In some embodiments, a single compiled instruction corresponds to a single set of hardware resource information or multiple sets of hardware resource information, and when a single compiled instruction corresponds to multiple sets of hardware resource information, there may be multiple sets of hardware resources that meet the resource occupancy condition.

Illustratively, taking the writing process of the hardware resource information of the compiled instruction in the resource description table as shown in fig. 4 as an example for illustration, the instruction a corresponds to the resource group 410 and the resource group 420, please refer to fig. 6, fig. 6 is a schematic diagram of the writing process of the multi-reservation table provided in an exemplary embodiment of the present application, as shown in fig. 6, the current first reservation table 610 is obtained, and the resource occupation condition in the first reservation table is used to indicate that the resource 0b (000010) is occupied in the cycle0, the resource 0c (000100) is occupied in the cycle1, the resources 1a (001000), 0c (000100), 0a (000001) are occupied in the cycle2, the resources 0c (000100), 0b (000010) are occupied in the cycle3, and the resources 1c (100000), 0c (000100) are occupied in the cycle 4; in response to there being two sets of hardware resources meeting the resource occupancy condition for the instruction a, where the resource set 410 is configured to instruct the instruction a to occupy the resource 0a from the current instruction execution cycle3, occupy the resource 0b at cycle4, occupy the resource 0c at cycle5, and the resource set 420 is configured to instruct the instruction a to occupy the resource 1a from the current instruction execution cycle, occupy the resource 1b at cycle4, occupy the resource 1c at cycle5, write the resource occupancy information corresponding to the two sets of resource hardware into the first resource reservation table 610, to obtain the second resource reservation table 621 corresponding to the resource set 410, and the second resource reservation table 622 corresponding to the resource set 420.

Step 340, for the writing process of the hardware resource information corresponding to the i+k compiling instruction in the plurality of second resource reservation tables, deleting the conflict reservation table from the plurality of second resource reservation tables in response to the existence of the conflict reservation table in the plurality of second resource reservation tables.

The conflict reservation table has resource conflict with hardware resource information corresponding to the ith+kth compiling instruction, and k is a positive integer.

In some embodiments, the conflicting reservation table is deleted from the plurality of second resource tables if and only if the plurality of second resource reservation tables are present, in response to the conflicting reservation tables being present.

In some embodiments, the number of collision reservation tables is less than the number of second resource reservation tables.

In some embodiments, the existence of the resource conflict means that the hardware resource information corresponding to the compiling instruction is already occupied in the occupation situation indicated by the resource reservation table, for example, the resource occupation situation of cycle0 to cycle5 is recorded in the resource reservation table, the instruction a needs to occupy the resource 0a in cycle3, if the cycle3 recorded in the resource reservation table occupies the resource 0a, the resource conflict exists, and the resource reservation table can be determined as the conflict reservation table.

For illustration, taking the writing process of the hardware resource information of the compiled instruction in the resource description table as shown in fig. 4 as an example, please refer to fig. 7, fig. 7 is a schematic diagram for deleting the conflict reservation table provided by an exemplary embodiment of the present application, as shown in fig. 7, the writing process of the hardware resource information of the instruction C in the second resource reservation table 711 and the second resource reservation table 712 is performed, in response to the existence of the second resource reservation table 711 in the second resource reservation table 711 and the second resource reservation table 712 as the conflict reservation table, deleting the second resource reservation table 711, and writing the hardware resource information of the instruction C in the second resource reservation table 712 to obtain the resource reservation table 720, wherein the instruction C needs to occupy the resource 0b (000010) in the cycle4, occupy the resource 0C (000100) in the cycle5, and the existence of the resource occupied by the cycle4 and the cycle5 conflicts with the resource occupied by the second resource reservation table 711.

In some embodiments, if the number of conflict reservation tables is equal to the number of second resource reservation tables, the conflict reservation tables are not deleted, the current instruction execution period is adjusted, the next instruction execution period is updated to the current instruction execution period, and then instruction resource conflict detection is performed again from the current instruction execution period.

In summary, in the method provided by the embodiment of the present application, a resource description table is obtained, where the resource description table includes a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions, the hardware resource information includes at least one set of hardware resources that can be used to complete the compiling instructions, a first resource reservation table is created, the first resource reservation table is used to record a hardware resource occupation situation of the plurality of compiling instructions, a writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table is performed, in response to a condition that a plurality of sets of hardware resource occupation conditions exist for the ith compiling instruction, the resource occupation information corresponding to the plurality of sets of hardware resources respectively is written in the first resource reservation table, i is a positive integer, where the resource occupation conditions are used to indicate that hardware resources required to complete the compiling instructions are not occupied, in response to a writing process of the hardware resource information corresponding to the ith+k compiling instruction in the plurality of second resource reservation tables, in response to a reservation table that a conflict exists in the plurality of second resource reservation tables, the conflict with the hardware resource information corresponding to the ith compiling instruction is deleted from the plurality of second resource reservation tables, and the hardware resource occupation information corresponding to the conflict with the ith and k+th reserved resource is a positive integer. By maintaining a plurality of reserved tables for compiled instructions with a plurality of groups of hardware resources, more selectable opportunities exist in instruction scheduling when available instructions are analyzed, different resource scenes can be compared more comprehensively in the conflict detection process of the instruction resources, optimal results are selected from a plurality of resources, and scheduling efficiency of instruction scheduling is improved.

Referring to fig. 8, fig. 8 is a flowchart of a second resource reservation table generating method according to an exemplary embodiment of the present application, where the method may be executed by a terminal, may be executed by a server, or may be executed by both the terminal and the server, and the embodiment of the present application is described by taking the method executed by the terminal as an example, as shown in fig. 8, and step 330 includes the steps of:

step 331, in response to the mth group of hardware resources according to the resource occupation condition for the ith compiling instruction, writing the resource occupation information corresponding to the mth group of hardware resources into the first resource reservation table to obtain an nth second resource reservation table corresponding to the mth group of hardware resources.

Wherein m and n are positive integers.

In some embodiments, if and only if the ith compiling instruction corresponds to a plurality of sets of hardware resources, and at least two sets of hardware resources in the plurality of sets of hardware resources meet the resource occupation condition, at least two corresponding second resource reservation tables can be generated.

Illustratively, taking the writing process of the hardware resource information of the compiled instruction in the resource description table as shown in fig. 4 as an example, the instruction a corresponds to the resource group 410 and the resource group 420, please refer to fig. 6, and in response to the 1 st group of hardware resources for the instruction a, that is, the resource group 410, meeting the resource occupation condition, the resource occupation information corresponding to the 1 st group of hardware resources is written into the first resource reservation table 610, so as to obtain the 1 st second resource reservation table 621 corresponding to the 1 st group of hardware resources; in response to the group 2 hardware resources for instruction a, i.e., resource group 420, meeting the resource occupancy condition, the resource occupancy information corresponding to the group 2 hardware resources is written into the first resource reservation table 610, resulting in a second resource reservation table 622 corresponding to the group 2 hardware resources.

In some embodiments, the ith compiled instruction is issued beginning with the jth instruction execution cycle, j being a positive integer. For example, after the first reservation table is created, instruction C is executed as the 1 st compilation instruction beginning with the 1 st instruction execution cycle, cycle 0.

In some embodiments, step 321 is implemented to, in response to the mth group of hardware resources for the ith compiled instruction conforming to the resource occupancy condition corresponding to the jth instruction execution cycle, write the resource occupancy information corresponding to the mth group of hardware resources from the jth instruction execution cycle into the first resource reservation table, to obtain the nth second resource reservation table.

Referring to fig. 6, after writing the hardware resource information of the 3 rd compiling instruction, for the writing process of the hardware resource information of the 4 th compiling instruction, that is, the instruction a, in response to the 1 st group of hardware resources for the instruction a conforming to the resource occupation condition corresponding to the 4 th instruction execution cycle, that is, cycle3, the resource occupation information corresponding to the 1 st group of hardware resources is written from the 4 th instruction execution cycle3 into the first resource reservation table 610, to obtain the 1 st second resource reservation table 621; in response to the 2 nd set of hardware resources for instruction a meeting the resource occupation condition corresponding to the 4 th instruction execution cycle, i.e., cycle3, the resource occupation information corresponding to the 2 nd set of hardware resources is written from the 4 th instruction execution cycle3 into the first resource reservation table 610, resulting in the 2 nd second resource reservation table 622.

And step 332, obtaining r second resource reservation tables in response to the completion of writing the hardware resource information for the ith compiling instruction.

Wherein r is used to indicate the number of multiple sets of hardware resources meeting the resource occupation condition.

In some embodiments, assuming that d is the number of resource groups of multiple groups of hardware resources corresponding to the ith compiled instruction, r.ltoreq.d.

For illustration, please refer to fig. 6, 2 second resource reservation tables are obtained in response to the writing of the two sets of hardware resource information for the instruction a, which are the second resource reservation table 621 and the second resource reservation table 622, respectively.

In summary, according to the method provided by the embodiment of the application, the resource occupation information corresponding to the mth group of hardware resources is written into the first resource reservation table in response to the mth group of hardware resources conforming to the resource occupation condition for the ith compiling instruction, the nth second resource reservation table corresponding to the mth group of hardware resources is obtained, the r second resource reservation table is obtained in response to the writing of the hardware resource information for the ith compiling instruction, and a plurality of reservation tables are maintained for the compiling instruction with a plurality of groups of hardware resources, so that more selectable opportunities exist for instruction scheduling in the process of analyzing the available instructions, more comprehensive comparison of different resource scenes in the process of conflict detection of the instruction resources can be ensured, optimal results are selected from a plurality of resources, and the scheduling efficiency of the instruction scheduling is improved.

According to the method provided by the embodiment of the application, the resource occupation information corresponding to the mth group of hardware resources is written into the first resource reservation table from the j instruction execution period by responding to the resource occupation condition corresponding to the j instruction execution period corresponding to the mth group of hardware resources of the ith compiling instruction, so that the nth second resource reservation table is obtained, and the writing mode of the hardware resource information is clarified.

Based on the second resource reservation table generating method, please refer to fig. 9, fig. 9 is a flowchart of a method for deleting a conflict reservation table according to an exemplary embodiment of the present application, where the method may be executed by a terminal, may be executed by a server, or may be executed by both the terminal and the server, and the embodiment of the present application is described by using the method executed by the terminal as an example, as shown in fig. 9, the step 340 includes the following steps:

and 341, determining the p second resource reservation table as a conflict reservation table to obtain q conflict reservation tables in response to the resource conflict between the i+kth compiling instruction and the p second resource reservation table.

Wherein p and q are positive integers, and q < r.

For illustration, please refer to fig. 7, in response to the compiling instruction C having a resource conflict with the 1 st second resource reservation table 711, the 1 st second resource reservation table 711 is determined as the conflict reservation table, resulting in 1 conflict reservation table.

In some embodiments, the ith compiled instruction is executed from a jth instruction execution cycle and the ith+kth compiled instruction is executed from a jth+l instruction execution cycle, wherein the jth instruction cycle through the jth+l instruction execution cycle are used to execute the ith compiled instruction through the ith+k-1 compiled instruction, and l is a positive integer.

Illustratively, assuming that the 3 rd compiled instruction is executed from the 1 st instruction execution cycle and the 5 th compiled instruction is executed from the 8 th instruction execution cycle, the 1 st instruction execution cycle through the 8 th instruction execution cycle are used to execute the 3 rd compiled instruction through the 4 th compiled instruction.

In some embodiments, step 341 is implemented to determine the p-th second resource reservation table as a conflict reservation table in response to the i+k-th compilation instruction having a resource conflict with the p-th second resource reservation table from the j+l-th instruction execution cycle, resulting in q conflict reservation tables.

For illustration, referring to fig. 7, in response to the instruction C having a resource conflict with the 1 st second resource reservation table 711 from the 5 th instruction execution cycle4, the 1 st second resource reservation table 711 is determined as a conflict reservation table, and 1 conflict reservation table is obtained.

In step 342, q collision reservation tables are deleted from the r second resource reservation tables.

For illustration, please refer to fig. 7, 1 conflict reservation table is deleted from 2 second resource reservation tables, namely the second resource reservation table 711 is deleted.

In some embodiments, the plurality of second resource reservation tables are all implemented as conflict reservation tables, i.e. r=q, and the writing process of the hardware resource information corresponding to the i+k compiling instructions in the r second resource reservation tables includes the following two steps:

in the first step, in response to the existence of r conflict reservation tables in the r second resource reservation tables, the ith+kth compiling instruction is adjusted to be executed from the jth+l+t instruction execution period, and t is a positive integer.

Referring to fig. 10, fig. 10 is a schematic diagram illustrating adjustment of an instruction execution cycle according to an exemplary embodiment of the present application, as shown in fig. 10, instruction B is executed from cycle3, and in response to 2 conflict reservation tables in 2 second resource reservation tables, instruction B is executed from cycle4, where the instruction B has a resource conflict between the resource 0a (000001) required to be occupied by cycle3 and the resource 0c (000100) required to be occupied by cycle4 and the second resource reservation table 1011, and the instruction B has a resource conflict between the resource 0c (000100) required to be occupied by cycle4 and the second resource reservation table 1012.

And secondly, in response to the fact that the hardware resources of the ith+k compiling instruction meet the resource occupation conditions corresponding to the j+l+t instruction execution periods, writing the resource occupation information corresponding to the hardware resources into r second resource reservation tables to obtain r third resource reservation tables.

The j-th instruction cycle to the j+l+t-th instruction execution cycle are used for executing the i-th compiling instruction to the i+k-1-th compiling instruction.

For illustration, referring to fig. 10, in response to the hardware resource for instruction B meeting the resource occupation condition corresponding to cycle4, the resource occupation information corresponding to the hardware resource is written into the second resource reservation table 1011 and the second reservation table 1012 to obtain the third resource reservation table 1021 and the third resource reservation table 1022.

In summary, in the method provided by the embodiment of the present application, by determining the p-th second resource reservation table as the conflict reservation table in response to the resource conflict between the i+k-th compiling instruction and the p-th second resource reservation table, q conflict reservation tables are obtained, and q conflict reservation tables are deleted from r second resource reservation tables, so that the deletion mode of the resource reservation tables is clarified, more selectable opportunities are ensured when the instruction scheduling is enabled to analyze the available instructions, and at the same time, additional resource expenditure caused by simultaneously maintaining too many reservation tables is avoided, thereby improving the conflict detection efficiency.

According to the method provided by the embodiment of the application, the p second resource reservation table is determined as the conflict reservation table by responding to the resource conflict between the i+k compiling instruction and the p second resource reservation table from the j+l instruction execution period, so that the q conflict reservation tables are obtained, the determination mode of the resource conflict is clarified, and the conflict detection efficiency is improved.

According to the method provided by the embodiment of the application, the ith+k compiling instruction is regulated to be executed from the j+l+t instruction execution period by responding to the existence of the r conflict reservation tables in the r second resource reservation tables, and the resource occupation information corresponding to the hardware resource is written into the r second resource reservation tables by responding to the resource occupation condition corresponding to the j+l+t instruction execution period of the hardware resource of the ith+k compiling instruction, so that the r third resource reservation tables are obtained, and the conflict detection efficiency is definitely realized when all the second resource reservation tables are realized as the processing mode media of the conflict reservation tables.

In some embodiments, after the resource description table is obtained, the method further includes a process for parsing the resource description table, please refer to fig. 11, fig. 11 is a flowchart of a method for parsing the resource description table, where the method may be executed by a terminal, may be executed by a server, or may be executed by both the terminal and the server, and the embodiment of the present application is described by taking the method executed by the terminal as an example, as shown in fig. 11, and further includes, after step 310, the following steps:

Step 1110, parsing the resource description table to obtain a plurality of time sequence occupancy tables.

The time sequence occupation table is used for indicating occupation condition of the compiling instruction on an instruction execution cycle in the execution process.

In some embodiments, the compiled instruction corresponds to a plurality of execution phases, and the at least one set of hardware resources includes hardware resources corresponding to the plurality of execution phases, and step 1110 includes the steps of:

first, a first compiling instruction is read from a resource description table, and a time sequence occupation table corresponding to the first compiling instruction is created.

In some embodiments, the timing occupancy table is created as an empty table, the timing occupancy table having a correspondence with the first compiled instruction.

Alternatively, a single first compiled instruction may correspond to one or more timing occupancy tables, where a single timing occupancy table includes a set of hardware resource information for the corresponding first compiled instruction.

And secondly, reading resource occupation information corresponding to an a-th hardware resource corresponding to the first compiling instruction from a resource description table, and analyzing the resource occupation information to obtain the occupation condition of the a-th hardware resource corresponding to the first compiling instruction on an instruction execution period in an a-th execution stage, wherein a is a positive integer.

Schematically, the resource occupation information corresponding to the 1 st hardware resource 0a of the first compiling instruction, that is, the instruction a, is read from the resource description table shown in fig. 4, and the resource occupation information is analyzed, so as to obtain the occupation condition of the 1 st hardware resource corresponding to the instruction a on the instruction execution cycle in the 1 st execution stage, that is, stage 0, where the resource 0a occupies 1 cycle, and the time interval from the next resource is 1 cycle.

And thirdly, updating the occupation condition into a time sequence occupation table.

Schematically, the occupation condition corresponding to the resource group 1 of the instruction a is updated to the time sequence occupation table, and the time sequence occupation table includes occupation conditions of resources 0a, 0b and 0c required to be occupied by the instruction a on instruction execution periods in a plurality of execution phases.

Referring to fig. 12, fig. 12 is a schematic diagram showing the timing occupation of an exemplary embodiment of the present application, where, as shown in fig. 12, a timing occupation table 1210 indicates the timing occupation condition of a resource group 1 corresponding to an instruction a in the execution process, a 1 st cycle is occupied by a resource 0a in the execution process, a 1 st cycle is a time interval from a resource 0b to a resource 0b, a 2 nd cycle is occupied by a resource 0b in the execution process, a 1 st cycle is a time interval from a resource 0c to a resource 0c, and a 3 rd cycle is occupied by a resource 0c in the execution process.

Fourth, aiming at the resource analysis process of the first compiling instruction, in response to the fact that the segmentation word is read and the first compiling instruction corresponds to unresolved hardware resources, a time sequence occupation table corresponding to the first compiling instruction is newly built, occupation conditions are updated based on the resource description table until the hardware resources of the first compiling instruction are analyzed, and a plurality of time sequence occupation tables corresponding to the first compiling instruction are obtained.

The division word is used for distinguishing an a-th hardware resource corresponding to the first compiling instruction from an a+1-th hardware resource.

Illustratively, in the process of analyzing the resources of the instruction a, in response to reading the segmentation word shown in fig. 4, and the instruction a corresponds to the unresolved resource group 2, a time sequence occupation table corresponding to the first compiling instruction is newly established, and the occupation condition is updated based on the resource description table until the hardware resources of the first compiling instruction are analyzed, so as to obtain a plurality of time sequence occupation tables corresponding to the first compiling instruction.

In some embodiments, the segmentation word is further used to distinguish the first compiling instruction from the second compiling instruction, and the resource parsing process for the compiling instruction further includes: and in response to the fact that the segmentation word is read and the hardware resource corresponding to the first compiling instruction is analyzed, creating a time sequence occupation table corresponding to the second compiling instruction, and updating the occupation condition based on the resource description table until the plurality of compiling instructions in the resource description table are analyzed, and obtaining the time sequence occupation tables corresponding to the plurality of compiling instructions respectively.

The segmentation word is used for distinguishing the first compiling instruction from the second compiling instruction.

Illustratively, taking the resource description table as shown in fig. 4 as an example for explanation, assuming that the hardware resource information of the instruction a, the instruction B, and the instruction C is further distinguished by using the partition word in the resource description table 400, the partition word exists between the instruction a and the instruction B in the resource description table 400, and the partition word exists between the instruction B and the instruction C. In response to the reading of the segmentation word and the analysis of the hardware resources corresponding to the instruction A, a time sequence occupation table corresponding to the instruction B is newly built and the occupation condition is updated based on the resource description table, in response to the reading of the segmentation word and the analysis of the hardware resources corresponding to the instruction B, a time sequence occupation table corresponding to the instruction C is newly built and the occupation condition is updated based on the resource description table until the analysis of the instruction A, the instruction B and the instruction C in the resource description table 400 is completed, and the time sequence occupation tables corresponding to the instruction A, the instruction B and the instruction C are obtained respectively.

In summary, according to the method provided by the embodiment of the application, the plurality of time sequence occupation tables are obtained by analyzing the resource description table, and the time sequence occupation tables are used for indicating the occupation condition of the compiling instruction on the instruction execution period in the execution process, so that the machine can quickly perform conflict detection according to the occupation condition, and the conflict detection efficiency is improved.

According to the method provided by the embodiment of the application, a first compiling instruction is read from a resource description table, a time sequence occupation table corresponding to the first compiling instruction is created, resource occupation information corresponding to an a-th hardware resource corresponding to the first compiling instruction is read from the resource description table, the resource occupation information is analyzed, the occupation condition of the a-th hardware resource corresponding to the first compiling instruction for the instruction execution period in the a-th execution stage is obtained, the occupation condition is updated into the time sequence occupation table, the resource analysis process of the first compiling instruction is responded, the time sequence occupation table corresponding to the first compiling instruction is newly created and the occupation condition is updated based on the resource description table in response to the fact that the segmentation word is read, until the hardware resource analysis of the first compiling instruction is completed, a plurality of time sequence occupation tables corresponding to the first compiling instruction are obtained, the a-th hardware resource corresponding to the first compiling instruction is distinguished from the a-th hardware resource corresponding to the first compiling instruction through the segmentation word, the relative independence of a-th hardware resource and the a+1-th hardware resource is guaranteed, scheduling errors caused by the indistinct resource description in the conflict detection process are avoided, and the scheduling efficiency of the instructions is improved.

Referring to fig. 13, fig. 13 is a schematic diagram of instruction resource conflict detection provided by an exemplary embodiment of the present application, as shown in fig. 13, based on a resource description table 400 shown in fig. 4, instruction resource conflict detection is performed, and it is assumed that in the instruction scheduling process, instruction C, instruction B, instruction a, and instruction C need to be scheduled according to a priority order from high to low, a solid rectangular box in the figure is a reserved table, a dotted rectangular box is used to indicate an instruction execution period, a number before a colon in the reserved table is used to identify the instruction execution period, a binary number after the colon is used to indicate occupied hardware resources, a number marked in an underlined form before the colon is used to identify a current instruction execution period, a number marked in italic after the colon is used to identify resources occupied by an inserted instruction, and a number marked in bold after the colon is used to identify resources where conflict exists. As shown in fig. 13, the resource conflict detection process for scheduling instruction C, instruction B, instruction a, instruction C using the reservation table includes the steps of:

1) Creating a first resource reservation table and initializing reservation table data to 0:000000, inserting the hardware resources required to be occupied by the instruction C from the current instruction execution cycle0, namely occupying the hardware resources 0b (000010) in the cycle0, occupying the hardware resources 0C (000100) in the cycle1, and occupying the hardware resources 0C (000100) in the cycle2, so as to obtain an updated first resource reservation table;

2) Inserting the hardware resource occupied by the instruction B from the current instruction execution cycle0, and adjusting the current instruction execution cycle to be cycle1 because the hardware resource 0c occupied by the instruction B in the cycles 1 and 2 conflicts with the hardware resource occupied by the cycles 1 and 2 in the reserved table; inserting the hardware resource required to occupy by the instruction B from the current instruction execution cycle1, and adjusting the current instruction execution cycle to be cycle2 because the hardware resource 0c required to occupy by the instruction B in cycle2 still has resource conflict with the hardware resource required to occupy by cycle2 in the first resource reservation table; inserting the hardware resources occupied by the instruction B from the current instruction execution cycle2, wherein the hardware resources are respectively occupied by cycle2 (000001), cycle3 (000100), and cycle4 (000100);

3) Inserting the hardware resources required to be occupied by the instruction A from the current instruction execution cycle2, wherein the instruction A has a resource group 1 and a resource group 2, and detecting resource conflict according to the sequence of the priority from high to low as the resource group 1 and the resource group 2, wherein the resource 1 corresponding to the instruction A has resource conflict with the first resource reservation table, the resource group 2 is adopted, the hardware resource 1a is occupied at cycle2 (001000), the hardware resource 1b is occupied at cycle3 (010000), and the hardware resource 1c is occupied at cycle4 (100000);

4) Inserting a hardware resource which is occupied by an instruction A from a current instruction execution period cycle2, and adjusting the current instruction execution period to be cycle3 because resource conflict exists between a resource 1 corresponding to the instruction A and a resource group 2 from cycle2 and the hardware resource in a first resource reservation table; reinserting the hardware resources occupied by the instruction A from the current instruction execution period cycle3, wherein the resource conflict does not exist between the resource group 1 and the resource group 2 corresponding to the instruction A and the hardware resources in the first resource reservation table, the resource occupation information corresponding to the resource group 1 is written into the first resource reservation table, the hardware resources 0a (000001) are occupied by the cycle3, the hardware resources 0b (000010) are occupied by the cycle4, the hardware resources 0c (000100) are occupied by the cycle5, and the 1 st second resource reservation table is obtained; writing the resource occupation information corresponding to the resource group 2 into a first resource reservation table, occupying the hardware resource 1a (001000) in the cycle3, occupying the hardware resource 1b (010000) in the cycle4, and occupying the hardware resource 1c (100000) in the cycle5 to obtain a 2 nd second resource reservation table;

5) Inserting a hardware resource which is occupied by an instruction C from the current instruction execution period cycle3, and adjusting the current instruction execution period to be cycle4 because resource conflict exists between the resource group 1 corresponding to the instruction C and the hardware resources in the 2 second resource reservation tables from cycle 3; reinserting the hardware resources occupied by the instruction C from the current instruction execution cycle4, wherein the resource group 1 corresponding to the instruction C still has resource conflict with the hardware resources in the 1 st second resource reservation table from cycle4, but does not have resource conflict with the 2 nd second resource reservation table, so the 1 st second resource reservation table is determined as a conflict reservation table and is deleted; the hardware resources occupied by the instruction C are inserted into the 2 second resource reservation tables from the current instruction execution cycle4, the hardware resources 0b are occupied in cycle5 (000010), the hardware resources 0C are occupied in cycle6 (000100), and the hardware resources 0C are occupied in cycle7 (000100), so that an updated reservation table is obtained.

In the above-mentioned instruction resource conflict detection process, since the mechanism of multiple reservation tables can be introduced for inserting the instruction a in step 4, all possible resource occupation schemes are reserved, and based on this, when the hardware resource required to be occupied by the instruction C is inserted in step 5, the scheme of completing the instruction a in the resource group 2 is reserved, so that the pause of 1 cycle can be reduced, and compared with the resource conflict detection mode of a single reservation table shown in fig. 1, the cycle pause can be reduced, and the instruction scheduling efficiency is improved.

Referring to fig. 14 schematically, fig. 14 is a performance comparison table provided by an exemplary embodiment of the present application, as shown in fig. 14, a common operators such as operator 1 to operator 9 are adopted, a single Zhang Yuliu table conflict detection mode is adopted in the instruction scheduling started by the AI compiler, and the performance is different from that brought by the conflict detection mode of the instruction resource provided by the embodiment of the present application, and as can be seen from the performance comparison table 1400, the conflict detection method of the instruction resource provided by the embodiment of the present application can reduce the execution cycle of the instruction consumed in the actual application process, and improve the instruction scheduling efficiency.

In some embodiments, the conflict detection of instruction resources provided in the embodiments of the present application includes an analysis process for a resource description table, where a time sequence occupation table in which resource occupation conditions are recorded is obtained by analyzing the resource description table, and the analysis process is that is, step 1110 described above, for a machine, it is necessary to analyze each piece of hardware resource information of each compiled instruction in the resource description table until the analysis is completed. Referring to fig. 15, fig. 15 is a schematic diagram of an analysis flow of a resource description table according to an exemplary embodiment of the present application, where the method may be executed by a terminal, may be executed by a server, or may be executed by both the terminal and the server, and the embodiment of the present application is described by taking the method executed by the terminal as an example, as shown in fig. 15, and the analysis process for the resource description table includes the following steps:

At step 1510, the hardware resource information is read.

In some embodiments, for the ith compiled instruction, hardware description information corresponding to the ith compiled instruction is obtained from the resource description table.

In step 1520, a timing occupancy table corresponding to the instruction is created.

Illustratively, an empty table is newly built for the instruction a as a timing occupancy table corresponding to the instruction a.

Step 1530, it is determined whether the hardware resources of the compiled instruction are resolved.

Optionally, in response to the analysis of the hardware resource information acquired in step 1520, ending the analysis process; alternatively, in response to the hardware resource information acquired in step 1520 not being parsed, step 1540 is performed.

In step 1540, the resource occupancy information is parsed.

In some embodiments, resolving the resource occupancy information includes analyzing a binary identification corresponding to a hardware resource occupied by the instruction, an instruction execution period occupied by the hardware resource, a time interval between the hardware resource and a next hardware resource, and the like.

And step 1550, updating the occupation situation into the time sequence occupation table.

For illustration, please refer to fig. 12, the timing occupation table 1210 includes occupation of the instruction execution cycle by the resource group 1 corresponding to the instruction a.

Step 1560, determining if the segmented word exists.

Optionally, in response to the presence of the segmented word, performing step 1520; alternatively, step 1530 is performed in response to the absence of the segmentation word.

For a schematic illustration, taking the resource analysis of the resource description table 400 shown in fig. 4 as an example, please refer to fig. 16, fig. 16 is a schematic diagram of a time sequence occupation table provided by an exemplary embodiment of the present application, and as shown in fig. 16, in response to the analysis of the resource description table, the time sequence occupation table 1610 corresponding to the instruction a resource group 1, the time sequence occupation table 1620 corresponding to the instruction a resource group 2, the time sequence occupation table 1630 corresponding to the instruction B, and the time sequence occupation table 1640 corresponding to the instruction C are obtained.

In some embodiments, the resource reservation table is stored in an array form. Illustratively, an example of storing a resource reservation table in an array manner is described, in the process of detecting a conflict of instruction resources provided in the embodiment of the present application, the array storing the resource reservation table is required to be updated based on the conflict situation of the resources to update the resource reservation table, so that after the conflict detection is completed, a resource reservation table for recording the occupation situation of hardware resources of a plurality of compiling instructions is obtained, the plurality of compiling instructions are executed according to the resource reservation table and occupy corresponding hardware resources, and no resource conflict situation exists, please refer to fig. 17, fig. 17 is a schematic diagram of a resource conflict detection flow provided in an exemplary embodiment of the present application, the method may be executed by a terminal, may also be executed by a server, and may also be executed by a terminal and a server together.

In step 1701, a first array storing a resource reservation table is initialized, and the current instruction execution period is assigned to 1.

In some embodiments, a first array is created for storing the resource reservation table, and initialized to a null array, initializing the current instruction execution cycle to cycle 1.

Step 1702, determine whether a target instruction exists.

In some embodiments, the target instruction refers to a compiled instruction that requires conflict detection.

Optionally, in response to the presence of the target instruction, performing step 1703; alternatively, in response to the absence of the target instruction, the conflict detection process of the instruction resource is ended.

Step 1703, obtaining hardware resource information corresponding to the compiling instruction and creating a corresponding second array.

In some embodiments, the second set is used to store the resource reservation table updated during the collision detection.

In some embodiments, the hardware resource information corresponding to the compiled instruction is obtained from a resource description table as shown in fig. 4.

Step 1704, determining whether there is a resource reservation table having no resource conflict with the resource group of the compiling instruction.

In some embodiments, having a resource reservation table that does not have a resource conflict with the resource group of the compiled instruction means that the resource reservation table exists such that the resource group of the compiled instruction meets the resource occupancy condition.

For illustration, please refer to fig. 7, in the writing process of the hardware resource information of the instruction C in the second resource reservation table 711 and the second resource reservation table 712, the second resource reservation table 712 exists so that the hardware resource corresponding to the instruction C meets the resource occupation condition.

Optionally, in response to there being a resource reservation table that does not have a resource conflict with the resource group of the compilation instruction, performing step 1706; alternatively, step 1705 is performed in response to there being no resource reservation table that has no resource conflict with the resource group of the compilation instruction.

In step 1705, the current instruction execution cycle is assigned a value of 1.

In some embodiments, a current instruction execution cycle value plus 1 is used to indicate an adjustment to the current instruction execution cycle, determining the next execution instruction cycle as the current execution instruction cycle.

Step 1706, determining whether there is a resource reservation table for which collision detection is not performed.

In some embodiments, there are multiple resource reservation tables with which each resource group of each compilation instruction needs to be collision detected.

Optionally, in response to the existence of a resource reservation table for which collision detection is not performed, performing step 1708; alternatively, step 1707 is performed in response to there being no resource reservation table for which collision detection is not performed.

Step 1707, the second array is overlaid on the first array.

In some embodiments, overlaying the second array over the first array refers to updating the stored information of the resource reservation table.

Step 1708, it is determined whether there are resource groups for which collision detection has not been performed.

In some embodiments, the compilation instruction corresponds to multiple resource groups, each of which requires conflict detection.

Optionally, in response to the presence of a resource group for which collision detection is not performed, performing step 1709; alternatively, step 1706 is performed in response to there being no resource group for which collision detection is not performed.

Step 1709, creating a resource reservation table based on the original resource reservation table.

In some embodiments, the resource reservation table coincides with the resource occupancy in the original resource reservation table.

Step 1710, it is determined whether there is a resource conflict between the resource reservation table and the resource group.

Optionally, in response to the resource reservation table having a resource conflict with the resource group, performing step 1711; alternatively, step 1712 is performed in response to the resource reservation table not having a resource conflict with the resource group.

Step 1711, discard the resource reservation table.

In some embodiments, discarding the resource reservation table refers to deleting the resource reservation table.

Step 1712, reserve resource reservation table and update the resource occupancy information corresponding to the resource group to the resource reservation table.

For illustration, please refer to fig. 7, in response to the hardware resource information of the instruction C having no resource conflict with the second resource reservation table 712, the hardware resource information of the instruction C is written into the second reservation table 712 to obtain the resource reservation table 720.

Step 1713, storing the resource reservation table in the second array.

In some embodiments, the second set is used to store data content respectively corresponding to the plurality of resource reservation tables.

Fig. 18 is a block diagram of a device for detecting collision of instruction resources according to an exemplary embodiment of the present application, and as shown in fig. 18, the device includes the following parts:

an obtaining module 1810, configured to obtain a resource description table, where the resource description table includes a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions, where the hardware resource information includes at least one set of hardware resources that can be used to complete the compiling instructions;

a processing module 1820, configured to create a first resource reservation table, where the first resource reservation table is configured to record a hardware resource occupation situation of the plurality of compiling instructions;

the processing module 1820 is further configured to, in response to a writing process of hardware resource information of the plurality of compiling instructions in the first resource reservation table, write resource occupation information corresponding to each of the plurality of groups of hardware resources into the first resource reservation table in response to a fact that a plurality of groups of hardware resources exist for an ith compiling instruction, where i is a positive integer, and the resource occupation condition is used to indicate that hardware resources required for completing the compiling instructions are unoccupied;

The processing module 1820 is further configured to, for a writing process of hardware resource information corresponding to the i+k compiling instruction in a plurality of second resource reservation tables, delete, in response to a conflict reservation table existing in the plurality of second resource reservation tables, the conflict reservation table from the plurality of second resource reservation tables, where the conflict reservation table has a resource conflict with the hardware resource information corresponding to the i+k compiling instruction, and k is a positive integer.

Referring to fig. 19, fig. 19 is a block diagram of a device module for detecting collision of instruction resources according to an exemplary embodiment of the present application, as shown in fig. 19, in some embodiments, the processing module 1820 includes:

a first processing unit 1821, configured to respond to the mth group of hardware resources for the ith compiling instruction conforming to the resource occupation condition, write resource occupation information corresponding to the mth group of hardware resources into the first resource reservation table, and obtain an nth second resource reservation table corresponding to the mth group of hardware resources, where m and n are positive integers;

the second processing unit 1822 is configured to obtain r second resource reservation tables in response to the writing of the hardware resource information for the ith compiling instruction, where r is used to indicate the number of the multiple sets of hardware resources.

In some embodiments, the ith compiled instruction is executed from a jth instruction execution cycle, j being a positive integer;

the first processing unit 1821 is configured to write, in response to the mth group of hardware resources for the ith compiled instruction conforming to the resource occupation condition corresponding to the jth instruction execution cycle, resource occupation information corresponding to the mth group of hardware resources from the jth instruction execution cycle to the first resource reservation table, to obtain the nth second resource reservation table.

In some embodiments, the processing module comprises:

a third processing unit 1823, configured to determine, in response to a resource conflict between the i+kth compiling instruction and the p-th second resource reservation table, the p-th second resource reservation table as the conflict reservation table, to obtain q conflict reservation tables, where p and q are positive integers, and q < r;

a fourth processing unit 1824 is configured to delete the q collision reservation tables from the r second resource reservation tables.

In some embodiments, the ith compiled instruction is executed from a jth instruction execution cycle, the ith+kth compiled instruction is executed from a jth+l instruction execution cycle, wherein the jth instruction cycle through the jth+l instruction execution cycle are used to execute the ith compiled instruction through the ith+k-1 compiled instruction, and l is a positive integer;

The third processing unit 1823 is configured to determine, in response to the i+kth compiled instruction having a resource conflict with the p-th second resource reservation table from the j+l instruction execution cycle, the p-th second resource reservation table as the conflict reservation table, and obtain the q conflict reservation tables.

In some embodiments, the processing module 1820 is further configured to adjust, for a writing process of hardware resource information corresponding to the i+k th compiling instruction in the r second resource reservation tables, execution of the i+k th compiling instruction from a j+l+t instruction execution period in response to r conflict reservation tables existing in the r second resource reservation tables, where t is a positive integer;

the processing module 1820 is further configured to, for a writing process of hardware resource information corresponding to the i+k th compiling instruction in the r second resource reservation tables, respond to the fact that the hardware resource corresponding to the i+k th compiling instruction meets the resource occupation condition corresponding to the j+l+t instruction execution period, write the resource occupation information corresponding to the hardware resource into the r second resource reservation tables, and obtain r third resource reservation tables;

and the j-th instruction cycle to the j+l+t-th instruction execution cycle are used for executing the i-th compiled instruction to the i+k-1-th compiled instruction.

In some embodiments, the processing module 1820 is further configured to parse the resource description table to obtain a plurality of timing occupancy tables, where the timing occupancy tables are used to indicate occupancy of instruction execution cycles by the compiled instruction during execution.

In some embodiments, the processing module 1820 is further configured to:

reading a first compiling instruction from the resource description table and creating a time sequence occupation table corresponding to the first compiling instruction;

reading resource occupation information corresponding to an a-th hardware resource corresponding to the first compiling instruction from the resource description table, and analyzing the resource occupation information to obtain the occupation condition of the a-th hardware resource corresponding to the first compiling instruction on the instruction execution period in an a-th execution stage, wherein a is a positive integer;

updating the occupation condition into the time sequence occupation table;

and aiming at the resource analysis process of the first compiling instruction, in response to the fact that a segmentation word is read and the first compiling instruction corresponds to unresolved hardware resources, creating a time sequence occupation table corresponding to the first compiling instruction, updating occupation conditions based on the resource description table until the hardware resources of the first compiling instruction are analyzed, and obtaining a plurality of time sequence occupation tables corresponding to the first compiling instruction, wherein the segmentation word is used for distinguishing an a-th hardware resource corresponding to the first compiling instruction from an a+1th hardware resource.

In some embodiments, the processing module 1820 is further configured to, for the resource parsing process of the compiled instruction, in response to reading the segmentation word and completing the parsing of the hardware resource corresponding to the first compiled instruction, create a timing occupation table corresponding to the second compiled instruction and update the occupation condition based on the resource description table until the plurality of compiled instructions in the resource description table are completed, obtain the timing occupation tables corresponding to the plurality of compiled instructions, respectively, where the segmentation word is used to distinguish the first compiled instruction from the second compiled instruction.

In some embodiments, the processing module 1820 is further configured to:

writing the resource occupation information corresponding to the hardware resources of the compiling instructions into the first resource reservation table from the current instruction execution period in response to the fact that the hardware resources of the compiling instructions meet the resource occupation conditions corresponding to the current instruction execution period in the writing process of the hardware resource information of the compiling instructions in the first resource reservation table, so as to obtain a fourth resource reservation table; or,

and in response to the resource conflict between the current instruction execution period and the first resource reservation table of the hardware resource information of the plurality of compiling instructions in the writing process of the first resource reservation table, updating the next instruction execution period of the current instruction execution period to the current instruction execution period until the hardware resource of the compiling instructions accords with the resource occupation condition corresponding to the current instruction execution period, and writing the resource occupation information corresponding to the hardware resource into the first resource reservation table from the current instruction execution period to obtain a fifth resource reservation table.

In some embodiments, the resource occupation condition includes a hardware resource corresponding to the compiled instruction, and from an instruction execution cycle of starting to execute the compiled instruction, there is no resource conflict with the first reservation table.

In summary, the device provided in the embodiment of the present application acquires a resource description table, where the resource description table includes a plurality of compiling instructions and hardware resource information corresponding to the compiling instructions, the hardware resource information includes at least one set of hardware resources that can be used to complete the compiling instructions, creates a first resource reservation table, where the first resource reservation table is used to record a hardware resource occupation situation of the plurality of compiling instructions, for a writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, writes, in response to a condition that a plurality of sets of hardware resource occupation conditions exist for an ith compiling instruction, resource occupation information corresponding to the plurality of sets of hardware resources respectively into the first resource reservation table, to obtain second resource reservation tables corresponding to the plurality of sets of hardware resources, where i is a positive integer, where the resource occupation conditions are used to indicate that hardware resources required to complete the compiling instructions are not occupied, and, for a writing process of the hardware resource information corresponding to the ith+k compiling instructions in the plurality of second resource reservation tables, and, in response to a writing process of the reservation table in the plurality of second resource reservation tables, deletes the conflict from the plurality of second resource reservation tables, where the conflict and the k+th reserved resource are the hardware resource reservation table is an integer. By maintaining a plurality of reserved tables for compiled instructions with a plurality of groups of hardware resources, more selectable opportunities exist in instruction scheduling when available instructions are analyzed, different resource scenes can be compared more comprehensively in the conflict detection process of the instruction resources, optimal results are selected from a plurality of resources, and scheduling efficiency of instruction scheduling is improved.

It should be noted that: in the device for detecting collision of instruction resources provided in the above embodiment, only the division of the above functional modules is used as an example, in practical application, the above functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above.

Fig. 20 shows a block diagram of a terminal 2000 according to an exemplary embodiment of the present application. The terminal 2000 may be: smart phones, tablet computers, MP3 players, MP4 players, notebook computers or desktop computers. Terminal 2000 may also be referred to by other names of user devices, portable terminals, laptop terminals, desktop terminals, etc.

In general, the terminal 2000 includes: a processor 2001 and a memory 2002.

Processor 2001 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so forth. The processor 2001 may be implemented in hardware in at least one of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). Processor 2001 may also include a main processor, which is a processor for processing data in an awake state, also called a central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 2001 may integrate an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content required to be displayed by the display screen. In some embodiments, the processor 2001 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.

Memory 2002 may include one or more computer-readable storage media, which may be non-transitory. Memory 2002 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in memory 2002 is used to store at least one instruction for execution by processor 2001 to implement the conflict detection method of instruction resources provided by the method embodiments of the present application.

In some embodiments, terminal 2000 may further include other components, and those skilled in the art will appreciate that the structure illustrated in fig. 20 is not limiting of terminal 2000 and may include more or less components than illustrated, or may combine certain components, or may employ a different arrangement of components.

The embodiment of the application also provides a computer device which can be implemented as a terminal or a server as shown in fig. 1. The computer device includes a processor and a memory, where at least one instruction, at least one program, a code set, or an instruction set is stored, where at least one instruction, at least one program, a code set, or an instruction set is loaded and executed by the processor to implement the method for detecting a conflict of instruction resources provided by the above method embodiments.

Embodiments of the present application also provide a computer readable storage medium having at least one instruction, at least one program, a code set, or an instruction set stored thereon, where the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the method for detecting a conflict of instruction resources provided by the above method embodiments.

Embodiments of the present application also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the conflict detection method of the instruction resources provided by the above-mentioned method embodiments.

Alternatively, the computer-readable storage medium may include: read Only Memory (ROM), random access Memory (Random Access Memory, RAM), solid state disk (Solid State Drives, SSD), or optical disk. The random access memory may include resistive random access memory (Resistance Random Access Memory, reRAM) and dynamic random access memory (Dynamic Random Access Memory, DRAM), among others. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims

1. A method for collision detection of instruction resources, the method comprising:

writing the resource occupation information corresponding to the mth group of hardware resources into the first resource reservation table in response to the mth group of hardware resources corresponding to the ith compiling instruction meeting the resource occupation condition aiming at the writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table to obtain an nth second resource reservation table corresponding to the mth group of hardware resources, wherein m and n are positive integers; responding to the completion of writing of the hardware resource information aiming at the ith compiling instruction, obtaining r second resource reservation tables, wherein r is used for indicating the number of the plurality of groups of hardware resources, i is a positive integer, and the resource occupation condition is used for indicating that the hardware resources required for completing the compiling instruction are unoccupied;

Aiming at the writing process of hardware resource information corresponding to the (i+k) th compiling instruction in a plurality of second resource reservation tables, responding to the resource conflict between the (i+k) th compiling instruction and the (p) th second resource reservation table, determining the (p) th second resource reservation table as the conflict reservation table to obtain q conflict reservation tables, wherein p and q are positive integers, and q < r; deleting the q conflict reservation tables from the r second resource reservation tables, wherein the conflict reservation tables have resource conflict with hardware resource information corresponding to the (i+k) th compiling instruction, and k is a positive integer; the ith compiling instruction is executed from a jth instruction execution period, the ith+k compiling instruction is executed from a jth+l instruction execution period, the jth instruction period to the jth+l instruction execution period are used for executing the ith compiling instruction to the ith+k-1 compiling instruction, and j and l are positive integers; and determining the p second resource reservation table as the conflict reservation table by responding to the resource conflict between the i+k-th compiling instruction and the p second resource reservation table from the j+l-th instruction execution period, so as to obtain the q conflict reservation tables.

2. The method according to claim 1, wherein the writing the resource occupancy information corresponding to the mth group of hardware resources into the first resource reservation table in response to the mth group of hardware resources for the ith compiling instruction meeting a resource occupancy condition, to obtain the nth second resource reservation table corresponding to the mth group of hardware resources, includes:

and in response to the fact that the mth group of hardware resources aiming at the ith compiling instruction accords with the resource occupation condition corresponding to the jth instruction execution period, writing the resource occupation information corresponding to the mth group of hardware resources into the first resource reservation table from the jth instruction execution period to obtain the nth second resource reservation table.

3. The method according to claim 1, wherein the method further comprises:

aiming at the writing process of hardware resource information corresponding to the ith+kth compiling instruction in the r second resource reservation tables, adjusting the ith+kth compiling instruction to be executed from the j+l+t instruction execution period in response to the existence of r conflict reservation tables in the r second resource reservation tables, wherein t is a positive integer;

aiming at the writing process of hardware resource information corresponding to the ith+k compiling instruction in the r second resource reservation tables, responding to the condition that the hardware resource corresponding to the ith+k compiling instruction accords with the resource occupation condition corresponding to the j+l+t instruction execution period, and writing the resource occupation information corresponding to the hardware resource into the r second resource reservation tables to obtain r third resource reservation tables;

4. A method according to any one of claims 1 to 3, further comprising, after said obtaining the resource description table:

analyzing the resource description table to obtain a plurality of time sequence occupation tables, wherein the time sequence occupation tables are used for indicating occupation conditions of the compiling instruction on instruction execution cycles in the execution process.

5. The method of claim 4, wherein the compiled instruction corresponds to a plurality of execution phases, and the at least one set of hardware resources includes hardware resources corresponding to the plurality of execution phases, respectively;

the analyzing the resource description table to obtain a plurality of time sequence occupation tables comprises the following steps:

Updating the occupation condition into the time sequence occupation table;

6. The method of claim 5, wherein the method further comprises:

and aiming at the resource analysis process of the compiling instruction, in response to the fact that the segmentation word is read and the hardware resource corresponding to the first compiling instruction is analyzed, creating a time sequence occupation table corresponding to the second compiling instruction, updating the occupation condition based on the resource description table until the plurality of compiling instructions in the resource description table are analyzed, and obtaining the time sequence occupation tables corresponding to the plurality of compiling instructions respectively, wherein the segmentation word is used for distinguishing the first compiling instruction from the second compiling instruction.

7. A method according to any one of claims 1 to 3, wherein the method further comprises:

8. A method according to any one of claims 1 to 3, wherein the resource occupation condition includes a hardware resource corresponding to the compiled instruction, and there is no resource conflict with the first reservation table since an instruction execution cycle in which the compiled instruction starts to be executed.

9. A collision detection apparatus for instruction resources, the apparatus comprising:

the processing module is further configured to, in response to the fact that an mth group of hardware resources for an ith compiling instruction meets a resource occupation condition, write resource occupation information corresponding to the mth group of hardware resources into the first resource reservation table to obtain an nth second resource reservation table corresponding to the mth group of hardware resources in a writing process of the hardware resource information of the plurality of compiling instructions in the first resource reservation table, where m and n are positive integers; responding to the completion of writing of the hardware resource information aiming at the ith compiling instruction, obtaining r second resource reservation tables, wherein r is used for indicating the number of the plurality of groups of hardware resources, i is a positive integer, and the resource occupation condition is used for indicating that the hardware resources required for completing the compiling instruction are unoccupied;

The processing module is further configured to determine, for a writing process of hardware resource information corresponding to an i+k-th compiling instruction in a plurality of second resource reservation tables, the p-th second resource reservation table as the conflict reservation table in response to resource conflict between the i+k-th compiling instruction and the p-th second resource reservation table, to obtain q conflict reservation tables, where p and q are positive integers, and q < r; deleting the q conflict reservation tables from the r second resource reservation tables, wherein the conflict reservation tables have resource conflict with hardware resource information corresponding to the (i+k) th compiling instruction, and k is a positive integer; the ith compiling instruction is executed from a jth instruction execution period, the ith+k compiling instruction is executed from a jth+l instruction execution period, the jth instruction period to the jth+l instruction execution period are used for executing the ith compiling instruction to the ith+k-1 compiling instruction, and j and l are positive integers; and determining the p second resource reservation table as the conflict reservation table by responding to the resource conflict between the i+k-th compiling instruction and the p second resource reservation table from the j+l-th instruction execution period, so as to obtain the q conflict reservation tables.

10. A computer device comprising a processor and a memory, wherein the memory has stored therein at least one program that is loaded and executed by the processor to implement the method of collision detection of instruction resources of any of claims 1 to 8.

11. A computer readable storage medium having stored therein at least one program loaded and executed by a processor to implement the method of collision detection of instruction resources of any of claims 1 to 8.