CN116893836A - Method, system, equipment and medium for realizing non-inductive upgrade of CPU microcode - Google Patents
Method, system, equipment and medium for realizing non-inductive upgrade of CPU microcode Download PDFInfo
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Abstract
The application belongs to the technical field of servers, and particularly provides a method, a system, equipment and a medium for realizing the noninductive upgrading of CPU microcode, wherein the method comprises the following steps: the BMC loads a microcode upgrading file; after loading is successful, the BMC receives the upgrade trigger signal and then controls the embedded microcontroller to enter a recovery mode; the embedded microcontroller is an embedded microcontroller positioned in the south bridge chip; the BMC obtains the control right of the south bridge peripheral interface and writes the microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating; after the updating is finished, the BMC gives up the control right of the south bridge peripheral interface and triggers a hot reset to force reload the microcode upgrading file from the flash memory connected with the south bridge; after the success of the microcode upgrade is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal. The method realizes the noninductive upgrading of the microcode of the CPU processor and saves a great deal of manual hot restarting time.
Description
Technical Field
The application relates to the technical field of servers, in particular to a method, a system, equipment and a medium for realizing the noninductive upgrading of CPU microcode.
Background
The CPU Microcode is a series of numbers used for compatibility and identification of various types of CPU, the updating of the BIOS of the main board is to update the numbers of the compatible processor in the main board, so that the main board and the CPU can be well matched for use, the CPU Microcode can also be understood as a patch interface reserved on CPU hardware, when the CPU is internally defective, part of the defects of the CPU can be repaired by loading Microcode (Microcode), the CPU Microcode can be used as a supplementary description of a new CPU, and the new CPU can be supported and used on the main board which is not supported originally.
The current CPU microcode upgrading method is that when an upgrading instruction is received, the CPU microcode to be upgraded is read from a preset position, the CPU microcode to be upgraded is written into a FALSH chip obtained by BIOS, a user sends a hot restarting instruction, and when the system is hot restarted, the newly written CPU microcode is loaded, so that the quick upgrading of the CPU microcode is completed.
In the current application scene of the server, the CPU (central processing unit ) microcode is required to be upgraded, after the upgrade microcode is written, a hot restarting instruction is required to be sent according to a user, the newly written CPU microcode is loaded when the system is restarted, the quick upgrade of the CPU microcode is completed, and the service continuity of the user and the service efficiency and the use stability of the server are influenced when the system is restarted. Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
Aiming at the problems that after updating microcode is refreshed, a hot restarting instruction is required to be sent according to a user, and a newly written CPU microcode is loaded when the system is restarted, so that the quick updating of the CPU microcode is completed, the service continuity of the user is affected, and the working efficiency and the use stability of a server are affected when the system is restarted, the application provides a method, a system, equipment and a medium for realizing the noninductive updating of the CPU microcode.
In a first aspect, the present application provides a method for implementing a CPU microcode noninductive upgrade, including the steps of:
the BMC loads a microcode upgrading file;
after loading is successful, the BMC receives the upgrade trigger signal and then controls the embedded microcontroller to enter a recovery mode; the embedded microcontroller is an embedded microcontroller positioned in the south bridge chip;
the BMC obtains the control right of the south bridge peripheral interface and writes the microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating;
after the updating is finished, the BMC gives up the control right of the south bridge peripheral interface and triggers a hot reset to force reload the microcode upgrading file from the flash memory connected with the south bridge;
after the success of the microcode upgrade is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal.
As a further limitation of the technical scheme of the application, the step of loading the microcode upgrade file by the BMC comprises the following steps:
after receiving the upgrade request, the BMC loads a microcode upgrade file through a BMC interface;
acquiring a digital signature of the microcode upgrade file;
performing signature verification on the obtained digital signature;
after verification is passed, the microcode upgrade file is loaded successfully;
and if the verification is not passed, outputting loading failure prompt information at the BMC interface.
As a further limitation of the technical scheme of the present application, after successful loading, the step of controlling the embedded microcontroller to enter the recovery mode after the BMC receives the upgrade trigger signal includes:
after successful loading, the BMC judges whether an upgrade trigger signal is received or not;
if not, executing the steps of: the BMC judges whether an upgrade trigger signal is received or not and continues to receive the trigger signal;
if yes, the BMC control pulls up the level signal of the GPIO pin of the embedded microcontroller to enable the embedded microcontroller to enter a recovery mode;
the BMC judges whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not;
if the feedback information is received, confirming that the embedded microcontroller enters a recovery mode;
checking whether the host enters an operating system;
if yes, executing the steps: the BMC obtains the control right of the south bridge peripheral interface and writes microcode into a flash memory connected with the south bridge peripheral interface for updating;
if not, continuing to execute the steps of: checking whether the machine enters an operating system;
if the feedback information is not received, the output mode enters an abnormal prompt message;
as a further limitation of the technical scheme of the application, the steps of the BMC obtaining the control right of the south bridge peripheral interface and writing the microcode upgrading file into the flash memory connected with the south bridge peripheral interface for updating comprise the following steps:
the BMC obtains the control right of the south bridge peripheral interface;
writing a microcode upgrading file into a flash memory connected with the south bridge peripheral interface through a complex logic programming unit;
verifying and updating the written microcode upgrading file;
acquiring an address of a south bridge peripheral interface connected with a flash memory;
judging whether the address exists or not;
if yes, the microcode is updated successfully, and the steps are executed: the BMC gives up the control right to the south bridge peripheral interface, triggers a hot reset and forces the reload of the microcode upgrade file from the flash memory connected with the south bridge;
if not, outputting a microcode update failure prompt message at the BMC interface.
As a further limitation of the technical scheme of the application, the BMC gives up the control right to the south bridge peripheral interface and triggers a hot reset, and the step of forcibly reloading the microcode upgrade file from the flash memory connected with the south bridge comprises the following steps:
BMC gives up control right to the south bridge peripheral interface;
meanwhile, the quick hot reset of the host operating system is triggered to force the microcode upgrade file to be reloaded from the flash memory connected with the south bridge.
As a further limitation of the technical scheme of the application, the step of triggering the rapid hot reset of the host operating system to force reloading the microcode upgrade file from the south bridge connected flash memory comprises the following steps:
checking whether the upgrade of the CPU microcode under the host operating system is successful;
if yes, executing the steps: the BMC outputs a control signal to enable the embedded microcontroller to be normal;
if not, outputting prompt information of failure in microcode upgrading under the BMC interface.
As a further limitation of the technical scheme of the application, the step of enabling the BMC to output a control signal to enable the embedded microcontroller to recover to be normal after the success of the microcode upgrade is confirmed comprises the following steps:
after the success of the microcode upgrade is confirmed, the BMC control pulls down the level signal of the GPIO pin of the embedded microcontroller, so that the embedded microcontroller is recovered to be normal.
In a second aspect, the present application further provides a system for implementing the non-inductive upgrade of the CPU microcode, which includes a host with an operating system, wherein a BMC is provided on a motherboard of the host, the BMC is connected with a south bridge chip, and the south bridge chip is connected with the CPU; the south bridge chip is also connected with a flash memory through a south bridge peripheral interface; an embedded microcontroller is arranged in the south bridge chip;
BMC, is used for loading the microcode upgrade file; the embedded microcontroller is controlled to enter a recovery mode after the loading is successful and the upgrading trigger signal is received; obtaining control right of the south bridge peripheral interface and writing microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating; after the updating is finished, the BMC gives up the control right to the south bridge peripheral interface, and triggers the quick hot reset of the host operating system to force the reload of the microcode upgrading file from the flash memory connected with the south bridge; after the success of the upgrade of the CPU microcode is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal.
As a further limitation of the technical scheme of the application, the BMC is configured to load a microcode upgrade file through a BMC interface after receiving an upgrade request; acquiring a digital signature of the microcode upgrade file; performing signature verification on the obtained digital signature; after verification is passed, the microcode upgrade file is loaded successfully; and if the verification is not passed, outputting loading failure prompt information at the BMC interface.
As a further limitation of the technical scheme of the application, the BMC is further configured to determine whether an upgrade trigger signal is received after successful loading; if not, judging whether an upgrade trigger signal is received, and continuing to receive the trigger signal; if so, controlling to pull up the level signal of the GPIO pin of the embedded microcontroller so as to enable the embedded microcontroller to enter a recovery mode; judging whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not; if the feedback information is received, confirming that the embedded microcontroller enters a recovery mode; checking whether the host enters an operating system; if yes, obtaining the control right of the south bridge peripheral interface and writing microcode into a flash memory connected with the south bridge peripheral interface for updating; if not, checking whether the machine enters an operating system; if the feedback information is not received, the output mode enters the abnormal prompt information.
As a further limitation of the technical scheme of the application, the BMC is connected with a complex logic programming unit; the BMC is used for obtaining the control right of the south bridge peripheral interface; writing a microcode upgrading file into a flash memory connected with the south bridge peripheral interface through a complex logic programming unit; acquiring an address of a south bridge peripheral interface connected with a flash memory; judging whether the address exists or not; if yes, the microcode is updated successfully, if not, a microcode updating failure prompt message is output at the BMC interface.
As a further limitation of the technical scheme of the application, the BMC is configured to relinquish control rights to the south bridge peripheral interface; meanwhile, triggering the quick hot reset of the host operating system to force the reload of the microcode upgrade file from the flash memory connected with the south bridge, and after confirming that the microcode upgrade is successful, the BMC controls the level signal of the GPIO pin of the embedded microcontroller to be pulled down so as to enable the embedded microcontroller to be restored to normal.
In a third aspect, the present application further provides an electronic device, where the electronic device includes: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores computer program instructions executable by the at least one processor to enable the at least one processor to perform the method of implementing a CPU microcode sensorless upgrade as described in the first aspect.
In a fourth aspect, the present disclosure further provides a non-transitory computer readable storage medium, where the non-transitory computer readable storage medium stores computer instructions, where the computer instructions cause the computer to execute the method for implementing the CPU microcode non-inductive upgrade according to the first aspect.
From the above technical scheme, the application has the following advantages: the BMC controls the serial peripheral interface of the south bridge chip and triggers the hot reset to realize the noninductive upgrading of the microcode of the CPU processor, save a great deal of manual hot restarting time, ensure the service continuity of users and effectively improve the working efficiency of the users and the use stability of the server.
In addition, the application has reliable design principle, simple structure and very wide application prospect.
It can be seen that the present application has outstanding substantial features and significant advances over the prior art, as well as its practical advantages.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic flow chart of a method of a first embodiment of the application.
Fig. 2 is a schematic flow chart of a method of a second embodiment of the application.
Fig. 3 is a schematic flow chart of a method of a third embodiment of the application.
Fig. 4 is a schematic block diagram of a system of one embodiment of the present application.
Fig. 5 is a schematic connection block diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
In the embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application. In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application. The application provides a method and a system for realizing the noninductive upgrading of CPU microcode. And controlling the ME to enter a recovery mode through the BMC, then obtaining ownership of the PCH SPI, and writing microcode into a proper position in the PCH SPI so as to temporarily store on the PCH SPI. After the microcode is written into the SPI of the PCH, the BMC gives up control over the SPI and triggers a hot reset to force the microcode to be reloaded from the flash. After the microcode is successfully upgraded, the BMC triggers the me reset to enable the me to be restored to be normal, the whole process equipment does not need to perform any operation, and the CPU processor microcode is successfully upgraded without sense.
When it needs to be described, the BMC and PCH (south bridge) chips are management units on the motherboard, and the Flash is a Flash memory connected to the BMC or PCH chip, and the Flash memory stores buffer data. The ME is an embedded microcontroller located in the PCH chipset, and the ME is the management system for the PCH. Fig. 1 is a flowchart of a method for implementing a CPU microcode non-inductive upgrade according to an embodiment of the present application, where the method includes the following steps:
step 11: the BMC loads a microcode upgrading file;
step 12: after loading is successful, the BMC receives the upgrade trigger signal and then controls the embedded microcontroller to enter a recovery mode; the embedded microcontroller is an embedded microcontroller positioned in the south bridge chip;
step 13: the BMC obtains the control right of the south bridge peripheral interface and writes the microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating;
step 14: after the updating is finished, the BMC gives up the control right of the south bridge peripheral interface and triggers a hot reset to force reload the microcode upgrading file from the flash memory connected with the south bridge;
step 15: after the success of the microcode upgrade is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal.
And controlling the ME to enter a recovery mode through the BMC, then obtaining ownership of the PCH SPI interface, and writing microcode into a flash memory connected with the PCH SPI interface so as to temporarily store on the PCH SPI. After the microcode is written into the PCH SPI, the BMC gives up control of the PCH SPI interface and triggers a hot reset to force the reload of the microcode from the PCH flash memory. After the microcode is successfully upgraded, the BMC triggers the ME reset to enable the ME to recover to be normal, the whole process equipment does not need to perform any operation, and the CPU processor microcode is successfully upgraded without sense.
As shown in fig. 2, a method for implementing a non-inductive upgrade of CPU microcode according to an embodiment of the present application includes the following steps:
step 21: after receiving the upgrade request, the BMC loads a microcode upgrade file through a BMC interface;
step 22: acquiring a digital signature of the microcode upgrade file;
step 23: performing signature verification on the obtained digital signature;
step 24: judging whether the verification is passed or not; if yes, go to step 26, if no, go to step 25;
step 25: outputting loading failure prompt information at a BMC interface;
step 26: the microcode upgrade file is loaded successfully; after receiving the upgrade trigger signal, the BMC controls the embedded microcontroller to enter a recovery mode; the embedded microcontroller is an embedded microcontroller positioned in the south bridge chip;
step 27: the BMC obtains the control right of the south bridge peripheral interface and writes the microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating;
step 28: after the updating is finished, the BMC gives up the control right of the south bridge peripheral interface and triggers a hot reset to force reload the microcode upgrading file from the flash memory connected with the south bridge;
step 29: after the success of the microcode upgrade is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal.
The BMC controls the PCH SPI and triggers the hot reset to realize the noninductive upgrading of the micro-code of the CPU processor, save a great deal of manual hot restart time, ensure the service continuity of the user, and effectively improve the working efficiency of the user and the use stability of the server.
As shown in fig. 3, a method for implementing a non-inductive upgrade of CPU microcode according to an embodiment of the present application includes the following steps:
step 31: after receiving the upgrade request, the BMC loads a microcode upgrade file through a BMC interface;
step 32: acquiring a digital signature of the microcode upgrade file;
step 33: performing signature verification on the obtained digital signature;
step 34: judging whether the verification is passed or not; if yes, go to step 36, if no, go to step 35;
step 35: outputting loading failure prompt information at a BMC interface;
firstly, loading a microcode upgrading file by the BMC, upgrading and loading the microcode upgrading file through the BMC interface firmware, and carrying out signature verification on the microcode upgrading file to verify that the microcode upgrading file is successfully uploaded.
Step 36: the method comprises the steps that microcode upgrade files are loaded successfully, and the BMC judges whether upgrade trigger signals are received or not;
if not, executing step 36, and continuing to receive and judge the trigger signal;
if yes, go to step 37;
after the microcode upgrade file is loaded successfully, an upgrade button on the BMC interface is effective, and the BMC executes the next operation after triggering the upgrade button.
Step 37: the BMC control pulls high the level signal of the GPIO pin of the embedded microcontroller to enable the embedded microcontroller to enter a recovery mode;
step 38: the BMC judges whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not;
if not, go to step 39;
if yes, confirming that the embedded microcontroller enters a recovery mode; step 40 is performed;
step 39: the output mode enters an abnormal prompt message;
after triggering the upgrade button, the BMC sends an instruction, the level signal of the GP10 pin for controlling the level signal of the HDA_Sd0 pin is pulled high, and the ME is enabled to enter a recovery mode, because the ME can manage and control the FW or FV area of the host in the non-recovery mode, after entering the recovery, the ME enters a recovery mode without accessing the SPI flash memory of the PCH, microcode can be normally refreshed, and after entering the recovery, the ME returns information to enable the BMC to acquire the ME state to enter the recovery mode;
step 40: checking whether the host enters an operating system;
if yes, go to step 41;
if not, go on to step 40;
step 41: the BMC obtains the control right of the south bridge peripheral interface;
step 42: writing the microcode upgrading file into the flash memory connected with the south bridge peripheral interface through the complex logic programming unit, and verifying and updating the written microcode upgrading file;
the ME enters a recovery mode, at the moment, the host enters an OS and is in a stable starting state mode, during the updating period of the microcode, the BMC needs to ensure that the safe thermal limit is kept during the updating period, otherwise, the sensor data collection is failed and normal operation is restored after the updating is completed, the ME enters the recovery mode, the BMC obtains ownership of the PCH SPI, the microcode is written into the PCH SPI address through the CPLD so as to temporarily store and verify the updating on the PCH SPI, and during the updating period, the BMC cannot record false sensor errors/warnings caused by the updating process and influence the updating process.
Step 43: acquiring an address of a south bridge peripheral interface connected with a flash memory;
step 44: judging whether the address exists or not;
if yes, the microcode is updated successfully, go to step 46;
if not, go to step 45;
step 45: and outputting microcode update failure prompt information at the BMC interface.
Step 46: BMC gives up control right to the south bridge peripheral interface; meanwhile, triggering the quick hot reset of the host operating system to force reload the microcode upgrade file from the flash memory connected with the south bridge;
the BMC gives up the control of the south bridge peripheral interface and triggers the quick hot reset of the host operating system after the microcode is successfully upgraded, and a memory is introduced to store the quick hot reset function so as to force the microcode to be reloaded from the flash of the PCH, so that the whole process server does not need any operation, and the microcode of the CPU processor is successfully upgraded without sense.
Step 47: checking whether the upgrade of the CPU microcode under the host operating system is successful;
if yes, go to step 49;
if not, go to step 48;
step 48: and outputting prompt information of failure of microcode upgrading under the BMC interface.
Step 49: the BMC control pulls the level signal of the GPIO pin of the embedded microcontroller low so that the embedded microcontroller returns to normal. That is, after the microcode is successfully upgraded, the BMC pulls the level signal of the GP10 pin for controlling the level signal of the HDA_Sd0 pin low to enable the ME to be recovered to be normal.
The BMC controls the PCH SPI and triggers the hot reset to realize the noninductive upgrading of the micro-code of the CPU processor, save a great deal of manual hot restart time, ensure the service continuity of the user, and effectively improve the working efficiency of the user and the use stability of the server.
As shown in fig. 4, the embodiment of the application further provides a system for implementing the non-inductive upgrade of the CPU microcode, which comprises a host provided with an operating system, wherein a BMC is arranged on a main board of the host, and is connected with a south bridge chip, and the south bridge chip is connected with the CPU; the south bridge chip is also connected with a flash memory through a south bridge peripheral interface; an embedded microcontroller is arranged in the south bridge chip;
BMC, is used for loading the microcode upgrade file; the embedded microcontroller is controlled to enter a recovery mode after the loading is successful and the upgrading trigger signal is received; obtaining control right of the south bridge peripheral interface and writing microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating; after the updating is finished, the BMC gives up the control right to the south bridge peripheral interface, and triggers the quick hot reset of the host operating system to force the reload of the microcode upgrading file from the flash memory connected with the south bridge; after the success of the upgrade of the CPU microcode is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal. The BMC is used for loading a microcode upgrading file through a BMC interface after receiving the upgrading request; acquiring a digital signature of the microcode upgrade file; performing signature verification on the obtained digital signature; after verification is passed, the microcode upgrade file is loaded successfully; and if the verification is not passed, outputting loading failure prompt information at the BMC interface. The BMC is also used for judging whether an upgrade trigger signal is received after the loading is successful; if not, judging whether an upgrade trigger signal is received, and continuing to receive the trigger signal; if so, controlling to pull up the level signal of the GPIO pin of the embedded microcontroller so as to enable the embedded microcontroller to enter a recovery mode; judging whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not; if the feedback information is received, confirming that the embedded microcontroller enters a recovery mode; checking whether the host enters an operating system; if yes, obtaining the control right of the south bridge peripheral interface and writing microcode into a flash memory connected with the south bridge peripheral interface for updating; if not, checking whether the machine enters an operating system; if the feedback information is not received, the output mode enters the abnormal prompt information.
The embodiment of the application also provides a system for realizing the noninductive upgrade of the CPU microcode, which comprises a host provided with an operating system, wherein a BMC is arranged on a main board of the host, the BMC is connected with a south bridge chip, and the south bridge chip is connected with the CPU; the south bridge chip is also connected with a flash memory through a south bridge peripheral interface; an embedded microcontroller is arranged in the south bridge chip; the BMC is connected with a complex logic programming unit;
BMC, is used for loading the microcode upgrade file; the embedded microcontroller is controlled to enter a recovery mode after the loading is successful and the upgrading trigger signal is received; obtaining control right of the south bridge peripheral interface and writing microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating; after the updating is finished, the BMC gives up the control right to the south bridge peripheral interface, and triggers the quick hot reset of the host operating system to force the reload of the microcode upgrading file from the flash memory connected with the south bridge; after the success of the upgrade of the CPU microcode is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal. The BMC is used for loading a microcode upgrading file through a BMC interface after receiving the upgrading request; acquiring a digital signature of the microcode upgrade file; performing signature verification on the obtained digital signature; after verification is passed, the microcode upgrade file is loaded successfully; and if the verification is not passed, outputting loading failure prompt information at the BMC interface. The BMC is also used for judging whether an upgrade trigger signal is received after the loading is successful; if not, judging whether an upgrade trigger signal is received, and continuing to receive the trigger signal; if so, controlling to pull up the level signal of the GPIO pin of the embedded microcontroller so as to enable the embedded microcontroller to enter a recovery mode; judging whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not; if the feedback information is received, confirming that the embedded microcontroller enters a recovery mode; checking whether the host enters an operating system; if yes, obtaining the control right of the south bridge peripheral interface and writing microcode into a flash memory connected with the south bridge peripheral interface for updating; if not, checking whether the machine enters an operating system; if the feedback information is not received, the output mode enters the abnormal prompt information.
The BMC is used for obtaining the control right of the south bridge peripheral interface; writing a microcode upgrading file into a flash memory connected with the south bridge peripheral interface through a complex logic programming unit; acquiring an address of a south bridge peripheral interface connected with a flash memory; judging whether the address exists or not; if yes, the microcode is updated successfully, if not, a microcode updating failure prompt message is output at the BMC interface. The control right for the south bridge peripheral interface is abandoned; meanwhile, triggering the quick hot reset of the host operating system to force the reload of the microcode upgrade file from the flash memory connected with the south bridge, and after confirming that the microcode upgrade is successful, the BMC controls the level signal of the GPIO pin of the embedded microcontroller to be pulled down so as to enable the embedded microcontroller to be restored to normal.
As shown in fig. 5, an embodiment of the present application further provides an electronic device, including: processor 510, communication interface 520, memory 530, and communication bus 540, wherein processor 510, communication interface 520, and memory 530 communicate with each other via communication bus 540. The communication bus may be used for information transfer between the electronic device and the sensor. The processor may call logic instructions in memory to perform the following method: step 31: after receiving the upgrade request, the BMC loads a microcode upgrade file through a BMC interface; step 32: acquiring a digital signature of the microcode upgrade file; step 33: performing signature verification on the obtained digital signature; step 34: judging whether the verification is passed or not; if yes, go to step 36, if no, go to step 35; step 35: outputting loading failure prompt information at a BMC interface; step 36: the microcode upgrade file is loaded successfully; the BMC judges whether an upgrade trigger signal is received or not; if not, executing step 36, and continuing to receive and judge the trigger signal; if yes, go to step 37; step 37: the BMC control pulls high the level signal of the GPIO pin of the embedded microcontroller to enable the embedded microcontroller to enter a recovery mode; step 38: the BMC judges whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not; if not, go to step 39; if yes, confirming that the embedded microcontroller enters a recovery mode; step 40 is performed; step 39: the output mode enters an abnormal prompt message; step 40: checking whether the host enters an operating system; if yes, go to step 41; if not, go on to step 40; step 41: the BMC obtains the control right of the south bridge peripheral interface; step 42: writing the microcode upgrading file into the flash memory connected with the south bridge peripheral interface through the complex logic programming unit, and verifying and updating the written microcode upgrading file; step 43: acquiring an address of a south bridge peripheral interface connected with a flash memory; step 44: judging whether the address exists or not; if yes, the microcode is updated successfully, go to step 46; if not, go to step 45; step 45: and outputting microcode update failure prompt information at the BMC interface. Step 46: BMC gives up control right to the south bridge peripheral interface; meanwhile, triggering the quick hot reset of the host operating system to force reload the microcode upgrade file from the flash memory connected with the south bridge; step 47: checking whether the upgrade of the CPU microcode under the host operating system is successful; if yes, go to step 49; if not, go to step 48; step 48: and outputting prompt information of failure of microcode upgrading under the BMC interface. Step 49: the BMC control pulls the level signal of the GPIO pin of the embedded microcontroller low so that the embedded microcontroller returns to normal.
Further, the logic instructions in the memory described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Embodiments of the present application provide a non-transitory computer readable storage medium storing computer instructions that cause a computer to perform the methods provided by the method embodiments described above, for example, including: step 31: after receiving the upgrade request, the BMC loads a microcode upgrade file through a BMC interface; step 32: acquiring a digital signature of the microcode upgrade file; step 33: performing signature verification on the obtained digital signature; step 34: judging whether the verification is passed or not; if yes, go to step 36, if no, go to step 35; step 35: outputting loading failure prompt information at a BMC interface; step 36: the microcode upgrade file is loaded successfully; the BMC judges whether an upgrade trigger signal is received or not; if not, executing step 36, and continuing to receive and judge the trigger signal; if yes, go to step 37; step 37: the BMC control pulls high the level signal of the GPIO pin of the embedded microcontroller to enable the embedded microcontroller to enter a recovery mode; step 38: the BMC judges whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not; if not, go to step 39; if yes, confirming that the embedded microcontroller enters a recovery mode; step 40 is performed; step 39: the output mode enters an abnormal prompt message; step 40: checking whether the host enters an operating system; if yes, go to step 41; if not, go on to step 40; step 41: the BMC obtains the control right of the south bridge peripheral interface; step 42: writing the microcode upgrading file into the flash memory connected with the south bridge peripheral interface through the complex logic programming unit, and verifying and updating the written microcode upgrading file; step 43: acquiring an address of a south bridge peripheral interface connected with a flash memory; step 44: judging whether the address exists or not; if yes, the microcode is updated successfully, go to step 46; if not, go to step 45; step 45: and outputting microcode update failure prompt information at the BMC interface. Step 46: BMC gives up control right to the south bridge peripheral interface; meanwhile, triggering the quick hot reset of the host operating system to force reload the microcode upgrade file from the flash memory connected with the south bridge; step 47: checking whether the upgrade of the CPU microcode under the host operating system is successful; if yes, go to step 49; if not, go to step 48; step 48: and outputting prompt information of failure of microcode upgrading under the BMC interface. Step 49: the BMC control pulls the level signal of the GPIO pin of the embedded microcontroller low so that the embedded microcontroller returns to normal.
As the method, system, apparatus and medium of implementing the CPU microcode non-inductive upgrade of the present application are the elements and algorithm steps of each example described in connection with the embodiments disclosed herein, and can be implemented in electronic hardware, computer software, or a combination of both, the components and steps of each example have been generally described in terms of functionality in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Although the present application has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present application is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present application by those skilled in the art without departing from the spirit and scope of the present application, and it is intended that all such modifications and substitutions be within the scope of the present application/be within the scope of the present application as defined by the appended claims. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The method for realizing the non-inductive upgrade of the CPU microcode is characterized by comprising the following steps:
the BMC loads a microcode upgrading file;
after loading is successful, the BMC receives the upgrade trigger signal and then controls the embedded microcontroller to enter a recovery mode; the embedded microcontroller is an embedded microcontroller positioned in the south bridge chip;
the BMC obtains the control right of the south bridge peripheral interface and writes the microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating;
after the updating is finished, the BMC gives up the control right of the south bridge peripheral interface and triggers a hot reset to force reload the microcode upgrading file from the flash memory connected with the south bridge;
after the success of the microcode upgrade is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal.
2. The method for implementing a CPU microcode noninductive upgrade of claim 1, wherein the step of the BMC loading the microcode upgrade file comprises:
after receiving the upgrade request, the BMC loads a microcode upgrade file through a BMC interface;
acquiring a digital signature of the microcode upgrade file;
performing signature verification on the obtained digital signature;
after verification is passed, the microcode upgrade file is loaded successfully;
and if the verification is not passed, outputting loading failure prompt information at the BMC interface.
3. The method for implementing the CPU microcode sensorless upgrade of claim 2, wherein the step of controlling the embedded microcontroller to enter the recovery mode after the BMC receives the upgrade trigger signal after the successful loading comprises:
after successful loading, the BMC judges whether an upgrade trigger signal is received or not;
if not, executing the steps of: the BMC judges whether an upgrade trigger signal is received or not and continues to receive the trigger signal;
if yes, the BMC control pulls up the level signal of the GPIO pin of the embedded microcontroller to enable the embedded microcontroller to enter a recovery mode;
the BMC judges whether feedback information which is returned by the embedded microcontroller and enters a recovery mode is received or not;
if the feedback information is received, confirming that the embedded microcontroller enters a recovery mode;
checking whether the host enters an operating system;
if yes, executing the steps: the BMC obtains the control right of the south bridge peripheral interface and writes microcode into a flash memory connected with the south bridge peripheral interface for updating;
if not, continuing to execute the steps of: checking whether the machine enters an operating system;
if the feedback information is not received, the output mode enters the abnormal prompt information.
4. The method for implementing a CPU microcode sensorless upgrade of claim 3, wherein the BMC obtains control rights of the south bridge peripheral interface and writes the microcode upgrade file into the flash memory connected to the south bridge peripheral interface for updating, the method comprising:
the BMC obtains the control right of the south bridge peripheral interface;
writing a microcode upgrading file into a flash memory connected with the south bridge peripheral interface through a complex logic programming unit;
verifying and updating the written microcode upgrading file;
acquiring an address of a south bridge peripheral interface connected with a flash memory;
judging whether the address exists or not;
if yes, the microcode is updated successfully, and the steps are executed: the BMC gives up the control right to the south bridge peripheral interface, triggers a hot reset and forces the reload of the microcode upgrade file from the flash memory connected with the south bridge;
if not, outputting a microcode update failure prompt message at the BMC interface.
5. The method of claim 4, wherein the step of the BMC relinquishing control of the south bridge peripheral interface and triggering a hot reset to force reloading of the microcode upgrade file from the south bridge connected flash memory comprises:
BMC gives up control right to the south bridge peripheral interface;
meanwhile, the quick hot reset of the host operating system is triggered to force the microcode upgrade file to be reloaded from the flash memory connected with the south bridge.
6. The method of claim 5, wherein the step of triggering a fast hot reset of the host operating system to force reloading of the microcode upgrade file from the south bridge connected flash memory comprises:
checking whether the upgrade of the CPU microcode under the host operating system is successful;
if yes, executing the steps: the BMC outputs a control signal to enable the embedded microcontroller to be normal;
if not, outputting prompt information of failure in microcode upgrading under the BMC interface.
7. The method of claim 6, wherein the step of the BMC outputting a control signal to restore the embedded microcontroller to normal after confirming the success of the microcode upgrade comprises:
after the success of the microcode upgrade is confirmed, the BMC control pulls down the level signal of the GPIO pin of the embedded microcontroller, so that the embedded microcontroller is recovered to be normal.
8. The system for realizing the non-inductive upgrade of the CPU microcode is characterized by comprising a host provided with an operating system, wherein a BMC is arranged on a main board of the host, and is connected with a south bridge chip which is connected with the CPU; the south bridge chip is also connected with a flash memory through a south bridge peripheral interface; an embedded microcontroller is arranged in the south bridge chip;
BMC, is used for loading the microcode upgrade file; the embedded microcontroller is controlled to enter a recovery mode after the loading is successful and the upgrading trigger signal is received; obtaining control right of the south bridge peripheral interface and writing microcode upgrading file into a flash memory connected with the south bridge peripheral interface for updating; after the updating is finished, the BMC gives up the control right to the south bridge peripheral interface, and triggers the quick hot reset of the host operating system to force the reload of the microcode upgrading file from the flash memory connected with the south bridge; after the success of the upgrade of the CPU microcode is confirmed, the BMC outputs a control signal to enable the embedded microcontroller to recover to be normal.
9. An electronic device, the electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores computer program instructions executable by at least one processor to enable the at least one processor to perform the method of implementing CPU microcode sensorless upgrades of any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform the method of implementing CPU microcode sensorless upgrade of any one of claims 1-7.
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| CN202310868968.5A CN116893836A (en) | 2023-07-14 | 2023-07-14 | Method, system, equipment and medium for realizing non-inductive upgrade of CPU microcode |
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| CN202310868968.5A CN116893836A (en) | 2023-07-14 | 2023-07-14 | Method, system, equipment and medium for realizing non-inductive upgrade of CPU microcode |
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