Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the process of transmitting the communication signal between the signal sender and the signal receiver, once the communication signal is intercepted by a malicious party, data carried by the communication signal is easily acquired by the malicious party. The data carried by the communication signal is acquired by a malicious party, so that potential safety hazards are brought to the signal sender and the signal receiver.
The inventors have found through research that a signal may be processed to process the signal into a signal having low interception performance before the signal is transmitted to a signal receiver. The technical scheme of the signal processing is as follows: and acquiring a signal to be sent to a signal receiver as a signal to be processed, dividing the signal to be processed, and determining the position of a target component included in each active area obtained by dividing on a transmission sequence corresponding to the signal to be processed. Each target component is then separately converted to a matching pseudo-random sequence code based on its position. The target component comprises a first component and a second component, wherein the first component is a part of the signal to be processed, the in-phase component of the signal to be processed is positioned in the corresponding active area; the second component is the portion of the signal to be processed where the quadrature component is located within the corresponding active region. Therefore, in the embodiment of the application, the target components in the signal to be processed are converted into the matched pseudo-random sequence codes, so that in the signal transmission process, a malicious party cannot know the matching relationship between the pseudo-random sequence and the target components, even if the signal is intercepted by the malicious party, the malicious party cannot know the data carried by the signal, and the probability of maliciously acquiring the data carried by the signal can be reduced by the scheme provided by the embodiment of the application.
Based on the above-mentioned signal processing technical scheme, the embodiment of the application provides a signal processing device and a signal processing method, and the signal processing device and the signal processing method provided by the embodiment of the application are specifically described below.
As shown in fig. 1, an embodiment of the present application provides a signal processing apparatus mainly including a modulator 11.
A modulator 11 for dividing a signal to be processed; determining the position of a target component included in each active area obtained by dividing on a transmission sequence corresponding to a signal to be processed; each target component is converted into a matching pseudo-random sequence code based on its position, respectively.
The target component comprises a first component and a second component, wherein the first component is a part of the signal to be processed, the in-phase component of the signal to be processed is positioned in the corresponding active area; the second component is the portion of the signal to be processed where the quadrature component is located within the corresponding active region.
The specific structure and interaction relation of each module related to the signal processing device are described below:
modulator 11:
the modulator 11 is mainly used for two points: firstly, dividing the signal to be processed, and determining the position of a target component included in each active area obtained by dividing on a transmission sequence corresponding to the signal to be processed. And secondly, respectively converting each target component into a matched pseudo-random sequence code based on the position of each target component.
The signal to be processed is a communication signal to be transmitted to the signal receiving side after being processed by the signal processing means, and is divided into an In-phase component (In-phase component) and a quadrature component (Quadrature component).
After acquiring the signal to be processed, the modulator 11 divides the signal to be processed. As shown in fig. 2, the division of the signal to be processed is accomplished by a division module 111 included in the modulator 11. A dividing module 111, configured to obtain a number of transmission bits corresponding to a signal to be processed; determining the number of active areas based on the data length and the number of transmission bits of the signal to be processed; dividing a signal to be processed based on the number of active areas; wherein each active region includes a first component and a second component having a data length no greater than the number of transmission bits.
In order to enable the capacity of carrying data in the transmission process to meet the requirement of the data transmission rate when the signal is transmitted to the signal receiving party subsequently so as to achieve high-performance transmission, the dividing module 111 needs to acquire the transmission bit number corresponding to the data transmission rate as the transmission bit number corresponding to the signal to be processed when dividing the signal to be processed. The specific process of determining the number of active areas by the dividing module 111 based on the data length and the number of transmission bits of the signal to be processed is: a ratio between the data length and the number of transmission bits is determined, and the number of active areas is determined based on the ratio. Specifically, if the determined ratio is an integer, the ratio is determined as the number of active areas. If the determined ratio is a non-integer, rounding down the determined ratio, and determining the rounded value plus 1 as the number of active areas. For example, if the data length is 110 bits and the number of transmission bits is 11 bits, the number of active areas is determined to be 10.
After determining the number of active areas, the dividing module 111 divides the signal to be processed according to the time sequence arrangement of the bits in the signal to be processed, and the in-phase component and the quadrature component of the signal to be processed need to be divided. Each active area obtained by dividing comprises a first component and a second component. The first component is the part of the signal to be processed, in which the in-phase component is located in the corresponding active area; the second component is the portion of the signal to be processed where the quadrature component is located within the corresponding active region.
Illustratively, as shown in fig. 3, fig. 3 is a schematic view of an active area. It can be seen from fig. 3 that the signal to be processed is divided into an active area 1 and an active area 2. Each active region includes a first component I and a second component Q, respectively, and the first component I and the second component Q carry 11 bits of data, respectively.
After dividing the signal to be processed to obtain the active areas, the modulator 11 determines the positions of the target components included in each of the active areas obtained by division on the transmission sequence corresponding to the signal to be processed, and as shown in fig. 2, the process of determining the positions is completed by a determining module 112 included in the modulator 11. A determining module 112, configured to perform, for each target component included in each active area: converting a bit sequence corresponding to the target component into a position value; determining a location of the target component on the transmission sequence based on the location value; wherein the position value is any one of the following: position values in gray code form, position values in decimal form. Since the target component includes a first component and a second component, the determining module 112 determines a corresponding position for each of the first component and each of the second component included in each of the active areas.
The specific process of converting the bit sequence corresponding to the target class into a position is related to the specific form of the position value, and thus the conversion method may include two kinds of:
first, when the position value is expressed in decimal form, the target component is converted into a decimal position value. Illustratively, the binary representation of the bit sequence corresponding to the target component is 110 1110 1101, which has a natural binary code position value of 1773. The target component is converted to a decimal place value 1435.
Second, the target component is converted into a gray code position value by the position value expressed in gray code form. The target component is converted into the Gray code position value to increase the anti-interference capability of the signal and reduce the error rate. The coding rule for converting the target component into the Gray code position value is as follows: each bit is exclusive-ored with the left bit in turn from the rightmost bit of the bit sequence corresponding to the target component, and the leftmost bit remains unchanged (corresponding to the left bit being 0) as the gray code value corresponding to the bit.
Illustratively, the binary representation of the bit sequence corresponding to the target component is 110 1110 1101, which is a natural binary code position value 1773. The target component is converted to a gray code position value denoted 1011001 1011. The target component is converted to a decimal place value represented as 1435.
Gray code belongs to reliability coding, and is a coding mode with minimized error. It is possible to reduce logic confusion from one state to the next by only changing one bit when switching between adjacent bits (e.g., adding one or subtracting one). Since only one bit is different between two adjacent code groups in the gray code, the position value expressed in the gray code form is more reliable than the case where other codes change two or more bits at the same time.
The location value of the target component describes the location of the target component on the transmission sequence of the signal to be processed, so the determining module 112 locates the location of the target component in the transmission sequence based on the location value after determining the location value corresponding to the target component. For example, when the target component is the first component, the position of the first component in the transmission sequence is located based on the position value corresponding to the first component. For example, when the target component is the second component, the position of the second component in the transmission sequence is located based on the position value corresponding to the second component.
After determining the position corresponding to each target component in each active area, the modulator 11 needs to convert the target component corresponding to each position into a matched pseudo-random sequence code, so that in the signal transmission process, even if a signal is intercepted maliciously, the malicious interceptor cannot acquire the data carried by the signal because the target component is converted into the matched pseudo-random sequence code. As shown in fig. 2, the process of converting the target component corresponding to each position into a matched pseudo random sequence code is performed by a conversion module 113 included in the modulator 11. A conversion module 113, configured to perform, for each target component included in each active area: determining a time slot corresponding to an active area where a target component is located; selecting a pseudo-random sequence code matched with the target component based on the determined time slot; and replacing the target component with the matched pseudo-random sequence code based on the position corresponding to the target component.
The conversion module 113 performs the same conversion process for each target component, and thus the conversion module 113 will be described below taking one target component conversion process as an example:
the transmission of a signal typically involves a plurality of consecutive time slots, with the transmission of the signal being based on an ordered sequence of time slots. In the embodiment of the application, each active area has a corresponding time slot, and the active areas are sent out in the corresponding time slots. For example, a data length of a signal to be transmitted is 1100 bits, and is divided into 11 slots, one slot is 11 bits in time, and one slot has a corresponding active area. The bit time here is the time required for transmitting 1 bit.
After determining the time slot corresponding to the active area where the target component is located, the conversion module 113 is specifically configured to select a pseudorandom sequence code set corresponding to the target component based on the determined time slot; selecting a pseudo-random sequence code corresponding to the target component in the pseudo-random sequence code set as a pseudo-random sequence code matched with the target component; the corresponding relation between the target component and the pseudo-random sequence code exists in the pseudo-random sequence code set, and the corresponding relation is the appointed setting of the signal initiator and the signal receiver.
The signal initiator and the signal receiver can preset a plurality of pseudo-random code sequence sets, time slots with corresponding relations exist in each pseudo-random code sequence set, and each pseudo-random code sequence set comprises a corresponding relation between available target components and pseudo-random sequence codes in the corresponding time slots.
After determining the time slot corresponding to the target component, selecting a pseudo-random sequence code set corresponding to the time slot, and then determining the pseudo-random sequence code matched with the target component based on the corresponding relation between the target component in the pseudo-random sequence code set and the pseudo-random sequence code. The corresponding relation between the target component and the pseudo-random sequence code exists in the pseudo-random sequence code corresponding to the time slot and the pseudo-random sequence code set, and the corresponding relation is the agreed setting of the signal initiator and the signal receiver. Because the malicious interception party cannot know the corresponding relation agreed by the signal initiator and the signal receiver, even if signals are intercepted by the malicious party in the signal transmission process, the malicious party cannot analyze the data carried by the signals, so that the possibility that the data carried by the signals are maliciously acquired can be reduced.
Further, the conversion module 113 is specifically configured to match the same pseudorandom sequence code for a first component of a different time slot and the same pseudorandom sequence code for a second component of the different time slot, and match different pseudorandom sequence codes for the first component and the second component in the same time slot.
The first components of different time slots can be matched with the same pseudo-random sequence code, and the second components of different time slots can be matched with the same pseudo-random sequence code, so that the same pseudo-random sequence code can be set in the pseudo-random sequence code set corresponding to different time slots, and the complexity of the set of the pseudo-random sequence codes appointed between the signal initiator and the signal receiver can be reduced because the pseudo-random sequence codes can be multiplexed among different time slots.
Different pseudo-random sequence codes are matched with the first component and the second component in the same time slot, so that the pseudo-random sequence codes corresponding to the first component and the second component are not overlapped on the transmission position, and the situation that signal transmission is wrong can be reduced.
Illustratively, the conversion module 113 replaces each target component in the active region 1 and the active region 2 shown in fig. 3 with a matching pseudo-random sequence code to form an active region schematic as shown in fig. 4. In fig. 4, the first component I and the second component Q in each active region are each replaced with a corresponding pseudo-random sequence code, i.e., PN shown in fig. 4.
The signal processing device provided by the embodiment of the application acquires a signal to be sent to a signal receiver as a signal to be processed, divides the signal to be processed, and determines the position of a target component included in each active area obtained by division on a transmission sequence corresponding to the signal to be processed. Each target component is then separately converted to a matching pseudo-random sequence code based on its position. The target component comprises a first component and a second component, wherein the first component is a part of the signal to be processed, the in-phase component of the signal to be processed is positioned in the corresponding active area; the second component is the portion of the signal to be processed where the quadrature component is located within the corresponding active region. Therefore, in the embodiment of the application, the target components in the signal to be processed are converted into the matched pseudo-random sequence codes, so that in the signal transmission process, a malicious party cannot know the matching relationship between the pseudo-random sequence and the target components, even if the signal is intercepted by the malicious party, the malicious party cannot know the data carried by the signal, and the probability of maliciously acquiring the data carried by the signal can be reduced by the scheme provided by the embodiment of the application.
In some embodiments of the present application, the signal processing apparatus may further include one or more of the following: constellation contamination 12, transmitter 13, generator 14.
In an embodiment of the present application, to further reduce the possibility of malicious acquisition of data carried by the signal, the signal processing apparatus may include a constellation contaminant 12. As shown in fig. 2, the signal to be transmitted, which is formed by the modulator 11 after converting each target component into a matched pseudo-random sequence code, is not directly transmitted to a signal receiver, but is provided to the constellation contaminant 12. A constellation contaminant 12, configured to obtain a signal to be sent transmitted by the modulator 11; adjusting target parameters of signals to be transmitted; wherein the target parameters include at least one of: amplitude and phase; the signal to be transmitted is a signal formed by the modulator 11 after converting each target component into a matched pseudo random sequence code.
The constellation diagram contaminant 12 adds noise to the signal to be transmitted, so that the constellation mapping relation related to the constellation diagram of the signal to be transmitted is not easy to be exposed or changed on the signal receiving side, and even if a malicious party intercepts the signal, the malicious party cannot obtain corresponding modulation phase information from the constellation diagram of the signal, and therefore the probability of malicious acquisition of data carried by the signal can be reduced. The noise superimposed on the signal to be transmitted here may include at least one of the following: randomly superimposed phase noise, randomly superimposed amplitude noise. Because the noise adopts a random superposition mode, a malicious party cannot find a superposition rule to crack the intercepted signals.
In the field of digital communication, a signal is usually represented by points on an amplitude and phase plane, namely a constellation diagram corresponding to the signal, and the representation mode can intuitively represent the mapping relation between the amplitude and the phase of the signal. In the constellation diagram, the abscissa axis of the constellation diagram represents the in-phase component I and the ordinate axis represents the quadrature component Q. Thus, the axis of abscissa may be referred to as the I-axis and the axis of ordinate may be referred to as the Q-axis. The polar coordinates of the constellation diagram have an I-axis on a 0 deg. phase reference and a Q-axis on a 90 deg. phase reference. The projection of the vector signal on the I axis is an in-phase component, the projection on the Q axis is a quadrature component, the included angle between the vector signal and the I axis is the phase information of the signal, the horizontal X axis is related to the in-phase carrier, and the vertical Y axis is related to the quadrature carrier.
The length of the connecting line of any point related to the signal in the constellation diagram to the origin of the constellation diagram coordinate system is the peak amplitude of the signal, and the amplitude is the square sum root of the in-phase component and the quadrature component. The angle between the connection line and the I-axis is the phase of the signal. In general, there is a certain mapping relation between points in the constellation diagram, each point in the signal is represented by n-bit binary system, and only one bit in the adjacent binary system representation changes, that is, the gray code is used for representing, which can reduce the symbol spacing between signals when burst errors occur, so that the correct symbol obtained by decoding by a signal receiver can be easier. Illustratively, as shown in fig. 5, one constellation is shown in fig. 5, which is a constellation of a 16QAM signal. A in FIG. 5 represents an amplitude, and
The phase of the signal to be transmitted is superimposed with random interference, namely, the phase of the signal is multiplied by an offset, so that an interception party cannot acquire the true constellation of the signal on the premise of not knowing the constellation mapping, and therefore, cannot acquire the data carried by the signal. And the signal receiver can perform decontamination treatment on the received signal phase according to the random phase sequence agreed by the signal sender to obtain real data. The offset here can be determined by the following formula:wherein, θ takes any one of values 0 to 1, and j represents an imaginary number.
The random interference is superimposed on the amplitude of the signal to be transmitted, namely, the amplitude of the signal is superimposed by a superposition amount, so that an interception party cannot acquire the true constellation diagram of the signal on the premise of not knowing the constellation mapping, and therefore, cannot acquire the data carried by the signal. And the signal receiver can perform decontamination treatment on the received signal amplitude according to the random amplitude sequence agreed by the signal sender to obtain real data. The manner of superimposing a superimposed amount here may be: the superimposed quantity is processed by multiplying, dividing, subtracting, adding at least one of the amplitudes of the signals. The amount of superposition here is chosen based on a random amplitude sequence.
In an embodiment of the present application, in order to avoid that a malicious party predicts the next communication transmission time by means of a signal detection technique and interferes with the signal according to the predicted time, the signal processing apparatus comprises a transmitter 13 as shown in fig. 2. A transmitter 13, configured to randomly set a start time of a transmission pulse corresponding to each time slot of a signal to be transmitted; transmitting a signal to be transmitted in each time slot based on the corresponding starting time; wherein the signal to be transmitted is a signal formed by the modulator after converting each target component into a matched pseudo-random sequence code.
The transmitter 13 transmits a signal to be transmitted to a signal receiver using fast hopping (MTSK). The fast frequency hopping can break long residence through fast frequency hopping among time slots under the fixed channel frequency, so that malicious parties cannot predict the occurrence time of next communication, and cannot intercept and interfere signals.
The transmitter 13 uses the start time of the random transmit pulse in addition to the signal transmitted in a frequency hopping manner. The transmitter 13 randomly sets the start time of the transmission pulse corresponding to each time slot of the signal to be transmitted, and transmits the signal to be transmitted in each time slot based on the corresponding start time, so that the regular periodicity of detecting signal transmission by a malicious party can be improved. The signal processed by the transmitter 13 can exhibit a high degree of randomness in both the transmission frequency and the transmission start time, helping to minimize the received energy required for successful communication.
The transmitter 13 is used in conjunction with the modulator 11 so that the signal to be transmitted it processes can be the signal that the modulator 11 forms after converting each target component into a matching pseudo-random sequence code. Transmitter 13 may also be used in conjunction with modulator 11 and constellation contaminant 12 such that the signal to be transmitted it processes is the signal processed by constellation contaminant 12.
In an embodiment of the application, the signal processing device further comprises a generator 14, as shown in fig. 2. A generator 14 for dividing the signal to be processed, forming an in-phase component and a quadrature component corresponding to the signal to be processed, and transmitting the in-phase component and the quadrature component to the modulator 11.
The generator 14 divides the channel by quasi-orthogonal codes to increase the channel capacity and outputs two single-polarity binary symbols, i.e., an In-phase component I (In-phase component) and a quadrature component Q (Quadrature component) corresponding to the signal to be processed. The generator 14 transmits the in-phase component and the quadrature component corresponding to the signal to be processed to the modulator 11 for use by the modulator 11.
In some embodiments of the application, the signal processing apparatus further comprises an interleaver 15, as shown in fig. 2, in order to reduce the occurrence of consecutive error symbols in the signal. An interleaver 15, configured to group bit sequences corresponding to the first signals to form a plurality of bit groups; changing the position relation between adjacent bits in the bit sequence based on the bits included in each bit packet to form a signal to be processed; wherein, after changing the position relationship, all bits in the same bit packet are not located in the same bit packet at the same time.
In practical applications, the signal transmitted into the channel will be distorted and disturbed to some extent due to the non-ideal amplitude phase characteristics of the transmission channel or the influence of various environmental disturbances and random noise. Although channel coding can correct some error bits, on a parameter-associated channel in mobile communication, the amplitude-frequency and phase-frequency characteristics of the channel change randomly with time, so that burst continuous error symbols are likely to appear in transmission information. The continuous error symbols may cause the signal receiver to fail to accurately acquire the data carried by the signal. The signal is thus interleaved by an interleaver 15 in order to reduce the occurrence of consecutive error symbols in the signal. The interleaver 15 is a device capable of changing the symbol positions without changing the symbol contents, and the interleaver 15 is designed to minimize the correlation of sequences before and after interleaving in such a manner that the structure of the sequences is changed randomly, that is, the order of the symbol sequences is changed using a random integer sequence generator. After passing through the interleaver 15, the successive error symbols of the bursts are spread out to become discrete individually occurring error symbols, so that the concentrated errors generated by the bursts during channel transmission are spread out to a large extent.
After the first signal is acquired, the interleaver 15 groups the bit sequence corresponding to the first signal to form a plurality of bit groups. The first signal here is a signal that needs to be processed as a signal to be processed. And then changing the position relation between adjacent bits in the bit sequence based on the bits included in each bit packet to form a signal to be processed. After the position relation of all bits in the same bit packet in the first signal is changed, the bits in the same bit packet are not simultaneously in the signal to be processed, so that the condition that continuous error code elements occur in the signal can be reduced. The interleaver 15 may randomly shuffle the signal using a random integer sequence generator, and does not have a method of decimating bits according to a strict packet to form a frame, and in order for the signal receiving end to perform a de-interleaving process on the signal, it is necessary to inform the signal receiving end of the random sequence in advance.
Illustratively, as shown in fig. 6, it is assumed that the interleaver 15 processes the first signal a, groups a bit sequence corresponding to the first signal a, and forms 4 consecutive bit groups after grouping, where 4 bits in each bit group are respectively indicated by 1-4. When changing the positional relationship between adjacent bits in the bit sequence based on the bits included in each bit packet, the 1 st bit in the 4 adjacent packets is taken out to constitute a new 4-bit packet, which is called a 1 st frame in fig. 4. The 2 nd bit of the 4 adjacent packets is taken out to form a new 4-bit packet, referred to as the 2 nd frame in fig. 4. The 3 rd bit of the 4 adjacent packets is extracted to form a new 4-bit packet, referred to as the 3 rd frame in fig. 4. The 4 th bit of the 4 adjacent packets is taken out to form a new 4-bit packet, referred to as the 4 th frame in fig. 4.
As shown in fig. 7, if the 2 nd frame is lost during the information transmission, if interleaving is not performed before, the signal receiving side will lose a certain whole bit packet; after the interleaving technique is adopted, even if the 2 nd bit of each bit packet is lost, the signal receiving side restores the signal to the signal shown in fig. 8, and the data in all bit packets can still be restored through channel decoding, so that the advantages of the interleaving technique are reflected. That is, the interleaver 15 disperses b bits in the codeword into n frames to change the positional relationship between adjacent bits. The larger the value of n, the better the transmission performance.
In some embodiments of the application, the signal processing apparatus further comprises an error correction encoder 16, as shown in fig. 2, for error correction of errors in the signal. An error correction encoder 16 for acquiring the second signal provided by the signal initiator; performing error correction coding processing on the second signal to form a first signal; wherein the first signal comprises all original symbols of the second signal and error correction codes added during the error correction coding process.
The second signal is a signal initiated by the signal initiation direction signal receiver. To ensure that the signal receiver is able to receive enough of the correct bits to enable the signal receiver to recover the correct data according to the RS decoding (Reed-solomon encodings). Therefore, the error correction encoder 15 is required to perform error correction encoding processing on the second signal to form the first signal. The first signal includes all original code elements of the second signal and error correction codes added during error correction coding processing, so that even if a plurality of bits on a signal received by a signal receiver are distorted by noise interference, the data carried by the signal can be recovered.
In some embodiments of the present application, the specific operation of the signal processing apparatus will be described below by taking the signal processing apparatus shown in fig. 9 as an example. The signal processing device in fig. 9 includes a modulator 11, a constellation contaminant 12, a transmitter 13, a generator 14, an interleaver 15, and an error correction encoder 16.
The signal initiator initiates a second signal "DATAI". The error correction encoder 16 acquires the second signal "DATAI", performs error correction encoding processing on the second signal "DATAI" to form the first signal "S1", and sends the first signal "S1" to the interleaver 15. The first signal "S1" here includes all original symbols of the second signal and error correction codes added at the time of error correction coding processing.
The interleaver 15 groups the bit sequence corresponding to the first signal "S1" to form a plurality of bit groups; based on the bits included in each bit packet, the positional relationship between adjacent bits in the bit sequence is changed to form a signal to be processed "S2". The interleaver 15 transmits the signal to be processed "S2" to the generator 14.
The generator 14 divides the signal to be processed "S2", forms an in-phase component and a quadrature component corresponding to the signal to be processed "S2", and transmits the in-phase component and the quadrature component corresponding to the signal to be processed to the modulator 11.
The modulator 11 divides the signal to be processed and determines the position of the target component included in each of the divided active areas on the transmission sequence corresponding to the signal to be processed. Based on the location of each target component, each target component is converted into a matched pseudo-random sequence code, forming a signal to be transmitted, and the signal to be transmitted "S3" is transmitted to the constellation contaminant 12.
The constellation contaminant 12 adjusts a target parameter of the signal to be transmitted "S3", e.g., the target parameter is phase. The constellation contaminant 12 sends the signal to be transmitted "S4" after adjusting the target parameter to the transmitter 13.
The transmitter 13 randomly sets the start time of the transmission pulse corresponding to the signal to be transmitted "S4" at each time slot; the signal to be transmitted is transmitted to the signal receiver as a transmitting signal 'DATAO' based on the corresponding starting time in each time slot, thereby completing the process of transmitting the signal of the signal sender to the signal receiver. When the transmitter 13 sends a signal to the signal receiving party, white noise may be added to the signal to further improve the security of the signal.
After receiving the signal sent by the sender 13, the signal receiver obtains the data carried by the signal through the above reverse processing procedure on the received signal. The receiver needs to know the corresponding relation between the pseudo random sequence code and the target component during the reverse processing. These correspondences are agreed in advance by the signal processing device and the signal receiving side.
Further, an embodiment of the present application further provides a signal processing method, as shown in fig. 10, including the following steps 201 to 203:
201. the signal to be processed is divided.
202. And determining the position of a target component included in each active area obtained by dividing on a transmission sequence corresponding to the signal to be processed. The target component comprises a first component and a second component, wherein the first component is a part of the signal to be processed, in which an in-phase component is located in a corresponding active area; the second component is the portion of the orthogonal component of the signal to be processed that is located within the corresponding active region.
203. Each of the target components is converted into a matching pseudo-random sequence code based on the position of each of the target components, respectively.
According to the signal processing method provided by the embodiment of the application, the signal to be sent to the signal receiver is acquired as the signal to be processed, the signal to be processed is divided, and the position of the target component included in each active area obtained by dividing on the transmission sequence corresponding to the signal to be processed is determined. Each target component is then separately converted to a matching pseudo-random sequence code based on its position. The target component comprises a first component and a second component, wherein the first component is a part of the signal to be processed, the in-phase component of the signal to be processed is positioned in the corresponding active area; the second component is the portion of the signal to be processed where the quadrature component is located within the corresponding active region. Therefore, in the embodiment of the application, the target components in the signal to be processed are converted into the matched pseudo-random sequence codes, so that in the signal transmission process, a malicious party cannot know the matching relationship between the pseudo-random sequence and the target components, even if the signal is intercepted by the malicious party, the malicious party cannot know the data carried by the signal, and the probability of maliciously acquiring the data carried by the signal can be reduced by the scheme provided by the embodiment of the application.
In some embodiments of the present application, the specific implementation of the above step 201 "dividing the signal to be processed" may include the following steps: acquiring the number of transmission bits corresponding to a signal to be processed; determining the number of active areas based on the data length and the number of transmission bits of the signal to be processed; dividing the signal to be processed based on the number of active areas; wherein each of the active areas includes a first component and a second component having a data length not greater than the number of transmission bits.
In some embodiments of the present application, the specific implementation process of determining the location of the target component included in each active area obtained by the dividing in the step 202 on the transmission sequence corresponding to the signal to be processed may include the following steps: executing, for each target component included in each of the active areas: converting the bit sequence corresponding to the target component into a position value; determining a position of the target component on the transmission sequence based on the position value; wherein the position value is any one of the following: position values in gray code form, position values in decimal form.
In some embodiments of the present application, the specific implementation of the step 203 "converting each of the target components into the matched pseudo random sequence code based on the position of each of the target components" may include the following steps: executing, for each target component included in each of the active areas: determining a time slot corresponding to an active area where the target component is located; selecting a pseudo-random sequence code matched with the target component based on the determined time slot; and replacing the target component with a matched pseudo-random sequence code based on the position corresponding to the target component.
In some embodiments of the present application, the specific implementation of the step of selecting the pseudo random sequence code matched with the target component based on the determined time slot may include the following steps: selecting a pseudo-random sequence code set corresponding to the target component based on the determined time slot; selecting a pseudo-random sequence code corresponding to the target component in the pseudo-random sequence code set as a pseudo-random sequence code matched with the target component; the corresponding relation between the target component and the pseudo-random sequence code exists in the pseudo-random sequence code set, and the corresponding relation is the appointed setting of the signal initiator and the signal receiver.
In some embodiments of the application, the first component for different time slots may match the same pseudo-random sequence code and the second component for different time slots may match the same pseudo-random sequence code, and the first and second components within the same time slot match different pseudo-random sequence codes.
In some embodiments of the present application, the signal processing method may further include the steps of: acquiring a signal to be transmitted; adjusting target parameters of the signals to be transmitted; wherein the target parameters include at least one of: amplitude and phase; the signal to be transmitted is a signal formed after each of the target components is converted into a matched pseudo-random sequence code.
In some embodiments of the present application, the signal processing method may further include the steps of: randomly setting the starting time of a transmitting pulse corresponding to each time slot of a signal to be transmitted; transmitting the signal to be transmitted in each time slot based on the corresponding starting time; the signal to be sent is a signal formed by the modulator after each target component is converted into a matched pseudo-random sequence code.
In some embodiments of the present application, the signal processing method may further include the steps of: grouping bit sequences corresponding to the first signals to form a plurality of bit groups; changing the position relation between adjacent bits in the bit sequence based on the bits included in each bit packet to form the signal to be processed; wherein, after changing the position relationship, all bits in the same bit packet are not located in the same bit packet at the same time.
In some embodiments of the present application, the signal processing method may further include the steps of: acquiring a second signal provided by a signal initiator; performing error correction coding processing on the second signal to form the first signal; wherein the first signal includes all original symbols of the second signal and an error correction code added at the time of error correction coding processing.
In some embodiments of the present application, the signal processing method may further include the steps of: dividing the signal to be processed to form an in-phase component and a quadrature component corresponding to the signal to be processed, and transmitting the in-phase component and the quadrature component to the modulator.
In the signal processing method provided in the embodiment of the present application, the details of the method adopted in each step may be referred to the corresponding details of the embodiment of the signal processing apparatus, and will not be described herein.
Further, an embodiment of the present application also provides a computer readable storage medium, where the storage medium includes a stored program, where the program controls a device where the storage medium is located to execute the above-mentioned signal processing method when running the program.
Further, according to the above embodiment, an embodiment of the present application further provides an electronic device, including: a memory for storing a program; and a processor coupled to the memory for executing the program to perform the signal processing method described above.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
It will be appreciated that the relevant features of the methods and apparatus described above may be referenced to one another. In addition, the "first", "second", and the like in the above embodiments are for distinguishing the embodiments, and do not represent the merits and merits of the embodiments.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present application is not directed to any particular programming language. It should be appreciated that the teachings of the present application as described herein may be implemented in a variety of programming languages and that the foregoing descriptions of specific languages are provided for disclosure of preferred embodiments of the present application.
Furthermore, the memory may include volatile memory, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), in a computer readable medium, the memory including at least one memory chip.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data tapping device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data tapping device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data cutting apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data-cutting apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.