CN116886100A - Signal sampling system - Google Patents
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- CN116886100A CN116886100A CN202311153624.2A CN202311153624A CN116886100A CN 116886100 A CN116886100 A CN 116886100A CN 202311153624 A CN202311153624 A CN 202311153624A CN 116886100 A CN116886100 A CN 116886100A
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- 230000011218 segmentation Effects 0.000 claims abstract description 20
- 239000002131 composite material Substances 0.000 claims abstract description 11
- 238000012545 processing Methods 0.000 claims description 18
- 230000003321 amplification Effects 0.000 claims description 17
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 10
- 238000005259 measurement Methods 0.000 description 5
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- 230000003139 buffering effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1265—Non-uniform sampling
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention discloses a signal sampling system, comprising: the device comprises a reference circuit module, a segmentation interception control module, a controller and an interception amplifying circuit; the reference circuit module is used for segmenting the reference voltage to form N-1 paths of reference array voltages; n is an integer greater than 1; the sectioning interception control module is connected with the reference circuit module and is used for dividing the acquired signal into N sections according to the reference array voltage to intercept and outputting a sectioning interception control signal to the controller; the controller is used for generating a channel selection control signal according to the segmentation interception control signal; the intercepting and amplifying circuit is respectively connected with the controller and the reference circuit module and is used for carrying out biasing and amplifying treatment on the acquired signal according to the channel selection control signal and the reference array voltage and outputting the acquired signal; the controller is also configured to form a composite signal based on the acquired signal. The technical scheme provided by the invention is used for improving the sampling precision of the signal.
Description
Technical Field
The invention relates to the technical field of signal acquisition and processing, in particular to a signal sampling system.
Background
Along with the rapid development of artificial intelligence technology, the signal sampling technology is widely applied in the fields of intelligent monitoring, early warning and the like. In the big data intelligence era, improvement of signal sampling precision has great significance to technological development.
The traditional methods for improving the signal sampling precision are three: oversampling, selecting a high resolution analog to digital converter, and maximizing the use of the reference voltage. The over-sampling scheme and the scheme for selecting the high-resolution analog-to-digital converter ADC are both slower in sampling speed, and the scheme for selecting the high-resolution analog-to-digital converter is higher in price; the solution of maximizing the use of the reference voltage also fails to meet the high precision requirements of some sampling systems.
Disclosure of Invention
The embodiment of the invention provides a signal sampling system, which improves the sampling precision of signals under the condition of not influencing the sampling speed.
The embodiment of the invention provides a signal sampling system, which comprises: the device comprises a reference circuit module, a segmentation interception control module, a controller and an interception amplifying circuit;
the reference circuit module is used for segmenting the reference voltage to form N-1 paths of reference array voltages; n is an integer greater than 1; the sectioning interception control module is connected with the reference circuit module and is used for dividing the acquired signal into N sections according to the reference array voltage to intercept and outputting a sectioning interception control signal to the controller; the controller is used for generating a channel selection control signal according to the segmentation interception control signal; the intercepting and amplifying circuit is respectively connected with the controller and the reference circuit module and is used for carrying out biasing and amplifying treatment on the acquired signals according to the channel selection control signals and the multi-path reference array voltage and outputting the acquired signals; the controller is also configured to form a composite signal based on the acquisition signal.
The reference circuit module is used for segmenting the reference voltage to form N-1 paths of reference array voltages; n is an integer greater than 1; the sectioning interception control module is connected with the reference circuit module and is used for dividing the acquired signal into N sections according to the reference array voltage to intercept and outputting a sectioning interception control signal to the controller; the controller is used for generating a channel selection control signal according to the segmentation interception control signal; the intercepting and amplifying circuit is respectively connected with the controller and the reference circuit module and is used for carrying out biasing and amplifying treatment on the acquired signals according to the channel selection control signals and the multi-path reference array voltage and outputting the acquired signals; the controller is also configured to form a composite signal based on the acquisition signal.
The signal sampling system is provided with a reference circuit module, a sectionalized intercepting control module and an intercepting amplifying circuit, wherein the reference circuit module can divide reference voltage into multiple paths of reference array voltages, so that the sectionalized intercepting control module intercepts a sampled signal into multiple sections according to the multiple paths of reference array voltages, the intercepting amplifying circuit can select the section where the current sampled signal is located according to the sectionalized condition, bias processing and amplifying processing are carried out on the current sampled signal according to the section so as to acquire the sampled signal with higher precision, and the controller synthesizes an initial sampled signal according to the sampled signal with higher precision. The embodiment performs sectional interception, offset and amplification processing on the sampled signals, so that the peak value of each section of intercepted signal is infinitely close to the reference voltage, full-scale measurement is achieved, signal acquisition precision is improved, the purpose of improving signal sampling precision is achieved under the condition that sampling speed is not affected, the sampling precision is related to the number of sections, namely, the sampling precision is programmable, the sampling precision can be increased by increasing the number of sections, and the method is flexible to apply and is suitable for high-precision control application. In addition, the signal sampling system in the embodiment can realize the multiple improvement of the sampling precision by only adding a small number of elements, and the sampling cost is saved.
Drawings
FIG. 1 is a schematic diagram of an oversampling scheme in the prior art;
fig. 2 is a schematic structural diagram of a signal sampling system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a reference circuit module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a segment interception control module according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a structure of a clipping amplifying circuit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The traditional method for improving the signal sampling precision mainly comprises three methods: first, in the oversampling manner, as shown in fig. 1, fig. 1 is a schematic diagram of an oversampling flow in the prior art. Oversampling refers to sampling an analog signal at a sampling frequency that is significantly higher than the nyquist rate. The specific flow may include: step S11: sampling by an N-bit ADC; step S12 may be performed subsequently: filtering the average value; finally, step S13 is executed: sampling Rate (OSR) downsampling; and finally obtaining a sampling result. The method can truly reconstruct an original signal, can improve the sampling resolution, and is widely applied to signal sampling in an embedded system; secondly, selecting the ADC with high resolution, wherein the difference of the effective bits and the precision of the ADCs with different resolutions is larger, the higher the resolution is, the higher the precision of the acquired signal is, and otherwise, the lower the precision is; and thirdly, maximizing the use of a reference voltage, and controlling the acquired signal to be infinitely close to the reference voltage through means such as signal amplification and the like, so that the sampling precision is improved. However, in implementing embodiments of the present invention, the inventors have found that for the first approach, the over-sampling technique is a technique that increases the ADC resolution at the expense of sampling speed, by which each increase in 1 Bit ADC resolution requires an increase in sampling rate of 4 times, such as 12 bits for 1 sample, 13 bits for 4 times, 14 bits for 16 times, 15 bits for 64 times, and 16 bits for 256 times, which is not a very desirable option for systems with sampling speed requirements; for the second scheme, the higher the resolution of the ADC, the slower the sampling speed and the higher the price, and the scheme is not a very ideal choice for systems with sampling speed and cost requirements; for the third scheme, even though the reference voltage is maximally utilized, some sampling systems still cannot meet the requirements. The embodiment of the invention provides a signal sampling system, which improves the sampling precision of signals under the condition of not influencing the sampling speed, and specifically comprises the following steps:
fig. 2 is a schematic structural diagram of a signal sampling system according to an embodiment of the present invention, as shown in fig. 2. The embodiment of the invention provides a signal sampling system 001, which comprises: a reference circuit module 100, a segment interception control module 300, a controller 400, and an interception amplifying circuit 200;
the reference circuit module 100 is used for segmenting the reference voltage REF to form N-1 paths of reference array voltages; n is an integer greater than 1; the segmentation interception control module 300 is connected with the reference circuit module 100 and is used for dividing the sampled signal into N segments according to the reference array voltage to intercept and outputting a segmentation interception control signal to the controller 400; the controller 400 is configured to generate a channel selection control signal according to the segment interception control signal; the intercepting and amplifying circuit 200 is respectively connected with the controller 400 and the reference circuit module 100, and is used for carrying out biasing and amplifying treatment on the acquired signal according to the channel selection control signal and the reference array voltage and outputting the acquired signal; the controller 400 is also configured to form a composite signal from the acquired signals.
In the embodiment of the invention, the signal sampling system is provided with a reference circuit module, a segmentation interception control module and an interception amplifying circuit, wherein the reference circuit module can divide reference voltage into multiple paths of reference array voltages, so that the segmentation interception control module intercepts a sampled signal into multiple sections according to the multiple paths of reference array voltages, the interception amplifying circuit can select the section where the current sampled signal is positioned according to the segmentation condition, and bias processing and amplifying processing are carried out on the current sampled signal according to the section so as to acquire the sampled signal with higher precision, and the controller synthesizes an initial sampled signal according to the acquired signal with higher precision. The embodiment performs sectional interception, offset and amplification processing on the sampled signals, so that the peak value of each section of intercepted signal is infinitely close to the reference voltage, full-scale measurement is achieved, signal acquisition precision is improved, the purpose of improving signal sampling precision is achieved under the condition that sampling speed is not affected, the sampling precision is related to the number of sections, namely, the sampling precision is programmable, the sampling precision can be increased by increasing the number of sections, and the method is flexible to apply and is suitable for high-precision control application. In addition, the signal sampling system in the embodiment can realize the multiple improvement of the sampling precision by only adding a small number of elements, and the sampling cost is saved.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
The reference circuit module 100 is capable of segmenting the reference voltage REF into N ranges. For example, if the reference voltage REF is 5V, the embodiment may be divided into 5 segments, wherein 0-1V is the first segment, 1-2V is the second segment, 2-3V is the third segment, 3-4V is the fourth segment, and 4-5V is the fifth segment. The corresponding N-1 reference array voltages are 1v,2v,3v,4v. In this embodiment, N is an integer greater than 1, and in this example, N takes a value of 5. The segmentation interception control module 300 can intercept the picked signal into N intervals according to the N-1 path reference array voltage, and if the range of the picked signal is 0 to 5v, the picked signal can be divided into 5 intervals of 0 to 1v,1 to 2v,2 to 3v,3 to 4v, and 4 to 5v according to the N-1 path reference array voltage of the reference voltage REF. The controller 400 can obtain the sectional interception control signal through the sectional interception control module 300, and then the controller 400 can obtain a specific section where the current acquired signal is located according to the sectional interception control signal, so that the controller 400 sends a channel selection control signal to the interception amplifying circuit 200, and the interception amplifying circuit 200 selects a specific section channel, performs corresponding bias and amplification processing on the acquired signal, and outputs an acquisition signal. It should be noted that, in this embodiment, bias processing corresponding to the sampled signals in different intervals is different, specifically, in this embodiment, the sampled signals in different intervals are biased to the same interval and amplified by different bias processing, so that the sampled signals are in the range interval of the reference voltage REF, and peak-peak values of the sampled signals intercepted in each section are infinitely close to the reference voltage, so as to achieve full-scale measurement, and further improve the accuracy of the sampled signals, thereby improving the accuracy of the final synthesized signal. In the above example, if the sampled signal range is 0-5V and the reference voltage REF is 5V, the N-1 path reference array voltages are 1V,2V,3V, and 4V. The corresponding picked signals are divided into 5 segments of 0-1V, 1-2V, 2-3V, 3-4V and 4-5V, and the bias processing can be carried out on the 5 segments through the interception amplifying circuit 200. Specifically, the interval 0-1V is biased by 0V, so that the interval 0-1V is formed; biasing the interval 1-2V by 1V to form an interval 0-1V; biasing the interval 2-3V by 2V to form an interval 0-1V; biasing the interval 3-4V by 3V to form an interval 0-1V; the interval 4-5V is offset by 4V to form an interval 0-1V. That is, the sampling signals of the 5 segments are all biased to the interval 0-1 v, and then the intercepting and amplifying circuit 200 amplifies the interval 0-1 v by 5 times, so that 5 segments are formed, the range is 0-5 v, each segment is located in the acquisition range of 0-5 v of the reference voltage REF, full-scale measurement can be performed on each segment in the embodiment, and the sampling speed is not influenced while the measurement accuracy is improved. After the acquisition signal is acquired by the intercept and amplifying circuit 200, the controller 400 may perform data synthesis according to the acquisition signal to form a synthesized signal as a final calculation result. The multiple of the improvement of the precision of the acquired signal is related to the number of signal segmentation interception, and the more the interception number is, the higher the precision is; according to the scheme, under the condition that the sampling rate is not influenced, the sampling precision of the signal is improved, the sampling precision can be adjusted through the amplification factor, the system is programmable, and the flexibility is high.
On the basis of the above embodiment, as shown in fig. 3, fig. 3 is a schematic structural diagram of a reference circuit module provided in the embodiment of the present invention, and the reference circuit module 100 may include N-1 circuit voltage divider 101 and N-1 follower circuits 102; the N-1 path voltage dividing circuit 101 is used for forming N-1 path reference array voltages distributed in an arithmetic progression according to the reference voltage REF，/>，…，/>) The method comprises the steps of carrying out a first treatment on the surface of the Outputting each path of reference array voltage through one-to-one corresponding reference voltage output end; follower circuits 102 are in one-to-one correspondence withThe reference voltage output end is connected for outputting the corresponding reference array voltage.
In the acquisition range corresponding to the reference voltage, for example, for the reference voltage 5V, the corresponding acquisition range is 0-5V, and the reference circuit module 100 can acquire each path of reference array voltage in the acquisition range through a multi-path voltage dividing circuit, for example, can form N-1 paths of reference array voltages distributed in an arithmetic progression through a voltage dividing mode. Each reference array voltage may be output through a unique corresponding follower circuit 102. The segmentation of the reference voltage REF is beneficial to realizing the segmentation of the sampled signals (analog signals in the embodiment), so that the signal peak value of each segment of sampled signals is infinitely close to the reference voltage, the reference voltage is used to the maximum extent, and the more the segments are, the higher the acquisition precision of the sampled signals is. The sampling precision is programmable, is related to the number of signal segmentation interception, is flexible to apply, and is more suitable for high-precision control application.
With continued reference to fig. 3, the reference voltage REF may be generated by the REF chip 103, specifically, the REF chip 103 may generate the reference voltage REF from the power supply signal VIN, where the power supply signal VIN may be connected to the ground GND through the voltage stabilizing capacitor C1, and the reference voltage REF may also be connected to the ground GND through the voltage stabilizing capacitor C1, so as to keep the power supply signal VIN and the reference voltage REF stable. Alternatively, the N-1-way voltage dividing circuit 101 may include N voltage dividing resistors R connected in series; the head end resistor of the N voltage dividing resistors connected in series is connected with a reference voltage REF; the tail resistor of the N voltage dividing resistors connected in series is connected with the ground end GND; the junction between adjacent divider resistors R serves as a reference voltage output. The multipath voltage dividing circuit can divide voltage through N voltage dividing resistors R, thereby realizing reference array voltages with different voltage values，/>，…，/>) The connection point between each adjacent divider resistor R can be used asA reference voltage output terminal. Alternatively, in order to form the reference array voltage of the arithmetic sequence, the embodiment may use voltage dividing resistors with the same resistance value for voltage division.
With continued reference to fig. 3, the follower circuit 102 may optionally include an operational amplifier; the first input ends of the operational amplifiers are connected with the reference voltage output ends in one-to-one correspondence; the second input end of the operational amplifier is connected with the output end of the operational amplifier. The following action of the operational amplifier is applied in this embodiment, so that the signal output by the output end of the operational amplifier is the same as the signal input by the first input end of the operational amplifier, that is, the operational amplifier outputs the reference array voltage output by the reference voltage output end. The operational amplifier has no amplifying function and is used for buffering only.
Fig. 4 is a schematic structural diagram of a segment interception control module according to an embodiment of the present invention, and optionally, the segment interception control module 300 may include: a comparison circuit array 301 and a logic circuit array 302; the comparison circuit array 301 includes N-1 comparators; the comparators are arranged in one-to-one correspondence with the N-1 paths of reference array voltages; the first input end of the comparator is connected with a voltage corresponding to one path of reference array，/>，…，/>) The second input ends of the comparators are connected with the sampled signals; the output ends of the comparators are connected with the logic circuit array 302 and are used for outputting the segment comparison control signals; the logic circuit array 302 is configured to output a segment intercept control signal according to the segment comparison control signal.
Each reference array voltage corresponds to a unique comparator. The comparator compares the corresponding reference array voltage with the sampled signal (analog signal), when the reference array voltage is greater than the sampled signal, the comparator outputs a high level, and when the reference array voltage is less than the sampled signal, the comparator outputs a low level, the comparator output level is the segment comparison control signal, and the logic circuit array 302 can collect the segment comparison control signals to form the segment interception control signal. Specifically, as shown in table 1, table 1 is a truth table of a segment interception control signal output by a logic circuit array, by comparing a sampled signal with a reference array voltage, the segment where the sampled signal is located can be directly locked, and a corresponding bias voltage is obtained according to the segment, the logic circuit array 302 sends the truth table of the segment interception control signal to the controller 400, and the controller 400 can resolve and select an analog channel of the interception amplifying circuit 200 corresponding to the sampled signal according to the segment interception control signal, so that corresponding bias and amplifying processing can be performed on the sampled signal in time.
Fig. 5 is a schematic structural diagram of an intercept and amplifying circuit according to an embodiment of the present invention, and optionally, the intercept and amplifying circuit 200 may include: an analog channel selection circuit 201 and a bias amplification circuit 202; the analog channel selection circuit 201 is respectively connected with the reference circuit module 100 and the controller 400, and is used for outputting bias voltage according to the N-1 path reference array voltage and the channel selection control signal; the bias amplifying circuit 202 is connected with the analog channel selecting circuit 201, and is used for performing bias and amplification processing on the acquired signal according to the bias voltage and outputting the acquired signal; the acquisition signal is located in an acquisition range corresponding to the reference voltage REF. The analog channel selection circuit 201 (which may be an analog switch) is capable of selecting the corresponding segment for the picked-up signal for biasing and amplifying processing according to the channel selection control signal. Specifically, the analog channel selection circuit 201 can select a corresponding voltage value from the N-1 channel reference array voltage and the zero voltage as the bias voltage according to the channel selection control signal, so that the bias amplification circuit 202 performs bias processing on the sampled signal according to the bias voltage, and further amplifies the sampled signal through the amplifier, so that the output sampled signal is located in a sampling range corresponding to the reference voltage REF and is infinitely close to the value of the reference voltage, the precision of the sampled signal is N times of the initial sampling precision, and the scheme can improve the sampling precision of the signal under the condition that the sampling rate is not affected. The channel selection control signal is given in a mode of combining a comparator and a logic gate circuit, and an analog switch (an analog channel selection circuit) is controlled by the signal to select a corresponding selected channel for acquisition. The signal sampling system of the embodiment has lower cost, and can increase sampling precision by times by adding a small number of components and software codes.
With continued reference to fig. 5, the bias amplifying circuit 202 may optionally include: a first stage operational amplifier and a second stage operational amplifier; the first input end of the first-stage operational amplifier is connected with a bias voltage Ref_out through a second resistor R2; the first input end of the first-stage operational amplifier is connected with the ground end GND through a third resistor R3; the second input end of the first-stage operational amplifier is connected with the sampled signal through a first resistor R1; the second input end of the first-stage operational amplifier is connected with the output end of the first-stage operational amplifier through a fourth resistor R4; the output end of the first-stage operational amplifier is connected with the second input end of the second-stage operational amplifier through a sixth resistor R6; the first input end of the second-stage operational amplifier is connected with the ground end GND through a fifth resistor R5; the second input end of the second-stage operational amplifier is connected with the output end of the second-stage operational amplifier through a seventh resistor R7; the output of the second stage operational amplifier is used as the output of the bias amplifying circuit 202 for outputting the acquisition signal. The first-stage operational amplifier is a bias circuit and can bias the sampled signal according to the bias voltage, and the second-stage operational amplifier is an amplifying circuit, so that the sampled signal is positioned in the acquisition range corresponding to the reference voltage REF.
Optionally, the output terminal voltage of the first stage operational amplifierThe method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>Is a bias voltage; />Is a picked-up signal; the acquisition signal->The method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>A magnification factor for the second stage operational amplifier; r6 is the resistance value of the sixth resistor; r7 is the resistance value of the seventh resistor. In this embodiment, the resistances of the controllable resistors R1, R2, R3, and R4 are equal, and the output voltage of the first-stage operational amplifier is obtained according to the operational principle of operational amplifier with short-circuit and virtual-circuit. For the output voltage (acquisition signal) of the second stage operational amplifier, since the number of segments N is related to the number of amplifications of the acquired signal, optionally +.>The intercepted signal is completely in the acquisition range and is infinitely close to the reference voltage, and the acquisition precision of the acquired signal is improved.
Optionally, as shown in fig. 4 and fig. 5, the signal sampling system further includes a mode converter (ADC) 500, where the mode converter 500 can convert the collected signal from an analog signal to a digital signal and send the digital signal to the controller 400, and the embodiment intercepts the collected signal in a segmented manner, so that the sampling rate is not affected, and the sampling rate is only related to the sampling rate of the ADC chip, and the embodiment can implement high-precision signal detection by using the ADC chip with lower precision and lower cost.
Optionally, the controller 400 is specifically configured to generate a composite coefficient according to the bias voltage and the amplification factor of the acquired signal, and take the product of the composite coefficient and the acquired signal as the composite signal. In this embodiment, the acquired signal is a signal after the offset and amplification processing, and the accuracy is higher, but not the initial acquired signal, in order to restore to the initial acquired signal, the embodiment generates a corresponding synthesis coefficient according to the offset voltage and the amplification factor of the acquired signal, so that the product of the synthesis coefficient and the acquired signal is used as the synthesized signal, and the synthesized signal is the size of the initial acquired signal. The invention adopts a method combining software and hardware to sample and process signals, the hardware design carries out sectional interception, biasing and amplification processing on the sampled signals, and the analog switch is controlled to select a specific analog channel through the channel selection control signal, so as to collect, synthesize data of the final collection result and finally realize the improvement of the precision of the collection signals.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A signal sampling system, comprising: the device comprises a reference circuit module, a segmentation interception control module, a controller and an interception amplifying circuit;
the reference circuit module is used for segmenting the reference voltage to form N-1 paths of reference array voltages; n is an integer greater than 1; the sectioning interception control module is connected with the reference circuit module and is used for dividing the acquired signal into N sections according to the reference array voltage to intercept and outputting a sectioning interception control signal to the controller; the controller is used for generating a channel selection control signal according to the segmentation interception control signal; the intercepting and amplifying circuit is respectively connected with the controller and the reference circuit module and is used for carrying out biasing and amplifying treatment on the acquired signal according to the channel selection control signal and the reference array voltage and outputting the acquired signal; the controller is also configured to form a composite signal based on the acquisition signal.
2. The signal sampling system of claim 1, wherein the reference circuit module comprises an N-1 circuit voltage divider circuit and N-1 follower circuits;
the N-1 path voltage dividing circuit is used for forming N-1 path reference array voltages distributed in an arithmetic series according to the reference voltages; outputting each path of reference array voltage through one-to-one corresponding reference voltage output end;
the follower circuits are connected with the reference voltage output ends in one-to-one correspondence and are used for outputting corresponding reference array voltages.
3. The signal sampling system of claim 2, wherein the N-1 voltage divider circuit comprises N voltage divider resistors connected in series;
the head end resistor of the N voltage dividing resistors connected in series is connected with the reference voltage; the tail resistor of the N voltage dividing resistors connected in series is connected with the ground terminal; the connection point between adjacent voltage dividing resistors is used as a reference voltage output end.
4. The signal sampling system of claim 2, wherein the follower circuit comprises an operational amplifier;
the first input ends of the operational amplifiers are connected with the reference voltage output ends in one-to-one correspondence; the second input end of the operational amplifier is connected with the output end of the operational amplifier.
5. The signal sampling system of claim 1, wherein the segmentation intercept control module comprises: a comparison circuit array and a logic circuit array;
the comparison circuit array comprises N-1 comparators; the comparator is arranged in one-to-one correspondence with the N-1 paths of reference array voltages; the first input end of the comparator is connected with a corresponding path of reference array voltage, and the second input ends of the comparators are connected with the sampled signals; the output ends of the comparators are connected with the logic circuit array and are used for outputting a segment comparison control signal;
the logic circuit array is used for outputting a segmentation interception control signal according to the segmentation comparison control signal.
6. The signal sampling system of claim 1, wherein the intercept amplification circuit comprises: an analog channel selection circuit and a bias amplification circuit;
the analog channel selection circuit is respectively connected with the reference circuit module and the controller and is used for outputting bias voltage according to the N-1 path reference array voltage and the channel selection control signal;
the bias amplifying circuit is connected with the analog channel selecting circuit and is used for carrying out bias and amplification processing on the acquired signal according to the bias voltage and outputting the acquired signal; the acquisition signal is positioned in an acquisition range corresponding to the reference voltage.
7. The signal sampling system of claim 6, wherein the bias amplifying circuit comprises: a first stage operational amplifier and a second stage operational amplifier;
the first input end of the first-stage operational amplifier is connected to the bias voltage through a second resistor; the first input end of the first-stage operational amplifier is connected with the ground end through a third resistor; the second input end of the first-stage operational amplifier is connected with the sampled signal through a first resistor; the second input end of the first-stage operational amplifier is connected with the output end of the first-stage operational amplifier through a fourth resistor; the output end of the first-stage operational amplifier is connected with the second input end of the second-stage operational amplifier through a sixth resistor;
the first input end of the second-stage operational amplifier is connected with the ground end through a fifth resistor; the second input end of the second-stage operational amplifier is connected with the output end of the second-stage operational amplifier through a seventh resistor; and the output end of the second-stage operational amplifier is used as the output end of the bias amplifying circuit and is used for outputting the acquisition signal.
8. The signal sampling system of claim 7, wherein the first resistor, the second resistor, the third resistor, and the fourth resistor have equal resistance values;
the output end voltage of the first stage operational amplifierThe method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>Is a bias voltage; />Is a picked-up signal;
the acquisition signalThe method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>A magnification factor for the second stage operational amplifier; r6 is the resistance value of the sixth resistor; r7 is the resistance value of the seventh resistor.
9. The signal sampling system of claim 8, wherein the signal sampling system comprises a plurality of sampling circuits,。
10. the signal sampling system of claim 6, wherein the controller is specifically configured to generate a composite coefficient based on the bias voltage and the amplification of the acquired signal, and to take the product of the composite coefficient and the acquired signal as the composite signal.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101915868A (en) * | 2010-07-14 | 2010-12-15 | 中国科学院电工研究所 | Acquisition circuit for improving acquisition precision of voltage signal |
| CN209460615U (en) * | 2019-04-16 | 2019-10-01 | 西安建筑科技大学 | A kind of SCM Based A/D acquisition device |
| CN112595415A (en) * | 2020-12-16 | 2021-04-02 | 合肥利弗莫尔仪器科技有限公司 | Photoelectric signal segmentation detection and acquisition device |
| CN115529041A (en) * | 2022-10-13 | 2022-12-27 | 湖北亿纬动力有限公司 | Sectional optional signal conditioning circuit and measuring device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101915868A (en) * | 2010-07-14 | 2010-12-15 | 中国科学院电工研究所 | Acquisition circuit for improving acquisition precision of voltage signal |
| CN209460615U (en) * | 2019-04-16 | 2019-10-01 | 西安建筑科技大学 | A kind of SCM Based A/D acquisition device |
| CN112595415A (en) * | 2020-12-16 | 2021-04-02 | 合肥利弗莫尔仪器科技有限公司 | Photoelectric signal segmentation detection and acquisition device |
| CN115529041A (en) * | 2022-10-13 | 2022-12-27 | 湖北亿纬动力有限公司 | Sectional optional signal conditioning circuit and measuring device |
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