CN116884857A - Method for forming package and package structure - Google Patents

Method for forming package and package structure Download PDF

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Publication number
CN116884857A
CN116884857A CN202310528841.9A CN202310528841A CN116884857A CN 116884857 A CN116884857 A CN 116884857A CN 202310528841 A CN202310528841 A CN 202310528841A CN 116884857 A CN116884857 A CN 116884857A
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CN
China
Prior art keywords
metal bump
layer
photosensitive
top surface
dielectric layer
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Pending
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CN202310528841.9A
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Chinese (zh)
Inventor
吴志伟
施应庆
邱文智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/929,180 external-priority patent/US20230411329A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116884857A publication Critical patent/CN116884857A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

According to an embodiment of the present application, a method for forming a package is provided that includes forming a first package assembly, forming the first package assembly including forming a first dielectric layer having a first top surface, and forming a first conductive feature. The first conductive feature includes a via embedded in the first dielectric layer and a metal bump having a second top surface that is higher than the first top surface of the first dielectric layer. The method further includes dispensing a photosensitive layer, wherein the photosensitive layer covers the metal bump, and performing a photolithography process to form a recess in the photosensitive layer. The metal bump is exposed to the recess, and the photosensitive layer has a third top surface higher than the metal bump. The second package assembly is bonded to the first package assembly and the solder regions extend into the grooves to bond the metal bumps to the second conductive features in the second package assembly. According to other embodiments of the present application, a package structure is also provided.

Description

Method for forming package and package structure
Technical Field
Embodiments of the present application relate to methods for forming packages and package structures.
Background
In the formation of integrated circuits, package components (such as transistors) are formed at the surface of a semiconductor substrate in a wafer. Metal bumps may be formed on the surface of the wafer. In the packaging process, the top die may be bonded to the bottom wafer by the solder regions. The bottom wafer saw may then be diced into dies. The formation process may cause difficulty due to the reduction of the pitch of the metal bump. For example, as the pitch decreases, the likelihood of solder bridging on adjacent metal bumps increases.
Disclosure of Invention
According to an embodiment of the present application, there is provided a method for forming a package including forming a first package assembly, the forming the first package assembly including: forming a first dielectric layer comprising a first top surface; a first conductive feature is formed. Wherein the first conductive member comprises: a via extending into the first dielectric layer; and a metal bump including a second top surface higher than the first top surface of the first dielectric layer. Forming the first package assembly further includes: dispensing a photosensitive layer, wherein the photosensitive layer covers the metal bump; and performing a photolithography process to form a groove in the photosensitive layer, wherein the metal bump is exposed to the groove, and wherein the photosensitive layer includes a third top surface higher than the metal bump. The method for forming the package further includes bonding the second package component to the first package component, wherein the solder region extends into the recess to bond the metal bump to the second conductive feature in the second package component.
According to another embodiment of the present application, there is provided a package structure including a first package assembly including: a dielectric layer; a conductive member. Wherein the conductive member comprises: a via embedded in the dielectric layer; and a metal bump protruding above the first top surface of the dielectric layer. And the first package component includes a photosensitive structure extending from a lower level to a higher level, wherein the lower level is below the second top surface of the metal bump and the higher level is above the second top surface of the metal bump. And the package structure includes a solder region extending into the photosensitive structure to connect to the metal bump, wherein the solder region extends laterally beyond an edge of the metal bump.
According to yet another embodiment of the present application, there is provided a package structure including a device die including: a first photosensitive structure; a first metal bump and a second metal bump adjacent to each other and extending above the first photosensitive structure; a second photosensitive structure over and contacting the first photosensitive structure. The package structure further includes a first solder region and a second solder region extending into the second photosensitive structure, wherein a portion of the second photosensitive structure separates the first solder region from the second solder region, and wherein the first metal bump and the second metal bump are below a first upper portion of the first solder region and a second upper portion of the second solder region, respectively; and a second package assembly. Wherein the second package assembly comprises: a first conductive member bonded to the first metal bump through the first solder region; and a second conductive member bonded to the second metal bump through the second solder region.
Embodiments of the present application relate to dielectric barrier layers and methods of forming the same.
Drawings
Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-13 and 14A illustrate cross-sectional views of intermediate stages in the formation of a package including a sawed device die, in accordance with some embodiments.
Fig. 14B illustrates a cross-sectional view of a package including a reconstituted wafer, in accordance with some embodiments.
Fig. 15 illustrates a cross-sectional view of a package according to some embodiments.
Fig. 16 illustrates a top view of a package according to some embodiments.
Fig. 17 illustrates a process flow for forming a package according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, of the different components used to implement the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
A package and a method of forming the same are provided. According to some embodiments of the present disclosure, a package includes a first package component (such as a device die) bonded to a second package component. The first package component includes metal bumps protruding beyond a surface dielectric layer of the first package component. A photopolymer is then applied over the metal bumps and surface dielectric layer, and then exposed and developed to form recesses in the photopolymer to expose the metal bumps. The solder regions bond the metal bumps to the second package component. The recess is for accommodating the solder region and has a function of preventing solder bridging to an adjacent solder region. The embodiments discussed herein will provide examples to enable the making or using of the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of the various embodiments. Like reference numerals are used to denote like elements throughout the various views and exemplary embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.
Fig. 1-13 and 14A illustrate cross-sectional views of intermediate stages in the formation of a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in the process flow 200 as shown in fig. 17.
Fig. 1 shows a cross-sectional view of a package assembly 20. According to some embodiments, package assembly 20 is or includes a device wafer including active devices and possibly passive devices, which are represented as integrated circuit devices 26. The package assembly 20 may include a plurality of chips 22 (also referred to as (device) dies), one of the device dies 22 being shown. According to alternative embodiments, the package assembly 20 is an interposer wafer that does not contain active devices and may or may not include passive devices. According to yet another alternative embodiment, package assembly 20 is or includes a package substrate tape that includes a coreless package substrate or a core package substrate having a core therein. In the discussion that follows, a device wafer is used as an example of the package assembly 20, and the package assembly 20 is therefore referred to as the wafer 20.
According to some embodiments, wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a group III-V compound semiconductor, such as GaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or the like. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate 24 to isolate active areas in semiconductor substrate 24. Although not shown, a through-hole may (or may not) be formed to extend into the semiconductor substrate 24, wherein the through-hole is for electrically interconnecting components on opposite sides of the semiconductor substrate 24.
According to some embodiments, wafer 20 includes integrated circuit devices 26, integrated circuit devices 26 being formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit device 26 may include transistors, resistors, capacitors, diodes, and the like. Details of integrated circuit device 26 are not shown here. According to alternative embodiments, wafer 20 is used to form an interposer (which does not contain active devices), and substrate 24 may be a semiconductor substrate or a dielectric substrate.
An interlayer dielectric (ILD) 28 is formed over semiconductor substrate 24 and fills spaces between gate stacks of transistors (not shown) in integrated circuit device 26. According to some embodiments, ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, low-k dielectric materials, and the like. ILD 28 may be formed using spin-on, flowable Chemical Vapor Deposition (FCVD), and the like. According to some embodiments, ILD 28 is formed using a deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), low Pressure Chemical Vapor Deposition (LPCVD), or the like.
Contact plugs 30 are formed in ILD 28 and are used to electrically connect integrated circuit device 26 to the metal lines and vias thereon. According to some embodiments, the contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multilayers thereof. The forming of the contact plug 30 may include forming a contact opening in the ILD 28, filling a conductive material into the contact opening, and performing a planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, to level a top surface of the contact plug 30 with a top surface of the ILD 28.
An interconnect structure 32 is formed over ILD 28 and contact plug 30. Interconnect structure 32 includes metal lines 34 and vias 36, with metal lines 34 and vias 36 being formed in a dielectric layer 38, also referred to as an inter-metal dielectric (IMD). Metal lines in the same layer are collectively referred to as a metal layer below. According to some embodiments, interconnect structure 32 includes a plurality of metal layers including metal lines 34 interconnected by through vias 36. The metal lines 34 and the vias 36 may be formed of copper or copper alloy, and they may also be formed of other metals. According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be less than about 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen Silsesquioxane (HSQ), methyl Silsesquioxane (MSQ), or the like. According to some embodiments, forming dielectric layer 38 includes depositing a porogen-containing dielectric material in dielectric layer 38, and then performing a curing process to drive off the porogen so that the remaining dielectric layer 38 is porous.
Forming metal lines 34 and vias 36 in dielectric layer 38 may include a single damascene process and/or a dual damascene process. Each of the damascene structures may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum nitride, and the like.
The metal lines 34 include top conductive (metal) features (denoted 34A), such as metal lines, metal pads, or vias. The top conductive feature 34A is located in a top dielectric layer (shown as dielectric layer 38A) that is the top layer of dielectric layer 38. According to some embodiments, top dielectric layer 38A is formed of a non-low-k dielectric material, which may include silicon nitride, undoped Silicate Glass (USG), silicon oxide, or the like, or multilayers thereof. According to an alternative embodiment, dielectric layer 38A is formed of a low-k dielectric material similar to the material of the lower dielectric layer of dielectric layer 38. Dielectric layer 38A may also have a multi-layer structure, for example comprising two USG layers and a silicon nitride layer therebetween. The top metal feature 34A may also be formed of copper or copper alloy and may have a dual damascene structure or a single damascene structure.
A passivation layer 40 (sometimes referred to as passivation-1 or passivation-1) is formed over the interconnect structure 32. The corresponding process is shown as process 202 in process flow 200 as shown in fig. 17. According to some embodiments, passivation layer 40 is formed of a non-low k dielectric material having a dielectric constant greater than or equal to the dielectric constant of silicon oxide. Passivation layer 40 may be formed of or include an inorganic dielectric material that may be selected from, and is not limited to, silicon nitride (SiN), silicon oxide (SiO) 2 ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiC), undoped Silicate Glass (USG), and the like, combinations thereof, and multilayers thereof.
The passivation layer 40 is patterned in an etching process, and a via 42 is formed in the passivation layer 40 to contact the metal line/pad 34A. The via 42 may be formed by a single damascene process according to some embodiments, or may be formed with the metal pad 44.
A metal pad 44 is formed over the via hole 42, and the metal pad 44 contacts the via hole 42. The corresponding process is shown as process 204 in process flow 200 as shown in fig. 17. Metal pad 44 may be electrically connected to integrated circuit device 26 by conductive features such as metal line 34 and via 36. According to some embodiments, metal pad 44 is an aluminum pad or an aluminum copper pad, and other metal materials may be used. According to some embodiments, the metal pad 44 has an aluminum percentage of greater than about 90% or 95%.
Referring to fig. 2, a passivation layer 46 is formed on the metal pad 44. Passivation layer 46 may be a single layer or a composite layer and may be formed of a non-porous material. According to some embodiments, passivation layer 46 is a composite layer including a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. Passivation layer 46 is then patterned by an etching process to form openings 47 such that passivation layer 46 may cover portions of metal pads 44 and some other portions of the top surfaces of metal pads 44 are exposed through openings 47.
Fig. 3 illustrates the formation of dielectric layer 48. According to some embodiments, the dielectric layer 48 comprises a polymer, which may include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. Thus, the dielectric layer 48 is alternatively referred to as a polymer layer 48, but it may also be formed of or comprise other dielectric materials, such as inorganic dielectric materials. The corresponding process is shown as process 206 in process flow 200 as shown in fig. 17. Forming polymer layer 48 may include spin coating and then curing polymer layer 48. An opening 50 is formed in the polymer layer 48, for example, by an exposure process followed by a development process.
Fig. 4-6 illustrate the formation of vias and overlying conductive pads. Referring to fig. 4, a metal seed layer 54 is deposited over the polymer layer. The corresponding process is shown as process 208 in process flow 200 as shown in fig. 17. Metal seed layer 54 is a conductive seed layer and may be a metal seed layer. According to some embodiments, the metal seed layer 54 is a composite layer comprising two or more layers. For example, the metal seed layer 54 may include a lower layer and an upper layer, wherein the lower layer may include a titanium layer, a titanium nitride layer, a tantalum nitride layer, and the like. The material of the upper layer may comprise copper or a copper alloy. According to an alternative embodiment, the metal seed layer 54 is a single layer, which may be a copper layer, for example. The metal seed layer 54 may be formed using Physical Vapor Deposition (PVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), etc., as well as other suitable methods. Metal seed layer 54 is a conformal layer that extends into opening 50.
Fig. 4 also shows the formation of a patterned plating mask 56. The corresponding process is shown as process 210 in process flow 200 as shown in fig. 17. According to some embodiments, the plating mask 56 is formed of or includes photoresist. The plating mask 56 is patterned to form openings 58 through which portions of the metal seed layer 54 are exposed. Patterning of the plating mask 56 may include an exposure process and a development process.
Fig. 5 shows the plating of a conductive material (component) 60 onto the openings 58 and the metal seed layer 54. The corresponding process is shown as process 212 in process flow 200 as shown in fig. 17. According to some embodiments, forming the conductive member 60 includes a plating process, which may include an electrochemical plating process, an electroless plating process, and the like. Plating may be performed in a plating chemistry solution. The conductive member 60 may include copper, aluminum, nickel, tungsten, etc., alloys thereof, and/or multilayers thereof. According to some embodiments, the conductive member 60 comprises copper and is free of aluminum.
Next, the plating mask 56 as shown in fig. 5 is removed, and portions of the underlying metal seed layer 54 are exposed. In a subsequent process, an etching process is performed to remove the exposed portions of the metal seed layer 54. The corresponding process is shown as process 214 in process flow 200 as shown in fig. 17. The resulting structure is shown in FIG. 6. Throughout the description, the conductive material 60 and corresponding underlying portions of the metal seed layer 54 are collectively referred to as redistribution lines (RDLs) 62.RDL 62 may include vias 64 (also referred to as vias or conductive vias) extending into polymer layer 48 and pad portions 66 (also referred to as conductive pads or metal pads) over polymer layer 48. According to some embodiments, conductive pad 66 has a flat top surface. According to an alternative embodiment, the top surface of the conductive pad 66 has a recess directly above the corresponding conductive via 64 due to the plating process, wherein a dashed line 67 is used to represent the recessed top surface of the conductive pad 66.
Fig. 7 illustrates the formation of a dielectric layer 70. According to some embodiments, the dielectric layer 70 is formed of or includes a polymeric (organic) layer of a polymer (which may be photosensitive), such as polyimide, PBO, BCB, epoxy, or the like. The corresponding process is shown as process 216 in process flow 200 as shown in fig. 17. According to some embodiments, forming the dielectric layer 70 includes coating the dielectric layer in a flowable form, and then performing a curing process to harden the dielectric layer 70. A planarization process, such as a CMP process or a mechanical polishing process, may or may not be performed to flush the top surface of the dielectric layer 70. Thus, the dielectric layer 70 is also referred to as a planarization layer. According to an alternative embodiment, the planarization process is not performed and the top surface of the dielectric layer 70 may have a topography that reflects the topography of the underlying components. For example, the portion of dielectric layer 70 directly above conductive pad 66 may have a top surface that is higher than the top surface of the surrounding portion of dielectric layer 70.
In a subsequent process, the dielectric layer 70 is patterned, for example, by an exposure process and a photo-development process. Openings 72 are thus formed in dielectric layer 70 and expose conductive pads 66. After the photo development process, the dielectric layer 70 is also post-baked so that even if the dielectric layer 70 receives light used in the exposure of the photosensitive layer 84 (fig. 9) again in a subsequent process, the dielectric layer 70 will not be patterned again.
Fig. 8 illustrates formation of UBM and formation of metal pillars and solder regions (if formed) according to some embodiments. The corresponding process is shown as process 218 in process flow 200 as shown in fig. 17. In an example formation process, metal seed layer 74 is deposited as a blanket layer, with some remaining portions of blanket seed layer 74 shown in fig. 8. According to some embodiments, metal seed layer 74 includes a titanium layer and a copper layer over the titanium layer. According to an alternative embodiment, the entire metal seed layer 74 is formed of a homogenous material, such as copper or a copper alloy, wherein the homogenous material is in contact with the dielectric layer 70 and the top surface of the conductive pad 66. The metal seed layer 74 may be formed by PVD, ALD, or the like.
Next, a conductive material 76 is plated. The process for plating the conductive material 76 may include forming a patterned plating mask (not shown) and plating the conductive material 76 in openings in the patterned plating mask. The patterned plating mask may include photoresist, and may be a single layer plating mask, a double layer plating mask, or a triple layer plating mask. The conductive material 76 may comprise copper, nickel, palladium, aluminum, alloys thereof, and/or multilayers thereof. According to some embodiments, a solder layer is also plated on the conductive material 76 and in the openings in the patterned plating mask. The patterned plating mask is then removed.
According to some embodiments, solder layer 78 is plated over conductive material 76. Plating is performed using the same plating mask used for plating material 76. According to an alternative embodiment, the solder layer is not plated. Thus, the solder layers 78 are shown as dashed lines to indicate that they may or may not be formed.
Blanket metal seed layer 74 is then etched and the portions of metal seed layer 74 exposed after removal of the plating mask are removed, while the portions of metal seed layer 74 directly beneath conductive material 76 are left. The resulting structure is shown in FIG. 8. The remaining portion of the metal seed layer is also referred to as Under Bump Metallization (UBM) 74.UBM 74 and conductive material 76 combine to form via 80 and electrical connector 82. In the discussion that follows, the electrical connector 82 is also referred to as a metal bump 82. The metal bump 82 protrudes above the top surface of the dielectric layer 70. According to some embodiments in which solder layer 78 is also formed, a reflow process may be performed after etching the metal seed layer such that solder layer 78 has a rounded surface.
Referring to fig. 9, a dielectric layer 84 is formed. The dielectric layer 84 may be a photosensitive layer that includes a photosensitive polymer such as polyimide, PBO, BCB, or the like. Dielectric layer 84 is coated on UBM 74 by spin coating. The corresponding process is shown as process 220 in process flow 200 as shown in fig. 17. After coating, the photosensitive layer 84 is pre-baked to drive off the solvent therein.
The top surface of the photosensitive layer 84 is higher than the top surface of the metal bump 82. It will be appreciated that since the metal bump 82 protrudes above the top surface of the dielectric layer 70, the top surface of the photosensitive layer 84 may not be flat and the portion of the photosensitive layer 84 directly above the metal bump 82 may be higher than the other portions. According to some embodiments, the top surface of photosensitive layer 84 is planarized in a polishing process, such as a CMP process and/or a mechanical polishing process. As a result, the entire top surface of photosensitive layer 84 is flat. According to an alternative embodiment, the planarization process is not performed. As a result, the top surface of the photosensitive layer 84 includes an upper (raised) portion directly above the metal bump 82, and a lower portion laterally offset from the metal bump 82.
According to alternative embodiments, the dielectric layer 84 may be an inorganic dielectric layer, which may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and the like. Thus, the dielectric layer 84 will be patterned by a process that includes forming a patterned etch mask (such as photoresist) over the dielectric layer 84, and then etching the dielectric layer 84 using the patterned etch mask to define the pattern.
According to some embodiments, wherein the dielectric layer 84 comprises a photosensitive material, an exposure process 88 is performed to expose the photosensitive layer 84. The corresponding process is shown as process 222 in process flow 200 as shown in fig. 17. The exposure process 88 is performed using a photolithography mask 86, and the photolithography mask 86 includes a transparent pattern 86A allowing light to pass therethrough and an opaque pattern 86B blocking light. The photosensitive layer 84 may be formed of a positive photosensitive material in which exposed portions will be removed upon development and unexposed portions will remain. Alternatively, the photosensitive layer 84 may be formed of a negative photosensitive material in which the unexposed portions will be removed and the exposed portions will remain upon development. Fig. 9 shows an example in which the photosensitive layer 84 is positive and the transparent pattern 86A in the photolithographic mask 86 is directly over the metal bump 82. According to other embodiments, a negative photosensitive layer 84 may be used, and the transparent and opaque patterns will be opposite to the pattern shown in fig. 9.
In the example shown, the pattern 86A directly above the metal bump 82 has a lateral dimension W2 that is greater than the lateral dimension W1 of the metal bump 82. Further, the pattern 86A may extend laterally beyond the edges of the metal bump 82. According to some embodiments, pattern 86A may extend laterally beyond the edges of metal bump 82 in all lateral directions (when viewed from the top) parallel to the top surface of photosensitive layer 84. According to alternative embodiments, pattern 86A may extend laterally beyond the edges of some, but not all, of metal bumps 82, with the lateral direction being parallel to the top surface of photosensitive layer 84.
According to an alternative embodiment, the pattern 86A may have its edges vertically aligned with the corresponding edges of the metal bump 82 such that the subsequently formed recess 90 (fig. 10) has boundaries vertically aligned with the corresponding edges of the underlying metal bump 82. According to alternative embodiments, the pattern 86A may have its edges laterally recessed from the corresponding edges of the metal bumps 82 such that the subsequently formed grooves 90 (fig. 10) have boundaries laterally recessed from the corresponding edges of the underlying metal bumps 82, and thus the lateral dimensions of the grooves are smaller than the lateral grooves of the underlying metal bumps 82.
Referring to fig. 10, the exposed photosensitive layer 84 is developed, and a groove 90 is formed in the photosensitive layer 84, exposing the metal bump 82. The corresponding process is shown as process 224 in process flow 200 as shown in fig. 17. According to some embodiments, bottom surface 90BS1 of recess 90 is coplanar (or substantially coplanar, e.g., has a height difference of less than about 1 μm or about 0.5 μm) with the top surface of metal bump 82. Thus, portions of photosensitive layer 84 are directly beneath grooves 90. This can be achieved by controlling the depth of focus in the exposure process, controlling the light intensity in the exposure process, controlling the duration of the exposure, etc.
According to an alternative embodiment, the bottom surface of photosensitive layer 84 is below the top surface of metal bump 82 and above top surface 70TS of dielectric layer 70. This can also be achieved by controlling the depth of focus in the exposure process, controlling the light intensity, controlling the duration of the exposure, etc. The bottom surface of the corresponding recess 90 is shown using dashed line 90BS 2.
According to yet another alternative embodiment, the top surface 70TS of the dielectric layer 70 is exposed to the recess 90. The corresponding bottom surface of the recess 90 is labeled 90BS3. The sidewalls of the corresponding recess 90 are also shown as 90SW. Since dielectric layer 70 has been post-baked, it is no longer affected by the exposure and development process used to pattern photosensitive layer 84. Thus, although the dielectric layer 70 may receive light for the exposure process 88 (fig. 9), the top surface 70TS of the dielectric layer 70 will not be recessed even if the dielectric layer 70 is exposed to the recess 90.
As described in the preceding paragraphs, the photosensitive layer 84 may or may not be planarized. According to an embodiment in which photosensitive layer 84 is planarized, the top surface of photosensitive layer 84 (except for the top surface under recess 90) is coplanar and is shown as top surface 84TS1. According to an alternative embodiment in which the photosensitive layer 84 is not planarized, the top surface 84TS2 of the portion of the photosensitive layer 84 surrounding the recess 90 may be raised to be higher than the top surface 84TS1 of the portion of the photosensitive layer 84 between the raised portions. The raised top surface 84TS2 is shown using dashed lines. As shown in fig. 14A, 14B and 15, top surface 84TS1 and top surface 84TS2 may also be observed in the final package. In subsequent figures, the raised top surface 84TS2 may be shown for only one of the grooves 90, while other grooves 90 may also have raised top surfaces 84TS2.
Referring to fig. 11, the package assembly 94 is aligned with the wafer 20. Although one package assembly 94 is shown, there may be multiple package assemblies 94, each package assembly 94 being bonded to one of the device die 22. In accordance with some embodiments, a dielectric layer 95 is formed on the surface of the package assembly 94. The dielectric layer 95 may be formed of a solder mask, an organic dielectric material, an inorganic dielectric material, or the like. According to some embodiments, package assembly 94 is or includes a device die (including active devices therein), an interposer, a package substrate, a printed circuit board, a package, and the like. Throughout the description, the package assembly 94 is also referred to as a top die. The package assembly 94 includes an electrical connector 96, which may be a metal post (such as a copper post), a bond pad, or the like. The electrical connector 96 is formed at a surface of the package assembly 94 and may or may not protrude beyond a bottom surface of the dielectric layer 95. Solder regions 98 are formed on the electrical connector 96. In the alignment process, the solder regions 98 and the electrical connectors 96 are aligned with the metal bumps 82.
The package assembly 94 is then placed on the device die 22 in the wafer 20. Solder regions 98 are inserted into the grooves 90. Next, a reflow process is performed to reflow solder regions 98 and solder layers 78 (if formed) so that package assembly 94 is bonded to device die 22. The corresponding process is shown as process 226 in process flow 200 as shown in fig. 17. The resulting solder regions are referred to as solder regions 98', as shown in fig. 12. In the bonding process, the bonding process is self-aligned because the solder regions 98' and the electrical connectors 96 are bounded by the sidewalls of the recess 90.
After the solder regions 98' are cured, the bottom surface of the electrical connector 96 may be above the top surface 84TS1 and/or the top surface 84TS2 of the photosensitive layer 84, the bottom surface of the electrical connector 96 may be flush with the top surface 84TS1 and/or the top surface 84TS2 of the photosensitive layer 84, or the bottom surface of the electrical connector 96 may be below the top surface 84TS1 and/or the top surface 84TS2 of the photosensitive layer 84. When the bottom surface of the electrical connector 96 is lower than the top surface 84TS2 of the photosensitive layer 84, the bottom portion of the electrical connector 96 is also inserted into the recess 90.
Referring to fig. 13, an underfill 102 is dispensed between wafer 20 and package assembly 94. The corresponding process is shown as process 228 in process flow 200 as shown in fig. 17. According to some embodiments, the underfill 102 fills the recess 90, partially or completely. For example, an upper portion of the recess 90 not occupied by the solder region 98' may be filled with an underfill 102. The bottom portion of the recess 90 may be an air gap when the solder region 98' blocks the flow of the underfill 102 into the bottom portion of the recess 90. Otherwise, the bottom portion of the recess 90 is also filled with an underfill 102.
In a subsequent process, as shown in fig. 14A, a sealant 104 is applied to encapsulate the package assembly 94. The corresponding process is shown as process 230 in process flow 200 as shown in fig. 17. Thereby forming reconstituted wafer 106. According to some embodiments, as shown in fig. 14A, the reconstituted wafer 106 is sawed along scribe lines 108 to separate the reconstituted wafer 106 into discrete packages 106'. The corresponding process is shown as process 232 in process flow 200 as shown in fig. 17. The discrete packages 106 'are identical to each other, with each package 106' including the device die 22 and the package assembly 94. In the resulting package 106', the edges of the encapsulant 104 are vertically aligned with the edges of the device die 22.
As discussed in the previous embodiments, the recess 90 may have a bottom surface that is flush with the top surface of the metal bump 82 or below the top surface of the metal bump 82. Also, the top surface of the dielectric layer 70 may or may not be exposed to the recess 90. According to some embodiments, the bottoms of all grooves 90 are at the same level, and the bottom level of grooves 90 may be discussed in the preceding paragraphs. According to alternative embodiments, the bottom level of the recess 90 in the same device die (and the same wafer 20) may be at different levels.
Fig. 14A shows four possible bonding structures 110A, 110B, 110C, and 110D, each including a respective metal bump 82, solder region 98', electrical connector 96, and recess 90. One package 106' (and reconstituted wafer 106) may include one or more of the bonding structures 110A, 110B, 110C, and 110D therein in any combination. Different bond structures in the same package/wafer may be caused by process variations or may be intentionally formed. It should also be noted that the components shown in the bonding structures 110A, 110B, 110C, and 110D are some possible combinations of components, and that possible features of some possible combinations of components include (and are not limited to) the bottom level of the recess 90, whether the solder region 98' contacts the sidewall of the photosensitive layer 84, whether the solder region 98' extends on the sidewall of the metal bump 82, and whether the solder region 98' extends on the sidewall of the electrical connector 96. All other possible combinations are also contemplated, as long as possible.
In the engagement structure 110A, the bottom of the groove 90 may be at any level labeled 90BS1, 90BS2, and 90BS 3. The entire solder region 98' is above the top surface of the metal bump 82 and in contact with the top surface of the metal bump 82. Solder regions 98' are also below the bottom surface of the electrical connector 96 and contact the bottom surface of the electrical connector 96 and may or may not extend on the side walls of the electrical connector 96.
In the bonding structure 110B, the bottom of the recess 90 may be between the top surface of the metal bump 82 and the top surface 70TS of the dielectric layer 70. According to some embodiments, the entire solder region 98' is above the metal bump 82. According to the alternative embodiment shown, the solder regions 98' extend below the top surface of the metal bump 82 and contact the sidewalls of the metal bump 82. The solder regions 98' may also contact the bottom surface and sidewalls of the electrical connector 96 or may be confined below the bottom surface of the electrical connector 96. The solder regions 98' may (or may not) extend to the sidewalls of the photosensitive layer 84, the sidewalls of the photosensitive layer 84 being exposed to the recess 90.
In the bonding structure 110C, the solder region 98' is spaced apart from the sidewalls of the photosensitive layer 84. The recess 90 extends to the top surface of the dielectric layer 70 or may extend lower as shown in phantom. The solder regions 98' contact the top surfaces of the metal bumps 82 and may contact the sidewalls of the metal bumps 82 to form a vertical interface or may not contact the sidewalls of the metal bumps 82. The solder regions 98' may also contact the bottom surface of the electrical connector 96 and may or may not contact the sidewalls of the electrical connector 96.
In the bonding structure 110D, the top surface 70TS of the dielectric layer 70 is exposed to the recess 90. Solder regions 98' contact the sidewalls of metal bump 82 to form a vertical interface. The solder regions 98' may extend to the top surface 70TS or may be higher than the top surface 70TS. Solder regions 98' are also below the bottom surface of the electrical connector 96 and contact the bottom surface of the electrical connector 96.
Fig. 14B illustrates a reconstituted wafer 106 according to an alternative embodiment. In these embodiments, the resulting package is used at the wafer level. For example, in high performance applications such as Artificial Intelligence (AI) applications, the reconstituted wafer 106 is used without being sawed, and the reconstituted wafer 106 may be held on a fixture and powered up when not being sawed. In the reconstituted wafer 106, the encapsulant 104 may contact the sidewalls of the wafer 20.
Fig. 15 shows a reconstituted wafer 106 and sawing package 106' according to an alternative embodiment. The package assembly 94 according to these embodiments may include a dielectric layer 170, a metal bump 182, a photosensitive layer 184, and a recess 190. The structure, materials and formation process of dielectric layer 170, metal bump 182, photosensitive layer 184 and recess 190 may be the same as the corresponding dielectric layer 70, metal bump 82, photosensitive layer 84 and recess 90 in wafer 20, and thus details are not repeated here. The relationship of the dielectric layer 170, the metal bump 182, the photoactive layer 184, and the recess 190 may also be similar to the relationship discussed with reference to the bonding structures 110A, 110B, 110C, and 110D. According to some embodiments, the grooves 190 are aligned with the respective underlying grooves 90 and may have a lateral dimension that is equal to, greater than, or less than the lateral dimension of the respective underlying grooves 90.
According to some embodiments, as shown in fig. 14A, 14B and 15, the reconstituted wafer 106 and package 106' includes a dielectric layer 70 and a photosensitive layer 84 over the dielectric layer 70. Both the dielectric layer 70 and the photosensitive layer 84 may be formed of a material selected from the same set (or different sets) of materials, such as polyimide, PBO, BCB, etc. The material of dielectric layer 70 may be the same as or different from the material of photosensitive layer 84. According to some embodiments, the interface between dielectric layer 70 and photosensitive layer 84 may be distinguishable whether dielectric layer 70 and photosensitive layer 84 are formed of the same material or are formed of different materials.
Fig. 16 illustrates a top view of a reconstituted wafer 106 and package 106 '(shown as 106/106') according to some embodiments. There may be a plurality of metal bumps 82, which may be arranged in an array or any other pattern. The recess 90, which may be filled with solder regions and possibly underfills, may extend laterally beyond the edges of the metal bump 82. Alternatively, the grooves 90 may be narrower than the corresponding underlying metal bump 82 or have the same top view shape and top view dimensions as the corresponding underlying metal bump 82.
In the embodiments shown above, some processes and components are discussed in accordance with some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows testing of a 3D package or 3DIC, use of probes and/or probe cards, and the like. Verification tests may be performed on intermediate structures or on final structures. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good die to improve yield and reduce cost.
Embodiments of the present disclosure have some advantageous features. By forming a dielectric layer (which may be a photosensitive layer) and recessing the dielectric layer to form a recess, the recess may retain the solder region and limit lateral expansion of the solder region. Thus, the solder areas can have a small pitch without the risk of bridging.
According to some embodiments of the present disclosure, a method includes forming a first package assembly, the forming the first package assembly including forming a first dielectric layer including a first top surface; forming a first conductive feature, wherein the first conductive feature comprises: a via embedded in the first dielectric layer; and a metal bump comprising a second top surface higher than the first top surface of the first dielectric layer; dispensing a photosensitive layer, wherein the photosensitive layer covers the metal bump; and performing a photolithography process to form a recess in the photosensitive layer, wherein the metal bump is exposed to the recess, and wherein the photosensitive layer includes a third top surface higher than the metal bump; and bonding the second package component to the first package component, wherein the solder region extends into the recess to bond the metal bump to the second conductive feature in the second package component.
In an embodiment, performing a lithographic process includes: performing an exposure process on the photosensitive layer; and developing the photosensitive layer to remove portions of the photosensitive layer overlying the metal bumps. In an embodiment, the recess extends laterally beyond the edge of the associated bump, and wherein a portion of the photoactive layer is directly below the recess. In an embodiment, the sidewalls of the metal bump are exposed to the recess, and wherein the solder region extends to a level below the second top surface of the metal bump to contact the sidewalls of the metal bump. In an embodiment, the first dielectric layer comprises a further photosensitive layer. In an embodiment, the recess extends to a first top surface of the first dielectric layer, and wherein the first dielectric layer is not patterned in the photolithographic process.
In an embodiment, the first dielectric layer and the photosensitive layer are formed of the same photosensitive material. In an embodiment, the method further comprises performing a planarization process on the photosensitive layer after dispensing the photosensitive layer and before performing the photolithography process. In an embodiment, at the beginning of the lithographic process, the third top surface of the photosensitive layer comprises a lower portion laterally offset from the metal bump; and an upper portion directly above the metal bump, wherein the upper portion is higher than the lower portion. In an embodiment, after the lithographic process is completed, the third top surface of the photosensitive layer comprises a raised portion surrounding the recess, and wherein the raised portion is part of the higher portion.
According to some embodiments of the present disclosure, a structure includes a first package component including a dielectric layer; a conductive member, wherein the conductive member includes a via extending into the dielectric layer; and a metal bump protruding above the first top surface of the dielectric layer; and a photosensitive structure extending from a lower level to a higher level, wherein the lower level is below the second top surface of the metal bump and the higher level is above the second top surface of the metal bump; and a solder region extending into the photosensitive structure to connect to the metal bump, wherein the solder region extends laterally beyond an edge of the metal bump. In an embodiment, the photosensitive structure comprises a photosensitive material selected from the group consisting of polyimide, PBO, and BCB.
In an embodiment, both the dielectric layer and the photosensitive structure comprise a photosensitive material. In an embodiment, the dielectric layer and the photosensitive structure are formed of the same photosensitive material and contact each other to form a distinguishable interface therebetween. In an embodiment, the solder region contacts a sidewall of the photosensitive structure. In an embodiment, the structure further comprises a second package component comprising a further metal bump, wherein the further metal bump is bonded to the metal bump by a solder region, and wherein a bottom surface of the further metal bump is flush with or below the first top surface of the dielectric layer.
According to some embodiments of the present disclosure, a structure includes a device die including a first photosensitive structure; a first metal bump and a second metal bump adjacent to each other and extending above the first photosensitive structure; a second photosensitive structure over and contacting the first photosensitive structure, wherein the second photosensitive structure comprises a first recess and a second recess, wherein the first metal bump and the second metal bump are below the first recess and the second recess, respectively; a first solder region and a second solder region extending into the first recess and the second recess, respectively, wherein a portion of the second photosensitive structure separates the first solder region from the second solder region; and a second package assembly including: a first conductive member bonded to the first metal bump through the first solder region; and a second conductive member bonded to the second metal bump through the second solder region.
In an embodiment, wherein the first recess is wider than the first metal bump. In an embodiment, the second photosensitive structure includes a lower portion directly below the first recess, and wherein the lower portion has a top surface that is flush with the first metal bump. In an embodiment, the first photosensitive structure and the second photosensitive structure are formed of the same photosensitive material.
According to an embodiment of the present application, there is provided a method for forming a package including forming a first package assembly, the forming the first package assembly including: forming a first dielectric layer comprising a first top surface; a first conductive feature is formed. Wherein the first conductive member comprises: a via extending into the first dielectric layer; and a metal bump including a second top surface higher than the first top surface of the first dielectric layer. Forming the first package assembly further includes: dispensing a photosensitive layer, wherein the photosensitive layer covers the metal bump; and performing a photolithography process to form a groove in the photosensitive layer, wherein the metal bump is exposed to the groove, and wherein the photosensitive layer includes a third top surface higher than the metal bump. The method for forming the package further includes bonding the second package component to the first package component, wherein the solder region extends into the recess to bond the metal bump to the second conductive feature in the second package component. In some embodiments, wherein performing the lithographic process comprises: performing an exposure process on the photosensitive layer; and developing the photosensitive layer to remove portions of the photosensitive layer overlying the metal bumps. In some embodiments, wherein the recess extends laterally beyond an edge of the metal bump, and wherein a portion of the photoactive layer is directly beneath the recess. In some embodiments, wherein the sidewalls of the metal bump are exposed to the recess, and wherein the solder region extends to a level below the second top surface of the metal bump to contact the sidewalls of the metal bump. In some embodiments, wherein the first dielectric layer comprises an additional photosensitive layer. In some embodiments, wherein the recess extends to a first top surface of the first dielectric layer, and wherein the first dielectric layer is not patterned in the photolithographic process. In some embodiments, wherein the first dielectric layer and the photosensitive layer are formed of the same photosensitive material. In some embodiments, the method for forming the package further includes performing a planarization process on the photosensitive layer after dispensing the photosensitive layer and before performing the photolithography process. In some embodiments, wherein at the beginning of the lithographic process, the third top surface of the photosensitive layer comprises: a lower portion laterally offset from the metal bump; and an upper portion directly above the metal bump, wherein the upper portion is higher than the lower portion. In some embodiments, wherein after the photolithographic process is completed, the third top surface of the photosensitive layer includes raised portions surrounding the grooves, and wherein the raised portions are portions of the higher portions.
According to another embodiment of the present application, there is provided a package structure including a first package assembly including: a dielectric layer; a conductive member. Wherein the conductive member comprises: a via embedded in the dielectric layer; and a metal bump protruding above the first top surface of the dielectric layer. And the first package component includes a photosensitive structure extending from a lower level to a higher level, wherein the lower level is below the second top surface of the metal bump and the higher level is above the second top surface of the metal bump. And the package structure includes a solder region extending into the photosensitive structure to connect to the metal bump, wherein the solder region extends laterally beyond an edge of the metal bump. In some embodiments, wherein the photosensitive structure comprises a photosensitive material selected from the group consisting of polyimide, polybenzoxazole, and benzocyclobutene. In some embodiments, wherein both the dielectric layer and the photosensitive structure comprise a photosensitive material. In some embodiments, wherein the dielectric layer and the photosensitive structure are formed of the same photosensitive material, and are in contact with each other to form a distinguishable interface therebetween. In some embodiments, the solder regions contact sidewalls of the photosensitive structure. In some embodiments, a second package assembly is also included, the second package assembly including a further metal bump, wherein the further metal bump is bonded to the metal bump by a solder region, and wherein a bottom surface of the further metal bump is flush with or below the first top surface of the dielectric layer.
According to yet another embodiment of the present application, there is provided a package structure including a device die including: a first photosensitive structure; a first metal bump and a second metal bump adjacent to each other and extending above the first photosensitive structure; a second photosensitive structure over and contacting the first photosensitive structure. The package structure further includes a first solder region and a second solder region extending into the second photosensitive structure, wherein a portion of the second photosensitive structure separates the first solder region from the second solder region, and wherein the first metal bump and the second metal bump are below a first upper portion of the first solder region and a second upper portion of the second solder region, respectively; and a second package assembly. Wherein the second package assembly comprises: a first conductive member bonded to the first metal bump through the first solder region; and a second conductive member bonded to the second metal bump through the second solder region. In some embodiments, wherein the first solder region is wider than the first metal bump. In some embodiments, wherein the second photosensitive structure includes a lower portion directly below the first upper portion of the first solder region, and wherein the lower portion has a top surface that is flush with the first metal bump. In some embodiments, wherein the first photosensitive structure and the second photosensitive structure are formed from the same photosensitive material.
The foregoing disclosure outlines components of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method for forming a package comprising:
forming a first package assembly comprising:
forming a first dielectric layer comprising a first top surface;
forming a first conductive feature, wherein the first conductive feature comprises:
a via extending into the first dielectric layer; and
a metal bump comprising a second top surface higher than the first top surface of the first dielectric layer;
dispensing a photosensitive layer, wherein the photosensitive layer covers the metal bump; and
performing a photolithography process to form a recess in the photosensitive layer, wherein the metal bump is exposed to the recess, and wherein the photosensitive layer includes a third top surface higher than the metal bump; and
Bonding a second package component to the first package component, wherein a solder region extends into the recess to bond the metal bump to a second conductive feature in the second package component.
2. The method of claim 1, wherein the performing the lithographic process comprises:
performing an exposure process on the photosensitive layer; and
the photosensitive layer is developed to remove portions of the photosensitive layer that cover the metal bumps.
3. The method of claim 1, wherein the recess extends laterally beyond an edge of the metal bump, and wherein a portion of the photosensitive layer is directly under the recess.
4. The method of claim 1, wherein sidewalls of the metal bump are exposed to the recess, and wherein the solder region extends to a level below the second top surface of the metal bump to contact the sidewalls of the metal bump.
5. The method of claim 1, wherein the first dielectric layer comprises an additional photosensitive layer.
6. The method of claim 5, wherein the recess extends to the first top surface of a first dielectric layer, and wherein the first dielectric layer is unpatterned in the photolithographic process.
7. The method of claim 6, wherein the first dielectric layer and the photosensitive layer are formed of the same photosensitive material.
8. The method of claim 1, further comprising performing a planarization process on the photosensitive layer after dispensing the photosensitive layer and before performing the photolithography process.
9. A package structure, comprising:
a first package assembly comprising:
a dielectric layer;
a conductive member, wherein the conductive member comprises:
a via embedded in the dielectric layer; and
a metal bump protruding above a first top surface of the dielectric layer; and
a photosensitive structure extending from a lower level to a higher level, wherein the lower level is below a second top surface of the metal bump and the higher level is above the second top surface of the metal bump; and
a solder region extending into the photosensitive structure to connect to the metal bump, wherein the solder region extends laterally beyond an edge of the metal bump.
10. A package structure, comprising:
a device die, the device die comprising:
a first photosensitive structure;
a first metal bump and a second metal bump adjacent to each other and extending above the first photosensitive structure;
A second photosensitive structure over and contacting the first photosensitive structure;
a first solder region and a second solder region extending into the second photosensitive structure, wherein a portion of the second photosensitive structure separates the first solder region from the second solder region, and wherein the first metal bump and the second metal bump are below a first upper portion of the first solder region and a second upper portion of the second solder region, respectively; and
a second package assembly, the second package assembly comprising:
a first conductive member bonded to the first metal bump through the first solder region; and
a second conductive member bonded to the second metal bump through the second solder region.
CN202310528841.9A 2022-06-15 2023-05-11 Method for forming package and package structure Pending CN116884857A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/366,438 2022-06-15
US17/929,180 2022-09-01
US17/929,180 US20230411329A1 (en) 2022-06-15 2022-09-01 Dielectric Blocking Layer and Method Forming the Same

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CN116884857A true CN116884857A (en) 2023-10-13

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