CN116882332B - Method for verifying sub-circuit characteristics of ring oscillator based on SPICE simulation - Google Patents
Method for verifying sub-circuit characteristics of ring oscillator based on SPICE simulation Download PDFInfo
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Abstract
A method for verifying ring oscillator subcircuit characteristics based on SPICE simulation, comprising the steps of: connecting a timing arc when the STA circuit is disconnected, searching a closed-loop sub-circuit in the STA circuit and judging whether the closed-loop sub-circuit can form circuit oscillation or not; based on a closed-loop sub-circuit capable of forming circuit oscillation, constructing a SPICE simulation netlist and completing SPICE simulation; and analyzing the SPICE simulation result file, obtaining time sequence data of the ring oscillator subcircuit, and performing verification analysis. According to the invention, through connecting the timing arc disconnected by the STA, positioning to the closed-loop subcircuit and judging whether the closed-loop subcircuit oscillates or not, and then building the SPICE simulation netlist of the closed-loop subcircuit, the SPICE dynamic simulation and verification analysis are completed, the defect that the STA cannot directly analyze the timing sequence of the ring oscillator subcircuit is overcome, the timing sequence characteristics of the ring oscillator can be accurately verified based on the timing sequence data of the SPICE simulation precision, and the change of the circuit oscillation frequency of the ring oscillator under different PVT conditions is researched.
Description
Technical Field
The invention relates to the technical field of ring oscillator circuit analysis, in particular to a method for verifying the subcircuit characteristics of a ring oscillator based on SPICE simulation.
Background
Currently, the mainstream voltage-controlled oscillators (Voltage Controlled Oscillator, VCOs for short) have two major types, namely an LC Oscillator and a Ring Oscillator (RO for short), and the LC Oscillator has a higher quality factor and good phase noise performance, but the limited frequency tuning range and the larger chip area of the LC Oscillator become key defects; in contrast, the ring oscillator has the outstanding advantages of large frequency tuning range, small occupied area, capability of providing multiphase output, simplicity and convenience in integration of a circuit and the like, and has the defects of poor noise resistance and higher frequency fluctuation.
The ring oscillator is a closed loop structure formed by connecting a plurality of delay units in series, and can be mainly divided into a single-ended inverter delay unit ring oscillator, a differential delay unit ring oscillator and the like according to the difference of the delay units. The ring oscillator can be manufactured entirely from standard CMOS technology, is cost effective, occupies less chip area, and is typically capable of generating clock signals in the frequency range of several MHz to several GHz. With the rapid development of CMOS processes and System On Chip (SOC) systems, ring oscillators are an attractive option and are widely used in clock generation circuits, which are excellent clock solutions in small-area, low-cost application scenarios. As the process nodes continue to decrease, parasitic capacitance contained in the ring oscillator decreases, and power consumption required by the ring oscillator decreases correspondingly. Since a ring oscillator has no high quality filter, its phase noise is worse than that of an LC oscillator, and is susceptible to PVT (Process, voltage, and Temperature) conditions, research on the ring oscillator tends to focus on both reducing the phase noise of the ring oscillator and improving reliability.
PVT variations in ring oscillators generally result from variations in the delay time due to variations in threshold voltage, carrier mobility and charge-discharge capacitance, whereas variations in the supply voltage directly affect the charge-discharge current of the ring oscillator, thereby changing the delay time and transition time of rising and falling edges of the ring oscillator, and noise from the supply power supply can also seriously affect the phase noise of the ring oscillator. In static timing analysis (STATIC TIMING ANALYSIS, STA for short), a circuit is abstracted into a directed acyclic graph, and a graph is formed according to the direction of circuit signal transmission, so that in general, the STA must have no loop and needs to be disconnected when the loop cannot occur. Aiming at the problem that STA cannot directly analyze the time sequence of the ring oscillator subcircuit, the invention researches the time sequence characteristics of the ring oscillator subcircuit in a SPICE dynamic simulation mode by constructing the SPICE simulation netlist of the ring oscillator subcircuit.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation.
In order to achieve the above object, the method for verifying the subcircuit characteristics of the ring oscillator based on SPICE simulation provided by the invention comprises the following steps:
connecting a timing arc of the disconnection of an STA circuit, searching a closed-loop sub-circuit in the STA circuit and judging whether the closed-loop sub-circuit can form circuit oscillation or not;
Based on a closed-loop sub-circuit capable of forming circuit oscillation, constructing a SPICE simulation netlist and completing SPICE simulation;
and analyzing the SPICE simulation result file, obtaining time sequence data of the ring oscillator subcircuit, and performing verification analysis.
Further, the step of searching the closed loop sub-circuit in the STA circuit and judging whether the closed loop sub-circuit can form circuit oscillation or not according to the timing arc of the disconnection of the STA circuit, further comprises: and traversing the STA circuit, taking the feedback closed-loop structural characteristic of the defined ring oscillator as a judging condition of the closed-loop subcircuit, stopping the traversing process after the closed-loop subcircuit meeting the judging condition is found, and cutting off the branch circuit which is not in the closed-loop structure to obtain the simplified closed-loop subcircuit.
Further, the method further comprises the following steps: and designating a starting point of an STA circuit traversal process, traversing according to a signal flow direction in the circuit, or setting the starting point as any circuit node before or on a closed loop of a branch circuit according to the branch circuit with a pre-known closed loop structure, and finding out a closed loop sub-circuit meeting a judgment condition.
Further, the ring oscillator feedback closed loop structure is characterized in that: starting from a logic cell with multiple inputs, the stimulus signal is coupled in at one input pin of the logic cell, passes through multiple logic cells and interconnections in the direction of signal transmission, and then returns to the other input pin of the logic cell.
Further, the step of searching the closed loop sub-circuit in the STA circuit and judging whether the closed loop sub-circuit can form circuit oscillation or not according to the timing arc of the disconnection of the STA circuit, further comprises:
On the found closed-loop sub-circuit, in addition to the logic unit Cell in to which the excitation signal is connected, analyzing the functional logic of all other logic units Cell i (i=1, 2, …, N), judging whether the sequential arcs of the logic units on the closed-loop structure work as inversion logic, and counting the total number M of the sequential arcs of all logic units Cell i (i=1, 2..n) working as inversion logic;
judging the working logic of a unit time sequence Arc ro and a unit time sequence Arc in of a logic unit Cell in on a closed loop structure according to the parity of M;
According to the high potential or low potential state maintained by the pins of the determined logic unit Cell in access Signal, the working logic of the unit time sequence Arc in where the pins are positioned is combined, and the accessed edge Signal in is derived to be a rising edge or a falling edge;
When the total number of timing arcs on a closed-loop structure and operating as an inversion logic in all logic cells Cell i (i=1, 2, …, N) and Cell in on a closed-loop sub-circuit is an odd number, it is determined that the closed-loop sub-circuit is capable of forming a circuit oscillation.
Further, the steps of constructing a SPICE simulation netlist and completing SPICE simulation based on a closed-loop subcircuit capable of forming circuit oscillation include: generating link library file information, subcircuit structure description, power supply voltage value, edge excitation signal construction and timing measurement statement, wherein,
In the aspect of subcircuit structure description, the logic of an internal unit is analyzed or an external constraint file is read, other input pins which are not in a closed loop structure and are contained in a logic unit are set to be in a high-potential or low-potential state, and the working logic of a logic unit time sequence arc on the closed loop is maintained;
in the aspect of edge excitation Signal construction, according to the power supply voltage of a logic unit Cell in connected with an excitation Signal and the edge type of an edge Signal in, constructing an excitation edge Signal which meets the normal operation of a ring oscillator sub-circuit;
In the aspect of time sequence measurement statement, the working logic of a unit time sequence arc on the closed loop structure obtained through analysis is combined, the overturning change state of an edge signal on each node of the closed loop sub-circuit is confirmed, accurate period and delay data can be measured by a measurement statement, and the complete signal waveform on each node of the closed loop sub-circuit is saved by a probe statement.
Further, the steps of constructing a SPICE simulation netlist and completing SPICE simulation based on the closed-loop subcircuit capable of forming circuit oscillation further comprise: after SPICE simulation is completed, when abnormal values exist in the measured period and delay data, the problems existing in the measurement statement in the netlist are positioned by combining the complete signal waveform, the SPICE simulation netlist is corrected and updated in time, the SPICE simulation is executed again, a reasonable simulation result is obtained, and a time sequence report is generated.
Further, the step of analyzing the SPICE simulation result file to obtain the time sequence data of the ring oscillator subcircuit and performing verification analysis further includes: and analyzing SPICE simulation result files, and carrying out function verification, trend analysis, jitter calculation, noise analysis or stability research of a circuit oscillation process of the ring oscillator based on the measured period and delay data and complete signal waveform data of the ring oscillator.
Further, the method further comprises the following steps: and modifying and updating the SPICE simulation netlist, organizing a plurality of groups of SPICE simulation results under different PVT conditions, and researching the change trend rule of the working frequency of the ring oscillator.
Further, when under a single unique PVT condition, the ring oscillator subcircuit operates at a stable oscillation frequency, and the Period of operation Period when the circuit oscillates is equal to the sum of all logic unit delays and interconnect line delays on the closed loop structure, the relationship is as follows:
Wherein R, F respectively represent a rising edge and a falling edge, edge represents an edge, the edge needs to consider the rising edge and the falling edge at the same time, Is the sum of the delay amounts of all logic units on the rising edge and the falling edge on the closed loop structure,The sum of delay amounts of all interconnection lines on the closed loop structure at the rising edge and the falling edge;
When the oscillation frequency of the ring oscillator subcircuit is changed under different PVT conditions, the simulation is continued after the process angle is switched or the voltage and the temperature are modified, and a plurality of sets of SPICE simulation time sequence results are obtained and are used for analyzing the trend rule of the oscillation frequency of the ring oscillator subcircuit along with the change of the PVT conditions.
To achieve the above object, the present invention further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor is configured to execute the computer program stored in the memory, so as to implement the method for verifying the sub-circuit characteristics of the ring oscillator based on SPICE simulation as described above.
To achieve the above object, the present invention also provides a computer-readable storage medium having at least one instruction stored therein, the instruction being loaded and executed by a processor to implement a method of verifying ring oscillator subcircuit characteristics based on SPICE simulation as described above.
Compared with the prior art, the method for verifying the sub-circuit characteristics of the ring oscillator based on SPICE simulation has the following beneficial effects:
When traversing a circuit structure in an STA, connecting a disconnected time sequence arc, finding out a truly existing closed loop subcircuit, further judging whether the closed loop circuit can form circuit oscillation according to the structural characteristics of a ring oscillator, constructing a correct SPICE simulation netlist based on the found ring oscillator subcircuit structure, acquiring accurate period and delay measurement data through mature SPICE simulation, and organizing complete signal waveforms on all nodes of the closed loop subcircuit, wherein the results can be organized into reliable and reliable time sequence reports;
The method overcomes the defect that STA cannot directly analyze the time sequence of the sub-circuit of the ring oscillator, and based on the time sequence data of SPICE simulation precision, the time sequence characteristics of the ring oscillator can be accurately verified, and the change of the oscillation frequency of the circuit under different PVT conditions can be studied.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for verifying ring oscillator subcircuit characteristics based on SPICE simulation in accordance with the present invention;
FIG. 2 is a schematic diagram of a ring oscillator subcircuit SPICE simulation result application in accordance with the present invention;
fig. 3 is a schematic structural view of an electronic device according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While the invention is susceptible of embodiment in the drawings, it is to be understood that the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the invention. It should be understood that the drawings and embodiments of the invention are for illustration purposes only and are not intended to limit the scope of the present invention.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the modifications of "a" and "an" as may be mentioned in the present disclosure are illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" should be understood to mean "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a flowchart of a method for verifying ring oscillator subcircuit characteristics based on SPICE simulation in accordance with the present invention, which is described in detail below with reference to FIG. 1.
In the embodiment of the invention, the SPICE simulation verification flow of the ring oscillator subcircuit is mainly divided into two key parts of positioning the ring oscillator subcircuit and realizing the SPICE simulation of the subcircuit, and feedback iteration subcircuits exist in each of the two key parts. In the process of positioning the ring oscillator subcircuit, when the found closed loop subcircuit is subjected to logic analysis and does not meet the circuit oscillation condition, the closed loop structure on the next branch circuit needs to be searched again for continuous analysis and judgment, the related process of SPICE simulation can be entered only after the circuit oscillation condition is met, and the process can be influenced by the specified circuit traversal starting point and the configured time sequence constraint file.
Specifically, in step 101, a closed loop sub-circuit is found.
In the STA, the circuit must be loop-free and sometimes needs to be disconnected, so the STA cannot directly analyze the closed-loop circuit structure, therefore, when traversing the established circuit structure in the STA, the STA needs to be connected to the open time sequence arc, and the closed-loop structure characteristic is fed back as the condition of finding the closed-loop sub-circuit structure strictly according to the defined RO (ring oscillator), after finding the closed-loop sub-circuit structure meeting the condition, the circuit traversal process can be stopped, and the branch circuit not on the closed-loop sub-circuit structure is cut off, so that the closed-loop sub-circuit structure is the simplest and unique. The timing arc generally refers to an arc with delay formed from input (input) to output (output) of a cell.
In the embodiment of the present invention, taking a single-ended inverter delay cell ring oscillator as an example, the feedback closed loop structure characteristic of the ring oscillator is defined as starting from a logic cell with multiple inputs, an excitation signal is connected to one input pin of the logic cell, passes through a plurality of logic cells and interconnection lines along the signal transmission direction, and then returns to the other input pin of the logic cell. And traversing the STA circuit by taking the feedback closed-loop structural characteristic as a judging condition of the RO closed-loop structure, and searching a closed-loop sub-circuit.
In the embodiment of the invention, after the closed loop structure is found, redundant branch circuits are cut off, the simplest closed loop subcircuit is obtained, useful circuit structure information can be reserved, the final SPICE simulation result is not influenced, and the SPICE simulation netlist construction and the simulation time sequence data organization are both based on the simplified closed loop subcircuit structure information.
In the embodiment of the invention, in the RO closed loop structure judging stage, a user needs to specify the starting point of the circuit traversal process and traverse the circuit according to the signal flow direction in the circuit, so that the circuit structure before the starting point can be skipped, and the invention has great practicability when the whole circuit design scale is large. In addition, since the ring oscillator structure is generally present in the clock circuit, when a user knows in advance that a closed loop structure exists in a certain branch circuit, the starting point can be set to be a certain circuit node before or on the closed loop, so that a closed loop sub-circuit meeting the conditions can be quickly found out.
At step 102, it is determined whether the closed loop subcircuit is capable of forming a circuit oscillation. If the found closed-loop subcircuit meets the oscillation condition, the next step is entered, otherwise, the step 101 is returned to, and the closed-loop subcircuit is continuously found.
In the embodiment of the present invention, in the RO oscillation condition analysis stage, the judgment of the unit function logic is based on the timing arcs of the logic units on all closed-loop sub-circuits, and on the found closed-loop sub-circuit structure, the function logic of all other logic units Cell i (i=1, 2, the..N.) except the logic unit Cell in to which the excitation signal is connected is analyzed, Judging whether the sequential arcs of the logic units on the closed loop structure work as inversion logic or not, and counting the total number M of the sequential arcs working as the inversion logic in all the logic units Cell i (i=1, 2.. The N), and then judging the working logic of the logic unit Cell in: since a closed loop structure of a ring oscillator requires a timing arc containing an odd number of inverting operating logic to be able to form a circuit oscillation, that is, the total number of timing arcs that the logic Cell in and all other logic cells Cell i (i=1, 2,.., N) operate as inverting logic on a closed loop structure is odd, the closed loop sub-circuit is able to form a circuit oscillation, and after the parity of M is determined, the operating logic of Cell in on the closed loop structure for Cell timing Arc ro and Cell timing Arc in is determined; Meanwhile, in order to maintain the working logic of the timing Arc ro, the high-low potential state that the pin of the Cell in access Signal should maintain can be determined, and by combining with the working logic of the unit timing Arc in where the pin is located, the accessed edge Signal in can be deduced to be a rising edge or a falling edge.
In embodiments of the present invention, interfaces for configurable options or files are provided to speed up the process of locating ring oscillator subcircuits. For example, in the RO closed loop structure judging and RO oscillation condition analyzing stage, the working logic of the constrained logic unit is determined in advance according to the read time sequence constraint file (Timing Constraint Files), which is helpful for accurately judging whether the closed loop sub-circuit can form circuit oscillation. Such a timing constraint file is necessary, in particular, when there are multiple loops in the circuit structure (e.g., in a sub-circuit structure consisting of multiple select devices where there are multiple closed loops), or when there are multiple operating logics in the logic cells on the closed loop structure. In practical application, interfaces of the configurable options or files are required to be provided open, so that the ring oscillator subcircuit can work normally, and the SPICE simulation netlist of the subcircuit can be built smoothly and simulation can be completed.
In the embodiment of the invention, the closed-loop subcircuit is searched in the STA circuit and whether the closed-loop subcircuit can form circuit oscillation is analyzed, a reasonable circuit traversing initial point is required to be designated in the process, and an external time sequence constraint file is also required to be configured in advance, so that the structure of the closed-loop subcircuit can be rapidly positioned, the working logic of each logic unit is accurately analyzed, and whether the closed-loop subcircuit can form the circuit oscillation is judged. The circuit traversing rule is changed in the existing STA flow, so that a timing arc of STA disconnection can be connected, a closed loop structure with clear circuit structure is obtained, circuit pin nodes which can be connected with excitation signals are determined while the circuit pin nodes are positioned to the sub-circuit structure of the ring oscillator, and the SPICE simulation netlist of the sub-circuit can be constructed correctly.
In step 103, a SPICE simulation netlist is built.
In the embodiment of the invention, after confirming that the closed-loop subcircuit obtained by traversing and cutting is a ring oscillator subcircuit structure capable of forming circuit oscillation, the SPICE simulation netlist can be automatically built according to the existing and analyzed data information, mainly comprising the contents of link library file information, subcircuit structure description, power supply voltage value, edge excitation signal construction, time sequence measurement statement and the like,
In terms of the description of the sub-circuit structure, in order to maintain the working logic of the logic unit timing arc on the closed loop, the rest of input pins need to be placed in a high-potential or low-potential state, and the input pins can be read through internal unit logic analysis or external constraint files, and the latter is a more reasonable and practical mode and needs to be configured in advance;
In terms of the construction of the edge excitation Signal, a reasonable excitation edge Signal which can meet the normal operation of the ring oscillator subcircuit can be established according to the power supply voltage of the logic unit Cell in and the edge type of the edge Signal in in the step 102;
In terms of time sequence measurement statement, attention is required to measure oscillation period and delay data, and the working logic of unit time sequence arcs on a closed loop structure obtained through analysis in step 102 is combined to confirm the overturning change state of edge signals on all nodes of a closed loop sub-circuit, so that accurate period and delay data can be measured by a measurement statement, and complete signal waveforms on all nodes of the sub-circuit can be saved by the probe statement.
At step 104, SPICE simulation is performed.
At step 105, SPICE simulation results are validated. Analyzing SPICE simulation result files to obtain cycle and delay measurement data of the ring oscillator, performing RO characteristic verification analysis, returning to step 103 if abnormal values exist in the simulation result, and generating a time sequence report if the simulation result is reasonable.
In the embodiment of the invention, in the SPICE simulation verification process of the ring oscillator subcircuit, when abnormal values such as negative values exist in the period and delay data measured after the SPICE simulation is completed, the problems existing in a measurement sentence in the netlist need to be positioned by combining the complete signal waveform, if the wrong edge type, the wrong edge number and the like are adopted, the SPICE netlist is corrected and updated in time to execute simulation again, and reasonable simulation results are ensured to be obtained to generate a time sequence report.
The timing data of SPICE simulation accuracy is a reliable basis for verifying and analyzing the timing characteristics of the ring oscillator subcircuit. The accurate SPICE simulation netlist is built through the found ring oscillator subcircuit structure, accurate period and delay measurement data and complete signal waveforms on all nodes of the closed-loop subcircuit are obtained through mature SPICE simulation, and the results can be organized into reliable and reliable time sequence reports. In SPICE simulation results, the signal waveform of the circuit oscillation process is the most basic data, and whether the measured period and delay data are reasonable or not can be confirmed by referring to the signal waveform, and the data can complete the functional verification and stability analysis of the ring oscillator.
Furthermore, the SPICE simulation netlist can be modified as required, and a plurality of groups of SPICE simulation results under different PVT conditions are organized to study the change trend rule of the working frequency of the ring oscillator.
In the embodiment of the invention, when under a single unique PVT condition, the RO sub-circuit should work according to a stable oscillation frequency, and the working Period of the circuit oscillation should be equal to the sum of all logic unit delays and interconnection line delays on a closed loop, namely the following relationship exists:
Wherein R, F respectively represent rising edge and falling edge, edge represents edge, and the edge needs to consider the rising edge and the falling edge at the same time, and the addition is added For the sum of the delay amounts at the rising and falling edges of all logic cells i (i=1, 2,.., N) on the closed loop structure,For the sum of the delay amounts at the rising edge and the falling edge of all the interconnect lines net i (i=1, 2,..n.) in the closed-loop structure, in a special case, if the delay of the interconnect line is ignored, the sum of the sum is zero.
When the oscillation frequency of the RO sub-circuit is changed under different PVT conditions, the simulation is continued after the process angle is switched or the voltage and the temperature are modified, and then a plurality of sets of SPICE simulation time sequence results can be organized to analyze the trend rule of the oscillation frequency of the RO sub-circuit along with the change of the PVT conditions. In addition, the complete signal waveform stored in the probe sentence can be used for researching the stability of the RO sub-circuit oscillation process, such as whether jitter or phase noise exists between different oscillation periods.
FIG. 2 is a schematic diagram of the application of SPICE simulation results to a ring oscillator subcircuit according to the present invention, and referring to FIG. 2, in step 201, the SPICE simulation netlist is updated under PVT conditions.
In the embodiment of the invention, in the process of constructing the SPICE simulation netlist, basic contents such as link library file information, subcircuit structure description, power supply voltage value and the like are firstly generated, and special treatment is needed: and accessing reasonable edge excitation signal waveforms according to logic analysis results in the process of positioning the ring oscillator subcircuit, and adopting correct edge types and edge numbers in a measurement statement.
At step 202, SPICE simulation is performed. In the SPICE dynamic simulation process, a SPICE simulation netlist internal. Measurement statement 203 is used for outputting cycle and delay data 205 of a sub-circuit, and a SPICE simulation netlist internal. Probe statement 204 is used for storing complete signal waveform data 206 of each node of the sub-circuit.
In an embodiment of the present invention, the complete signal waveform data 206 is the most important underlying data that has an indicative reference to the period and delay data 205. Wherein, the multiple groups of period and delay data 205 obtained by changing PVT conditions can be used for functional verification 207 of the sub-circuits, including the relationship between period and delay data, the logic function verification of each logic unit, and the like; the trend analysis 208 may also be used for sub-circuits, including a trend of a change in the oscillation frequency of the circuit, a trend of a change in delay of each logic unit, and so on. In addition, interference noise may be introduced on the stimulus signal waveform or the supply voltage of each logic unit, and when the number of cycles of the stored complete signal waveform 206 is sufficiently large, the stability of the signal waveform at each circuit node may be evaluated by means of jitter calculation 209 or noise analysis 210, etc.
The method for verifying the sub-circuit characteristics of the ring oscillator based on SPICE simulation overcomes the defect that STA cannot directly analyze the sub-circuit time sequence of the ring oscillator, can accurately verify the time sequence characteristics of the ring oscillator based on the time sequence data of SPICE simulation precision, and can study the change of the circuit oscillation frequency under different PVT conditions.
In an embodiment of the present invention, there is further provided an electronic device, fig. 3 is a schematic structural diagram of the electronic device according to the present invention, and as shown in fig. 3, the electronic device of the present invention includes a processor 301, and a memory 302, where,
Memory 302 stores a computer program that, when read for execution by processor 301, performs the steps in the method embodiments described above for verifying ring oscillator subcircuit features based on SPICE simulations.
In an embodiment of the invention, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to perform, at run-time, the steps of the method embodiment of verifying ring oscillator subcircuit characteristics based on SPICE simulations as described above.
In the present embodiment, the above-described computer-readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for verifying ring oscillator subcircuit characteristics based on SPICE simulation, comprising the steps of:
connecting a timing arc of the disconnection of an STA circuit, searching a closed-loop sub-circuit in the STA circuit and judging whether the closed-loop sub-circuit can form circuit oscillation or not;
Based on a closed-loop sub-circuit capable of forming circuit oscillation, constructing a SPICE simulation netlist and completing SPICE simulation;
Analyzing SPICE simulation result files, obtaining time sequence data of the ring oscillator subcircuit, and performing verification analysis;
the step of searching a closed loop sub-circuit in the STA circuit and judging whether the closed loop sub-circuit can form circuit oscillation or not, and the step of connecting the timing arc of the disconnection of the STA circuit further comprises the following steps:
On the found closed-loop sub-circuit, all other logic cells Cell i (i=1, 2,..once., N) are analyzed for functional logic, except for the logic Cell in that has the excitation signal in, judging whether the time sequence arcs of the logic units on the closed loop structure work as the inversion logic or not, and counting the total number M of the time sequence arcs working as the inversion logic in all the logic units Cell i (i=1, 2., N);
judging the working logic of a unit time sequence Arc ro and a unit time sequence Arc in of a logic unit Cell in on a closed loop structure according to the parity of M;
According to the high potential or low potential state maintained by the pins of the determined logic unit Cell in access Signal, the working logic of the unit time sequence Arc in where the pins are positioned is combined, and the accessed edge Signal in is derived to be a rising edge or a falling edge;
When the total number of timing arcs on a closed-loop structure and operating as inverted logic in all logic cells Cell i (i=1, 2,..n.) and Cell in on a closed-loop sub-circuit is an odd number, it is determined that the closed-loop sub-circuit is capable of forming a circuit oscillation;
The step of constructing the SPICE simulation netlist and completing SPICE simulation based on the closed-loop subcircuit capable of forming circuit oscillation further comprises the following steps: generating link library file information, subcircuit structure description, power supply voltage value, edge excitation signal construction and timing measurement statement, wherein,
In the aspect of subcircuit structure description, the logic of an internal unit is analyzed or an external constraint file is read, other input pins which are not in a closed loop structure and are contained in a logic unit are set to be in a high-potential or low-potential state, and the working logic of a logic unit time sequence arc on the closed loop is maintained;
in the aspect of edge excitation Signal construction, according to the power supply voltage of a logic unit Cell in connected with an excitation Signal and the edge type of an edge Signal in, constructing an excitation edge Signal which meets the normal operation of a ring oscillator sub-circuit;
In the aspect of time sequence measurement statement, the working logic of a unit time sequence arc on the closed loop structure obtained through analysis is combined, the overturning change state of an edge signal on each node of the closed loop sub-circuit is confirmed, accurate period and delay data can be measured by a measurement statement, and the complete signal waveform on each node of the closed loop sub-circuit is saved by a probe statement.
2. The method of verifying ring oscillator subcircuit characteristics based on SPICE simulation of claim 1, wherein the step of connecting the timing arc of a STA circuit disconnection, looking up a closed loop subcircuit in the STA circuit and determining if it is capable of forming a circuit oscillation, further comprises: and traversing the STA circuit, taking the feedback closed-loop structural characteristic of the defined ring oscillator as a judging condition of the closed-loop subcircuit, stopping the traversing process after the closed-loop subcircuit meeting the judging condition is found, and cutting off the branch circuit which is not in the closed-loop structure to obtain the simplified closed-loop subcircuit.
3. The SPICE simulation based method of verifying ring oscillator subcircuit characteristics of claim 2, further comprising: and designating a starting point of an STA circuit traversal process, traversing according to a signal flow direction in the circuit, or setting the starting point as any circuit node before or on a closed loop of a branch circuit according to the branch circuit with a pre-known closed loop structure, and finding out a closed loop sub-circuit meeting a judgment condition.
4. The SPICE simulation based method for verifying ring oscillator subcircuit characteristics as defined in claim 2, wherein the ring oscillator feedback closed loop structure characteristics are: starting from a logic cell with multiple inputs, the stimulus signal is coupled in at one input pin of the logic cell, passes through multiple logic cells and interconnections in the direction of signal transmission, and then returns to the other input pin of the logic cell.
5. The method for verifying ring oscillator subcircuit characteristics based on SPICE simulation of claim 1, wherein the steps of constructing SPICE simulation netlist and completing SPICE simulation based on closed loop subcircuit capable of forming circuit oscillation further comprise: after SPICE simulation is completed, when abnormal values exist in the measured period and delay data, the problems existing in the measurement statement in the netlist are positioned by combining the complete signal waveform, the SPICE simulation netlist is corrected and updated in time, the SPICE simulation is executed again, a reasonable simulation result is obtained, and a time sequence report is generated.
6. The method for verifying a ring oscillator subcircuit feature based on SPICE simulation of claim 1, wherein the step of parsing SPICE simulation result file, obtaining timing data of the ring oscillator subcircuit, and performing verification analysis further comprises: and analyzing SPICE simulation result files, and carrying out function verification, trend analysis, jitter calculation, noise analysis or stability research of a circuit oscillation process of the ring oscillator based on the measured period and delay data and complete signal waveform data of the ring oscillator.
7. The SPICE simulation based method of verifying ring oscillator subcircuit characteristics of claim 1, further comprising: and modifying and updating the SPICE simulation netlist, organizing a plurality of groups of SPICE simulation results under different PVT conditions, and researching the change trend rule of the working frequency of the ring oscillator.
8. The method of verifying ring oscillator subcircuit characteristics based on SPICE simulation of claim 7, wherein the ring oscillator subcircuit operates at a stable oscillation frequency when in a single unique PVT condition, and the Period of operation when the circuit oscillates is equivalent to the sum of all logic cell delays and interconnect line delays on a closed loop structure, the relationship being as follows:
Wherein R, F respectively represent a rising edge and a falling edge, edge represents an edge, the edge needs to consider the rising edge and the falling edge at the same time, Is the sum of the delay amounts of all logic units on the rising edge and the falling edge on the closed loop structure,The sum of delay amounts of all interconnection lines on the closed loop structure at the rising edge and the falling edge;
When the oscillation frequency of the ring oscillator subcircuit is changed under different PVT conditions, the simulation is continued after the process angle is switched or the voltage and the temperature are modified, and a plurality of sets of SPICE simulation time sequence results are obtained and are used for analyzing the trend rule of the oscillation frequency of the ring oscillator subcircuit along with the change of the PVT conditions.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor for executing the computer program stored in the memory to implement the method of verifying ring oscillator subcircuit characteristics based on SPICE simulations of any of claims 1 to 8.
10. A computer readable storage medium having stored therein at least one instruction, wherein the instructions are loaded and executed by a processor to implement the method of verifying ring oscillator subcircuit characteristics based on SPICE simulations of any of claims 1 to 8.
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