CN116882332B - Method for verifying sub-circuit characteristics of ring oscillator based on SPICE simulation - Google Patents

Abstract

A method for verifying ring oscillator subcircuit characteristics based on SPICE simulation, comprising the steps of: connecting a timing arc when the STA circuit is disconnected, searching a closed-loop sub-circuit in the STA circuit and judging whether the closed-loop sub-circuit can form circuit oscillation or not; based on a closed-loop sub-circuit capable of forming circuit oscillation, constructing a SPICE simulation netlist and completing SPICE simulation; and analyzing the SPICE simulation result file, obtaining time sequence data of the ring oscillator subcircuit, and performing verification analysis. According to the invention, through connecting the timing arc disconnected by the STA, positioning to the closed-loop subcircuit and judging whether the closed-loop subcircuit oscillates or not, and then building the SPICE simulation netlist of the closed-loop subcircuit, the SPICE dynamic simulation and verification analysis are completed, the defect that the STA cannot directly analyze the timing sequence of the ring oscillator subcircuit is overcome, the timing sequence characteristics of the ring oscillator can be accurately verified based on the timing sequence data of the SPICE simulation precision, and the change of the circuit oscillation frequency of the ring oscillator under different PVT conditions is researched.

Description

A method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation

Technical Field

The present invention relates to the technical field of ring oscillator circuit analysis, and in particular to a method for verifying characteristics of a ring oscillator subcircuit based on SPICE simulation.

Background technique

Currently, the mainstream voltage-controlled oscillators (VCOs) are divided into two categories: LC oscillators and ring oscillators (RO). LC oscillators have high quality factors and good phase noise performance, but their limited frequency tuning range and large chip area become key defects. In contrast, ring oscillators have outstanding advantages such as large frequency tuning range, small footprint, multi-phase output, simple circuit and easy integration. However, their shortcomings are poor noise resistance and high frequency fluctuation.

The ring oscillator is a closed loop structure formed by multiple delay units connected in series. According to the different delay units, it can be mainly divided into single-ended inverter delay unit ring oscillator and differential delay unit ring oscillator. The ring oscillator can be completely manufactured by standard CMOS technology, which not only saves costs but also takes up less chip area. It can generally generate clock signals with a frequency range of several MHz to several GHz. With the rapid development of CMOS technology and system on chip (System on Chip, referred to as SOC), ring oscillators have become an attractive choice and are widely used in clock generation circuits. They are excellent clock solutions in small-area, low-cost application scenarios. As the process node continues to shrink, the parasitic capacitance contained in the ring oscillator becomes smaller, and the required power consumption is also reduced accordingly. In addition, the ring oscillator has a high reconfigurability and can easily form modules such as frequency dividers, multi-phase clock generators, and time-to-digital converters. Since the ring oscillator does not have a high-quality filter, its phase noise is worse than that of the LC oscillator and is easily affected by PVT (Process, Voltage, Temperature) conditions. Therefore, research on ring oscillators often focuses on reducing the phase noise of the ring oscillator and improving reliability.

The PVT deviation of the ring oscillator generally originates from the threshold voltage, carrier mobility and delay time deviation caused by changes in charge and discharge capacitance, and the change in the supply voltage will directly affect the charge and discharge current of the ring oscillator, thereby changing the delay time of the ring oscillator and the transition time of the rising edge and the falling edge. At the same time, the noise from the power supply will also seriously affect the phase noise of the ring oscillator. In static timing analysis (Static Timing Analysis, referred to as STA), the circuit is abstracted into a directed acyclic graph, and a graph is formed according to the direction of circuit signal transmission. Since infinite loops cannot occur, in general, there must be no loops in STA, and loops need to be disconnected. In view of the problem that STA cannot directly analyze the timing of the ring oscillator subcircuit, the present invention studies the timing characteristics of the ring oscillator subcircuit by building a SPICE simulation netlist of the ring oscillator subcircuit in a SPICE dynamic simulation manner.

Summary of the invention

In order to address the defects of the prior art, the purpose of the present invention is to provide a method for verifying the characteristics of a ring oscillator sub-circuit based on SPICE simulation. The method first connects the timing arc disconnected by STA, locates the closed-loop sub-circuit and determines whether it oscillates, then builds a SPICE simulation netlist of the closed-loop sub-circuit, completes SPICE dynamic simulation, and parses the SPICE simulation results to obtain accurate and reliable timing data for verification analysis.

In order to achieve the above object, the method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation provided by the present invention comprises the following steps:

Connect the disconnected timing arcs of the STA circuit, search for a closed-loop subcircuit in the STA circuit and determine whether it can form circuit oscillation;

Based on the closed-loop subcircuit that can form circuit oscillation, build a SPICE simulation netlist and complete the SPICE simulation;

Parse the SPICE simulation result file, obtain the timing data of the ring oscillator subcircuit, and perform verification analysis.

Furthermore, the timing arc connecting the disconnected STA circuit, the step of searching for a closed-loop sub-circuit in the STA circuit and determining whether it can form a circuit oscillation, also includes: traversing the STA circuit, using the defined ring oscillator feedback closed-loop structure characteristics as the judgment condition for the closed-loop sub-circuit, stopping the traversal process after finding a closed-loop sub-circuit that meets the judgment condition, cutting off branch circuits that are not on the closed-loop structure, and obtaining a simplified closed-loop sub-circuit.

Furthermore, it also includes: specifying the starting point of the STA circuit traversal process, traversing in the direction of signal flow in the circuit, or setting the starting point to any circuit node before or on the closed loop of a branch circuit that is known to have a closed loop structure, and finding a closed loop sub-circuit that meets the judgment conditions.

Furthermore, the ring oscillator feedback closed-loop structure is characterized in that: starting from a logic unit with multiple inputs, an excitation signal is connected to an input pin of the logic unit, passes through multiple logic units and interconnections along the direction of signal transmission, and then returns to another input pin of the logic unit.

Furthermore, the step of connecting the timing arc disconnected by the STA circuit, searching for a closed-loop subcircuit in the STA circuit and determining whether it can form a circuit oscillation, further includes:

On the found closed-loop subcircuit, except for the logic cell Cell _in connected to the excitation signal, analyze the functional logic of all other logic cells Cell _i (i=1, 2, ..., N), determine whether the timing arcs of these logic cells on the closed-loop structure work as inverting logic, and count the total number M of timing arcs working as inverting logic in all logic cells Cell _i (i=1, 2, ..., N);

According to the parity of M, the working logic of the unit timing arc Arc _ro and the unit timing arc Arc _in of the logic unit Cell _in on the closed loop structure is determined;

According to the high potential or low potential state maintained by the pin of the determined logic unit Cell _in accessing the signal, combined with the working logic of the unit timing arc _Arc in where the pin is located, it is deduced that the edge signal Signal _in accessing is a rising edge or a falling edge;

When the total number of timing arcs in all logic cells Cell _i (i=1, 2, . . . , N) and Cell _in the closed-loop subcircuit working as inverting logic in the closed-loop structure is an odd number, it is determined that the closed-loop subcircuit can form circuit oscillation.

Furthermore, the steps of building a SPICE simulation netlist and completing the SPICE simulation based on the closed-loop subcircuit capable of forming circuit oscillation include: generating link library file information, subcircuit structure description, power supply voltage value, edge excitation signal construction, and timing measurement statement declaration, wherein:

In terms of sub-circuit structure description, by analyzing the internal unit logic or reading the external constraint file, the other input pins of the logic unit that are not on the closed-loop structure are set to a high potential or low potential state to maintain the working logic of the timing arc of the logic unit on the closed loop;

In terms of edge excitation signal construction, according to the supply voltage of the logic unit Cell _in connected to the excitation signal and the edge type of the edge signal Signal _in , an excitation edge signal that satisfies the normal operation of the ring oscillator subcircuit is constructed;

In terms of timing measurement statement declaration, combined with the working logic of the unit timing arc on the closed-loop structure obtained by analysis, the flip change state of the edge signal at each node of the closed-loop sub-circuit is confirmed to ensure that the .measure statement can measure accurate period and delay data, and the .probe statement is used to save the complete signal waveform at each node of the closed-loop sub-circuit.

Furthermore, the step of building a SPICE simulation netlist and completing the SPICE simulation based on a closed-loop sub-circuit that can form circuit oscillation also includes: after the SPICE simulation is completed, when there are abnormal values in the measured period and delay data, locating the problem of the .measure statement in the netlist in combination with the complete signal waveform, correcting the error in time and updating the SPICE simulation netlist, executing the SPICE simulation again, obtaining reasonable simulation results and generating a timing report.

Furthermore, the step of parsing the SPICE simulation result file, obtaining the timing data of the ring oscillator subcircuit, and performing verification analysis also includes: parsing the SPICE simulation result file, and performing functional verification, trend analysis, jitter calculation, noise analysis, or stability research of the circuit oscillation process of the ring oscillator subcircuit based on the measured period and delay data and complete signal waveform data of the ring oscillator.

Furthermore, it also includes: modifying and updating the SPICE simulation netlist, organizing multiple groups of SPICE simulation results under different PVT conditions, and studying the changing trend of the operating frequency of the ring oscillator.

Furthermore, when under a single unique PVT condition, the ring oscillator subcircuit operates at a stable oscillation frequency, and the working period Period of the circuit oscillation is equal to the sum of all logic unit delays and interconnection delays in the closed-loop structure, and the relationship is as follows:

Among them, R and F represent the rising edge and falling edge respectively, and edge represents the edge. The edge needs to consider both the rising edge and the falling edge. It is the sum of the delays of all logic units on the closed-loop structure at the rising and falling edges. It is the sum of the delays of all interconnected lines on the closed-loop structure at the rising and falling edges;

Under different PVT conditions, the oscillation frequency of the ring oscillator subcircuit will change. After switching the process angle or modifying the voltage and temperature, the simulation will continue to obtain multiple sets of SPICE simulation timing results, which are used to analyze the trend of the oscillation frequency of the ring oscillator subcircuit as the PVT conditions change.

To achieve the above-mentioned purpose, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation as described above.

To achieve the above objectives, the present invention also provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, and the instruction is loaded and executed by a processor to implement the method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation as described above.

The method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation provided by the present invention has the following beneficial effects compared with the prior art:

When traversing the circuit structure in STA, connect the disconnected timing arcs to find the real closed-loop subcircuit. According to the structural characteristics of the ring oscillator, it can be further determined whether the closed-loop circuit can form circuit oscillation. Based on the found ring oscillator subcircuit structure, build the correct SPICE simulation netlist. Through mature SPICE simulation, obtain accurate period and delay measurement data, as well as the complete signal waveform at each node of the closed-loop subcircuit. These results can be organized into reliable and trustworthy timing reports.

This method overcomes the shortcoming that STA cannot directly analyze the timing of the ring oscillator sub-circuit. Based on the timing data with SPICE simulation accuracy, it can accurately verify the timing characteristics of the ring oscillator and study the changes in its circuit oscillation frequency under different PVT conditions.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

FIG1 is a flow chart of a method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation according to the present invention;

FIG2 is a schematic diagram of the application of SPICE simulation results of a ring oscillator subcircuit according to the present invention;

FIG. 3 is a schematic diagram of the structure of an electronic device according to the present invention.

Detailed ways

The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a flow chart of a method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation according to the present invention. The method of the present invention will be described in detail below with reference to FIG. 1 .

In the embodiment of the present invention, the SPICE simulation verification process of the ring oscillator subcircuit is mainly divided into two key parts: locating the ring oscillator subcircuit and implementing the subcircuit SPICE simulation, and each of them has a feedback iteration sub-process. In the process of locating the ring oscillator subcircuit, when the closed-loop subcircuit found does not meet the circuit oscillation condition after logical analysis, it is necessary to re-find the closed-loop structure on the next branch circuit to continue analysis and judgment. Only when the circuit oscillation condition is met will the SPICE simulation related process be entered, and the specified circuit traversal starting point and the configured timing constraint file will affect the process.

Specifically, in step 101, a closed-loop subcircuit is found.

Since in STA, the circuit must be loop-free and needs to be disconnected when there is a loop, STA cannot directly analyze the closed-loop circuit structure. Therefore, when traversing the established circuit structure in STA, it is necessary to connect the timing arc disconnected by STA and strictly follow the defined RO (ring oscillator) feedback closed-loop structure characteristics as the condition for finding a closed-loop sub-circuit structure. When a closed-loop sub-circuit structure that meets the conditions is found, the circuit traversal process can be stopped, and the branch circuits that are not on the closed-loop sub-circuit structure can be cut off, so that the closed-loop sub-circuit structure is the simplest and unique. The timing arc generally refers to the arc with a delay from the input to the output of the unit.

In the embodiment of the present invention, a single-ended inverter delay unit ring oscillator is taken as an example. The feedback closed-loop structural feature of the ring oscillator is defined as starting from a logic unit with multiple inputs, the excitation signal is connected to an input pin of the logic unit, and after passing through multiple logic units and interconnection lines along the direction of signal transmission, it returns to another input pin of the logic unit. The feedback closed-loop structural feature is used as the judgment condition of the RO closed-loop structure, and the STA circuit is traversed to find the closed-loop subcircuit.

In an embodiment of the present invention, after finding the closed-loop structure, redundant branch circuits are cut off to obtain the most simplified closed-loop sub-circuit, which can retain useful circuit structure information and will not affect the final SPICE simulation results. The SPICE simulation netlist construction and simulation timing data organization are both based on the simplified closed-loop sub-circuit structure information.

In the embodiment of the present invention, in the RO closed-loop structure judgment stage, the user needs to specify the starting point of the circuit traversal process, and traverse according to the direction of signal flow in the circuit, then the circuit structure before the starting point will be skipped, which will be very practical when the overall circuit design scale is large. In addition, since the ring oscillator structure generally exists in the clock circuit, when the user knows in advance that there is a closed-loop structure in a branch circuit, the starting point can be set to a circuit node before or on the closed loop, so that the closed-loop sub-circuit that meets the conditions can be quickly found.

In step 102, it is determined whether the closed-loop subcircuit can form circuit oscillation. If the found closed-loop subcircuit meets the oscillation condition, the next step is entered, otherwise the process returns to step 101 to continue searching for the closed-loop subcircuit.

In the embodiment of the present invention, in the RO oscillation condition analysis stage, the judgment of the unit functional logic is based on the timing arcs of the logic units on all closed-loop sub-circuits. On the found closed-loop sub-circuit structure, except for the logic unit Cell _in connected to the excitation signal, the functional logics of all other logic units Cell _i (i=1, 2, ..., N) are analyzed to determine whether the timing arcs of these logic units on the closed-loop structure work as inverted logic, and the total number M of timing arcs working as inverted logic in all logic units Cell _i (i=1, 2, ..., N) can be counted to determine the working logic of the logic unit Cell _in : since the closed-loop structure of the ring oscillator needs to contain an odd number of timing arcs of inverted working logic to form circuit oscillation, that is, when the total number of timing arcs of the logic unit Cell _in and all other logic units Cell _i (i=1, 2, ..., N) working as inverted logic on the closed-loop structure is an odd number, the closed-loop sub-circuit can form circuit oscillation. After the parity of M is determined, the unit timing arc Arc of Cell _in on the closed-loop structure is determined. _ro and the working logic of the cell timing arc Arc _in are determined; at the same time, in order to maintain the working logic of the timing arc Arc _ro , the high and low potential states that the pin of the Cell _in access signal should maintain can be determined, and combined with the working logic of the cell timing arc Arc _in where the pin is located, it can be deduced that the accessed edge signal Signal _in is a rising edge or a falling edge.

In an embodiment of the present invention, some configurable options or file interfaces are provided to accelerate the process of locating the ring oscillator subcircuit. For example, in the RO closed-loop structure judgment and RO oscillation condition analysis stage, the working logic of the constrained logic unit is determined in advance according to the read-in timing constraint file (Timing Constraint Files), which helps to accurately determine whether the closed-loop subcircuit can form circuit oscillation. In particular, when there are multiple loops in the circuit structure (such as a subcircuit structure with multiple closed loops composed of a multi-way selection device), or when there are multiple working logics in the logic unit on the closed-loop structure, such a timing constraint file is indispensable. In practical applications, it is necessary to open the interfaces of these configurable options or files to ensure that the ring oscillator subcircuit can work normally, and the SPICE simulation netlist of its subcircuit can be smoothly built and the simulation can be completed.

In an embodiment of the present invention, a closed-loop subcircuit is found in the STA circuit and analyzed to see whether it can form circuit oscillation. This process requires specifying a reasonable circuit traversal initial point and configuring the external timing constraint file in advance, so that the closed-loop subcircuit structure can be quickly located, and the working logic of each logic unit can be accurately analyzed to determine whether the closed-loop subcircuit can form circuit oscillation. The circuit traversal rules are changed in the existing STA process so that the timing arc disconnected by STA can be connected to obtain a closed-loop structure with a clear circuit structure. While locating the ring oscillator subcircuit structure, the circuit pin node that can be connected to the excitation signal is also determined, which is conducive to correctly building the SPICE simulation netlist of the subcircuit.

In step 103, a SPICE simulation netlist is constructed.

In the embodiment of the present invention, after confirming that the closed-loop subcircuit obtained by traversal and cutting is a ring oscillator subcircuit structure that can form circuit oscillation, a SPICE simulation netlist can be automatically constructed according to the existing and analyzed data information, mainly including link library file information, subcircuit structure description, power supply voltage value, edge excitation signal construction, timing measurement statement declaration, etc., wherein,

In terms of sub-circuit structure description, in order to maintain the working logic of the timing arc of the logic unit on the closed loop, the remaining input pins need to be placed in a high potential or low potential state. This can be read through internal unit logic analysis or external constraint files. The latter is a more reasonable and practical method and needs to be configured in advance.

In terms of edge excitation signal construction, according to the supply voltage of the logic cell Cell _in and the edge type of the edge signal Signal _in in step 102, a reasonable excitation edge signal that satisfies the normal operation of the ring oscillator sub-circuit can be established;

In terms of timing measurement statement declaration, attention should be paid to the measurement of oscillation period and delay data. Combined with the working logic of the unit timing arc on the closed-loop structure obtained in step 102, the flip change state of the edge signal at each node of the closed-loop subcircuit should be confirmed to ensure that the .measure statement can measure accurate period and delay data. The .probe statement can be used to save the complete signal waveform at each node of the subcircuit.

At step 104, a SPICE simulation is performed.

In step 105, the SPICE simulation results are verified. This step parses the SPICE simulation result file, obtains the period and delay measurement data of the ring oscillator, and performs RO feature verification analysis. If there are abnormal values in the simulation results, it returns to step 103. If the simulation results are reasonable, a timing report is generated.

In an embodiment of the present invention, in the SPICE simulation verification process of the ring oscillator subcircuit, when there are abnormal values such as negative values in the period and delay data measured after the SPICE simulation is completed, it is necessary to locate the problem of the .measure statement in the netlist in combination with the complete signal waveform, such as using the wrong edge type and number of edges, correct the error in time, update the SPICE netlist and perform the simulation again to ensure that reasonable simulation results are obtained to generate a timing report.

SPICE simulation-accurate timing data is a reliable basis for verifying and analyzing the timing characteristics of the ring oscillator subcircuit. By finding the ring oscillator subcircuit structure and building the correct SPICE simulation netlist, accurate period and delay measurement data, as well as the complete signal waveform at each node of the closed-loop subcircuit are obtained through mature SPICE simulation. These results can be organized into reliable and trustworthy timing reports. In the SPICE simulation results, the signal waveform of the circuit oscillation process is the most basic data. It can be used as a reference to confirm whether the measured period and delay data are reasonable. These data can complete the functional verification and stability analysis of the ring oscillator.

Furthermore, the SPICE simulation netlist can be modified as needed, and multiple groups of SPICE simulation results under different PVT conditions can be organized to study the changing trend of the operating frequency of the ring oscillator.

In the embodiment of the present invention, when under a single unique PVT condition, the RO subcircuit should operate at a stable oscillation frequency, and the working period Period of the circuit oscillation should be equal to the sum of all logic unit delays and interconnection line delays in the closed loop, that is, the following relationship exists:

Among them, R and F represent the rising edge and falling edge respectively, and edge represents the edge. The edge needs to consider both the rising edge and the falling edge. is the sum of the delays of all logic cells cell _i (i=1, 2, ..., N) at the rising and falling edges in the closed-loop structure, It is the sum of the delays of all interconnection lines net _i (i=1, 2, ..., N) on the closed-loop structure at the rising and falling edges. In special cases, if the delay of the interconnection lines is ignored, the sum of this added term is zero.

Under different PVT conditions, the oscillation frequency of the RO subcircuit will change. By switching the process corner or modifying the voltage and temperature and continuing the simulation, multiple sets of SPICE simulation timing results can be organized to analyze the trend of the RO subcircuit oscillation frequency as the PVT conditions change. In addition, the complete signal waveform saved by the .probe statement can also be used to study the stability of the RO subcircuit oscillation process, such as whether there is jitter or phase noise between different oscillation cycles.

FIG2 is a schematic diagram of the application of SPICE simulation results of a ring oscillator subcircuit according to the present invention. Referring to FIG2 , in step 201 , under PVT conditions, the SPICE simulation netlist is updated.

In the embodiment of the present invention, in the process of building a SPICE simulation netlist, the basic contents such as link library file information, subcircuit structure description, and power supply voltage value are first generated, and what needs special processing is: according to the logic analysis result in the process of locating the ring oscillator subcircuit, a reasonable edge excitation signal waveform is connected, and the correct edge type and edge number are used in the .measure statement.

In step 202, SPICE simulation is performed. During the SPICE dynamic simulation process, the .measure statement 203 inside the SPICE simulation netlist is used to output the period and delay data 205 of the subcircuit, and the .probe statement 204 inside the SPICE simulation netlist is used to save the complete signal waveform data 206 of each node of the subcircuit.

In the embodiment of the present invention, the complete signal waveform data 206 is the most important basic data, which has an indicative reference function for the period and delay data 205. Among them, the multiple sets of period and delay data 205 obtained by changing the PVT conditions can be used for the functional verification 207 of the sub-circuit, including the relationship between the period and delay data, the logic function verification of each logic unit, etc.; it can also be used for the trend analysis 208 of the sub-circuit, including the change trend of the circuit oscillation frequency, the change trend of the delay of each logic unit, etc. In addition, interference noise can be introduced into the excitation signal waveform or the power supply voltage of each logic unit. When the number of cycles of the saved complete signal waveform 206 is large enough, the stability of the signal waveform at each circuit node can be evaluated by jitter calculation 209 or noise analysis 210.

The method for verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation provided by the present invention overcomes the shortcoming that STA cannot directly analyze the timing of the ring oscillator subcircuit, and based on the timing data with SPICE simulation accuracy, it is possible to accurately verify the timing characteristics of the ring oscillator and study the change of the circuit oscillation frequency under different PVT conditions.

In an embodiment of the present invention, an electronic device is further provided. FIG. 3 is a schematic diagram of the structure of an electronic device according to the present invention. As shown in FIG. 3 , the electronic device of the present invention includes a processor 301 and a memory 302, wherein:

The memory 302 stores a computer program. When the computer program is read and executed by the processor 301 , the computer program executes the steps in the above-mentioned method embodiment for verifying the characteristics of the ring oscillator sub-circuit based on SPICE simulation.

In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the method embodiment of verifying the characteristics of a ring oscillator subcircuit based on SPICE simulation when running.

In this embodiment, the above-mentioned computer-readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. A method for verifying ring oscillator subcircuit characteristics based on SPICE simulation, comprising the steps of:

connecting a timing arc of the disconnection of an STA circuit, searching a closed-loop sub-circuit in the STA circuit and judging whether the closed-loop sub-circuit can form circuit oscillation or not;

Based on a closed-loop sub-circuit capable of forming circuit oscillation, constructing a SPICE simulation netlist and completing SPICE simulation;

Analyzing SPICE simulation result files, obtaining time sequence data of the ring oscillator subcircuit, and performing verification analysis;

the step of searching a closed loop sub-circuit in the STA circuit and judging whether the closed loop sub-circuit can form circuit oscillation or not, and the step of connecting the timing arc of the disconnection of the STA circuit further comprises the following steps:

On the found closed-loop sub-circuit, all other logic cells Cell _i (i=1, 2,..once., N) are analyzed for functional logic, except for the logic Cell _in that has the excitation signal in, judging whether the time sequence arcs of the logic units on the closed loop structure work as the inversion logic or not, and counting the total number M of the time sequence arcs working as the inversion logic in all the logic units Cell _i (i=1, 2., N);

judging the working logic of a unit time sequence Arc _ro and a unit time sequence Arc _in of a logic unit Cell _in on a closed loop structure according to the parity of M;

According to the high potential or low potential state maintained by the pins of the determined logic unit Cell _in access Signal, the working logic of the unit time sequence Arc _in where the pins are positioned is combined, and the accessed edge Signal _in is derived to be a rising edge or a falling edge;

When the total number of timing arcs on a closed-loop structure and operating as inverted logic in all logic cells Cell _i (i=1, 2,..n.) and Cell _in on a closed-loop sub-circuit is an odd number, it is determined that the closed-loop sub-circuit is capable of forming a circuit oscillation;

The step of constructing the SPICE simulation netlist and completing SPICE simulation based on the closed-loop subcircuit capable of forming circuit oscillation further comprises the following steps: generating link library file information, subcircuit structure description, power supply voltage value, edge excitation signal construction and timing measurement statement, wherein,

In the aspect of subcircuit structure description, the logic of an internal unit is analyzed or an external constraint file is read, other input pins which are not in a closed loop structure and are contained in a logic unit are set to be in a high-potential or low-potential state, and the working logic of a logic unit time sequence arc on the closed loop is maintained;

in the aspect of edge excitation Signal construction, according to the power supply voltage of a logic unit Cell _in connected with an excitation Signal and the edge type of an edge Signal _in, constructing an excitation edge Signal which meets the normal operation of a ring oscillator sub-circuit;

In the aspect of time sequence measurement statement, the working logic of a unit time sequence arc on the closed loop structure obtained through analysis is combined, the overturning change state of an edge signal on each node of the closed loop sub-circuit is confirmed, accurate period and delay data can be measured by a measurement statement, and the complete signal waveform on each node of the closed loop sub-circuit is saved by a probe statement.

2. The method of verifying ring oscillator subcircuit characteristics based on SPICE simulation of claim 1, wherein the step of connecting the timing arc of a STA circuit disconnection, looking up a closed loop subcircuit in the STA circuit and determining if it is capable of forming a circuit oscillation, further comprises: and traversing the STA circuit, taking the feedback closed-loop structural characteristic of the defined ring oscillator as a judging condition of the closed-loop subcircuit, stopping the traversing process after the closed-loop subcircuit meeting the judging condition is found, and cutting off the branch circuit which is not in the closed-loop structure to obtain the simplified closed-loop subcircuit.

3. The SPICE simulation based method of verifying ring oscillator subcircuit characteristics of claim 2, further comprising: and designating a starting point of an STA circuit traversal process, traversing according to a signal flow direction in the circuit, or setting the starting point as any circuit node before or on a closed loop of a branch circuit according to the branch circuit with a pre-known closed loop structure, and finding out a closed loop sub-circuit meeting a judgment condition.

4. The SPICE simulation based method for verifying ring oscillator subcircuit characteristics as defined in claim 2, wherein the ring oscillator feedback closed loop structure characteristics are: starting from a logic cell with multiple inputs, the stimulus signal is coupled in at one input pin of the logic cell, passes through multiple logic cells and interconnections in the direction of signal transmission, and then returns to the other input pin of the logic cell.

5. The method for verifying ring oscillator subcircuit characteristics based on SPICE simulation of claim 1, wherein the steps of constructing SPICE simulation netlist and completing SPICE simulation based on closed loop subcircuit capable of forming circuit oscillation further comprise: after SPICE simulation is completed, when abnormal values exist in the measured period and delay data, the problems existing in the measurement statement in the netlist are positioned by combining the complete signal waveform, the SPICE simulation netlist is corrected and updated in time, the SPICE simulation is executed again, a reasonable simulation result is obtained, and a time sequence report is generated.

6. The method for verifying a ring oscillator subcircuit feature based on SPICE simulation of claim 1, wherein the step of parsing SPICE simulation result file, obtaining timing data of the ring oscillator subcircuit, and performing verification analysis further comprises: and analyzing SPICE simulation result files, and carrying out function verification, trend analysis, jitter calculation, noise analysis or stability research of a circuit oscillation process of the ring oscillator based on the measured period and delay data and complete signal waveform data of the ring oscillator.

7. The SPICE simulation based method of verifying ring oscillator subcircuit characteristics of claim 1, further comprising: and modifying and updating the SPICE simulation netlist, organizing a plurality of groups of SPICE simulation results under different PVT conditions, and researching the change trend rule of the working frequency of the ring oscillator.

8. The method of verifying ring oscillator subcircuit characteristics based on SPICE simulation of claim 7, wherein the ring oscillator subcircuit operates at a stable oscillation frequency when in a single unique PVT condition, and the Period of operation when the circuit oscillates is equivalent to the sum of all logic cell delays and interconnect line delays on a closed loop structure, the relationship being as follows:

Wherein R, F respectively represent a rising edge and a falling edge, edge represents an edge, the edge needs to consider the rising edge and the falling edge at the same time, Is the sum of the delay amounts of all logic units on the rising edge and the falling edge on the closed loop structure,The sum of delay amounts of all interconnection lines on the closed loop structure at the rising edge and the falling edge;

When the oscillation frequency of the ring oscillator subcircuit is changed under different PVT conditions, the simulation is continued after the process angle is switched or the voltage and the temperature are modified, and a plurality of sets of SPICE simulation time sequence results are obtained and are used for analyzing the trend rule of the oscillation frequency of the ring oscillator subcircuit along with the change of the PVT conditions.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor for executing the computer program stored in the memory to implement the method of verifying ring oscillator subcircuit characteristics based on SPICE simulations of any of claims 1 to 8.

10. A computer readable storage medium having stored therein at least one instruction, wherein the instructions are loaded and executed by a processor to implement the method of verifying ring oscillator subcircuit characteristics based on SPICE simulations of any of claims 1 to 8.