CN116880775A

CN116880775A - Hardware management module, chip, electronic equipment and method for storage space

Info

Publication number: CN116880775A
Application number: CN202311143507.8A
Authority: CN
Inventors: 周滔; 熊焰
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2023-09-06
Filing date: 2023-09-06
Publication date: 2023-10-13
Anticipated expiration: 2043-09-06
Also published as: CN116880775B

Abstract

The application discloses a hardware management module, a chip, electronic equipment and a method for a storage space, and belongs to the technical field of chips. The hardware management module includes: the first register set is used for storing the states of n management units; the first logic gate circuit is used for calculating a state vector of at least one management level according to the states of the n management units; the first retriever is used for determining a first management level from at least one management level according to the first capacity to be allocated, and storing a state vector of the first management level into the second register group; the second retriever is used for determining a first element from the state vector of the first management level and storing index information of a first management unit corresponding to the first element into the second register group; the signal conversion unit is used for converting the index information of the first management unit into a first base address of the storage space and storing the first base address into the second register group. And the storage space management is realized through a hardware mechanism, so that the storage space management difficulty is reduced.

Description

Hardware management module, chip, electronic equipment and method for storage space

Technical Field

The present application relates to the field of chip technologies, and in particular, to a hardware management module for a storage space, a chip, an electronic device, and a method.

Background

Storage Space (Storage Space) is used for storing data or instructions, and a programmer can manage the Storage Space in order to improve the utilization efficiency of the Storage Space.

In the related art, a storage space is statically managed. The programmer is required to memorize the use state and the release time of the storage space occupied by each task, and the programmer thinks the base address for operating the storage space to avoid the address stepping in the process of allocating the storage space.

This approach requires the programmer to pay attention to the storage space occupied by all tasks, which can easily lead to errors in storage space allocation.

Disclosure of Invention

The application provides a hardware management module, a chip, electronic equipment and a method for a storage space. The technical scheme is described below.

According to an aspect of an embodiment of the present application, there is provided a hardware management module for a storage space, the hardware management module including: the first register group, the first logic gate circuit, the first retriever, the second register group, the second retriever and the signal conversion unit; the storage space comprises n management units, the first register group is used for storing states of the n management units, and n is a positive integer;

The first logic gate circuit is used for calculating a state vector of at least one management level according to the states of the n management units, each element in the state vector is used for representing the states of the corresponding first number of management units, and different management levels correspond to different first numbers;

the first retriever is configured to determine a first management level from the at least one management level according to a first capacity to be allocated, and store a state vector of the first management level into the second register group; wherein a first number corresponding to the first management level is adapted to the first capacity;

the second retriever is configured to determine a first element from the state vector of the first management level, and store index information of a first management unit corresponding to the first element into the second register set, where states of a first number of management units corresponding to the first element are idle states, and the first management unit is one management unit of the first number of management units corresponding to the first element;

the signal conversion unit is used for converting the index information of the first management unit into a first base address in the storage space and storing the first base address into the second register group; wherein the first base address is used to indicate a location of the first capacity in the storage space.

According to an aspect of an embodiment of the present application, there is provided a chip including: a memory and a hardware management module for the memory space as described above.

According to an aspect of an embodiment of the present application, there is provided an electronic device including a hardware management module of a storage space as described above.

According to an aspect of the embodiment of the present application, there is provided a storage space management method based on a hardware management module, where the hardware management module includes: the first register group, the first logic gate circuit, the first retriever, the second register group, the second retriever and the signal conversion unit; the storage space comprises n management units, the first register group is used for storing states of the n management units, and n is a positive integer; the method comprises the following steps: the first logic gate circuit calculates a state vector of at least one management level according to the states of the n management units, wherein each element in the state vector is used for representing the states of the corresponding first number of management units, and different management levels correspond to different first numbers;

the first retriever determines a first management level from the at least one management level according to a first capacity to be allocated, and stores a state vector of the first management level into the second register group; wherein a first number corresponding to the first management level is adapted to the first capacity;

The second retriever determines a first element from the state vector of the first management level, and stores index information of a first management unit corresponding to the first element into the second register group, wherein states of a first number of management units corresponding to the first element are idle states, and the first management unit is one management unit of the first number of management units corresponding to the first element;

the signal conversion unit converts index information of the first management unit to a first base address in the storage space, and stores the first base address into the second register set; wherein the first base address is used to indicate a location of the first capacity in the storage space.

The technical scheme provided by the application is that the hardware management module for managing the storage space is arranged, so that the management of the storage space is realized from the hardware level. Under the condition that the storage space with the target capacity needs to be allocated, the hardware management module finds an address segment which is in an idle state and is matched with the target capacity from the storage space according to the target capacity, returns the address segment corresponding to the base address, and finishes the allocation process of the storage unit in the storage space from the base address.

On one hand, the hardware management module is used for managing the states of all positions in the storage space, so that operation resources in the central processing unit are not required to be consumed excessively in the process of managing the storage space. Compared with the method that a programmer manually selects the base address according to the execution condition of each task; according to the embodiment of the application, the storage space is managed through the hardware management module, and the hardware management module automatically searches the base address meeting the target capacity in the storage space, so that the attention degree of programmers to serial relations and execution conditions of each task is reduced, the address segment in an occupied state is prevented from being allocated again, and the reliability of storage space management is improved.

On the other hand, in the process of allocating the storage space by the hardware management module, the hardware structures such as the register group in the hardware management module are multiplexed, so that the volume of the hardware management module is reduced while the storage space allocation is realized, the cost of the hardware management module is reduced, and the influence on other functional modules arranged in a chip after the hardware management module is introduced is reduced.

Drawings

FIG. 1 is a schematic diagram of tasks and assigned address segments provided by an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of the inventive concepts provided by an exemplary embodiment of the present application;

FIG. 3 is a schematic diagram of a hardware management module of a multi-core chip according to an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a hardware management module for a memory space according to an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a state representation of a management unit provided by an exemplary embodiment of the present application;

FIG. 6 is a schematic diagram of various management levels provided by an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a method for determining a state vector according to an exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a first logic gate type provided by an exemplary embodiment of the present application;

FIG. 9 is a schematic diagram of a first logic gate type provided by another exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of the components of a hardware management module provided by an exemplary embodiment of the present application;

FIG. 11 is a state flow diagram of a finite state according to an exemplary embodiment of the present application;

FIG. 12 is a circuit diagram of a hardware management module provided in an exemplary embodiment of the application;

FIG. 13 is a flowchart of a method for providing a hardware management module based memory space in accordance with an exemplary embodiment of the present application;

FIG. 14 is a flow chart of allocating memory provided by an exemplary embodiment of the present application;

FIG. 15 is a schematic diagram of allocating memory provided by an exemplary embodiment of the present application;

FIG. 16 is a flow chart of freeing memory provided by an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

Before describing the present application, the background art related to the present application will be explained first.

Generally, for a Memory space (e.g., a Level1 Memory (L1 Memory)) in a chip, a programmer is required to manage the Memory space in a static manner. That is, the programmer needs to plan the use of memory of different address segments of the L1 memory in advance, manually memorize the use period of an address segment in the execution process of a certain task, and release the address segment at the moment.

FIG. 1 is a schematic diagram of tasks and assigned address segments provided by an exemplary embodiment of the present application.

In FIG. 1, tasks (tasks) A-D are assigned four different address segments, respectively; wherein, the address segment allocated to task A is [0:1023], and the address segment allocated to task B is [1024:2047]. The task A and the task B are in parallel operation relation, and address overlapping cannot occur between address sections respectively allocated to the task A and the task B; if address overlapping occurs between the address segments respectively allocated to the task a and the task B, the data content to be used stored in the address segment allocated to the task a may be erroneously overwritten by the task B, thereby causing an operation error of the task a.

It can be seen from fig. 1 that task E starts to run after task D finishes running, so task E can use the address segment [7000:8000] released after task D finishes executing, but task a and task C have not yet run, so the assigned address segment [0:1023] of task a and the assigned address segment [2048:6000] of task C cannot be assigned to task E.

When task F starts to execute, task A and task B have ended, so that address fields [0:1023], [1024:2047] are assigned to task F without causing execution errors of task A and task B, that is, address fields [0:1023], [1024:2047] can be assigned to task F.

As can be seen from fig. 1 and the description, this method for static management of storage space relies entirely on manual control by a programmer, who needs to make clear the parallel/serial relationship between tasks to reasonably allocate memory for each task. This method is extremely a trial of the level of care of the programmer. Particularly, when the number of tasks is relatively large and the task serial-parallel relationship scene is complex, programmers have great burden, so that the allocation process of the storage space is easy to make mistakes.

In addition, a memory management mechanism similar to an operating system is provided in the related art, and the memory space is managed by means of software, wherein the software is used for providing marks representing idle states of address segments in the memory space, and the allocation and release of the memory space are realized by operating the marks through a software program. Because the use condition of each address segment in the storage space is dynamically changed, each time the storage space is managed, software is required to count the idle state of each address segment in the storage space at the current moment, so that the software calling period is too long, and a large amount of operation resources in the central processing unit are occupied; it can be seen that this approach has some negative impact in achieving management of storage space, and further improvements in the method of managing storage space are needed.

Fig. 2 is a schematic diagram of the inventive concept provided by an exemplary embodiment of the present application.

The hardware management module provided in the present application may also be referred to as a hardware memory management (Hardware Memory Management, HMM) module. The hardware management module is controlled by a central processing unit (Central Processing Unit, CPU), and is connected with the central processing unit through a central processing unit bus (CPU Main Pipeline). The hardware management module can be understood as a circuit structure on a chip, and the circuit structure can realize the management of the storage space.

The hardware management module has the functions of distributing the storage space and releasing the storage space, the central processor sends an instruction to the hardware management module through the central processor bus, the hardware management module manages the storage space according to the instruction after receiving the instruction and generates a processing result, and the hardware management module feeds the processing result back to the central processor through the central processor bus.

Optionally, the instructions include at least one of: allocation instructions and release instructions. The allocation instruction is used for instructing the hardware management module to allocate the address block of the first capacity from the storage space, and the release instruction is used for instructing the hardware management module to release the address block of the second capacity from the base address in the storage space.

The hardware management module assists a programmer to complete a management process of the storage space, the programmer calls an allocation instruction or a release instruction, the central processor analyzes the allocation instruction or the release instruction into an instruction form which can be identified by the hardware management module after receiving the allocation instruction or the release instruction, and the analyzed allocation instruction or the analyzed release instruction is transmitted to the hardware management module through a bus of the central processor.

The allocation instruction and the release instruction mentioned here are instructions designed for the hardware management module.

For an allocation instruction, the programmer need only indicate in the allocation instruction the value of the first capacity that needs to be allocated, and need not indicate the base address of the first capacity in memory space. That is, the programmer only needs to request the first capacity allocated from the storage space from the device, and the process of determining which part of the address segment in the storage space is allocated is implemented by the hardware management module. This eliminates the need for the programmer to pay attention to the occupation of each address segment in the storage space at any time, which helps to relieve the pressure of the programmer on managing the storage space.

For the release instruction, the programmer indicates the second capacity in the storage space to be released and the base address of the address segment to be released by the release instruction.

Alternatively, the allocation instructions and release instructions may be in a low-level language (e.g., assembly language) or a high-level language that needs to be compiled, and the application is not limited in this regard. Illustratively, the allocation instruction includes an allocation identifier, a first capacity, and a register sequence number for storing a first base address; the allocation identifier is used for indicating the function of an allocation instruction, and the first capacity refers to the capacity which needs to be allocated from the storage space, namely the number of addresses which should be included in an allocated address field; the first base address is one address in an address segment which is determined by the hardware management module and is matched with the target capacity, and any memory corresponding to the matched address segment can be accessed by shifting the first base address; the sequence number of the register used for storing the first base address is used for indicating to the hardware management module which register is used for storing the first base address after the first base address is determined, so that a programmer obtains the first base address by accessing the register corresponding to the sequence number, and the corresponding address segment in the storage space is used according to the first base address.

Illustratively, a method of defining the allocation instructions and the release instructions is described.

1. Allocation instructions: ALLOCATE_BUFFER out Rd, in Rs1

Wherein "ALLOCATE_BUFFER" is an allocation identifier used for characterizing that the instruction is used for allocating memory space, "out" represents output, "Rd" is used for indicating a register sequence number storing a first base address, the register is any available register in a general-purpose register, that is, "out: rd" represents output of information stored in the register with the sequence number Rd; "in" indicates reading in, "Rs1" indicates a sequence number of a register for storing a value corresponding to the first capacity, that is, "in: rs1" indicates reading the first capacity to be allocated from the register of sequence number Rs 1.

The allocation instruction can be described in simplified terms as: base= allocate (size).

2. Release instruction: FREE_BUFFER in: rs1, in: rs2

Where "free_buffer" is a release flag characterizing that the instruction is to release memory, "Rs1" is to indicate the sequence number of the register storing the second base address, and "Rs2" is to indicate the sequence number of the register storing the second capacity to be released.

The allocation instruction may be simply described as free (base).

The methods of use of the dispense instructions and release instructions are described by way of example.

For example, at a certain time, a programmer wants to apply for allocation of 128 bytes of memory for temporary storage of data, then the programmer needs to specify a first capacity and then call the allocation instruction.

Illustratively: the instructions that need to be used in this process are: mov Rx, 128, allocate_ buffer Ry, rx.

Where "mov" means using the general register Rx store 128 and "allocate_buffer Ry, rx" means allocating a block of address segments greater than or equal to 128 bytes from the memory space and returning the first base address in the allocated address segment stored in the general register Ry.

When the address field of the 128byte is used up, the address field needs to be released, in which case a release instruction "free_buffer Ry, rx" may be invoked.

Here, "free_buffer Ry, rx" means that, starting from the second base address stored in the general register Ry, the corresponding address segment in the memory space is released according to the second capacity stored in the general register Rx.

FIG. 3 is a schematic diagram of a hardware management module of a multi-core chip according to an exemplary embodiment of the present application.

For a multi-core chip (i.e., a chip that includes multiple central processing units), the central processing units store different data and instructions in the respective memory areas due to the different memory areas that each central processing unit has. Thus, each central processor in a multi-core processor may have an independent hardware management module, respectively.

For example, fig. 3 includes 4 central processing units, CPU1, CPU2, CPU3, and CPU4, respectively. The 4 central processing units correspond to the independent 4 hardware management modules, namely HMM1, HMM2 HMM3 and HMM4. Specifically, CPU1 corresponds to HMM1, CPU2 corresponds to HMM2, CPU3 corresponds to HMM3, and CPU4 corresponds to HMM4.

For example, 1 hardware management module may be shared by a plurality of central processing units. Therefore, the hardware management module is used for managing the storage spaces respectively corresponding to the plurality of central processing units, and the occupied volume of the hardware management module in the chip is reduced.

FIG. 4 is a schematic diagram of a hardware management module for a memory space according to an exemplary embodiment of the present application. The hardware management module includes: a first register group 410, a first logic gate 420, a first retriever 430, a second register group 440, a second retriever 450, and a signal conversion unit 460; wherein the storage space comprises n management units.

The storage space refers to a logic storage structure, the storage space is used for providing addressing space and corresponding logic storage units (Logic Storage Unit, LSU) for upper-layer applications, and a Data structure (Meta Data) is arranged inside the storage space and used for realizing mapping relation between the logic storage units and addresses of lower-layer storage spaces. The storage space also has an access operation set for accessing the lower storage space, and the data access request analysis of the upper layer for the logic storage unit is transferred to the lower storage space.

The memory space may correspond to an address block comprising at least one memory address for accessing a memory location in the memory space. For example, the address block corresponding to the memory space is [0, 10000], and then the corresponding 100 th memory cell in the memory space can be accessed through the address 100.

In some embodiments, the memory space used by the hardware management module for management is a static address space, and the memory can be accessed by using the static address space corresponding to any static address.

Optionally, the types of storage space include, but are not limited to, memory, cache, and storage space in a hard disk. For example, the storage space is an L1 Memory, and the L1 Memory has the characteristics of fast reading speed and small storage capacity. The L1 Memory is used for storing data or instructions with higher use frequency in the task execution process of the central processing unit. Optionally, the L1 Memory refers to a Memory space corresponding to a Memory disposed near the central processing unit. Of course, the storage space may be referred to as an L2 Memory, an L3 Memory, or the like, and the present application is not limited thereto.

In some embodiments, the management unit refers to a functional unit implemented by the hardware management module to manage the storage space. Optionally, the management unit is a basic unit for managing the storage space by the hardware management module, that is, when the hardware management module manages the storage space, the storage space is allocated or released by taking the management unit as a unit.

Optionally, the management unit includes at least one storage unit. Illustratively, one management unit includes m storage units, where m is a positive integer. For example, one management unit includes 256 storage units. As another example, 1024 storage units are included in one management unit.

Alternatively, in order to facilitate management of the storage space using the management unit, a plurality of storage units included in one management unit are consecutive, that is, the m storage units are consecutive. Since each memory unit corresponds to at least one address in the memory space, one management unit corresponds to one address segment in the memory space.

The number of storage units included in the management unit is determined according to actual needs, and the present application is not limited herein. For example, to simplify the structure of the hardware management module, a management unit may be designed to include a large number of memory units (for reasons related to this part, see below). For example, in order to improve the utilization efficiency of the storage space and reduce the waste of the storage units, the management unit may be designed to include a small amount of storage space, so as to reduce the number of underutilized storage units in the process of performing storage space allocation in units of the management unit and improve the utilization efficiency of the storage units.

In some implementations, the number of management units is related to the total capacity of the storage space as well as the capacity of a single management unit. For example, in the case where the unit of the total capacity of the storage space and the unit of the capacity of the management unit are unified, the number of management units is equal to the total capacity of the storage space divided by the capacity of the management unit. If the quotient of the total capacity of the storage space divided by the capacity of the management unit is a non-integer, the result of rounding up the quotient is taken as the value of n. For example, the total capacity of the storage space is equal to 512.5 kbytes, the capacity of the management unit is 1024 bytes (1K), 512.5K/1 k=512.5, and the whole is equal to 513, n=513.

In order to avoid repeated management of a certain address segment, there is no overlap between address segments respectively corresponding to different management units, i.e. the different management units do not include the same storage unit. In one example, assuming that the management units in the hardware management module include 1024 bytes, the total capacity of the storage space is 512 kbytes, the storage space is divided into 512 management units; the address segment corresponding to the management unit 0 is [0, 1023], the address segment corresponding to the management unit 1 is [1024, 2047], and so on. Alternatively, the management unit is also referred to as a minimum management unit (entry).

The following describes each component in the hardware management module.

The first register set 410 is used for storing the states of n management units, where n is a positive integer.

In some embodiments, the first register set 410 includes at least one register therein for storing the state of at least one management unit for any one of the registers in the first register set 410. Illustratively, the first register set is for storing a value of at least n bits.

Optionally, the state of the management unit comprises at least one of: idle state, occupied state. The idle state indicates that m storage units included in the management unit are unoccupied, and the occupied state indicates that at least one storage unit in the m storage units is in an occupied state.

Since the allocation of the memory space by the hardware management module is in units of management units, that is, for all the memory units included in one management space, either the memory units are allocated to the same task or any one of the memory units cannot be allocated individually, the state of the management unit is used to reflect the state of each memory unit included in the management unit, that is, the overall state of the address segment corresponding to the management unit.

For example, one management unit includes 128 storage units, and in the case that the 128 storage units are in an idle state, the management unit is in an idle state; in the case where at least one of the 128 memory cells is in an occupied state, the management unit is in an occupied state.

Alternatively, the state of the management unit is represented using a 1 bit (bit) character, in which case the first register set 410 includes n bits. Illustratively, "1" indicates that the management unit is in an idle state and "0" indicates that the management unit is in an occupied state. Illustratively, "0" indicates that the management unit is in an idle state and "1" indicates that the management unit is in an occupied state. It should be noted that, the idle state and the occupied state are determined according to actual needs, and the circuit structures in the hardware management module are slightly different in different representation modes, but the function of managing the storage space can be realized, and the specific content of the part is referred to below.

In one example, for the case in which the storage space includes 512 management units in the above embodiment, n is equal to 512, that is, the first register group 410 includes at least 512 bits. The value of any one of the 512 bits is used to represent the status of one of the 512 management units.

Fig. 5 is a schematic diagram of a state representation of a management unit provided by an exemplary embodiment of the present application. As shown in fig. 5, the first register set 500 includes 512 bits, each bit being used to represent the status of one management unit. The state 510 corresponding to bit 4 as in fig. 5 is represented by a value of 0.

The first logic gate circuit 420 is configured to calculate a state vector of at least one management level according to the states of the n management units, where each element in the state vector is used to characterize the states of a corresponding first number of management units, and different management levels correspond to different first numbers.

The first logic gate circuit 420 refers to a circuit structure connected to the first register set 410, and the first logic gate circuit 420 is configured to perform a logic operation based on the values stored in the respective registers in the first register set 410, so as to implement hierarchical management on n management units. The management levels in the embodiment of the present application are concepts used in the process of designing the hardware management module, and the hardware management module only needs to maintain the state vectors of each management level in the working process, and for specific details of the state vectors, please refer to the following.

In some embodiments, the number of management levels in the hardware management module is in positive correlation with the number of management units included in the storage space, with other variables being controlled. That is, the greater the number of management units, the greater the number of management levels; the fewer the number of management units, the fewer the number of management levels.

Optionally, the number of management levels is equal toWherein->For the round-up function, x is a positive integer greater than 1, x equals 2, 3, 4, … …, n represents the number of management units that the storage space comprises. For example, if the storage space includes 512 management units, in the case of x=2, the number of management levels is equal to 10, and the 10 management levels are respectively from low to high: management level 0, management level 1, management level 2, … …, management level 8, management level 9.

In some embodiments, each management level has a state vector. Illustratively, the hardware management module is provided with t management levels, wherein t is a positive integer #) For the lowest management level (the underlying management level) of the t management levels, the state vector of the underlying management level is used to characterize the states of the n management units.

Optionally, the state vector of the underlying management level is determined by the first register set 410. Illustratively, the first register set 410 is 4 bits, i.e. the storage space is divided into 4 management units, and the content stored in the first register set 410 of 4 bits is 0001, which is expressed from right to left: the states of the management units 3 and 2 are "0", the states of the management units 1 and 0 are "0", respectively, i.e. the state vector of the bottom management level is expressed as (0, 1).

In some embodiments, for other management levels of the at least one management level other than the underlying management level, the state vectors of these management levels are determined by the first logic gate 420 from the state vectors of the underlying management level.

The first logic gate circuit 420 includes at least one logic gate for performing a logic operation. Alternatively, the logic gate in the first logic gate circuit refers to a two-bit logic gate, that is, the logic gate needs two input signals to output one signal.

Illustratively, the types of the individual logic gates in the first logic gate 420 are the same. For example, the logic gates in the first logic gate circuit 420 are all AND gates. For another example, the logic gates in the first logic gate circuit 420 are all OR gates.

In some embodiments, at least one logic gate is divided into different logic gate layers, including at least one logic gate therein. That is, the first logic gate circuit 420 includes at least one logic gate layer. The logic gate layer is used to determine a state vector of the management hierarchy. Optionally, for any one of the at least one logic gate layer, the output signals of k logic gates included in the logic gate layer are state vectors of a certain management level, and k is a positive integer.

Illustratively, different logic gate layers each include a different number of logic gates.

In one example, for a certain logic gate layer of the at least one logic gate layer, each logic gate in the logic gate layer performs logic processing on the value stored in the first register set 410 to obtain a state vector of a management level corresponding to the logic gate. That is, the state vectors of the other management levels are directly determined according to the state vector of the underlying management level, in which case there is at least one bit of the input data of any one of the logic gates in the first logic gate layer 420 stored in the first register group 410.

For example, the hardware management module can determine 3 management levels, the state vector of the underlying management level of the 3 management levels being determined by the first register set 410; logic processing is performed on the state vector of the bottom management level by the logic gate layer 1 in the first logic gate circuit 420 to obtain a state vector of the 2 nd management level; the state vector of the lower management level is logically processed by the logic gate layer 2 in the first logic gate circuit 420 to obtain the state vector of the 3 rd management level.

In one example, for a particular one of the at least one logic gate layers, the logic gate layer determines a state vector for an i-th management level from the state vector for the i-1-th management level, i being a positive integer greater than or equal to 1. In this case, the first logic gate 420 determines that at least one management level corresponds to a state vector, respectively, from the first register set 410 layer by layer up from the underlying management level. In addition to the management levels adjacent to the underlying management level, the input data of the logic gates in the logic gate levels respectively corresponding to the other management levels are elements in the adjacent underlying layer vectors.

Optionally, for management level i and management level i+1 that do not belong to the underlying management level. Assuming that the state vector of the management level i is calculated by the logic gate layer j, and the state vector of the management level i+1 is calculated by the logic gate layer j+1, the input data of the logic gate in the logic gate layer j-1 is the output data of the corresponding logic gate in the j-th logic gate layer, and for details of this portion, please refer to the following embodiments.

For example, the hardware management module can determine 3 management levels, and then the state vector of the bottom management level of the 3 management levels is determined by the first register set 410; logic processing is performed on the state vector of the bottom management level by the logic gate layer 1 in the first logic gate circuit 420 to obtain a state vector of the 2 nd management level; the state vector of the second management level is logically processed by the logic gate layer 2 in the first logic gate circuit 420 to obtain the state vector of the 3 rd management level.

Because the corresponding first numbers in different management levels are different, the number of logic gates required to be set for determining the state vector of the management level of the upper layer is less by the state vector of the management level of the adjacent lower layer, which is beneficial to reducing the use requirement of hardware resources in the hardware management module. For details of this section, please refer to the following.

The first logic gate circuit is arranged in the mode, so that the number of logic gates needing to be arranged in the first logic gate circuit is reduced, the size of the first logic gate circuit is reduced, and the cost for realizing the hardware management module is reduced.

Fig. 6 is a schematic diagram of various management levels provided by an exemplary embodiment of the present application.

In FIG. 6, the state vector of management level 0 (Free [0] [0:511 ]) is logically processed by the logic gate layer 1 to obtain the state vector of management level 1 (Free [1] [0:511 ]), the state vector of management level 1 (Free [1] [0:511 ]) is logically processed by the logic gate layer 2 to obtain the state vector of management level 2 (Free [2] [0:511 ]), … …, and so on to obtain the state vector of management level 9 (Free [9] [0:511 ]).

In some implementations, the first number corresponding to a management hierarchy is used to characterize the number of management units corresponding to elements of the management hierarchy. The elements in the state vector refer to any basic unit composing the state vector, for example, a certain state vector a= a =, a ），/>I.e. an element in the state vector i=1, 2, 3,/-for example>The value of (2) is 0 or 1.

Optionally, an element in the state vector is used to characterize the state of a first number of management units that are address sequential.

In some embodiments, the first number of different management levels is different.

Optionally, the first number has a positive correlation with the number of levels of the management hierarchy. That is, the greater the number of levels of the management level, the greater the value of the first number corresponding to the management level; the smaller the number of levels of the management level, the smaller the value of the first number corresponding to the management level.

Optionally, the first number of values is inversely related to the number of levels of the management level, which is the same as the processing principle that the first number of values is directly related to the number of levels of the management level, and the first number of values is described below as an example of the positive relationship between the first number of values and the number of levels of the management level.

Illustratively, the respective first numbers of management levels arranged from the bottom layer to the upper layer rise exponentially. For example, the first number corresponding to management level 0 (i.e., the bottom management level) is 1, i.e., each element in the state vector of the bottom management level corresponds to a management unit, and the value of the element is used to reflect the state of 1 management unit corresponding to the element; the first number corresponding to the management level 1 (i.e., the management level adjacent to the underlying management level) is 2, that is, each element in the state vector of the management level 1 corresponds to 2 management units, the value of the element is used to reflect the states of the 2 corresponding management units, and when all 2 management units are in the idle state, the value of the element is a value (such as the value of "1") representing the idle state; in other cases, the values of the elements are all values representing the occupied state (e.g., the value "0"), the first number corresponding to the management level 2 (i.e., the higher-level management level adjacent to the management level 1) is 4, and so on.

In some embodiments, in order to improve the utilization efficiency of the storage space, if an element in a state vector of a certain management level is used to characterize the states of a plurality of management units (i.e. the first number corresponding to the management level is greater than 1), for any two adjacent elements in the state vector of the management level: the management unit corresponding to the element a and the management unit corresponding to the element b are overlapped.

For example, for element "5" and element "6" in the state vector of management level 1 (Free [1] [0:511 ]) of FIG. 6, element "6" in the state vector of management level 1 (Free [1] [0:511 ]) is determined by the logic gates from element "7" and element "6" in the state vector of management level 0 (Free [0] [0:511 ]); element "5" in the management level 1 state vector (Free [1] [0:511 ]) is determined by a logic gate from element "6" and element "5" in the management level 0 state vector (Free [0] [0:511 ]). That is, element "6" in the state vector (Free [1] [0:511 ]) of management level 1 is used to characterize the states of management units 6 and 7, element "5" in the state vector (Free [1] [0:511 ]) of management level 1 is used to characterize management units 6 and 5, and management unit 5 is a management unit that manages overlapping management of element "5" and element "6" in the state vector (Free [1] [0:511 ]).

In some embodiments, the dimensions of the state vectors of at least one management level are the same, and for a state vector corresponding to any one management level, the dimension of the state vector is n×1; the state vectors of the at least one management level constitute a state matrix. Optionally, the state matrix is of the scale:row, n columns, where row 1 in the state matrix is the state vector of the underlying management level, row 2 in the state matrix is the state vector of the management level adjacent to the underlying management level, and so on.

In some embodiments, the first logic gate 420 acts on the first register set 410, and in the case of value determination in the first register set 410, the first logic gate 420 completes layer-by-layer signal computation in a short time based on the value stored in the first register set 410, resulting in a state vector for each management level.

Illustratively, the output data (or referred to as output signal, output state) of any one of the first logic gates 420 is the value of a certain element in the state vector of a certain management level. That is, by reading the states of the logic gates in a certain logic gate layer in the first logic gate circuit 420, the state vector of the management level corresponding to the logic gate layer is obtained. That is, the state vectors of the other management levels, in addition to the underlying management level, can be determined by collecting the output states of the logic gates in the first logic gate 420. For details of the first logic gate 420, please refer to the following embodiments.

With this arrangement, only the first register set and the first logic gate circuit need to be included in the hardware management module to generate and hold the state vector of each management level; there is no need to additionally provide a register set for storing the state vector of each management level for a long time in the hardware management module. On one hand, the register quantity required by setting the hardware management module is reduced, and the cost of the hardware management module is reduced; on the other hand, in the case that the bits stored in the first register group change, the first logic gate circuit can quickly update the state vector of each management level through signal calculation, which helps to promote the efficiency of updating the state vector of the logic level.

The first retriever 430 is configured to determine a first management level from at least one management level according to a first capacity to be allocated, and store a state vector of the first management level into the second register group 440; wherein a first number corresponding to the first management level is adapted to the first capacity.

In some embodiments, the first capacity to be allocated is used to characterize the capacity that needs to be allocated from the storage space. Optionally, the first capacity to be allocated is determined according to allocation instructions invoked by a programmer. For specific content of the allocation instruction, please refer to the above embodiment, if the allocation instruction carries the first capacity to be allocated.

Alternatively, the unit of the first capacity is a management unit. E.g. the first capacity is 3 management units. Alternatively, the unit of the first capacity is larger than one management unit, or the unit of the first capacity is smaller than one management unit. For example, the unit of the first capacity is 2048 bytes, and one management unit corresponds to 1024 bytes. In this case, it is necessary to convert the unit of the first capacity into management units, the unit-converted first capacity being (2048/1024) 2 management units; then, the first retriever 430 in the hardware management module retrieves the first capacity after the unit conversion, and determines a first management level.

In some embodiments, the first retriever 430 belongs to a 1/0 retriever, and is configured to retrieve a position where a certain numerical value appears from a string of 01 characters in the retrieval order.

Optionally, the first retriever 430 is a leading 1 retriever (loading_one) for retrieving the binary representation of the first capacity, and determining the most significant bit in the binary representation of the first capacity as the number of levels corresponding to the first management level.

For example, assuming that the value of F is equal to an exponent result based on 2 and the number of management levels is an exponent, the increment logic of the first data conforms to the carry rule of the number of binary representations, and the most significant bit in the binary representation of the first capacity is used as the number of levels of the first management level, so that the determined first number of the first management levels is greater than or equal to the first capacity, and the processing logic of the first capacity management unit in idle state is conveniently determined according to the state vector of the first management level.

For the case where the first number is equal to an exponent result that is exponential to the number of levels of the management hierarchy, y=3, 4, 5, … …, the first retriever 430 means for performing the calculationElement(s) of->The result is the number of layers of the first management level; where s represents a first capacity in units of management units.

For the case that the first number is another value, the first retriever 430 is configured to determine a first number that matches the first capacity, and use a management hierarchy corresponding to the first number that matches the first capacity as the first management hierarchy.

Optionally, the first retriever 430 determines that the first number corresponding to the first management level is closest to the first capacity, and the first number corresponding to the first management level is greater than the first capacity. For example, the first capacity is equal to 3, and the determined first number corresponding to the first management level is equal to 4.

Optionally, the first retriever 430 determines that the first number corresponding to the first management level is closest to the first capacity, and the first number corresponding to the first management level is less than the first capacity. For example, the first capacity is equal to 5, and the determined first number corresponding to the first management level is equal to 4.

As can be seen from the above, the first retriever 430 is of a type related to the first number of the management levels, and the composition of the first retriever 430 may be actually set as required.

In some embodiments, the second register set 440 is an intermediate register used in the process of managing the memory space by the hardware management module, and the second register set 440 is used to register intermediate data generated when managing the memory space. Illustratively, the generation of intermediate data during the memory allocation process includes, but is not limited to, a state vector of a first management level, a first base address, etc., and the relevant content of the data registered in the second register set 440 is described below.

The hardware management module includes a first register set 410 and a second register set 440, where the first register set 410 records the states of n management units, and the second register set 440 registers all intermediate data generated in the storage space management process, that is, the hardware management module has a design of multiplexing the second register set 440, which is helpful to reduce the number of register sets included in the hardware management module.

Optionally, the capacity of the second register set 440 is equal to the capacity of the first register set 410. Illustratively, the first register set 410 is 512 bits, and the second register set 440 is 512 bits. That is, the number of bits included in the second register group 440 is equal to the number of management units. Optionally, the capacity of the second register set 440 is greater than the capacity of the first register set 410.

In some embodiments, after the first retriever 430 determines the number of layers of the first management level, a management level corresponding to the first capacity is determined, and the state vector of the first management level is stored through the second register group 440.

Optionally, after determining the number of layers of the first management level, the second register set 440 obtains the state vector of the first management level through the first logic gate 420 or the first register set 410. Illustratively, if the first management level is not the underlying management level, the state vector of the first management level is derived from the output signals of the logic gates in the first logic gate 420; if the first management level is the bottom management level, then the state vector of the first management level is the data stored in the first register set 410.

The second retriever 450 is configured to determine a first element from the state vector of the first management hierarchy, and store index information of a first management unit corresponding to the first element into the second register group 440, where states of a first number of management units corresponding to the first element are all idle states, and the first management unit is one management unit of the first number of management units corresponding to the first element.

In some embodiments, the first element refers to an element having a target value in a state vector of the first management level, where the target value is used to represent that management units corresponding to the first element are all in an idle state. For example, a target value of "1", i.e., "1", indicates an idle state.

In some embodiments, the second retriever 450 is a 0/1 retriever for determining the first element from the state vector of the first management level, in search order. Optionally, the search order is related to a sequence number of an element in the state vector of the first management level. For example, the search order is from low to high by element number or from low to high by element number.

Illustratively, the first element refers to an element with the smallest element index information in the element with the value representing the idle state in the state vector of the first management level, and the element index information is used to represent the position of the element in the state vector. Illustratively, the first element refers to an element with the smallest element index information among elements of the state vector of the first management level whose values represent idle states.

In some embodiments, the first element corresponds to a first number of management units, the first number being a first number corresponding to a first management level. For example, if the first number corresponding to the first management level is 4, the first element corresponds to 4 management units with consecutive addresses in the storage space.

In some embodiments, the first management unit refers to any one of a first number of management units to which the first element corresponds, that is, in the case where the first element corresponds to a plurality of management units, the first management unit is any one of the plurality of management units.

Optionally, the first management unit refers to a management unit with the smallest corresponding address segment in the storage space among the first number of management units corresponding to the first element. For example, the first element corresponds to the management unit 2, the management unit 3, and the management unit 4, wherein the address field of the management unit 2 in the storage space is [2047, 3071], the address field of the management unit 3 in the storage space is [3072, 4095], and the address field of the management unit 4 in the storage space is [4096, 5119], and the management unit 2 is regarded as the minimum management unit.

Optionally, the index information of the first management unit is used to identify the first management unit. For example, the index information of the first management unit is used to characterize the serial numbers of the first management unit among the n management units. Illustratively, the index information of the first management unit pertains to a one-hot (one-hot) signal.

The signal conversion unit 460 is configured to convert the index information of the first management unit to a first base address in the storage space, and store the first base address into the second register group 440; wherein the first base address is used to indicate a location of the first capacity in the storage space.

In some embodiments, the first base address is used to indicate a location in the memory space of the first capacity allocated by the hardware management module. Optionally, the first base address is a lowest address (a minimum value) included in an address segment allocated in the storage space, and any storage unit corresponding to the allocated first capacity in the storage space can be accessed by offsetting the first base address. Illustratively, the first base address belongs to an index (index) signal, and the signal conversion unit 460 is configured to convert index information of the first management unit belonging to the one-hot signal into the first base address belonging to the index signal.

In summary, the technical scheme provided by the application is provided with the hardware management module for managing the storage space, so that the management of the storage space is realized from the hardware level. Under the condition that the storage space with the target capacity needs to be allocated, the hardware management module finds an address segment which is in an idle state and is matched with the target capacity from the storage space according to the target capacity, returns the address segment corresponding to the base address, and finishes the allocation process of the storage unit in the storage space from the base address.

On the other hand, in the process of allocating the storage space by the hardware management module, the hardware structures such as the register group in the hardware management module are multiplexed, so that the volume of the hardware management module is reduced while the storage space allocation is realized, the hardware cost of the hardware management module is reduced, and the influence on other functional modules arranged in a chip after the hardware management module is introduced is reduced.

In the following, the principle of implementing the hardware management module to dynamically allocate storage space is described in several embodiments.

After determining the first base address corresponding to the first capacity in the storage space, the hardware management module feeds back the first base address to the central processing unit as a processing result corresponding to the allocation instruction, and the central processing unit feeds back the first base address to the programmer through input and output equipment (such as a screen) to inform the programmer that an address segment of the first capacity which can be used is already in the storage space, and the address segment can be accessed based on the first base address.

Because the states of the management units at different moments are changed, after the allocation of the storage space is completed, the hardware management module needs to identify the allocated management units when receiving the subsequent instruction, so that the allocated management units are prevented from being allocated to other tasks again, and sustainable dynamic management of the storage space is realized.

Therefore, after the determination signal conversion unit determines the first base address, the hardware management module needs to convert the state of the management unit based on the first capacity allocation from the idle state to the occupied state, and the structure of the hardware management module for realizing the part of the functions is described below.

In some embodiments, the hardware management module further comprises: a mask calculation unit and a second logic gate circuit; the mask calculation unit is used for generating a first mask vector according to the first capacity and the first base address, and the first mask vector is used for indicating a management unit which needs to be adjusted to an occupied state in the n management units; the second logic gate circuit is used for adjusting states of a first number of management units corresponding to the first element in the first register group from an idle state to an occupied state according to the first mask vector.

In some embodiments, the mask calculation unit includes a shifter for generating an initial mask vector through a shift process according to the first capacity and the first base address, and shifting bits in the initial mask vector to generate a first mask vector.

In some embodiments, the first mask vector is used to adjust the state of at least one of the n management units stored in the first register set. Optionally, the first mask vector includes n elements, where n is a positive integer. Illustratively, the elements in the first mask vector are in one-to-one correspondence with the bits stored in the first register set.

Optionally, the process of generating the first mask vector is implemented by cooperation of a third register set in the hardware management module and the mask calculation unit; wherein, the shifter included in the mask calculation unit is used for changing the numerical value of the bit.

Since in the memory space the direction from right to left will generally be denoted the direction from lower to higher, the first base address is typically the smallest address in the allocated address field. Therefore, the shifter in the mask calculation unit is a left shift shifter, and of course, the shifter may be a right shift shifter, which is not limited herein.

Illustratively, in the process of generating the first mask vector, the n-bit initial mask vector, that is, the initial mask vector includes n elements, where the values of the respective elements included in the initial mask vector are not exactly equal, is registered in the third register set.

For example, n elements include s+1 elements of the first value, the remaining elements of the n elements are all equal to the second value, s represents the value of the first capacity in units of management units; wherein the first value is one of "0" or "1" and the second value is the other of "0" or "1" different from the first value. The first value is illustratively the same as the value used to characterize the management unit as being in the idle state.

Illustratively, the first values in the initial mask vector are consecutive, e.g., s+1 first values are located low in the initial mask vector. And in the generation process of the initial mask vector, the shifter in the mask calculation unit shifts s+1 bits positioned at the lower position in the third register group to obtain the initial mask vector. And then, the shifter shifts the s+1 first numerical values in the initial mask vector according to the first base address respectively to obtain a first mask vector, and the third register group stores the first mask vector.

The third register set in the hardware management module may be a second register set, or may be another register set different from the first register set and different from the second register set. After the first base address is determined and fed back to the central processing unit, the first base address stored in the second register set can be erased, so that the second register set is used as a third register set, multiplexing of the second register set is realized, the number of registers required to be set in the hardware management module is reduced, the size of the hardware management module is reduced, and the hardware management module is conveniently laid out in the existing chip structure.

In some embodiments, the second logic gate is a circuit acting on the first register set and the second register set. Optionally, the second logic gate circuit includes at least one logic gate therein. Optionally, the second logic gate circuit includes: a two-bit logic gate and a single-bit logic gate.

Optionally, the second logic gate circuit includes a two-bit logic gate and a single-bit logic gate. The single-bit logic gate is used for carrying out logic processing on the elements in the first mask vector to obtain the processed elements.

The two input signals of the two-bit logic gate are respectively: the processed element at the first position in the first mask vector (i.e., the processed element obtained after the single-bit logic gate processes the element at the first position in the first mask vector) and the bit value at the first position in the first register set, and the output signal of the double-bit logic gate is used as the bit value after the first position in the first register set is updated.

Illustratively, the single-bit logic gates in the second logic gate circuit are NOT gates for NOT-ing the elements in the first mask vector (e.g., converting "0" to "1" and "1" to "0"), and the double-bit logic gates are AND gates included in the second logic gate circuit.

The second logic gate circuit is used for adjusting the value of each bit according to whether the management unit corresponding to each bit in the first register group is allocated or not, so that the allocated management unit can be converted into the occupied state from the idle state in the state of representing the corresponding bit of the first register group.

Illustratively, the second logic gate logically operates on one bit at a corresponding position in the first register set and the third register set. For example, the q-th two-bit logic gate in the second logic gate circuit is configured to perform an and operation on the bit value of the q-th bit in the third register set after the q-th bit is subjected to the not gate processing and the q-th bit in the first register set, where the q-th two-bit logic gate logic processing obtains an output signal as a value of the q-th bit in the first register set, and q is a positive integer less than or equal to n.

In one example, using a "1" to indicate an idle state, a "0" to indicate an occupied state, a first value of "1", a second value of "0", and n equal to 3, the contents stored in the first register set prior to no allocation of memory space are: 1110 ("1110" from right to left indicates that the management units are in occupied state, the management units 1, 2 and 3 are in idle state), the first capacity is 2 management units, the first base address is 1, the third register set is implemented through the second register set, then in the process of generating the first mask vector, the initial mask vector is 0011, any first numerical value in the second register set is shifted to the left by 1 bit through the mask calculation unit, the obtained first mask vector is 0110, and the second logic gate circuit is used for carrying out logic processing on the first register set and the bit in the first mask vector to obtain 1000, namely, the data in the first register set is 1000, namely, the states of the management unit 1 and the management unit 2 are converted from idle state to occupied state.

In some embodiments, the second logic circuit has a single logic gate and a double logic gate, where the single logic gate performs logic processing on the elements in the first mask vector one by one to obtain processed elements, and the double logic gate performs logic processing on each bit in the first register set one by one and on the processed elements corresponding to each bit respectively to obtain updated values. This arrangement helps to reduce the hardware resource requirements of the second logic circuit.

In other embodiments, the second logic circuit has c single logic gates and c double logic gates, where c is a positive integer greater than 1, so that the second logic circuit can update the values of multiple bits in the first register at the same time, which is helpful for improving the speed of the hardware management module for managing the storage space.

By arranging the mask calculation unit and the second logic circuit, the allocated management unit is converted from the idle state to the occupied state, the dynamic update of the state of the management unit is realized, the possibility of repeated allocation of the allocated management unit by the hardware management module is facilitated, and the reliability of management of the storage space by the hardware management module is facilitated.

The following describes the structure of the hardware management module for realizing the function of releasing the memory space.

In some embodiments, the structure of the hardware management module for implementing the storage space allocation function and the structure for implementing the storage space release function overlap, and the processing logic for performing the storage space release process is simpler than the processing logic for performing the storage space allocation process. Optionally, the release instruction called by the programmer includes the second base address and the second capacity, so the hardware management module does not need to search to determine the second base address, and only needs to adjust the states of the management units of the second capacity starting from the second base address, and the states of the management units to be released are characterized as idle states from occupied states. In the subsequent storage space allocation process, the hardware management module is convenient to allocate the released management units to other tasks again.

In some embodiments, the mask calculation unit is further configured to generate a second mask vector according to a second capacity to be released and a second base address, where the second base address is used to mark that the second capacity needs to be released in the storage space; the management units needing to be adjusted to an idle state in the n management units of the second mask vector; the second logic gate is further configured to adjust a state of a management unit of a second capacity in the first register set from the second base address to an idle state from an occupied state according to the second mask vector.

In some embodiments, the second capacity to be released is in units of management units. Optionally, in the case that the unit of the second capacity is not the management unit, the hardware management module needs to convert the second capacity into the second capacity with the unit of the management unit, and uses the second capacity after the unit conversion to perform the storage space release process.

In some embodiments, the second base address is used to indicate a management unit that needs to be released from the storage space, and the second base address may be any address in an address segment corresponding to the second capacity to be released in the storage space. Optionally, the second base address refers to the lowest address in the address segment corresponding to the second capacity to be released in the storage space, and the lowest address refers to the address with the smallest value in the address segment corresponding to the address segment.

The second base address may also be other addresses in the address field to be released, not limited herein.

In some embodiments, the second mask vector is used to adjust the state of at least one of the n management units stored in the first register set. Optionally, the process of generating the second mask vector is implemented by cooperation of a shifter in the third register set and the mask calculation unit.

Illustratively, in generating the second mask vector, the n-bit initial mask vector, i.e., the initial mask vector, includes n elements therein, is registered in the third register set. Optionally, the values of the individual elements included in the initial mask vector are not all equal.

For example, the n elements include y elements having a second value, the values of the remaining elements of the n elements are the first values, and y represents the second capacity in units of management units; wherein the first value is one of "0" or "1", and the second value is the other of "0" or "1" different from the first value.

Illustratively, the second values in the initial mask vector are consecutive, e.g., y second values are located at lower positions in the initial mask vector, then the shifter shifts the consecutive y second values in the initial mask vector according to the second base address, and after the shifter operation is completed, the contents stored in the third register set are the second mask vector.

The second logic gate circuit performs bit logic processing on the bits stored in the first register set and the bits in the second mask vector stored in the third register set, and updates the state of the management unit released in the first register set using the result of the logic processing.

For a specific description of the mask calculation unit and the second logic gate, please refer to the related embodiments related to memory allocation, and the detailed description is omitted herein.

The mask computing unit and the second logic gate circuit realize the distribution of the storage space and the release of the storage space, realize the hardware of the management of the storage space and help the programmer to manage the storage space.

The logic of the first logic gate for hierarchical management of the management unit is described in the following by several embodiments.

In some embodiments, the first logic gate circuit includes at least one logic gate layer including logic gates for logically operating on states characterized by elements in the state vector; for a first logic gate in a first logic gate layer of the at least one logic gate layer, the first logic gate is configured to perform logic operation on elements at a first position and a second position of a state vector in a second management level, so as to obtain an element at the first position in a state vector in a third management level; wherein the second management level is adjacent to the third management level, the number of levels of the second management level is lower than the number of levels of the third management level, and the total number of elements spanned between the second location and the first location is related to the first number corresponding to the second management level.

In some embodiments, the second management level is adjacent to the third management level. Optionally, the number of levels of the second management level is lower than the number of levels of the third management level, for example, the number of levels of the second management level is equal to 1, and the number of levels is lower than the number of levels of the third management level by 2. For another example, the number of levels of the second management level is equal to 6 and the number of levels below the third management level is 7.

Optionally, the total number of elements spanned between the second location and the first location has a positive correlation with the first number corresponding to the second management level, that is, the greater the first number corresponding to the second management level, the greater the total number of elements spanned between the second location and the first location; the smaller the corresponding first number of second management levels, the fewer the total number of elements that span between the second location and the first location.

Optionally, the value of the first position is smaller than the value of the second position, i.e. the first position is located at a lower position relative to the second position. For example, if the first value corresponding to a certain second management level is equal to 4, when the first position corresponds to the element "3" in the state vector of the second management level, the second position corresponds to the element "7" in the state vector of the second management level.

Illustratively, a total number of elements spanned between a first location and a second location in the state vector of the first management level is equal to a first number corresponding to the first management level.

In some embodiments, logic gates in the same logic gate layer are used to process different elements in a state vector of the same management level. For example, for the p-th logic gate layer, the logic gate layer is configured to perform logic processing on an element in the state vector of the p-th management level to obtain the state vector of the p+1th management level, where p is a positive integer.

For ease of understanding, the principle of determining the corresponding state vector by the logic gate layer is described with reference to fig. 7.

In FIG. 7, a first number of state vectors (Free [0] [0:511 ]) corresponding to management level 0 is equal to 1, and state vectors (Free [0 ]) of management level 0 are stored in a first register set, and each logic gate in a logic gate layer a in the first logic gate circuit is used for performing a logic gate operation on states of two adjacent elements in the state vector of management level 0, for example, a logic gate a1 is used for performing an AND operation on an element "7" and an element "6" in the state vector of management level 0, so as to obtain a value of an element "6" in the state vector (Free [1] [0:511 ]); the logic gate a2 is used for performing AND operation on the element '6' and the element '5' in the state vector (Free [0] [0:511 ]) of the management level 0 to obtain the value of the element '5' in the state vector (Free [1] [0:511 ]) of the management level 1; the logic gate a3 is configured to perform an and operation on the element "5" and the element "4" in the state vector (Free [0] [0:511 ]) of the management level 0, to obtain the value of the element "4" in the state vector (Free [1] [0:511 ]) of the management level 1; the logic gate a4 is used for performing AND operation on the element '4' and the element '3' in the state vector (Free [0] [0:511 ]) of the management level 0 to obtain the value of the element '3' in the state vector (Free [1] [0:511 ]) of the management level 1.

The first number corresponding to management level 1 is equal to 2. Alternatively, the state vector (Free [1] [0:511 ]) of management level 1 is represented by the output signals of the individual logic gates in logic gate layer a (the output signals comprise 0 or 1). Each logic gate in logic gate layer b in the first logic gate circuit is configured to perform a logic gate operation on states of two elements of span 2 in the state vector of management level 1. If the logic gate b1 is used for performing AND operation on the element "7" and the element "5" in the state vector (Free [1] [0:511 ]) of the management level 1, to obtain the value of the element "5" in the state vector (Free [2] [0:511 ]) of the management level 2; the logic gate b2 is used for performing AND operation on the element '6' and the element '4' in the state vector (Free [1] [0:511 ]) of the management level 1 to obtain the value of the element '4' in the state vector (Free [2] [0:511 ]) of the management level 2; the logic gate b3 ANDs element "5" and element "3" in the state vector (Free [1] [0:511 ]) of management level 1, resulting in the value of element "3" in the state vector (Free [2] [0:511 ]) of management level 2.

The first number corresponding to management level 2 is equal to 4, and the state vector (Free 2 0:511) of management level 2 is represented by the output signals of the individual logic gates in logic gate layer c (the output signals comprise 0 or 1). Each logic gate in logic gate layer c in the first logic gate circuit is configured to perform a logic gate operation on the states of two elements of the management level 2 state vector that span 4. For example, the logic gate c1 is used to AND the element 7 and the element 3 in the state vector (Free [2] [0:511 ]) of the management level 2, so as to obtain the state of the element 3 in the state vector (Free [3] [0:511 ]) of the management level 3.

The relationship between the number of management units corresponding to the element and the first number may be further explained in connection with the present example.

For element "4" in the management level 2 state vector (Free [2] [0:511 ]), element "4" in the management level 2 state vector (Free [2] [0:511 ]) is in the idle state only if both element "6" and element "4" in the management level 1 are in the idle state. For element "6" in the management level 1 state vector (Free [1] [0:511 ]), element "6" in the management level 1 state vector (Free [1] [0:511 ]) represents the idle state only when element "7" and element "6" in the management level 0 are in the idle state. For element "4" in the management level 1 state vector (Free [1] [0:511 ]), element "5" and element "4" in the management level 0 state vector (Free [0] [0:511 ]) are idle states, and element "4" in the management level 1 state vector (Free [1] [0:511 ]) is indicative of an idle state.

Since the elements 4, 5, 6, 7 in the state vector (Free [0] [0:511 ]) of the management level 0 correspond to the management unit 4, the management unit 5, the management unit 6, and the management unit 7, respectively, that is, the element 4 in the state vector of the management level 2 corresponds to the management unit 4, the management unit 5, the management unit 6, and the management unit 7; then element 4 in the state vector of management level 2 is in the idle state only if management unit 4, management unit 5, management unit 6 and management unit 7 are in the idle state.

By the two paragraphs, it is not difficult to find that the span between the input signals of the logic gates in the corresponding logic gate layer of the first logic gate circuit is set according to the corresponding first number of the management layers, so that the effect that the elements in the state vector of the management layers represent the idle states of the management units of the first number can be achieved.

In the explanation with respect to fig. 7, the default "1" indicates an idle state, and "0" indicates an occupied state, and thus, the logic gates in the respective logic gate layers of the first logic gate circuit are and gates. In practice, a "0" may be used to indicate an idle state, and a "1" may be used to indicate an occupied state, where the logic gates in each logic gate layer of the first logic gate circuit are all or gates, and the connection relationship between the logic gates in each logic gate layer in the first logic gate layer does not need to be changed.

Through the hierarchical arrangement mode, the output signals corresponding to the logic gate levels of the first logic gate circuit can represent whether the first number of management units are in an idle state or not, statistics on states of a plurality of management units is facilitated, and time consumption for searching for continuous management units adapting to the first capacity is shortened.

In some embodiments, the first logic gate circuit includes the same type of logic gate, and the type of logic gate is any one of the following: and gate, or gate.

Optionally, in the case where "0" indicates that the management unit is in an occupied state and "1" indicates that the management unit is in an idle state, the logic gate in the first logic gate circuit is an and gate; optionally, in the case where "1" indicates that the management unit is in the occupied state and "0" indicates that the management unit is in the idle state, the logic gate in the first logic gate circuit is an or gate.

Fig. 8 is a schematic diagram of a first logic gate type provided by an exemplary embodiment of the present application. The logic gates included in the first logic gate circuit are and gates as shown at 810 in fig. 8.

Fig. 9 is a schematic diagram of a first logic gate type provided by another exemplary embodiment of the present application. The logic gates included in the first logic gate circuit are or gates as shown at 910 in fig. 9.

By providing different logic gates for different occupancy states, a rich implementation of the first logic gate is provided.

The principle of the first retriever will be described by several embodiments.

In some embodiments, the first retriever is a leading retriever, the leading retriever being operable to determine a first value based on the first capacity and the corresponding storage capacity of the management unit, the first value being the most significant bit of the binary representation of the first capacity. For details on the first retriever, please refer to the above embodiments.

The most significant digit of a significant value refers to the non-0 digit that is most significant in the binary representation of the first capacity. For example, the binary representation of the first capacity is 00001011, then the first retriever determines that the most significant bit of the significant value is the 4 th bit from right to left.

In one example, in combination with the first number setting manner with 2 as a base number and the management levels as an index, when the first logic circuit makes the first number increment manner corresponding to each management level respectively satisfy the above-mentioned index form, the leading retriever is used to determine the number of layers of the first management level according to the highest bit of the effective value in the binary representation of the first capacity, so that the determined first number corresponding to the first management level is adapted to the first capacity.

That is, the number of management units corresponding to the first element determined from the state vector of the first management level is greater than or equal to the first capacity, and for the case that the number of management units corresponding to the first element is greater than the first capacity, the number of management units corresponding to the first element does not exceed 2 times of the first capacity, so that the utilization rate of the allocated management units is improved, the space occupation and waste of the management units are reduced, and the utilization efficiency of the management units is improved.

Compared with setting one element corresponding to one management unit, if k management spaces are required to be allocated, k is a positive integer greater than 1, a circuit is required to realize the function of searching for continuous k management units representing idle states from states of n management units, the function relates to multiple circulation and judgment, complex circuit structure realization is required to be realized, and the volume of a hardware management module is not beneficial to control. The hardware management module provided by the application manages n management units by using a hierarchical structure, only one leading 1 retriever is needed to determine that the most significant bit of the first capacity k finds the corresponding first management hierarchy, and in the subsequent process of determining k continuous management units, only 1 first element representing an idle state is needed to be determined from the state vector of the first management hierarchy (the process can be realized by only one retriever (a second retriever)), so that the management unit which is continuous in at least one address and in the idle state and corresponds to the first element can be directly found, the allocation logic of the storage space is clearer and simpler, and the hardware implementation is convenient.

In some embodiments, the second retriever is a post-amble (level) retriever operable to search, from the state vector of the first management level, for a first element representing the idle state as the first element in a low-to-high order.

In some embodiments, the first element 1 characterizing the idle state refers to: the element in the state vector of the first management level has the smallest element index number (i.e., lowest order) and is used to characterize the element in the idle state.

Illustratively, in the case where "1" indicates an idle state, the second retriever is a trailing 1 (level_one) retriever for searching the state vector of the first management level for the lowest element that characterizes the idle state, i.e. the lowest position in the state vector having a value of 1. For example, the state vector corresponding to the first management level is 0011010, and each bit from right to left in "0011010" respectively indicates: element 0 is in the occupied state, element 1 is in the idle state, element 2 is in the occupied state, element 3 is in the idle state, element 4 is in the idle state, element 5 is in the occupied state, and element 6 is in the occupied state; in the case where the second retriever is the leading retriever 1, the first element is element 1.

Illustratively, in the case where "0" represents an idle state, the second retriever is a trailing 0 (zero) retriever for searching the state vector of the first management level for the lowest element that characterizes the idle state, i.e. the lowest position in the state vector with a value of 0. For example, the state vector corresponding to the first management level is 0011010, and each element from right to left in "0011010" respectively represents: element 0 is in an idle state, element 1 is in an occupied state, element 2 is in an idle state, element 3 is in an occupied state, element 4 is in an occupied state, element 5 is in an idle state, and element 6 is in an idle state; in the case where the second retriever is the leading retriever 0, the first element is element 0.

Alternatively, the second retriever may be a leading retriever.

Illustratively, in the case where "1" represents an idle state, the second retriever is a preamble 1 retriever for searching for a most significant element representing the idle state from the state vector of the first management level, and taking the element as the first element. For example, the state vector corresponding to the first management level is 0011010, and each element from right to left in "0011010" respectively represents: element 0 is in the occupied state, element 1 is in the idle state, element 2 is in the occupied state, element 3 is in the idle state, element 4 is in the idle state, element 5 is in the occupied state, and element 6 is in the occupied state; if the second retriever is the leading retriever 1, the second retriever determines the first element from the state vector corresponding to the first management hierarchy to be the element 4.

Illustratively, in the case where "0" represents an idle state, the second retriever is a leading 0 retriever. The second retriever is operable to search for a most significant element from the state vector of the first management level, the most significant element representing the idle state, and to take the element as the first element.

For example, the state vector corresponding to the first management level is 0011010, and each element from right to left in "0011010" respectively represents: element 0 is in an idle state, element 1 is in an occupied state, element 2 is in an idle state, element 3 is in an occupied state, element 4 is in an occupied state, element 5 is in an idle state, and element 6 is in an idle state; if the second retriever is the leading retriever 0, the second retriever determines the first element from the state vector corresponding to the first management hierarchy to be the element 6.

It should be noted that, in the embodiments of the present application, the state vector is a 01 string, and the state vector may also be referred to as a state string; the character string indicates the order of the lower bits to the upper bits from right to left according to the management habit (binary carry habit) of the memory space. The type of the second retriever is set according to actual needs, and the application is defined herein.

In some embodiments, for a lowest management level of the at least one management level, a state vector of the lowest management level is used to characterize the states of the n management units stored by the first register set.

The lowest management level is the bottom management level of at least one management level, and details of this embodiment are described above, and are not repeated here.

In some embodiments, the hardware management module includes a finite state machine and a control rate accelerator (Control Law Accelerator, CAL) including a first register set, a first logic gate, a first retriever, a second register set, a second retriever, and a signal conversion unit; the finite state machine (Finite State Machine, FSM) is used for controlling the control rate accelerator to allocate the storage space with the first capacity from the storage space when the allocation instruction from the central processing unit is received, and feeding back the execution result of the allocation instruction to the central processing unit through the bus of the central processing unit.

Optionally, the finite state machine is further configured to control the control rate accelerator to release the second capacity of storage space from the storage space when receiving the release instruction from the central processing unit, and feedback the execution result of the release instruction to the central processing unit through the bus of the central processing unit.

A finite state machine is understood to describe the sequence of states an object experiences during its lifecycle, and in response to various instructions from the outside world, where an object refers in the present application to a process in which a hardware management module manages storage space.

The control rate accelerator is used for storing the state of the management unit and realizing the management or release of the storage space. Optionally, the control rate accelerator includes a register resource and a computing resource, and details of the control rate accelerator are described in the above embodiments, which are not repeated herein.

Optionally, the control rate accelerator includes: the mask register comprises a first register group, a first logic gate circuit, a first retriever, a second register group, a second retriever, a signal conversion unit, a mask calculation unit, a second logic circuit and the like.

Fig. 10 is a schematic diagram showing the composition of a hardware management module according to an exemplary embodiment of the present application. Finite state machine 1020 is used to control rate accelerator 1010, and the state of finite state machine 1020 is used to characterize the progress of operation of the various components in control rate accelerator 1010.

In some embodiments, control connections exist between the finite state machine and each component in the control rate accelerator, and the finite state machine controls the first register set, the first logic gate circuit, the first retriever, the second register set, the second retriever, the signal conversion unit and other components in the control rate accelerator, so that the control rate accelerator can complete management of the storage space.

Illustratively, the finite state machine sends an indication to a component in the control rate accelerator that begins executing the corresponding step upon receipt of the indication; after the function execution of the component is completed, the component transmits an indication completion signal to the finite state machine; after the finite state machine receives the indication completion signal, the state of the finite state machine is adjusted, and other components in the control rate accelerator are instructed to execute corresponding functions until the storage space allocation or the storage space release is completed.

In some embodiments, the finite state machine performs state transitions according to the execution of the various components in the control rate accelerator. The state flow can be understood as that the state of the finite state machine is changed, and in the case that the storage space management process is not finished, the state flow further includes the step that the finite state machine instructs other components in the control rate accelerator to execute the storage space management process.

Optionally, the state of the finite state machine comprises at least one of: IDLE state (IDLE), legal CHECK state (check_size), layer number calculation state (cal_idx), element determination state (cal_base_1hot), signal transition state (trans_base), MASK processing state (free_mask), and result feedback state (wait_done).

Optionally, the idle state is used for indicating that the hardware management module is in a standby state, and can accept a next allocation instruction or release instruction.

Optionally, the legitimacy check state is used to indicate that a legitimacy check is being performed on the first capacity or the second capacity. If the first capacity or the second capacity is illegal (for example, the first capacity (or the second capacity) exceeds the capacity upper limit of the storage space, the first capacity (or the second capacity) is negative, etc.), the hardware management module ends executing the instruction; if the first capacity or the second capacity is determined to be legal, the allocation instruction or the release instruction is normally executed.

Optionally, the tier number calculation state is used to instruct a first retriever in the control rate accelerator to calculate a tier number of the first management tier according to the first capacity.

Optionally, the signal conversion state is used to instruct a signal conversion unit in the control rate accelerator to determine the first base address based on index information of the first management unit.

Optionally, the mask processing state is used to instruct a mask calculation unit in the control rate accelerator to calculate the first mask vector or the second mask vector.

Optionally, the result feedback status is used to indicate that the processing result is being fed back to the central processor, and update the status of the management unit in the first register set.

Fig. 11 is a state flow diagram of a finite state according to an exemplary embodiment of the present application.

After the hardware management module executes the last control instruction, the finite state machine is in a standby state and waits for receiving the next control instruction, and the types of the control instructions comprise: allocation instructions and release instructions.

After receiving a control instruction, the finite state machine is converted into a legal check state from a standby state. If the capacity in the control instruction (the first capacity in the allocation instruction or the second capacity in the release instruction) does not pass the validity check, the finite state machine transitions from the validity check state to the result feedback state. At this time, the hardware management module feeds back a processing result to the central processing unit through the central processing unit bus, and the processing result is used for representing that the storage space management failure occurs.

If the second capacity in the release instruction passes the validity check, the finite state machine is converted from the validity check state to a signal conversion state, and the control signal conversion unit determines a second base address. After the signal conversion unit is completed, the finite state machine is converted from the signal conversion state to the mask processing state. After the mask calculation unit generates the second mask vector, the finite state machine transitions from the mask processing state to the result feedback state.

If the first capacity in the allocation instruction passes the validity check, the finite state machine is converted from the validity check state to the layer number calculation state, and the first management level is determined through the first retriever. After the first retriever determines the first management level, the finite state machine transitions from the layer number calculation state to the element calculation state. Then, a second register group in the control rate accelerator acquires a state vector of the first management level from the first register group or the first logic gate circuit, a first element is determined from the state vector of the first management level through the second retriever, and after element index information of the first element is stored in the second register group, the finite state machine is converted from an element determination state to a signal conversion state. The signal conversion unit determines the first base address by signal conversion.

Thereafter, the finite state machine transitions from the signal transition state to the mask processing state. The mask calculation unit generates a first mask vector based on the first capacity and the first base address. The finite state machine is converted from a mask processing state to a result feedback state, the control rate accelerator carries out logic processing on bits in the first register group according to the first mask vector through the second logic gate circuit, and the hardware management module feeds back a first base address to the central processing unit through the central processing unit bus.

Fig. 12 is a circuit diagram of a hardware management module according to an exemplary embodiment of the present application.

As shown in fig. 12, the Hardware Management Module (HMM) includes a Finite State Machine (FSM) and a control rate accelerator (CAL), and the Finite State Machine (FSM) controls the control rate accelerator (CAL). In the corresponding Hardware Management Module (HMM) design of fig. 12, "1" is used to indicate an idle state and "0" is used to indicate an occupied state. The control rate accelerator (CAL) includes: the device comprises a first register group, a first logic gate circuit (a circuit which acts on data stored in the first register group and comprises at least one AND gate), a first retriever (free_tmp_r), a second register group (free_tmp_r), a second retriever (free_one), a signal conversion unit (onehot 2 bin) and a mask calculation unit (mask_cal).

Wherein a state matrix (free matrix) of state vectors of at least one management level is maintained by the first register set and the second logic gate.

The first retriever (scaling_one) is configured to determine a number of levels (idx) of the first management level according to the first capacity (size).

The second register set (free tmp r) is used for hosting intermediate data generated in the memory space management process.

The second retriever (level_one) is configured to search a lowest order representing an idle state in the state vector of the first management level from a lower order to a higher order so as to take an element of the lowest order in the state vector of the first management level as a first element.

The signal conversion unit (onehot 2 bin) is used for determining the first base address in the memory space allocation process.

The mask calculation unit (mask cal) is used to change the state of the allocated management unit or the released management unit in the first register set.

For details of the above components, reference is made to the above description, and details are not repeated here. By arranging the hardware management module, the management of the storage space is realized on the hardware level, and the pressure of a programmer on managing the storage space is reduced.

The following is an embodiment of the method, and for details not disclosed in the embodiment of the method, please refer to an embodiment of the hardware management module of the storage space of the present application.

FIG. 13 is a flowchart of a method for providing a memory space based on a hardware management module according to an exemplary embodiment of the present application. The method may be performed by a hardware management module as shown in fig. 4, for example. The hardware management module includes: the first register group, the first logic gate circuit, the first retriever, the second register group, the second retriever and the signal conversion unit; the storage space comprises n management units, the first register group is used for storing states of the n management units, and n is a positive integer; the method may include (1310-1340).

In step 1310, the first logic gate circuit calculates, according to the states of the n management units, a state vector of at least one management level, where each element in the state vector is used to characterize the states of a corresponding first number of management units, and different management levels correspond to different first numbers.

In some embodiments, in the event of a change in the stored data in the first register set, the first logic gate computes the state vector for at least one management level in a short time based on the bit values stored in the first register set on-the-fly. That is, the first logic gate is able to complete the process of updating the state vector of at least one management level within a short period of time after the data change in the first register set.

For example, at a first moment, the hardware management device receives the allocation instruction a, after completing the first capacity a requested by the allocation instruction a, the first register set adjusts the states of the allocated management units, and the first logic gate circuit calculates a state vector of at least one management level according to the states of n management units stored in the first register set. At the second moment, when the hardware management device receives the allocation instruction B, the hardware management module may directly determine the management unit allocated to the allocation instruction B according to the state vector calculated in the previous step.

Step 1320, the first retriever determines a first management level from the at least one management level according to the first capacity to be allocated, and stores a state vector of the first management level into the second register group; wherein a first number corresponding to the first management level is adapted to the first capacity.

In some embodiments, the first capacity is indicated by an allocation instruction. Optionally, the first retriever determines the most significant bit in the binary representation of the first capacity and uses the most significant bit as a hierarchical level of the first management hierarchy to determine the first management hierarchy.

Optionally, the first number corresponding to the first management level and the first capacity adaptation refer to: the first quantity corresponding to the first management level is larger than or equal to the first capacity, and the gap between the first quantity corresponding to the first management level and the first capacity is smaller than the gap between the first quantity corresponding to other management levels and the first capacity. For example, the first capacity has a value of 5, and the first number corresponding to the first management level is equal to 8.

Optionally, the first number corresponding to the first management level and the first capacity adaptation refer to: the first quantity corresponding to the first management level is smaller than or equal to the first capacity, and the gap between the first quantity corresponding to the first management level and the first capacity is smaller than the gap between the first quantity corresponding to other management levels and the first capacity. For example, the first capacity has a value of 5, and the first number corresponding to the first management level is equal to 4.

In some embodiments, after determining the number of levels of the first management level, the second register set reads the state vector of the first management level from the first register set or the first logic gate. For details of this portion, please refer to the above embodiments, and detailed description thereof is omitted.

In step 1330, the second retriever determines the first element from the state vector of the first management hierarchy, and stores index information of a first management unit corresponding to the first element into the second register group, where the states of the first number of management units corresponding to the first element are all idle states, and the first management unit is any one of the first number of management units corresponding to the first element. If the first management unit is the management unit with the smallest serial number of the corresponding address segment in the first number of management units corresponding to the first element.

In some embodiments, the second retriever is to find a first element in the state vector of the first management level that represents an idle state from a high order to a low order, or the second retriever is to find a first element in the state vector of the first management level that represents an idle state from a low order to a high order.

Optionally, the values of the elements in the state vector of the first management level include: a value representing an idle state and a value representing an occupied state; if the value of an element of the state vector of the first management level is a value representing an idle state, the first number of management units corresponding to the element are all in the idle state; if the value of an element of the state vector of the first management level is a value representing the occupied state, it is indicated that at least one occupied management unit exists in the first number of management units corresponding to the element, and the occupied management unit means that the management unit is in the occupied state, that is, the management unit is allocated to other tasks for use and is not released.

Illustratively, "1" indicates an idle state and "0" indicates an occupied state, at which time the second retriever may be a trailing 1 retriever for searching the state vector of the first management level for the element whose first value indicates an idle state from a low order to a high order. For a specific description of this embodiment, please refer to the above embodiment, and a detailed description is omitted here.

Step 1340, the signal conversion unit converts the index information of the first management unit to a first base address in the storage space, and stores the first base address into the second register set; wherein the first base address is used to indicate a location of the first capacity in the storage space.

In summary, the storage space is allocated through the hardware management module, so that when a programmer needs to consider that the usable storage space is allocated for in, the hardware management module only needs to provide the capacity to be allocated, the allocation of the storage space can be automatically performed according to the capacity to be allocated, the programmer does not need to provide the base address of the storage space to be allocated, and the efficiency of managing the storage space by the programmer is improved.

Fig. 14 is a flowchart providing allocation of memory in accordance with another exemplary embodiment of the present application.

For the steps 1310-1340, please refer to the above embodiments, and the description thereof is omitted.

The hardware management module further comprises: a mask calculation unit and a second logic gate circuit; the method further comprises the steps of: in step 1350, the mask calculation unit generates a first mask vector according to the first capacity and the first base address, where the first mask vector is used to indicate a management unit that needs to be adjusted to an occupied state from the n management units.

In step 1360, the second logic gate adjusts the states of the first number of management units corresponding to the first element in the first register set from the idle state to the occupied state according to the first mask vector.

It should be noted that, in the case of receiving an allocation instruction, the execution sequence of step 1310 does not necessarily occur before step 1320, and step 1310 may occur after step 1360. That is, after the data stored in the first register set is changed, the first logic gate recalculates the state vector of the at least one management level based on the data newly stored in the first register set.

For a specific description of this embodiment, please refer to the above embodiment, and a detailed description is omitted here.

Fig. 15 is a schematic diagram of allocating memory in accordance with an exemplary embodiment of the present application.

The hardware management module receives a control instruction, wherein the control instruction is an allocation instruction comprising a first capacity to be allocated. If the unit of the first capacity is not the management unit, the hardware simulation module first needs to perform unit conversion on the first capacity, and assuming that the capacity of the management unit is 1024 bits, the unit of the first capacity is 1024 bits, and the first capacity is decimal, the unit-converted first capacity=The method comprises the steps of carrying out a first treatment on the surface of the Where size represents the first capacity in decimal, ceil () represents the round-up function.

Optionally, the step is implemented by a binary conversion unit in the hardware management module, where the binary conversion unit includes a shifter for completing the step of converting the unit of the first capacity into the management unit; wherein the binary converter is used for convertingConversion to binary tablesThe manner of illustration.

It should be noted that the storage space management process is performed based on the first capacity after the unit conversion, that is, the first retriever determines, from the first capacity, that "the first capacity" mentioned in the first management hierarchy refers to the first capacity after the unit conversion.

After the above steps are completed, the hardware management module starts the allocation process of the storage space, and the process mainly includes the following steps (1) to (6).

And (1) determining the layer number of the first management level by the first retriever according to the first capacity. Optionally, the first retriever is a loading_one module, configured to find an index (idx) of a most significant bit of 1 in the first capacity, that is, a layer number of the first management level. The loading_one is a standard universal module.

And (2) selecting a state vector of the first management level from the first register group or the first logic gate circuit according to the level number of the first management level by the second register group for storage.

And (3) determining the first element from the state vector of the first management level by the second retriever, and registering index information of the first management unit in the second register group.

Optionally, in this embodiment, a "1" is used to indicate an idle state, a "0" is used to indicate an occupied state, and the second retriever is a class_one module, configured to find a lowest bit of "1" from a state vector of the first management level registered in the second register set, so as to obtain index information of the first management unit. Optionally, the index information of the first management unit is a one hot signal, and the least_one is also a standard universal module.

And (4) converting the index information of the first management unit into a first base address by the signal conversion unit. The operation converts the one hot signal into an index signal, namely, the index of which 1bit is determined to be base_addr; base_addr is the first base address.

And (5) generating a first mask vector by the mask calculation unit according to the first capacity and the first base address.

Optionally, the generating process of the first mask vector is as follows: firstly, generating an initial mask vector mask, wherein the initial mask vector mask=512'd 1< < size, "< <" represents a left shift operation, the initial mask vector mask comprises a first capacity of ' 1 ' and continuously distributed low bits, and the numerical values of other positions are ' 0 '; a first mask vector is then generated from the initial mask vector, the first mask vector entry_mask=mask < < base_addr. The second register set registers the first mask vector.

And (6) the second logic gate circuit adjusts the states of the management units of the first quantity corresponding to the first element in the first register group according to the first mask vector. For details of this step, please refer to the above embodiments.

In this way, a plurality of consecutive management units in an idle state, which meet the first capacity requirement, can be quickly searched from the n management units, which helps to improve the efficiency of allocating storage space.

FIG. 16 is a flowchart providing a release of memory in accordance with an exemplary embodiment of the present application.

In some embodiments, the method further comprises: in step 1610, the mask calculation unit generates a second mask vector according to the second capacity to be released and a second base address, where the second base address is used to mark that the second capacity needs to be released in the storage space.

Step 1620, a management unit which needs to be adjusted to an idle state in the n management units of the second mask vector; the second logic gate adjusts the state of the management unit of the second capacity from the second base address in the first register set from the occupied state to the idle state according to the second mask vector.

In some embodiments, the first logic gate circuit includes at least one logic gate layer including logic gates for logically operating on states characterized by elements in the state vector; the first logic gate circuit calculates a state vector of at least one management level according to states of the n management units, and the first logic gate circuit comprises: for a first logic gate in a first logic gate layer of the at least one logic gate layer, the first logic gate logically operates on the first position and the second position of the state vector in the second management layer to obtain the first position element in the state vector in the third management layer; wherein the second management level is adjacent to the third management level, the number of levels of the second management level is lower than the number of levels of the third management level, and the total number of elements spanned between the second location and the first location is related to the first number corresponding to the second management level.

In some embodiments, the hardware management module includes a finite state machine and a control rate accelerator, the control rate accelerator including a first register set, a first logic gate, a first retriever, a second register set, a second retriever, and a signal conversion unit; and the finite state machine controls the control rate accelerator to allocate the storage space with the first capacity from the storage space under the condition of receiving an allocation instruction from the central processing unit, and feeds back the execution result of the allocation instruction to the central processing unit through a bus of the central processing unit.

It should be noted that, the method provided in the above embodiment and the embodiment of the hardware management module of the storage space belong to the same concept, and the specific implementation process of the method is detailed in the embodiment of the hardware management module of the storage space, which is not described herein. The beneficial effects of the above method embodiment refer to the description of the hardware management module embodiment of the storage space, and are not repeated here.

The embodiment of the application also provides a chip, which comprises a memory and a hardware management module of the memory space.

The embodiment of the application also provides electronic equipment, which comprises the hardware management module of the storage space. Optionally, the electronic device includes a chip including a memory and a hardware management module. The hardware management module is used for managing the storage space of the memory by adopting the scheme provided by the embodiment.

It should be understood that references herein to "a plurality" are to two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and principles of the application are intended to be included within the scope of the application.

Claims

1. A hardware management module for a storage space, the hardware management module comprising: the first register group, the first logic gate circuit, the first retriever, the second register group, the second retriever and the signal conversion unit; the storage space comprises n management units, the first register group is used for storing states of the n management units, and n is a positive integer;

2. The hardware management module of claim 1, wherein the hardware management module further comprises: a mask calculation unit and a second logic gate circuit;

The mask calculation unit is used for generating a first mask vector according to the first capacity and the first base address, and the first mask vector is used for indicating a management unit which needs to be adjusted to an occupied state in the n management units;

the second logic gate circuit is configured to adjust states of a first number of management units corresponding to the first element in the first register set from an idle state to an occupied state according to the first mask vector.

3. The hardware management module of claim 2, wherein,

the mask calculation unit is further used for generating a second mask vector according to a second capacity to be released and a second base address, and the second base address is used for marking that the second capacity needs to be released in the storage space; the second mask vector is used for adjusting the management units to be in an idle state in the n management units;

the second logic gate is further configured to adjust a state of a management unit of the second capacity in the first register set from the second base address to an idle state from an occupied state according to the second mask vector.

4. The hardware management module of claim 1, wherein the first logic gate circuit comprises at least one logic gate layer including logic gates for logically operating on states characterized by elements in the state vector;

For a first logic gate in a first logic gate layer of the at least one logic gate layer, the first logic gate is configured to perform logic operation on elements at a first position and a second position of a state vector in a second management level, so as to obtain an element at the first position in a state vector in a third management level;

wherein the second management level is adjacent to the third management level, the number of levels of the second management level is lower than the number of levels of the third management level, and the total number of elements spanned between the second location and the first location is related to a first number corresponding to the second management level.

5. The hardware management module of claim 4, wherein each of the logic gates included in the first logic gate circuit is of a same type, and the type of logic gate is any one of: and an AND gate or an OR gate.

6. The hardware management module according to claim 1, wherein the first retriever is a preamble retriever, the preamble retriever being configured to determine a first value according to the first capacity and a storage capacity corresponding to the management unit, the first value being a highest bit of a significant value in a binary representation of the first capacity.

7. The hardware management module of claim 1, wherein the second retriever is a post-amble retriever to search for a first element characterizing an idle state as the first element from a state vector of the first management level in order from low to high.

8. The hardware management module of claim 1, wherein for a lowest management level of the at least one management level, a state vector of the lowest management level is used to characterize the states of the n management units stored by the first register set.

9. The hardware management module of claim 1, wherein the hardware management module comprises a finite state machine and a control rate accelerator, the control rate accelerator comprising the first register set, the first logic gate, the first retriever, the second register set, the second retriever, and the signal conversion unit;

the finite state machine is used for controlling the control rate accelerator to allocate the storage space with the first capacity from the storage space under the condition of receiving an allocation instruction from the central processing unit, and feeding back an execution result of the allocation instruction to the central processing unit through a bus of the central processing unit.

10. The hardware management module of claim 9, wherein the finite state machine performs state flow according to execution conditions of each element in the control rate accelerator;

the state of the finite state machine includes at least one of: idle state, legal checking state, layer number calculation state, element determination state, signal conversion state, mask processing state and result feedback state.

11. A chip comprising a memory and a hardware management module for the memory space according to any one of claims 1 to 10.

12. An electronic device comprising a hardware management module of a storage space according to any of claims 1 to 10.

13. The utility model provides a memory space management method based on hardware management module, its characterized in that, hardware management module includes: the first register group, the first logic gate circuit, the first retriever, the second register group, the second retriever and the signal conversion unit; the storage space comprises n management units, the first register group is used for storing states of the n management units, and n is a positive integer; the method comprises the following steps:

The first logic gate circuit calculates a state vector of at least one management level according to the states of the n management units, wherein each element in the state vector is used for representing the states of the corresponding first number of management units, and different management levels correspond to different first numbers;

14. The method of claim 13, wherein the hardware management module further comprises: a mask calculation unit and a second logic gate circuit; the method further comprises the steps of:

the mask calculation unit generates a first mask vector according to the first capacity and the first base address, wherein the first mask vector is used for indicating a management unit which needs to be adjusted to an occupied state in the n management units;

the second logic gate circuit adjusts states of a first number of management units corresponding to the first element in the first register set from an idle state to an occupied state according to the first mask vector.

15. The method of claim 14, wherein the method further comprises:

the mask calculation unit generates a second mask vector according to the second capacity to be released and a second base address, and the second base address is used for marking the second capacity to be released in the storage space; the second mask vector is used for adjusting the management units to be in an idle state in the n management units;

the second logic gate adjusts the state of the management unit of the second capacity in the first register set from the second base address to an idle state from an occupied state according to the second mask vector.

16. The method of claim 13, wherein the first logic gate circuit comprises at least one logic gate layer comprising logic gates for logically operating on states characterized by elements in the state vector;

the first logic gate circuit calculates a state vector of at least one management level according to the states of the n management units, and the first logic gate circuit comprises:

for a first logic gate in a first logic gate layer in the at least one logic gate layer, performing logic operation on elements at a first position and a second position of a state vector in a second management level by the first logic gate to obtain the elements at the first position in the state vector in a third management level;

17. The method of claim 13, wherein the hardware management module comprises a finite state machine and a control rate accelerator, the control rate accelerator comprising the first register set, the first logic gate, the first retriever, the second register set, the second retriever, and the signal conversion unit; the method further comprises the steps of:

And under the condition that the finite state machine receives an allocation instruction from the central processing unit, the finite state machine controls the control rate accelerator to allocate the storage space with the first capacity from the storage space, and the execution result of the allocation instruction is fed back to the central processing unit through a bus of the central processing unit.