CN116867320B - Display panel and display device - Google Patents
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- CN116867320B CN116867320B CN202310795332.2A CN202310795332A CN116867320B CN 116867320 B CN116867320 B CN 116867320B CN 202310795332 A CN202310795332 A CN 202310795332A CN 116867320 B CN116867320 B CN 116867320B
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- 239000004065 semiconductor Substances 0.000 claims description 78
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- 239000002184 metal Substances 0.000 claims description 61
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- 238000005538 encapsulation Methods 0.000 claims description 9
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- 238000010586 diagram Methods 0.000 description 3
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- 239000004642 Polyimide Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 238000004020 luminiscence type Methods 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
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- 229920001721 polyimide Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application belongs to the field of display, and particularly relates to a display panel and a display device, wherein the display panel comprises a substrate base plate and a plurality of pixel units, each pixel unit comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, the display panel further comprises a driving transistor, the driving transistor comprises a first transistor, a second transistor and a third transistor, the first transistor is connected with the blue sub-pixel, the second transistor is connected with the green sub-pixel, and the third transistor is connected with the red sub-pixel; the front projection of the red sub-pixel onto the substrate and the front projection of the green sub-pixel onto the substrate are located within the front projection of the blue sub-pixel onto the substrate, at least part of the front projections of the drive transistors intersecting on the substrate. The green sub-pixel and the red sub-pixel are laminated on the blue sub-pixel, namely, part of the driving transistors are laminated, and one pixel unit occupies a small space of the display panel, so that the pixel density of the display panel can be remarkably improved.
Description
Technical Field
The application belongs to the field of display, and particularly relates to a display panel and a display device.
Background
An OLED (Organic Light-Emitting Diode) display panel has advantages of self-luminescence, flexibility, thin thickness, high brightness, low power consumption, fast response, wide color gamut, etc., and is widely used in electronic products such as televisions, mobile phones, notebooks, etc.
The OLED display panel includes at least red, green and blue pixels to implement RGB display. Because the display life of the blue pixel material is short, the light emitting area of the blue pixel is usually designed to be large, and meanwhile, the precision of the manufacturing process of the red, green and blue pixels is limited, so that a group of red, green and blue pixels occupy large space of the display panel, and the improvement of the pixel density (PPI) of the OLED display panel is limited.
Disclosure of Invention
The application aims to provide a display panel and a display device, so as to improve the pixel density of an OLED display panel.
In order to achieve the above object, the present application provides a display panel, including a substrate and a plurality of pixel units, wherein the plurality of pixel units are arranged on the substrate in an array in a row direction and a column direction, the pixel units include red sub-pixels, green sub-pixels and blue sub-pixels, the display panel further includes a driving transistor, the driving transistor is arranged on a first side of the substrate, the driving transistor includes a first transistor, a second transistor and a third transistor, the first transistor is connected with the blue sub-pixels, the second transistor is connected with the green sub-pixels, and the third transistor is connected with the red sub-pixels;
The orthographic projection of the red sub-pixel on the substrate and the orthographic projection of the green sub-pixel on the substrate are positioned in the orthographic projection of the blue sub-pixel on the substrate, and at least part of orthographic projections of the driving transistors on the substrate intersect.
Optionally, the display panel includes a first pixel structure layer, a first isolation layer, and a second pixel structure layer sequentially formed on a first side of the substrate;
the first pixel structure layer comprises a first cathode layer, a first light-emitting layer and a first anode layer, the first cathode layer comprises a first cathode, the first light-emitting layer comprises a blue light-emitting part, the first anode layer comprises a first anode, the first cathode, the blue light-emitting part and the first anode are arranged in a stacked mode, the blue light-emitting part is connected with the first cathode and the first anode, and the blue sub-pixel comprises the first cathode, the blue light-emitting part and the first anode;
The second pixel structure layer comprises a second cathode layer, a second light-emitting layer and a second anode layer, the second cathode layer comprises a second cathode and a third cathode, the second light-emitting layer comprises a red light-emitting part and a green light-emitting part, the second anode layer comprises a second anode and a third anode, the second cathode, the green light-emitting part and the second anode are arranged in a stacked mode, the green light-emitting part is connected with the second cathode and the second anode, and the green sub-pixel comprises the second cathode, the green light-emitting part and the second anode;
the third cathode, the red light emitting part and the third anode are stacked, the red light emitting part is connected with the third cathode and the third anode, and the red sub-pixel comprises the third cathode, the red light emitting part and the third anode.
Optionally, the red light emitting part and the green light emitting part are arranged at intervals, and the red light emitting part and the green light emitting part are respectively positioned at two sides in the row direction of the blue light emitting part and at two sides in the column direction of the blue light emitting part.
Optionally, the first cathode layer, the first light emitting layer and the first anode layer are sequentially formed on the substrate, and the first cathode layer can reflect the light emitted by the blue light emitting part;
the second anode layer, the second light-emitting layer and the second cathode layer are sequentially formed on the first isolation layer, and the first anode layer and the second anode layer are light-transmitting structure layers.
Optionally, the display panel further includes a first metal layer and a second metal layer, where the first metal layer is formed on a first side of the substrate, and the second metal layer is formed on a side of the first isolation layer away from the substrate;
The first metal layer comprises a first cathode wire, the second metal layer comprises a second cathode wire, the first cathode wire is connected with adjacent first cathodes, the second cathode wire is connected with adjacent second cathodes, and the second cathodes are connected with the third cathodes.
Optionally, the first cathode layer, the first light emitting layer and the first anode layer are sequentially formed on the substrate, and the second anode layer, the second light emitting layer and the second cathode layer are sequentially formed on the first isolation layer;
The display panel further comprises a second isolation layer, a third isolation layer, a first semiconductor layer, a second semiconductor layer and a third metal layer, wherein the first metal layer, the second isolation layer, the first semiconductor layer, the third metal layer, the first isolation layer, the second semiconductor layer, the second metal layer and the third isolation layer are sequentially formed on the first side of the substrate base plate;
the first semiconductor layer comprises a first semiconductor part, the second semiconductor layer comprises a second semiconductor part, the first metal layer comprises a first source electrode and a first drain electrode, the second metal layer comprises a second source electrode and a second drain electrode, and the third metal layer comprises a first grid electrode;
The first source electrode and the first drain electrode are arranged at intervals, the second isolation layer covers the first source electrode, the first drain electrode and the first cathode wiring, the first semiconductor part is connected with the first source electrode, the first drain electrode and the first grid electrode, the first drain electrode is connected with the first anode electrode, and the first transistor comprises the first source electrode, the first drain electrode, the first semiconductor part and the first grid electrode;
The second source electrode and the second drain electrode are arranged at intervals, the third isolation layer covers the second source electrode, the second drain electrode and the second cathode wiring, the second semiconductor portion is connected with the second source electrode, the second drain electrode and the first grid electrode, the second drain electrode is connected with the second anode electrode, and the second transistor comprises the second source electrode, the second drain electrode, the second semiconductor portion and the first grid electrode.
Optionally, the second metal layer further includes a third source electrode and a third drain electrode, the third metal layer further includes a second gate electrode, the second semiconductor layer further includes a third semiconductor portion, the third source electrode and the third drain electrode are disposed at intervals, the third isolation layer covers the third source electrode and the third drain electrode, the third semiconductor portion is connected with the third source electrode, the third drain electrode and the second gate electrode, the third drain electrode is connected with the third anode electrode, and the third transistor includes the third semiconductor portion, the third source electrode, the third drain electrode and the second gate electrode.
Optionally, the second metal layer further includes a third source and a third drain, the first metal layer further includes a fourth source and a fourth drain, the third metal layer further includes a second gate, the second semiconductor layer further includes a third semiconductor portion, the first semiconductor layer further includes a fourth semiconductor portion, the third source and the third drain are disposed at intervals, the third insulating layer covers the third source and the third drain, the third semiconductor portion is connected to the third source, the third drain, and the second gate, the third drain is connected to the third anode, the third transistor includes the third semiconductor portion, the third source, the third drain, and the second gate, the fourth source and the fourth drain are disposed at intervals, the second insulating layer covers the fourth source and the fourth drain, and the fourth semiconductor portion is connected to the fourth source, the fourth drain, and the fourth drain.
Optionally, the display panel further includes a substrate layer, the substrate layer is formed on a first side of the substrate, and the first pixel structure layer is formed on a side of the substrate layer away from the substrate; and/or
The display panel further comprises an encapsulation layer, and the encapsulation layer is formed on one side, away from the substrate, of the second pixel structure layer.
The present application also provides a display device including:
The display panel;
And the main board is connected with the display panel.
The display panel and the display device disclosed by the application have the following beneficial effects:
In the application, the orthographic projection of the red sub-pixel on the substrate and the orthographic projection of the green sub-pixel on the substrate are positioned in the orthographic projection of the blue sub-pixel on the substrate, namely, the green sub-pixel and the red sub-pixel are overlapped on the blue sub-pixel, and at least part of orthographic projections of the driving transistors on the substrate are intersected, namely, part of the driving transistors are overlapped, so that the design is designed, the occupied space of a pixel unit of the display panel is reduced, and the pixel density of the display panel can be obviously improved.
Other features and advantages of the application will be apparent from the following detailed description, or may be learned by the practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic top view of a display panel according to a first embodiment of the application.
Fig. 2 is a schematic diagram of a sub-pixel stack of a display panel according to a first embodiment of the application.
Fig. 3 is a schematic cross-sectional view of a display panel according to a first embodiment of the application.
Fig. 4 is a schematic diagram of a sub-pixel stack of a display panel according to a second embodiment of the application.
Fig. 5 is a schematic cross-sectional view of a display panel according to a second embodiment of the application.
Fig. 6 is a schematic structural diagram of a display device according to a third embodiment of the present application.
Reference numerals illustrate:
100. a substrate base;
201. a blue sub-pixel; 202. a green sub-pixel; 203. a red subpixel;
301. A first transistor; 302. a second transistor; 303. a third transistor;
410. A first cathode layer; 411. a first cathode; 420. a first light emitting layer; 421. a blue light emitting section; 430. a first anode layer; 431. a first anode; 440. a second anode layer; 441. a second anode; 442. a third anode;
450. A second light emitting layer; 451. a green light emitting part; 452. a red light emitting section; 460. a second cathode layer; 461. a second cathode; 462. a third cathode; 470. a first insulating layer; 480. a first metal layer; 481. a first cathode trace; 482. a first source electrode; 483. a first drain electrode; 484. a fourth source electrode; 485. a fourth drain electrode;
490. a second metal layer; 491. a second source electrode; 492. a second drain electrode; 493. a third source electrode; 494. a third drain electrode; 500. a second insulating layer; 510. a third insulating layer;
520. A first semiconductor layer; 521. a first semiconductor portion; 522. a fourth semiconductor portion; 530. a second semiconductor layer; 531. a second semiconductor portion; 532. a third semiconductor portion; 540. a third metal layer; 541. a first gate; 542. a second gate;
600. a substrate layer; 700. an encapsulation layer;
10. A display panel; 20. and a main board.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The application will be described in further detail with reference to the drawings and the specific examples. It should be noted that the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
Example 1
Referring to fig. 1 and 2, the display panel in this embodiment includes a substrate 100 and a plurality of pixel units arranged in an array in a row direction and a column direction on the substrate 100. The substrate 100 may include a glass substrate or a polyimide (Pi) substrate. The pixel unit includes a blue subpixel 201, a green subpixel 202, and a red subpixel 203. The display panel further includes a driving transistor disposed on the first side of the substrate 100, the driving transistor including a first transistor 301, a second transistor 302, and a third transistor 303, the first transistor 301 being connected to the blue subpixel 201, the second transistor 302 being connected to the green subpixel 202, and the third transistor 303 being connected to the red subpixel 203.
Wherein the front projection of red sub-pixel 203 onto substrate 100 and the front projection of green sub-pixel 202 onto substrate 100 are located within the front projection of blue sub-pixel 201 onto substrate 100. At least part of the front projections of the drive transistors on the substrate 100 intersect, e.g. the front projection of the first transistor 301 on the substrate 100 intersects the front projection of the second transistor 302 on the substrate 100.
Because the display life of the blue pixel material is short, the light emitting area of the blue pixel is designed to be large, so that a group of red, green and blue pixels occupy large space of the display panel, and the improvement of the pixel density of the OLED display panel is limited.
In this embodiment, the orthographic projection of the red sub-pixel 203 on the substrate 100 and the orthographic projection of the green sub-pixel 202 on the substrate 100 are located in the orthographic projection of the blue sub-pixel 201 on the substrate 100, that is, the green sub-pixel 202 and the red sub-pixel 203 are stacked on the blue sub-pixel 201, and at least part of the orthographic projections of the driving transistors on the substrate 100 intersect, that is, part of the driving transistors are stacked, so that the design is designed to reduce the space occupied by one pixel unit in the display panel, thereby significantly improving the pixel density of the display panel.
For example, referring to fig. 2 and 3, the substrate base 100 has opposite first and second sides. The display panel includes a first pixel structure layer, a first insulating layer 470, and a second pixel structure layer sequentially formed on a first side of the substrate 100. The first insulating layer 470 may be an organic insulating layer.
The first pixel structure layer includes a first cathode layer 410, a first light emitting layer 420, and a first anode layer 430, the first cathode layer 410 includes a first cathode 411, the first light emitting layer 420 includes a blue light emitting portion 421, the first anode layer 430 includes a first anode 431, the first cathode 411, the blue light emitting portion 421, and the first anode 431 are stacked and disposed, and the blue light emitting portion 421 connects the first cathode 411 and the first anode 431. The blue subpixel 201 includes a first cathode 411, a blue light emitting portion 421, and a first anode 431.
The second pixel structure layer includes a second anode layer 440, a second light emitting layer 450, and a second cathode layer 460. The second anode layer 440 includes a second anode 441 and a third anode 442, the second light emitting layer 450 includes a green light emitting portion 451 and a red light emitting portion 452, and the second cathode layer 460 includes a second cathode 461 and a third cathode 462. The second cathode 461, the green light-emitting portion 451, and the second anode 441 are stacked, and the green light-emitting portion 451 is connected to the second cathode 461 and the second anode 441. The green subpixel 202 includes a second cathode 461, a green light emitting portion 451, and a second anode 441.
The third cathode 462, the red light emitting portion 452, and the third anode 442 are stacked, and the red light emitting portion 452 connects the third cathode 462 and the third anode 442. The red subpixel 203 includes a third cathode 462, a red light emitting portion 452, and a third anode 442.
The green light emitting portion 451 and the red light emitting portion 452 are stacked above the blue light emitting portion 421, and a part of light emitted from the blue light emitting portion 421 needs to be emitted through the green light emitting portion 451 or the red light emitting portion 452, and since the green light emitting portion 451 and the red light emitting portion 452 occupy a small area, the blue light emitting portion 421 occupies a large area, and a part of blue light is emitted through the green light emitting portion 451 or the red light emitting portion 452, the influence on the transmittance of blue light is small, and the green light emitting portion 451 and the red light emitting portion 452 are not blocked, and the influence on the red light and the green light is not affected.
The green light-emitting portion 451 and the red light-emitting portion 452 may be stacked above the blue light-emitting portion 421, but the present invention is not limited thereto, and the green light-emitting portion 451 and the red light-emitting portion 452 may be stacked below the blue light-emitting portion 421, as the case may be.
Referring to fig. 2 and 3, the red light emitting portion 452 and the green light emitting portion 451 are disposed at intervals, and the red light emitting portion 452 and the green light emitting portion 451 are located at both sides in the row direction of the blue light emitting portion 421 and at both sides in the column direction of the blue light emitting portion 421, respectively. As an example, as shown in fig. 1, the green light emitting part 451 is provided at the upper left corner of the blue light emitting part 421, and the red light emitting part 452 is provided at the lower right corner of the blue light emitting part 421.
The green light emitting part 451 is disposed at the upper left corner of the blue light emitting part 421, and the red light emitting part 452 is disposed at the lower right corner of the blue light emitting part 421, so that the green light emitting part 451 and the red light emitting part 452 can maintain a certain interval, and the center distance between the green light emitting part 451 and the red light emitting part 452 is small, which is beneficial for the light mixing of the green light emitting part 451 and the red light emitting part 452. The green light emitting portion 451 and the red light emitting portion 452 are arranged so as to avoid interference with each other during vapor deposition.
The specific positions of the green light emitting portion 451 and the red light emitting portion 452 are not limited to the upper left corner and the lower right corner of the blue light emitting portion 421, respectively, and the present application is not limited as the case may be.
Referring to fig. 2 and 3, the first cathode layer 410, the first light emitting layer 420, and the first anode layer 430 are sequentially formed on the substrate 100, the blue light emitting portion 421 emits light at a low level, and the first cathode layer 410 can reflect light emitted from the blue light emitting portion 421 to emit light emitted from the blue light emitting portion 421. The materials of the first cathode layer 410 and the second cathode layer 460 may be silver, and the thickness of the second cathode layer 460 is greater than that of the first cathode layer 410, so that the first cathode layer 410 can reflect the light emitted by the blue light emitting portion 421.
The light emitted from the blue light emitting portion 421 is reflected by the first cathode layer 410, so that the light utilization rate of the blue light emitting portion 421 can be improved, and the light emitting lifetime of the blue light emitting portion 421 can be advantageously improved.
The second anode layer 440, the second light emitting layer 450 and the second cathode layer 460 are sequentially formed on the first insulation layer 470, and the first anode layer 430 and the second anode layer 440 are light-transmitting structure layers. The first anode layer 430 and the second anode layer 440 may each be Indium Tin Oxide (ITO).
The first anode layer 430 and the second anode layer 440 are light-transmitting structure layers, so that the first anode layer 430 and the second anode layer 440 can prevent the blue light-emitting portion 421 from blocking the light. The first anode layer 430 and the second anode layer 440 are centrally disposed and also reduce interference from variations in upper and lower pole voltages.
Note that, the first cathode layer 410, the first light emitting layer 420, and the first anode layer 430 may be sequentially formed on the substrate 100, but not limited thereto, and the positions of the first cathode layer 410 and the first anode layer 430 may be interchanged, so that the blue light emitting portion 421 emits light at the top, as the case may be.
Referring to fig. 2 and 3, the display panel further includes a first metal layer 480 and a second metal layer 490, the first metal layer 480 is formed on a first side of the substrate 100, and the second metal layer 490 is formed on a side of the first insulating layer 470 remote from the substrate 100. The first metal layer 480 includes a first cathode trace 481, and the second metal layer 490 includes a second cathode trace, the first cathode trace 481 is connected to the adjacent first cathode 411, the second cathode trace is connected to the adjacent second cathode 461, and the second cathode 461 is connected to the third cathode 462.
The first cathode wire 481 is used for connecting the adjacent first cathode 411, the second cathode wire is used for connecting the adjacent second cathode 461, and the second cathode 461 is connected with the third cathode 462, so that the impedance can be reduced, and the voltage drop of the cathode caused by the impedance can be reduced. In addition, the cathode wiring can also shield light to a certain extent, so that interference between adjacent pixels is reduced.
Referring to fig. 2 and 3, the display panel further includes a second insulating layer 500, a third insulating layer 510, a first semiconductor layer 520, a second semiconductor layer 530, and a third metal layer 540. The first metal layer 480, the second isolation layer 500, the first semiconductor layer 520, the third metal layer 540, the first isolation layer 470, the second semiconductor layer 530, the second metal layer 490, and the third isolation layer 510 are sequentially formed on the first side of the substrate 100. The second insulating layer 500 and the third insulating layer 510 may be organic insulating layers.
The first semiconductor layer 520 includes a first semiconductor portion 521, the second semiconductor layer 530 includes a second semiconductor portion 531, the first metal layer 480 includes a first source electrode 482, a first drain electrode 483, the second metal layer 490 includes a second source electrode 491 and a second drain electrode 492, and the third metal layer 540 includes a first gate electrode 541.
The first source electrode 482 and the first drain electrode 483 are disposed at intervals, and the second insulating layer 500 covers the first source electrode 482, the first drain electrode 483, and the first cathode trace 481. The first semiconductor portion 521 is connected to the first source 482, the first drain 483, and the first gate 541, the first drain 483 is connected to the first anode 431, and the first transistor 301 includes the first source 482, the first drain 483, the first semiconductor portion 521, and the first gate 541.
The second source 491 and the second drain 492 are spaced apart, and the third insulating layer 510 covers the second source 491, the second drain 492, and the second cathode trace. The second semiconductor portion 531 is connected to the second source 491, the second drain 492, and the first gate 541, the second drain 492 is connected to the second anode 441, and the second transistor 302 includes the second source 491, the second drain 492, the second semiconductor portion 531, and the first gate 541. That is, the first transistor 301 and the second transistor 302 share a gate.
When the blue light emitting portion 421 and the green light emitting portion 451 emit light simultaneously in displaying a screen, a scan signal is written to the first gate 541, the first transistor 301 and the second transistor 302 are turned on simultaneously, and a data voltage can be written to control the blue light emitting portion 421 and the green light emitting portion 451 to emit light simultaneously; when one of the blue light-emitting portion 421 and the green light-emitting portion 451 emits light, a scanning signal is written to the first gate 541, the first transistor 301 and the second transistor 302 are simultaneously turned on, and a data voltage is written to one of the first transistor 301 and the second transistor 302, so that one of the blue light-emitting portion 421 and the green light-emitting portion 451 emits light.
The first transistor 301 and the second transistor 302 share the gate, which not only reduces the gate wiring and one metal layer, but also completely overlaps the first transistor 301 and the second transistor 302, so that the occupied area of the first transistor 301 and the second transistor 302 is minimized, and the pixel density of the display panel can be significantly improved.
It should be noted that the first transistor 301 and the second transistor 302 share a gate, but the third metal layer 540 may be, but not limited to, two metal layers separated by an insulating layer, so that the first transistor 301 and the second transistor 302 may have independent gates, and thus the first transistor 301 and the second transistor 302 may be turned on or off separately, as the case may be. The blue light emitting portion 421 and the green light emitting portion 451 are controlled by the first transistor 301 and the second transistor 302, respectively, but the present invention is not limited thereto, and the positions of the green light emitting portion 451 and the red subpixel 203 may be interchanged, as the case may be.
Referring to fig. 2 and 3, the second metal layer 490 further includes a third source electrode 493 and a third drain electrode 494, the third metal layer 540 further includes a second gate electrode 542, and the second semiconductor layer 530 further includes a third semiconductor portion 532. The third source 493 and the third drain 494 are spaced apart, and the third insulating layer 510 covers the third source 493 and the third drain 494. The third semiconductor portion 532 is connected to the third source 493, the third drain 494 and the second gate 542, the third drain 494 is connected to the third anode 442, and the third transistor 303 includes the third semiconductor portion 532, the third source 493, the third drain 494 and the second gate 542.
The third transistor 303 includes a third semiconductor portion 532, a third source 493, a third drain 494, and a second gate 542, and the third transistor 303 can be independently controlled to be turned on or off by the second gate 542, so that the requirement of the display driving circuit can be reduced.
Referring to fig. 2 and 3, the display panel further includes a substrate layer 600, the substrate layer 600 is formed on a first side of the substrate 100, the first pixel structure layer is formed on a side of the substrate layer 600 away from the substrate 100, and the first transistor 301 is also located on a side of the substrate layer 600 away from the substrate 100. The substrate layer 600 may be an inorganic insulating layer.
A substrate layer 600 is formed on the substrate 100, and the influence of the light leakage current on the driving transistor can be reduced by the substrate layer 600.
Referring to fig. 2 and 3, the display panel further includes an encapsulation layer 700, and the encapsulation layer 700 is formed on a side of the second pixel structure layer remote from the substrate 100.
The encapsulation layer 700 may block water and oxygen, thereby protecting the blue sub-pixel 201, the green sub-pixel 202, and the red sub-pixel 203, and delaying the lifetime of the display panel.
The display panel is manufactured by:
1. Forming a substrate layer 600 by a film forming process;
2. Forming a first metal layer 480 by film formation, exposure and etching;
3. forming a first cathode layer 410 using a film formation + exposure + etching process;
4. Forming a second isolation layer 500 by film formation, exposure and etching;
5. forming a first semiconductor layer 520 using a film formation + exposure + etching process;
6. Forming a first light emitting layer 420 using a film formation + exposure + etching process;
7. forming a first anode layer 430 using a film formation + exposure + etching process;
8. Forming a third metal layer 540 by a film formation + exposure + etching process;
9. forming a first insulating layer 470 using a film forming process;
10. forming a second semiconductor layer 530 using a film formation + exposure + etching process;
11. Forming a first metal layer 490 using a film formation + exposure + etching process;
12. Forming a second anode layer 440 using a film formation + exposure + etching process;
13. forming a third isolation layer by adopting a film forming, exposing and etching process;
14. Forming a second light emitting layer 450 by an evaporation process;
15. forming a second cathode layer 460 using an evaporation process;
16. The encapsulation layer 700 is formed using a film forming process.
Example two
The difference between the second embodiment and the first embodiment is that the structure of the third transistor 303 is different.
Referring to fig. 4 and 5, the second metal layer 490 further includes a third source 493 and a third drain 494, the first metal layer 480 further includes a fourth source 484 and a fourth drain 485, the third metal layer 540 further includes a second gate 542, the second semiconductor layer 530 further includes a third semiconductor portion 532, and the first semiconductor layer 520 further includes a fourth semiconductor portion 522.
The third source 493 and the third drain 494 are spaced apart, and the third insulating layer 510 covers the third source 493 and the third drain 494. The third semiconductor portion 532 is connected to the third source 493, the third drain 494 and the second gate 542, the third drain 494 is connected to the third anode 442, and the third transistor 303 includes the third semiconductor portion 532, the third source 493, the third drain 494 and the second gate 542.
The fourth source electrode 484 and the fourth drain electrode 485 are disposed at an interval, the second insulating layer 500 covers the fourth source electrode 484 and the fourth drain electrode 485, the fourth semiconductor portion 522 is connected to the fourth source electrode 484, the fourth drain electrode 485, and the second gate electrode 542, and the fourth drain electrode 485 is connected to another sub-pixel.
For some display panels, at least a portion of the pixel units include, in addition to the blue sub-pixel 201, the green sub-pixel 202, and the red sub-pixel 203, an additional peep-proof sub-pixel, and the fourth drain 485 may be connected to the peep-proof sub-pixel to control the peep-proof sub-pixel to be turned on or turned off. For some display panels, at least a part of the pixel units include, in addition to the blue sub-pixel 201, the green sub-pixel 202 and the red sub-pixel 203, an additionally arranged white sub-pixel, so as to implement RGBW display, and the fourth drain electrode 485 may be connected with the white sub-pixel to control the white sub-pixel to be turned on or off. For a display panel in which the pixel unit includes only the blue sub-pixel 201, the green sub-pixel 202, and the red sub-pixel 203, the fourth drain 485 may also be connected to a sub-pixel of another pixel unit, for example, the red sub-pixel 203 of another pixel unit, as the case may be.
Example III
Referring to fig. 6, the display device of the present embodiment includes a display panel 10 and a main board 20, and the main board 20 is connected to the display panel 10. The display panel 10 may include the display panel 10 disclosed in the first and second embodiments.
The display device comprises a display panel 10, wherein the orthographic projection of a red sub-pixel 203 on a substrate 100 and the orthographic projection of a green sub-pixel 202 on the substrate 100 in the display panel 10 are positioned in the orthographic projection of a blue sub-pixel 201 on the substrate 100, namely, the green sub-pixel 202 and the red sub-pixel 203 are laminated on the blue sub-pixel 201, and at least part of orthographic projections of driving transistors on the substrate 100 intersect, namely, part of driving transistors are laminated, so that the design is designed, the occupied space of one pixel unit of the display panel 10 is reduced, and the pixel density of the display panel 10 can be remarkably improved. The display panel 10 is used for a display device, and can improve the display effect of the display device.
The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly, and may be fixedly attached, detachably attached, or integrally formed, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made in the above embodiments by those skilled in the art within the scope of the application, which is therefore intended to be covered by the appended claims and their equivalents.
Claims (9)
1. The display panel comprises a substrate base plate and a plurality of pixel units, wherein the pixel units are arranged on the substrate base plate in an array mode in the row direction and the column direction, and each pixel unit comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel;
Wherein the orthographic projection of the red sub-pixel on the substrate and the orthographic projection of the green sub-pixel on the substrate are positioned in the orthographic projection of the blue sub-pixel on the substrate, and at least part of orthographic projections of the driving transistor on the substrate intersect;
The display panel comprises a first pixel structure layer, a first isolation layer and a second pixel structure layer which are sequentially formed on the first side of the substrate;
the first pixel structure layer comprises a first cathode layer, a first light-emitting layer and a first anode layer, the first cathode layer comprises a first cathode, the first light-emitting layer comprises a blue light-emitting part, the first anode layer comprises a first anode, the first cathode, the blue light-emitting part and the first anode are arranged in a stacked mode, the blue light-emitting part is connected with the first cathode and the first anode, and the blue sub-pixel comprises the first cathode, the blue light-emitting part and the first anode;
The second pixel structure layer comprises a second cathode layer, a second light-emitting layer and a second anode layer, the second cathode layer comprises a second cathode and a third cathode, the second light-emitting layer comprises a red light-emitting part and a green light-emitting part, the second anode layer comprises a second anode and a third anode, the second cathode, the green light-emitting part and the second anode are arranged in a stacked mode, the green light-emitting part is connected with the second cathode and the second anode, and the green sub-pixel comprises the second cathode, the green light-emitting part and the second anode;
the third cathode, the red light emitting part and the third anode are stacked, the red light emitting part is connected with the third cathode and the third anode, and the red sub-pixel comprises the third cathode, the red light emitting part and the third anode.
2. The display panel according to claim 1, wherein the red light emitting portion and the green light emitting portion are provided at an interval, the red light emitting portion and the green light emitting portion being located on both sides in a row direction of the blue light emitting portion and on both sides in a column direction of the blue light emitting portion, respectively.
3. The display panel according to claim 1, wherein the first cathode layer, the first light-emitting layer, and the first anode layer are sequentially formed on the substrate base plate, the first cathode layer being capable of reflecting light emitted from the blue light-emitting portion;
the second anode layer, the second light-emitting layer and the second cathode layer are sequentially formed on the first isolation layer, and the first anode layer and the second anode layer are light-transmitting structure layers.
4. The display panel of claim 1, further comprising a first metal layer formed on a first side of the substrate and a second metal layer formed on a side of the first insulating layer away from the substrate;
The first metal layer comprises a first cathode wire, the second metal layer comprises a second cathode wire, the first cathode wire is connected with adjacent first cathodes, the second cathode wire is connected with adjacent second cathodes, and the second cathodes are connected with the third cathodes.
5. The display panel of claim 4, wherein the first cathode layer, the first light-emitting layer, and the first anode layer are sequentially formed on the substrate base plate, and the second anode layer, the second light-emitting layer, and the second cathode layer are sequentially formed on the first insulating layer;
The display panel further comprises a second isolation layer, a third isolation layer, a first semiconductor layer, a second semiconductor layer and a third metal layer, wherein the first metal layer, the second isolation layer, the first semiconductor layer, the third metal layer, the first isolation layer, the second semiconductor layer, the second metal layer and the third isolation layer are sequentially formed on the first side of the substrate base plate;
the first semiconductor layer comprises a first semiconductor part, the second semiconductor layer comprises a second semiconductor part, the first metal layer comprises a first source electrode and a first drain electrode, the second metal layer comprises a second source electrode and a second drain electrode, and the third metal layer comprises a first grid electrode;
The first source electrode and the first drain electrode are arranged at intervals, the second isolation layer covers the first source electrode, the first drain electrode and the first cathode wiring, the first semiconductor part is connected with the first source electrode, the first drain electrode and the first grid electrode, the first drain electrode is connected with the first anode electrode, and the first transistor comprises the first source electrode, the first drain electrode, the first semiconductor part and the first grid electrode;
The second source electrode and the second drain electrode are arranged at intervals, the third isolation layer covers the second source electrode, the second drain electrode and the second cathode wiring, the second semiconductor portion is connected with the second source electrode, the second drain electrode and the first grid electrode, the second drain electrode is connected with the second anode electrode, and the second transistor comprises the second source electrode, the second drain electrode, the second semiconductor portion and the first grid electrode.
6. The display panel according to claim 5, wherein the second metal layer further includes a third source electrode and a third drain electrode, wherein the third metal layer further includes a second gate electrode, wherein the second semiconductor layer further includes a third semiconductor portion, wherein the third source electrode and the third drain electrode are spaced apart, wherein the third insulating layer covers the third source electrode and the third drain electrode, wherein the third semiconductor portion is connected to the third source electrode, the third drain electrode, and the second gate electrode, wherein the third drain electrode is connected to the third anode electrode, and wherein the third transistor includes the third semiconductor portion, the third source electrode, the third drain electrode, and the second gate electrode.
7. The display panel according to claim 5, wherein the second metal layer further includes a third source and a third drain, wherein the first metal layer further includes a fourth source and a fourth drain, wherein the third metal layer further includes a second gate, wherein the second semiconductor layer further includes a third semiconductor portion, wherein the first semiconductor layer further includes a fourth semiconductor portion, wherein the third source and the third drain are spaced apart, wherein the third insulating layer covers the third source and the third drain, wherein the third semiconductor portion is connected to the third source, the third drain, and the second gate, wherein the third drain is connected to the third anode, wherein the third transistor includes the third semiconductor portion, the third source, the third drain, and the second gate, wherein the fourth source and the fourth drain are spaced apart, wherein the second layer covers the fourth source and the fourth drain, wherein the third insulating layer covers the fourth source and the fourth drain, wherein the fourth semiconductor portion is connected to the fourth source, the third drain, and the fourth drain.
8. The display panel of claim 1, further comprising a substrate layer formed on a first side of the substrate, the first pixel structure layer formed on a side of the substrate layer remote from the substrate; and/or
The display panel further comprises an encapsulation layer, and the encapsulation layer is formed on one side, away from the substrate, of the second pixel structure layer.
9. A display device, comprising:
The display panel according to any one of claims 1 to 8;
And the main board is connected with the display panel.
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