CN116865755A - Pipelined ADC linearization calibration circuit and method applied to front-end sampling protection structure - Google Patents
Pipelined ADC linearization calibration circuit and method applied to front-end sampling protection structure Download PDFInfo
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- H—ELECTRICITY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention discloses a pipeline ADC linearization calibration circuit with a front-end sampling protection structure, which comprises: the device comprises a pseudo-random code generation circuit, a jitter injection circuit, a sampling circuit, a pipeline ADC circuit and a digital linear calibration module; the pseudo random code generated by the pseudo random code generating circuit controls the level of the upper polar plate connection of the calibration capacitor of the jitter injection circuit to realize the injection of the jitter signal into the sampling circuit; the sampling circuit outputs the input signal and the dithering signal to the pipeline ADC circuit after superposing the input signal and the dithering signal; the output end of the pipeline ADC circuit is connected with the input end of the digital linear calibration module. The embodiment of the invention also provides a calibration method applied to the pipeline ADC linearization calibration circuit with the front-end sampling protection structure. According to the invention, the analog signal and the dithering signal are superposed and quantized by the pipelined ADC, and the randomness of the dithering converts the frequency spectrum spurious generated by nonlinear influence in the circuit into uniform in-band noise through randomization, so that the linearity is improved, and the signal to noise ratio of the ADC is not influenced.
Description
Technical Field
The invention belongs to the technical field of mixed signal integrated circuits, and particularly relates to a pipeline ADC linearization calibration circuit with a front-end sampling protection structure and a calibration method.
Background
Analog-to-digital converters (Analog to Digital Circuit, ADCs) are an important component of mixed signal systems, and among the various ADCs, pipelined ADCs are widely used with their unique trade-off advantages in terms of accuracy, speed, power consumption and area. However, the existing pipeline ADC technology has a not negligible disadvantage, and with the development of radio frequency communication, the higher the signal frequency is, the wider the bandwidth is, and the higher linearity requirement is provided for the high-speed radio frequency ADC in radio frequency communication. While the development of the process node increases the speed, the power supply voltage and the intrinsic gain are reduced, and the linearity of the operational amplifier is deteriorated, which becomes a bottleneck for improving the linearity of the ADC.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a pipeline ADC linearization calibration circuit and a calibration method applied to a front-end sampling structure. The technical problems to be solved by the invention are realized by the following technical scheme:
a pipelined ADC linearization calibration circuit for use with a front-end sampling architecture, comprising: the device comprises a pseudo-random code generation circuit, a jitter injection circuit, a sampling circuit, a pipeline ADC circuit and a digital linear calibration module;
the output end of the pseudo-random code generation circuit is connected with the input end of the jitter injection circuit and the input end of the digital linear calibration module, and the pseudo-random code generated by the pseudo-random code generation circuit controls the level of connection of the upper polar plate of the calibration capacitor of the jitter injection circuit so as to inject a jitter signal into the sampling circuit;
the sampling circuit is used for receiving an input signal, and outputting the input signal and the dithering signal to the pipeline ADC circuit after superposition;
and the output end of the pipeline ADC circuit is connected with the input end of the digital linear calibration module.
In one embodiment of the invention, the jitter injection circuit comprises a jitter injection module and the calibration capacitance;
the input end of the jitter injection circuit is connected with the output end of the pseudo-random code generation circuit, and the output end of the jitter injection circuit is connected with the upper polar plate of the calibration capacitor;
and the lower polar plate of the calibration capacitor is connected with the input end of the sampling circuit.
In one embodiment of the present invention, the sampling circuit includes: the device comprises an input buffer, a first switch, a second switch, a sampling capacitor, a third switch and an output buffer;
the input end of the input buffer is used for receiving an input signal, and the output end of the input buffer is connected with one end of the first switch;
the other end of the first switch is connected with one end of the second switch and one polar plate of the sampling capacitor;
the other end of the second switch is grounded;
the other polar plate of the sampling capacitor is connected with one end of the third switch, the input end of the output buffer and the lower polar plate of the calibration capacitor;
the other end of the third switch is grounded;
and the output end of the output buffer is connected with the pipeline ADC circuit.
In one embodiment of the present invention, the digital linear calibration module is configured to perform linear calibration on the pseudo-random code and the digital code output by the pipelined ADC circuit, and output a calibration signal.
In one embodiment of the invention, the pipelined ADC circuit comprises: multiple stages of sub-ADC circuits connected in series in sequence.
The embodiment of the invention also provides a calibration method applied to the pipeline ADC linearization calibration circuit with the front-end sampling protection structure, which is applied to the calibration circuit of the first aspect of the embodiment of the invention, and comprises the following steps:
s1, starting a pseudo-random code generation circuit when a pipeline ADC circuit works to generate a pseudo-random code;
s2, inputting the pseudo-random code into a jitter injection circuit to control the level of upper polar plate connection of a calibration capacitor of the jitter injection circuit so as to realize the injection of a jitter signal into a sampling circuit and the input of the pseudo-random code into a digital linear calibration module;
s3, the sampling circuit receives an input signal and the dithering signal, and outputs the input signal and the dithering signal to the pipeline ADC circuit after being overlapped;
s4, the pipeline ADC circuit quantizes the input signal and outputs the digital code of each stage to the digital linear calibration module;
and S5, the digital linear calibration module carries out linear calibration on the digital codes and the pseudo random codes of each stage and outputs calibration signals.
In one embodiment of the present invention, the specific step of S5 is:
and the digital linear calibration module multiplies the digital codes of each stage by the corresponding coefficient of each stage to obtain a coefficient code value of each stage, and subtracts the result of multiplying the pseudo-random code and the pseudo-random coefficient after adding the coefficient code values of each stage to obtain a calibration signal.
The invention has the beneficial effects that:
the invention converts the pseudo-random code into the dithering signal and adds the dithering signal into the sampling circuit, and meanwhile, the digital end obtains the pseudo-random code. The analog signal and the dithering signal are overlapped and quantized by the pipelined ADC, and because of the randomness of dithering, spectrum spurious which generates nonlinear effects in the circuit is converted into uniform in-band noise through randomization, so that high-power harmonic waves can be attenuated to improve linearity, and the nonlinear effects of the circuit are reduced to the minimum. The pseudo random code is used to subtract the dithering signal at the digital end, so that the signal to noise ratio of the ADC is not affected. The method is suitable for the pipeline ADC with the front-end sampling protection structure, can be operated in the background, and has simple calibration algorithm.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic diagram of a pipeline ADC linearization calibration circuit with a front-end sampling protection structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a sample-and-hold circuit according to an embodiment of the present invention;
fig. 3 is a first-stage transmission graph of a pipeline ADC linearization calibration circuit with a front-end sampling structure according to an embodiment of the invention;
fig. 4 is a schematic diagram of a transmission curve of a first-stage superimposed jitter signal applied to a pipelined ADC linearization calibration circuit with a front-end sampling structure according to an embodiment of the present invention;
FIG. 5 is a graph comparing simulation results before and after calibration according to an embodiment of the present invention;
fig. 6 is a flowchart of a calibration method applied to a pipelined ADC linearization calibration circuit with a front-end sampling structure according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
As shown in fig. 1, a first aspect of an embodiment of the present invention provides a pipelined ADC linearization calibration circuit having a front-end sampling structure, including: the device comprises a pseudo-random code generation circuit, a jitter injection circuit, a sampling circuit, a pipeline ADC circuit and a digital linear calibration module.
The output end of the pseudo-random code generating circuit is connected with the input end of the jitter injection circuit and the input end of the digital linear calibration module, and the pseudo-random code generated by the pseudo-random code generating circuit controls the level of the upper polar plate connection of the calibration capacitor Cd of the jitter injection circuit so as to inject the jitter signal into the sampling circuit.
The sampling circuit is used for receiving an input signal, and outputting the input signal and the dithering signal to the pipeline ADC circuit after superposition;
the output end of the pipeline ADC circuit is connected with the input end of the digital linear calibration module.
In this embodiment, the pseudo-random code generating circuit, the jitter injection circuit, and the sampling circuit form a sample-hold circuit, and the input signal and the jitter signal are superimposed to quantize the pipeline ADC by using the randomizing characteristic of the jitter signal, so that spectrum spurious that generates nonlinear effects in the circuit is uniformly converted into noise in a frequency band through randomizing, so that harmonics with high power are attenuated, thereby improving linearity. And the digital linear calibration module subtracts the dither signal of the injection circuit by using the known pseudo-random code to perform linear calibration, so that the signal-to-noise ratio is not affected.
In this embodiment, when the pipeline ADC circuit works normally, the calibration mode is turned off, and neither the pseudo-random code generating circuit nor the jitter injection circuit works, and the ADC digital code is directly output. And the external device starts a calibration mode, and at the moment, the pseudo random code generating circuit starts to generate pseudo random codes (PRBS) and sends the pseudo random codes (PRBS) to the jitter injection circuit and the digital linear calibration module. And then the pseudo-random code controls the level of the upper polar plate connection of the calibration capacitor Cd in the jitter injection circuit to realize the injection of the jitter signal with known amplitude, namely the pseudo-random signal. The dither signal is superimposed with the input signal and transferred to the individual circuits, quantized and amplified through nonlinear calibration of the circuits. And then obtaining the ADC digital codes of each stage, sending the ADC digital codes into a digital linear calibration module for linear calibration, and outputting data to finish calibration.
Further, as shown in fig. 2, the jitter injection circuit includes a jitter injection module and a calibration capacitor Cd;
the input end of the jitter injection circuit is connected with the output end of the pseudo random code generation circuit, and the output end of the jitter injection circuit is connected with the upper polar plate of the calibration capacitor Cd. The lower polar plate of the calibration capacitor Cd is connected with the input end of the sampling circuit.
Further, the sampling circuit includes: the device comprises an input buffer, a first switch, a second switch, a sampling capacitor Cst, a third switch and an output buffer;
the input end of the input buffer is used for receiving an input signal, and the output end of the input buffer is connected with one end of the first switch. The other end of the first switch is connected with one end of the second switch and one polar plate of the sampling capacitor Cst; the other end of the second switch is grounded; the other polar plate of the sampling capacitor Cst is connected with one end of the third switch, the input end of the output buffer and the lower polar plate of the calibration capacitor Cd; the other end of the third switch is grounded. The output end of the output buffer is connected with the pipeline ADC circuit.
A pipelined ADC circuit comprising: multiple stages of sub-ADC circuits connected in series in sequence.
The digital linear calibration module is used for carrying out linear calibration on the pseudo-random code and the digital code output by the pipeline ADC circuit and outputting a calibration signal. Specifically, the digital linear calibration module multiplies the digital code of each stage output by each stage of sub ADC circuit with the corresponding coefficient of each stage to obtain a coefficient value of each stage, the digital linear calibration module multiplies the pseudo-random code and the pseudo-random coefficient, and the coefficient value of each stage is added and then subtracted from the result of the pseudo-random code and the pseudo-random coefficient to obtain a calibration signal. That is, the pseudo-random code is used to subtract the dither signal that can be injected into the circuit, and the signal-to-noise ratio of the ADC is not affected if the subtraction is complete.
Specifically, the pseudo-random code generating circuit generates pseudo-random code D PRBS Pseudo-random code D PRBS And sending the signals to a digital linear calibration module, and sending the generated dithering signals to a sampling circuit to be overlapped with the input signals and quantized by a pipeline ADC. Pipeline ADC obtains all-level digital codes D through quantization 1 、D 2 、···、D N To the digital terminal. When the calibration mode is not operated, the output digital code is D OUT_UNCAL ＝D 1 ×α 1 +D 2 ×α 2 +···+D N ×α N . When the calibration mode is turned on, the output digital code subtracts the PRBS code, i.e., D OUT_CALI ＝D 1 ×α 1 +D 2 ×α 2 +···+D N ×α N -D PRBS ×α PRBS Because the dither signal is equal to D PRBS ×α PRBS Therefore, the jitter signal added into the circuit is subtracted, so that the function of the circuit is not affected, and the calibration is finished.
In this embodiment, the sampling capacitor Cst in the sampling circuit is responsible for sampling an input signal and holding a sampled value, and outputs the sampled value through the output buffer. And a calibration capacitor Cd is added on the sampling capacitor Cst, a Cd lower plate is connected with an output buffer, and the voltage of the upper plate is controlled by a pseudo-random code generated by a pseudo-random code generating circuit. By being connected to a voltage value, a random signal is generated, called jitter. The dither signal and the sampled input signal are superposed and injected into the output buffer and the post-stage pipeline ADC circuit, and the dither signal has random characteristics and can influence the output buffer, the sub-ADC and the operational amplifier, and nonlinear influences generated in the circuits are uniformly converted into noise in a frequency band through randomization, so that high-power harmonic waves can be attenuated, and the linearity is improved.
The sub-ADC, the lower-stage board sampling and the operational amplifier form a pipeline ADC.
As shown in FIG. 3, the first stage is a 1.5-bit/stage pipeline ADC transmission curve, and the calibration method requires an additional comparator to be added to the subsequent sub-ADC, so that the input range can be expanded, the input range of +/-1 Vref/4 is increased within the allowable range of the output amplitude, thereby providing conditions for adding the dither signal, and the amplitude of the added dither signal can not influence the calibration effect.
As shown in fig. 4, the first stage is a pipeline ADC transmission curve of 1.5 bits/stage superimposed dither signal, so that the overall curve moves left and right along with the superposition of dither signals, which randomizes the input signal falling on the curve, and can reduce nonlinear harmonic power. And the shape of the whole curve is not changed, so that the quantization characteristic is not changed, and the quantization performance is not affected.
As shown in fig. 5, the data is obtained by mathematically modeling the pipelined ADC and adding a linearization calibration module to analyze the data. In the figure, the gray graph is an uncalibrated waveform, the black graph is a calibrated waveform, and the high stray harmonic power of the uncalibrated spectrogram can be observed, and the harmonic effect caused by the nonlinear influence of the amplifier is great. And the linearization technology randomizes the harmonic waves after calibration, so that the harmonic waves are uniformly dispersed on the background noise, and the linearity can be improved. According to the data, the linearity of the ADC before calibration is 78.81dB, the signal-to-noise ratio is 69.53dB, the linearity of the ADC after calibration is 88.72dB, and the signal-to-noise ratio is 69.22dB. The calibration algorithm enables the ADC not to be affected by harmonic wave any more, improves the linearity by 10dB, and has important significance for improving the linearity of the high-speed ADC.
Example two
As shown in fig. 6, an embodiment of the present invention provides a calibration method applied to a pipelined ADC linearization calibration circuit having a front-end sampling structure, implemented by a calibration circuit according to embodiment one, including the following steps:
s1, when the pipeline ADC circuit works, a pseudo-random code generating circuit is started to generate a pseudo-random code. When the pipeline ADC circuit works normally, the calibration mode is closed, the pseudo-random code generation circuit and the jitter injection circuit do not work, and the ADC digital code is directly output. And starting a calibration mode from the outside, and starting to generate a pseudo-random code by the pseudo-random code generation circuit, and sending the pseudo-random code to the jitter injection circuit and the digital linear calibration module end.
S2, inputting a pseudo-random code into a jitter injection circuit to control the level of the upper polar plate connection of a calibration capacitor Cd of the jitter injection circuit so as to realize the injection of a jitter signal into a sampling circuit and the input of the pseudo-random code into a digital linear calibration module;
s3, the sampling circuit receives the input signal and the dithering signal, and outputs the superimposed input signal and dithering signal to the pipeline ADC circuit;
s4, the pipeline ADC circuit carries out quantization on the input signal and outputs the digital code of each stage to the digital linear calibration module;
s5, the digital linear calibration module carries out linear calibration on the digital codes and the pseudo random codes of each stage and outputs calibration signals.
The specific steps of S5 are as follows:
the digital linear calibration module multiplies the digital codes of each stage by the corresponding coefficient of each stage to obtain a coefficient value of each stage, and subtracts the result of multiplying the coefficient value of each stage by the pseudo-random code and the pseudo-random coefficient after adding the coefficient value of each stage to obtain a calibration signal.
The pseudo-random code controls the level of the upper polar plate connection of the calibration capacitor Cd in the injection circuit, and the injection of the dither signal with known amplitude, namely the pseudo-random signal, is realized. The dither signal and the input signal are superposed and transmitted to each circuit, quantized and amplified, and nonlinear calibration of the circuit is carried out. And then obtaining the ADC digital codes of each stage, and sending the ADC digital codes into a calibration module. And the digital linear calibration module aligns the digital codes of each stage with the pseudo-random code, multiplies the digital codes by coefficients, performs subtraction operation and then outputs data to finish calibration.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. A pipelined ADC linearization calibration circuit for use with a front-end sampling architecture, comprising: the device comprises a pseudo-random code generation circuit, a jitter injection circuit, a sampling circuit, a pipeline ADC circuit and a digital linear calibration module;
the output end of the pseudo-random code generation circuit is connected with the input end of the jitter injection circuit and the input end of the digital linear calibration module, and the pseudo-random code generated by the pseudo-random code generation circuit controls the level of connection of the upper polar plate of the calibration capacitor of the jitter injection circuit so as to inject a jitter signal into the sampling circuit;
the sampling circuit is used for receiving an input signal, and outputting the input signal and the dithering signal to the pipeline ADC circuit after superposition;
and the output end of the pipeline ADC circuit is connected with the input end of the digital linear calibration module.
2. The pipelined ADC linearization calibration circuit with front-end sampling architecture of claim 1, wherein the dither injection circuit includes a dither injection module and the calibration capacitor;
the input end of the jitter injection circuit is connected with the output end of the pseudo-random code generation circuit, and the output end of the jitter injection circuit is connected with the upper polar plate of the calibration capacitor;
and the lower polar plate of the calibration capacitor is connected with the input end of the sampling circuit.
3. A pipelined ADC linearization calibration circuit for use with a front-end sampling architecture in accordance with claim 2, wherein the sampling circuit comprises: the device comprises an input buffer, a first switch, a second switch, a sampling capacitor, a third switch and an output buffer;
the input end of the input buffer is used for receiving an input signal, and the output end of the input buffer is connected with one end of the first switch;
the other end of the first switch is connected with one end of the second switch and one polar plate of the sampling capacitor;
the other end of the second switch is grounded;
the other polar plate of the sampling capacitor is connected with one end of the third switch, the input end of the output buffer and the lower polar plate of the calibration capacitor;
the other end of the third switch is grounded;
and the output end of the output buffer is connected with the pipeline ADC circuit.
4. A pipelined ADC linearization calibration circuit with a front-end sampling architecture according to claim 3, wherein the digital linearization calibration module is configured to perform a linearization calibration on the pseudorandom code and the digital code output by the pipelined ADC circuit, and output a calibration signal.
5. A pipelined ADC linearization calibration circuit for use with a front-end sampling architecture according to claim 1, wherein the pipelined ADC circuit comprises: multiple stages of sub-ADC circuits connected in series in sequence.
6. A calibration method applied to a pipelined ADC linearization calibration circuit having a front-end sampling structure, characterized by being applied to a calibration circuit according to any one of claims 1-5, comprising the steps of:
s1, starting a pseudo-random code generation circuit when a pipeline ADC circuit works to generate a pseudo-random code;
s2, inputting the pseudo-random code into a jitter injection circuit to control the level of upper polar plate connection of a calibration capacitor of the jitter injection circuit so as to realize the injection of a jitter signal into a sampling circuit and the input of the pseudo-random code into a digital linear calibration module;
s3, the sampling circuit receives an input signal and the dithering signal, and outputs the input signal and the dithering signal to the pipeline ADC circuit after being overlapped;
s4, the pipeline ADC circuit quantizes the input signal and outputs the digital code of each stage to the digital linear calibration module;
and S5, the digital linear calibration module carries out linear calibration on the digital codes and the pseudo random codes of each stage and outputs calibration signals.
7. The calibration method for the pipeline ADC linearization calibration circuit with the front-end sampling structure according to claim 6, wherein the specific step of S5 is as follows:
and the digital linear calibration module multiplies the digital codes of each stage by the corresponding coefficient of each stage to obtain a coefficient code value of each stage, and subtracts the result of multiplying the pseudo-random code and the pseudo-random coefficient after adding the coefficient code values of each stage to obtain a calibration signal.
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