CN116865585A - Control method and system for modularized parallel low-cost three-level inverter - Google Patents

Control method and system for modularized parallel low-cost three-level inverter Download PDF

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Publication number
CN116865585A
CN116865585A CN202310785899.1A CN202310785899A CN116865585A CN 116865585 A CN116865585 A CN 116865585A CN 202310785899 A CN202310785899 A CN 202310785899A CN 116865585 A CN116865585 A CN 116865585A
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vector
small
reference voltage
duty cycle
sector
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秦昌伟
褚志元
李晓艳
禹金标
石文文
梁栋
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Shandong Jianzhu University
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Shandong Jianzhu University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a control method and a control system for modularized parallel low-cost three-level inverters, which are used for connecting DC side neutral points of the parallel low-cost three-level inverters, so that zero sequence circulation caused by unbalanced midpoint voltage can be eliminated; zero sequence circulation suppression and neutral point voltage balance are realized by adjusting the duty ratio of small vectors, zero sequence circulation of a modularized parallel low-cost three-level inverter system is suppressed, neutral point voltage balance is ensured, and output current quality can be improved under steady-state and dynamic conditions. The control method is suitable for the operation conditions that the given currents of the parallel modules are equal and unequal and the operation conditions that the filter inductances of the inverters are equal and unequal.

Description

Control method and system for modularized parallel low-cost three-level inverter
Technical Field
The invention belongs to the technical field of power electronic power conversion, and particularly relates to a control method and a control system for a modularized parallel low-cost three-level inverter.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
The Three-Level Inverter (Three-Level Inverter) has the advantages of low voltage stress and loss of a switching tube, low harmonic content, good output waveform quality and the like, and is widely applied to the fields of photovoltaic power generation, composite energy storage, electric energy control and the like. Among them, diode Clamped (NPC) and T-Type (T-Type) three-level inverters are two most commonly used circuit topologies, but there are still limitations of a large number of switching transistors. The low-cost three-level inverter adopts a small number of switching tubes, reduces the system cost, maintains the multi-level output function and has wide application prospect.
The modularized parallel three-level inverter can improve the capacity, the reliability and the efficiency of a system and shorten the production period on the premise of not increasing the current stress of a switching tube, but the parallel form of a common direct current bus and an alternating current bus causes the problems of circulation, unbalanced midpoint voltage and the like, wherein Zero sequence circulation (Zero-Sequence Circulating Current, ZSCC) is a main constituent component of the circulation.
Zero sequence circulation and neutral point voltage unbalance cause serious distortion of inverter output current, increase switching tube voltage stress and loss, reduce system efficiency, even damage switching tube, seriously threaten system operation safety.
The inventor finds that the existing zero sequence loop current inhibition and midpoint voltage balance control method is only applicable to a T-type and NPC three-level inverter parallel system; the low cost three level inverter topology has limitations, output states are limited, and no intermediate vector can be generated. Therefore, the existing control method cannot be directly applied, and therefore, the control method suitable for the low-cost three-level inverter parallel system needs to be researched.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a control method and a control system for a modularized parallel low-cost three-level inverter, wherein zero-sequence circulation suppression and neutral-point voltage balance are realized by adjusting the duty ratio of small vectors, the zero-sequence circulation of the modularized parallel low-cost three-level inverter can be effectively suppressed, the neutral-point voltage balance is controlled, and the waveform quality of output current is obviously improved.
To achieve the above object, a first aspect of the present invention provides a control method of a modular parallel low-cost three-level inverter, the dc-side neutral points of the respective parallel low-cost three-level inverters being connected to each other, the control method comprising:
determining a sector and a region where a reference voltage vector is located, selecting a basic voltage vector to synthesize the reference voltage vector, and calculating a small vector duty ratio initial value;
inputting the tracking error of the zero sequence loop current to a zero sequence loop current controller based on limited time adjustment to obtain a small vector duty ratio first distribution factor correction value;
the direct-current side capacitor voltage deviation of the low-cost three-level inverter is input to a midpoint voltage balance controller based on proportion adjustment, and a small vector duty ratio second distribution factor correction value is obtained;
correcting the small vector duty cycle according to the small vector duty cycle first distribution factor correction value, the small vector duty cycle second distribution factor correction value and the small vector duty cycle initial value;
and designing a switching sequence according to the corrected small vector duty ratio, the sector and the area where the reference voltage vector is located, and generating a corresponding PWM driving signal according to the designed switching sequence to control the on and off of the switching tube.
A second aspect of the present invention provides a control system for modular parallel low-cost three-level inverters, each of the parallel low-cost three-level inverters having a dc-side neutral point connected to each other, comprising:
a small vector duty cycle initial value calculation module configured to: determining a sector and a region where a reference voltage vector is located, selecting a basic voltage vector to synthesize the reference voltage vector, and calculating a small vector duty ratio initial value;
a small vector duty cycle first division factor correction value determination module configured to: inputting the tracking error of the zero sequence loop current to a zero sequence loop current controller based on limited time adjustment to obtain a small vector duty ratio first distribution factor correction value;
a small vector duty cycle second division factor correction value determination module configured to: the direct-current side capacitor voltage deviation of the low-cost three-level inverter is input to a midpoint voltage balance controller based on proportion adjustment, and a small vector duty ratio second distribution factor correction value is obtained;
a small vector duty cycle correction module configured to: correcting the small vector duty cycle according to the small vector duty cycle first distribution factor correction value, the small vector duty cycle second distribution factor correction value and the small vector duty cycle initial value;
PWM drive control module: and designing a switching sequence according to the corrected small vector duty ratio, the sector and the area where the reference voltage vector is located, and generating a corresponding PWM driving signal according to the designed switching sequence to control the on and off of the switching tube.
A third aspect of the present invention provides a computer apparatus comprising: the control system comprises a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, when the computer device runs, the processor and the memory are communicated through the bus, and the machine-readable instructions are executed by the processor to execute a control method of the modularized parallel low-cost three-level inverter.
A fourth aspect of the invention provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor performs a method of controlling a modular parallel low cost three level inverter.
The one or more of the above technical solutions have the following beneficial effects:
in the invention, the neutral points of the DC sides of the low-cost three-level inverters which are connected in parallel are connected, so that zero sequence circulation caused by unbalanced midpoint voltage can be eliminated; the zero-sequence circulation suppression and the balance of the midpoint voltage are realized by adjusting the duty ratio of small vectors, the zero-sequence circulation of a modularized parallel low-cost three-level inverter system is suppressed, the balance of the midpoint voltage is ensured, the output current quality can be improved under the steady-state and dynamic conditions, and the control method is suitable for the operation conditions that the given currents of all parallel modules are equal and unequal and the operation conditions that the filter inductances of all inverters are equal and unequal.
In the invention, the zero sequence loop controller based on limited time adjustment has better zero sequence loop inhibition capability and stronger anti-interference capability than the traditional PI regulator.
Additional aspects of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention.
FIG. 1 is a circuit topology of a modular parallel low-cost three-level inverter according to an embodiment of the present invention;
FIG. 2 is a space vector diagram of a low-cost three-level inverter according to an embodiment of the present invention;
FIG. 3 is a block diagram of a control method according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a novel switching sequence of the control method in the sector 1 and the area a according to the first embodiment of the present invention;
FIG. 5 is a simulated waveform diagram of a "conventional PI regulator+conventional switching sequence" method for a given current magnitude equality;
FIG. 6 is a simulated waveform diagram of a control method according to a first embodiment of the present invention when given current amplitudes are equal;
FIG. 7 is a simulated waveform diagram of a control method according to a first embodiment of the present invention when given current amplitudes are equal;
FIG. 8 is a simulated waveform diagram of a "conventional PI regulator+conventional switching sequence" method when the given current magnitudes are not equal;
FIG. 9 is a simulated waveform diagram of a control method according to a first embodiment of the present invention when given current amplitudes are not equal;
FIG. 10 is a simulated waveform diagram of a control method according to a first embodiment of the present invention when given current amplitudes are not equal;
FIG. 11 is a simulated waveform diagram of a control method according to a first embodiment of the present invention when the given current amplitude of the first inverter increases from 30A step to 40A;
fig. 12 is a simulated waveform diagram of a control method according to the first embodiment of the present invention when the given current amplitude of the second inverter increases from 20A step to 30A.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present invention.
Embodiments of the invention and features of the embodiments may be combined with each other without conflict.
Example 1
The system structure of the modularized parallel low-cost three-level inverter is shown in fig. 1, and is formed by connecting two identical low-cost three-level inverters in parallel, wherein each low-cost three-level inverter comprises ten switching tubes, and the number of the switching tubes is further reduced compared with that of the traditional T-shaped three-level inverter. The DC side of the low-cost three-level inverter adopts a filter capacitor, and the output end of a three-phase bridge arm is connected into a power grid through the filter inductor to transmit high-quality electric energy to the power grid. The input end and the output end of the different low-cost three-level inverters are respectively connected together to realize system capacity expansion and improve system efficiency and reliability.
The system generally adopts a vector control scheme based on grid voltage orientation, a phase-locked loop (Phase Locked Loop, PLL) is used for detecting the grid voltage phase angle, and a current loop is used for realizing grid-connected current rapid and accurate tracking control.
Specifically, the first stage is lowThe cost three-level inverter includes two dc-side capacitors (C 11 ，C 21 ) Ten switch tubes (S) 11 ，S 21 ，…，S 101 ) And an output side filter. Wherein the connection point between the two direct-current side capacitors is the neutral point of the direct-current side, namely point O 1 。S 11 、S 21 、S 31 、S 41 The four switching tubes form a common switching unit through serial connection, S 51 、S 61 By series connection of a first group of independent switch units S 71 、S 81 By series connection of a second group of independent switch units S 91 、S 101 The third group of independent switch units is formed by series connection. S is S 11 Emitter junction S of (1) 21 、S 51 、S 71 、S 91 A collector electrode of (a); s is S 41 Is connected with the collector S 31 、S 61 、S 81 、S 101 An emitter of (a); s is S 11 Is connected with V dc Positive electrode of S 41 Emitter junction V of (1) dc Is a negative electrode of (a); s is S 21 Emitter, S of 31 The collector of (2) is connected with the neutral point of the DC side, namely point O 1 The method comprises the steps of carrying out a first treatment on the surface of the By inductance L 1 As an output side filter (R) 1 For its equivalent series resistance), i.e. three sets of inductances L 1 Respectively connected to S 51 Output terminal of (2) and S 61 A between input terminals 1 Point, S 71 Output terminal of (2) and S 81 B between input terminals 1 Point, S 91 Output terminal of (2) and S 101 C between input terminals 1 And (5) a dot.
The second low cost three level inverter includes two dc side capacitors (C 12 ，C 22 ) Ten switch tubes (S) 12 ，S 22 ，…，S 102 ) And an output side filter. Wherein the connection point between the two direct-current side capacitors is the neutral point of the direct-current side, namely point O 2 。S 12 、S 22 、S 32 、S 42 The four switching tubes form a common switching unit through serial connection, S 52 、S 62 By series connection of a first group of independent switch units S 72 、S 82 By series connection of a second group of independent switch units S 92 、S 102 The third group of independent switch units is formed by series connection. S is S 12 Emitter junction S of (1) 22 、S 52 、S 72 、S 92 A collector electrode of (a); s is S 42 Is connected with the collector S 32 、S 62 、S 82 、S 102 An emitter of (a); s is S 12 Is connected with V dc Positive electrode of S 42 Emitter junction V of (1) dc Is a negative electrode of (a); s is S 22 Emitter, S of 32 The collector of (2) is connected with the neutral point of the DC side, namely point O 2 The method comprises the steps of carrying out a first treatment on the surface of the By inductance L 2 As an output side filter (R) 2 For its equivalent series resistance), i.e. three sets of inductances L 2 Respectively connected to S 52 Emitter and S of (2) 61 A between the collectors 2 Point, S 72 Emitter and S of (2) 82 B between collector electrodes 2 Point, S 92 Emitter and S of (2) 102 C between emitters 2 And (5) a dot.
DC side neutral point O of first low-cost three-level inverter 1 Neutral point O on DC side of second low-cost three-level inverter 2 The output side of the first low-cost three-level inverter is connected with the output side of the second low-cost three-level inverter, and the switching on and off of each switching tube is realized based on a space vector modulation (Space Vector Modulation, SVM) method.
Wherein the switching tube refers to an insulated Gate bipolar transistor (insulator-Gate BipolarTransistor, IGBT); the switching tube can also be realized by adopting other types of transistors, and the switching tube can be specifically selected according to the actual requirements of those skilled in the art.
The embodiment provides a control method of modularized parallel low-cost three-level inverters, wherein direct-current side neutral points of all parallel low-cost three-level inverters are connected with each other, and the control method comprises the following steps:
determining a sector and a region where a reference voltage vector is located, selecting a basic voltage vector to synthesize the reference voltage vector, and calculating a small vector duty ratio initial value;
inputting the tracking error of the zero sequence loop current to a zero sequence loop current controller based on limited time adjustment to obtain a small vector duty ratio first distribution factor correction value;
the direct-current side capacitor voltage deviation of the low-cost three-level inverter is input to a midpoint voltage balance controller based on proportion adjustment, and a small vector duty ratio second distribution factor correction value is obtained;
correcting the small vector duty cycle according to the small vector duty cycle first distribution factor correction value, the small vector duty cycle second distribution factor correction value and the small vector duty cycle initial value;
and designing a switching sequence according to the corrected small vector duty ratio, the sector and the area where the reference voltage vector is located, and generating a corresponding PWM driving signal according to the designed switching sequence to control the on and off of the switching tube.
The switching states of a low cost three level inverter include three types: [ P ]]、[O]And [ N ]]. Under the condition of neutral point voltage balance, a direct current power supply V is selected dc The negative electrode (see FIG. 1) is used as a reference, when the switch state is [ P ]]When the bridge arm output voltage is V dc The method comprises the steps of carrying out a first treatment on the surface of the When the switch state is [ O ]]When the bridge arm output voltage is V dc 2; when the switch state is [ N ]]And when the bridge arm output voltage is 0.
The space vector diagram of the low-cost three-level inverter is shown in fig. 2, and the whole space vector diagram is divided into six sectors (i.e., sectors 1-6), each sector is further divided into two small areas (i.e., area a and area B), an outer area is defined as area a, and an inner area is defined as area B. The basic voltage vector, the switching state and the switching tube which is turned on are shown in table 1. It can be seen that the basic voltage vectors of the low cost three-level inverter include a large vector, a small vector, and a zero vector.
Table 1 basic voltage vector, switching state, and on-switching tube for low cost three level inverter
And judging the sector and the area where the reference voltage vector is located according to the amplitude and the phase angle of the reference voltage vector.
Without loss of generality, the basic voltage vector selection and duty cycle calculation method will be described by taking sector 1 and area a as examples. When the reference voltage vector is in sector 1 and area A, a large vector V is selected L1 [PNN]Large vector V L2 [PPN]Small vector V S1 [POO]/[ONN]And a small vector V S2 [PPO]/[OON]And synthesizing a reference voltage vector. According to the principle of volt-second equilibrium, it is possible to obtain:
wherein d L1 、d L2 、d S1 And d S2 Respectively large vectors [ PNN]Large vector [ PPN]Small vector [ POO ]]/[ONN]And small vector [ PPO ]]/[OON]Duty cycle of V ref Is the reference voltage vector.
When four basic voltage vectors synthesize a reference voltage vector, the duty ratio of each basic voltage vector cannot be directly calculated, so that the duty ratio of the basic voltage vector is solved by adopting an indirect calculation method. The expressions of the large vector [ PNN ], the large vector [ PPN ], the small vector [ POO ]/[ ONN ] and the small vector [ PPO ]/[ OON ] are respectively as follows:
substituting the expression of each basic voltage vector into a volt-second equilibrium equation and simplifying the equation to obtain:
where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively.
Small vector V S1 And a small vector V S2 The sum of the duty cycles is:
introducing a small vector duty cycle allocation factorWill d S1 And d S2 Expressed as:
consider the duty cycle d L1 And d L2 Constraint 0 of (2)<d L1 <1，0<d L2 <1, further obtain the partitioning factorThe constraint conditions of (2) are:
consider a small vector duty cycle allocation factorThe minimum and maximum values of (a) are respectively:
selecting allocation factorsFor its upper limit value->And lower limit value->Average value of (2), namely:
substituting the distribution factor given by the formula (9) into the expression of the duty ratio to obtain the initial value of the duty ratio of each basic voltage vector, wherein the initial value of the duty ratio of the small vector is:
wherein d s1p 、d s1n 、d s2p And d s2n Respectively represent basic voltage vectors [ POO ]]、[ONN]、[PPO]And [ OON ]]Is a duty cycle of (c).
The zero sequence circulation of the jth (j=1, 2) inverter is defined as the sum of its three-phase output currents, namely:
i zj ＝i aj +i bj +i cj (11)
in order to eliminate zero sequence circulation caused by unbalanced midpoint voltage, the neutral points of the DC sides of the inverters are connected together.
To achieve unity power factor operation, the q-axis current set point for each inverter is set to 0, namely:
fig. 3 is a control block diagram of the method of the present invention, including zero sequence loop current suppression, midpoint voltage balance control, small vector duty cycle allocation factor updating, and switching sequence design.
1. Construction of zero sequence circulation mathematical model
Selecting a direct-current power supply negative electrode N as a reference, and according to kirchhoff voltage law, a mathematical model of a j-th inverter is as follows:
wherein L is j 、R j Filtering of the j-th inverter respectivelyWave inductance and equivalent resistance thereof, u xj 、i xj (x=a, b, c) is the output voltage, output current, e, respectively, of the inverter x For the grid voltage u ON Is the voltage between the neutral point of the power grid and the negative electrode of the direct current power supply.
Adding the above formulas can obtain:
wherein u is zj And represents the zero sequence voltage of the j-th inverter.
When two inverters are connected in parallel, the zero sequence circulation amplitude values are equal and the directions are opposite, and the two inverters are:
under the neutral point voltage balance working condition, u zj The expressions in sector 1, region a are:
wherein d zj Represents the zero sequence duty cycle, d of the jth inverter L1j 、d L2j 、d S1pj 、d S1nj 、d S2pj And d S2nj Respectively represent the basic voltage vector [ PNN ] of the jth inverter]、[PPN]、[POO]、[ONN]、[PPO]And [ OON ]]Is a duty cycle of (c).
The relationship between the zero sequence circulation and the zero sequence duty ratio of the modularized parallel low-cost three-level inverter is as follows:
tracking error e=i z2_ref -i z2 As an input of the zero sequence circulation controller, the output y of the zero sequence circulation controller is used as a first distribution factor correction value of the small vector duty ratio of the first inverter and the second inverter, namely:
wherein d s12 Representing small vector [ POO ] in inverter 2]/[ONN]Is a duty cycle of (c).
To sum up, the zero sequence duty cycles of the first and second inverters in sector 1, region a can be expressed as:
the relationship between zero sequence circulation and zero sequence duty cycle of the modular parallel low cost three level inverter using the first division factor to modify the small vector duty cycle may be further expressed as:
2. zero sequence loop controller design and system stability analysis
The zero sequence loop current inhibition scheme based on the simplified limited time regulator is designed, and compared with the traditional PI regulator, the zero sequence loop current inhibition scheme has better zero sequence loop current inhibition capability and stronger anti-interference capability.
The error dynamic equation can be expressed as:
according to the finite time control theory, the simplified zero sequence circulation controller is designed as follows:
wherein sign (·) is a sign function, α 1 ∈[0,1]，
Substitution of formula (23) into formula (22) yields:
given the lyapunov function:
deriving equation (25) and substituting equation (24) into the derivative, taking k into account 1 Is defined by:
according to the finite time stability theory, the tracking error of the control variable y can be converged to zero in finite time.
In order to realize decoupling of zero sequence loop current inhibition and midpoint voltage balance control, the output of the zero sequence loop current controller is respectively applied to two inverters, and the duty ratio of each basic voltage vector in the sector 1 and the area A can be expressed as:
wherein d s1j And d s2j Respectively represent the small vectors [ POO ] in the j-th inverter]/[ONN]And small vector [ PPO ]]/[OON]Is a duty cycle of (c).
3. Neutral point voltage balance controller design
Sampling a capacitor C at the DC side of the first inverter 11 And C 21 The voltage at two ends calculates the deviation of the voltage of two capacitors and sends the deviation to a proportion regulator to obtain a small vectorThe second distribution factor correction value y of the quantity duty cycle np The method comprises the following steps:
y np ＝k np (V C1 -V C2 ) (29)
wherein V is C1 And V C2 Respectively the capacitance C 11 And C 21 Voltage across the two terminals, k np Is the coefficient of the proportioner.
And further distributing the second distribution factor correction value obtained by the midpoint voltage controller to the duty ratios of the P-type and N-type small vectors to realize midpoint balance control, namely:
4. small vector duty cycle correction
For a modularized parallel low-cost three-level inverter system, zero sequence loop current inhibition and midpoint voltage balance control are realized by adjusting the duty ratio of small vectors, namely:
to ensure that the small vector duty cycle is greater than 0, the total adjustment of the first and second split factors should be limited to between-1 and 1, and the scaling factors α and β are introduced such that:
wherein alpha+beta < 1.
To sum up, each inverter updates the small vector duty cycle allocation factor in sector 1, region a as:
and designing a switching sequence based on the duty ratio of the updated basic vector and the sector and area where the reference voltage vector is located, converting the switching sequence into a PWM driving signal of a switching tube, and controlling the operation of the modularized parallel low-cost three-level inverter system.
5. Novel switch sequence design
The instantaneous zero Sequence voltages (Instantaneous Zero-Sequence Voltage, IZSV) defining the base Voltage vector are:
the instantaneous zero sequence voltages of the individual basic voltage vectors are shown in table 2, it can be seen that: the small vectors have redundant states, and the P-type and N-type small vectors generate the same line voltage, but the corresponding instantaneous zero sequence voltages are different.
TABLE 2 IZSV of Low cost three level inverter base Voltage vector
An average Zero-Sequence Voltage (AZSV) is defined as an average value of Zero-Sequence voltages in one switching cycle. When the space vector modulation method is adopted, the average zero sequence voltage difference of each inverter induces zero sequence circulation. By adjusting the duty ratio of the small vector, the AZSV of the two inverters can be the same, thereby realizing zero sequence circulation suppression.
The traditional switch sequence design method takes a large vector as a switch sequence initial vector, and the reference voltage vector generates sector switching to cause zero sequence loop peak, which is due to the fact that IZSV of the initial large vector is different. For this purpose, the inventive method designs a novel switching sequence (see fig. 4) to eliminate zero sequence loop current spikes caused by sector switching. Specifically, nine-segment or eleven-segment switching sequences are designed to improve the output waveform quality. The switching sequence specifically comprises:
when the reference voltage vector is located in region a within sector 1, the switching sequence is designed as follows:
[ONN]-[OON]-[PNN]-[PPN]-[POO]-[PPO]-[POO]-[PPN]-[PNN]-[OON]-[ONN]；
when the reference voltage vector is located in region B within sector 1, the switching sequence is designed as follows:
[ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN]；
when the reference voltage vector is located in region a within sector 2, the switching sequence is designed as follows:
[NON]-[OON]-[NPN]-[PPN]-[OPO]-[PPO]-[OPO]-[PPN]-[NPN]-[OON]-[NON]；
when the reference voltage vector is located in region B within sector 2, the switching sequence is designed as follows:
[NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON]；
when the reference voltage vector is located in region a within sector 3, the switching sequence is designed as follows:
[NON]-[NOO]-[NPN]-[NPP]-[OPO]-[OPP]-[OPO]-[NPP]-[NPN]-[NOO]-[NON]；
when the reference voltage vector is located in region B within sector 3, the switching sequence is designed as follows:
[NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON]；
when the reference voltage vector is located in region a within sector 4, the switching sequence is designed as follows:
[NNO]-[NOO]-[NNP]-[NPP]-[OOP]-[OPP]-[OOP]-[NPP]-[NNP]-[NOO]-[NNO]；
when the reference voltage vector is located in region B within sector 4, the switching sequence is designed as follows:
[NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO]；
when the reference voltage vector is located in region a within sector 5, the switching sequence is designed as follows:
[NNO]-[ONO]-[NNP]-[PNP]-[OOP]-[POP]-[OOP]-[PNP]-[NNP]-[ONO]-[NNO]；
when the reference voltage vector is located in region B within sector 5, the switching sequence is designed as follows:
[NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO]；
when the reference voltage vector is located in region a within sector 6, the switching sequence is designed as follows:
[ONN]-[ONO]-[PNN]-[PNP]-[POO]-[OPO]-[POO]-[PNP]-[PNN]-[OON]-[ONN]；
when the reference voltage vector is located in region B within sector 6, the switching sequence is designed as follows:
[ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN]。
when the reference voltage vector is switched in the sector, the IZSV of the initial small vector in the switching sequence is the same, and in each switching period, the IZSV has the same change rule (i.e. V dc /6→V dc /3→2V dc /3→5V dc /6→2V dc /3→V dc /3→V dc /6). Therefore, the novel switching sequence can effectively eliminate zero sequence loop current peak.
To increase the dc voltage utilization, the system is typically operated in a high modulation mode, i.e., the reference voltage vector is located in region a of each sector. Therefore, only the simulation waveform at the modulation degree of 0.8 is given.
Fig. 5 is a simulated waveform diagram of a "conventional PI regulator + conventional switching sequence" method for a given current magnitude equality, including a first inverter three-phase output current (i a1 、i b1 、i c1 ) Zero sequence circulation (i) z1 ) And the three-phase output current (i) of the second inverter a2 、i b2 、i c2 ). Because the zero sequence circulation amplitudes of the first inverter and the second inverter are equal and opposite, only the zero sequence circulation of the first inverter is given. At this time, THD i1 And THD (total heat transfer) i2 2.73% and 1.88% respectively, but with zero sequence loop peak, the amplitude is as high as 3A.
FIGS. 6 and 7 show the process of the present inventionGiven a simulated waveform of equal current amplitude, including the line voltage (V) ab1 ) Three-phase output current (i) a1 、i b1 、i c1 ) Zero sequence circulation (i) z1 ) Capacitance voltage (V) C1 、V C2 ) Line voltage (V) of the second inverter ab2 ) Three-phase output current (i) a2 、i b2 、i c2 ). At this time, the two capacitor voltages at the direct current side are equal, the method realizes the balance control of the midpoint voltage, the line voltage of each inverter is in a five-level waveform, and the THD is realized V1 And THD (total heat transfer) V2 58.27% and 58.36% respectively. As can be seen by comparing fig. 5 and 6: compared with the method of the traditional PI regulator and the traditional switching sequence, the method of the invention can eliminate zero sequence loop current peak and THD i1 And THD (total heat transfer) i2 The output current waveform quality is obviously improved by respectively reducing the output current waveform quality to 2.45 percent and 1.84 percent.
FIG. 8 is a simulated waveform diagram of a "conventional PI regulator+conventional switching sequence" method for a given current magnitude imbalance, including a first inverter three-phase output current (i a1 、i b1 、i c1 ) Zero sequence circulation (i) z1 ) And the three-phase output current (i) of the second inverter a2 、i b2 、i c2 ). THD at this time i1 And THD (total heat transfer) i2 2.71% and 3.62% respectively, but there is a zero sequence loop peak with amplitude of 3A.
Fig. 9 and 10 are simulated waveforms of the method of the present invention when given currents are unequal, including the line voltage (V ab1 ) Three-phase output current (i) a1 、i b1 、i c1 ) Zero sequence circulation (i) z1 ) Capacitance voltage (V) C1 、V C2 ) And the line voltage (V) of the second inverter ab2 ) Three-phase output current (i) a2 、i b2 、i c2 ). At this time, the two capacitor voltages at the direct current side are equal, the method realizes the balance control of the midpoint voltage, the line voltage of each inverter is in a five-level waveform, and the THD is realized V1 And THD (total heat transfer) V2 58.41% and 58.74% respectively. As can be seen by comparing fig. 7 and 8: and the 'traditional PI regulator + traditional switching sequence' squareCompared with the method, the method of the invention can eliminate zero sequence loop peak and THD i1 And THD (total heat transfer) i2 Respectively to 2.53% and 3.34%. The method is suitable for the working conditions of equal and unequal current amplitudes, and has obvious advantages.
FIG. 11 is a simulated waveform of the method of the present invention for a given current imbalance and a step increase in the magnitude of a given current in a first inverter, including the three-phase output current (i) a1 、i b1 、i c1 ) Zero sequence circulation (i) z1 ) And the three-phase output current (i) of the second inverter a2 、i b2 、i c2 ). When t=0.34 s, the given current amplitude of the second inverter is increased from 30A step to 40A, zero sequence circulation is not changed obviously, and the inverter parallel system operates normally.
FIG. 12 is a simulated waveform of the method of the present invention for a given current imbalance and a step increase in the magnitude of a given current in a second inverter, including the three-phase output current (i) from the first inverter a1 、i b1 、i c1 ) Zero sequence circulation (i) z1 ) And the three-phase output current (i) of the second inverter a2 、i b2 、i c2 ). When t=0.34 s, the given current amplitude of the second inverter is increased from 20A step to 30A, zero sequence circulation does not change obviously, the inverter works normally, namely the method is suitable for inhibiting zero sequence circulation under the dynamic condition.
Example two
An object of the present embodiment is to provide a control system of a modularized parallel low-cost three-level inverter, in which dc-side neutral points of the parallel low-cost three-level inverters are connected to each other, comprising:
a small vector duty cycle initial value calculation module configured to: determining a sector and a region where a reference voltage vector is located, selecting a basic voltage vector to synthesize the reference voltage vector, and calculating a small vector duty ratio initial value;
a small vector duty cycle first division factor correction value determination module configured to: inputting the tracking error of the zero sequence loop current to a zero sequence loop current controller based on limited time adjustment to obtain a small vector duty ratio first distribution factor correction value;
a small vector duty cycle second division factor correction value determination module configured to: the direct-current side capacitor voltage deviation of the low-cost three-level inverter is input to a midpoint voltage balance controller based on proportion adjustment, and a small vector duty ratio second distribution factor correction value is obtained;
a small vector duty cycle correction module configured to: correcting the small vector duty cycle according to the small vector duty cycle first distribution factor correction value, the small vector duty cycle second distribution factor correction value and the small vector duty cycle initial value;
PWM drive control module: and designing a switching sequence according to the corrected small vector duty ratio, the sector and the area where the reference voltage vector is located, and generating a corresponding PWM driving signal according to the designed switching sequence to control the on and off of the switching tube.
Example III
It is an object of the present embodiment to provide a computing device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the steps of the method described above when executing the program.
Example IV
The present embodiment provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor performs the steps of the above method.
The steps involved in the devices of the second, third and fourth embodiments correspond to those of the first embodiment of the method, and the detailed description of the embodiments can be found in the related description section of the first embodiment. The term "computer-readable storage medium" should be taken to include a single medium or multiple media including one or more sets of instructions; it should also be understood to include any medium capable of storing, encoding or carrying a set of instructions for execution by a processor and that cause the processor to perform any one of the methods of the present invention.
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented by general-purpose computer means, alternatively they may be implemented by program code executable by computing means, whereby they may be stored in storage means for execution by computing means, or they may be made into individual integrated circuit modules separately, or a plurality of modules or steps in them may be made into a single integrated circuit module. The present invention is not limited to any specific combination of hardware and software.
While the foregoing description of the embodiments of the present invention has been presented in conjunction with the drawings, it should be understood that it is not intended to limit the scope of the invention, but rather, it is intended to cover all modifications or variations within the scope of the invention as defined by the claims of the present invention.

Claims (10)

1. A control method of modular parallel low-cost three-level inverters, characterized in that dc-side neutral points of each parallel low-cost three-level inverter are connected to each other, the control method comprising:
determining a sector and a region where a reference voltage vector is located, selecting a basic voltage vector to synthesize the reference voltage vector, and calculating a small vector duty ratio initial value;
inputting the tracking error of the zero sequence loop current to a zero sequence loop current controller based on limited time adjustment to obtain a small vector duty ratio first distribution factor correction value;
the direct-current side capacitor voltage deviation of the low-cost three-level inverter is input to a midpoint voltage balance controller based on proportion adjustment, and a small vector duty ratio second distribution factor correction value is obtained;
correcting the small vector duty cycle according to the small vector duty cycle first distribution factor correction value, the small vector duty cycle second distribution factor correction value and the small vector duty cycle initial value;
and designing a switching sequence according to the corrected small vector duty ratio, the sector and the area where the reference voltage vector is located, and generating a corresponding PWM driving signal according to the designed switching sequence to control the on and off of the switching tube.
2. The method for controlling a modular parallel low-cost three-level inverter according to claim 1, wherein the calculation of the initial value of the small vector duty cycle is specifically:
substituting the phase angles of the basic voltage vector expression and the reference voltage vector into a volt-second balance equation to obtain the sum of small vector duty ratios;
introducing a small vector duty ratio distribution factor, and obtaining a small vector duty ratio expression according to the sum of the small vector duty ratios;
determining the maximum value and the minimum value of the small vector duty cycle allocation factor according to the constraint condition of the large vector duty cycle and the limiting condition of the small vector duty cycle allocation factor;
selecting the average value of the maximum value and the minimum value of the small vector duty ratio distribution factors as the small vector duty ratio distribution factor value;
substituting the obtained small vector duty ratio distribution factor value into a small vector duty ratio expression to obtain a small vector duty ratio initial value.
3. The method of claim 1, wherein the dc side capacitor voltage deviation of the low cost three level inverter is multiplied by a scaling factor to obtain the small vector duty cycle second division factor correction value.
4. A method of controlling a modular parallel low cost three level inverter according to claim 1, wherein the zero sequence loop controller based on finite time adjustment is:
wherein sign (·) is a sign function, k 1 Is the parameter of the zero sequence circulation controller, alpha 1 ∈[0,1]Y is the output of the zero sequence loop controller, and e (t) is the tracking error between the set value and the measured value of the zero sequence loop.
5. The method for controlling a modular parallel low-cost three-level inverter according to claim 4, wherein the small-vector duty cycle first distribution factor correction value is applied to each low-cost three-level inverter to obtain the small-vector duty cycle corrected by each low-cost three-level inverter based on the small-vector duty cycle first distribution factor correction value for the purpose of achieving zero-sequence loop current suppression and neutral-point voltage balance control decoupling.
6. The method for controlling a modular parallel low-cost three-level inverter according to claim 1, wherein the designed switching sequence is specifically:
when the reference voltage vector is located in the outer region a within sector 1, the switching sequence is designed as follows:
[ONN]-[OON]-[PNN]-[PPN]-[POO]-[PPO]-[POO]-[PPN]-[PNN]-[OON]-[ONN]；
when the reference voltage vector is located in the inner region B within sector 1, the switching sequence is designed as follows:
[ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN]；
when the reference voltage vector is located in the outer region a within sector 2, the switching sequence is designed as follows:
[NON]-[OON]-[NPN]-[PPN]-[OPO]-[PPO]-[OPO]-[PPN]-[NPN]-[OON]-[NON]；
when the reference voltage vector is located in the inner region B within sector 2, the switching sequence is designed as follows:
[NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON]；
when the reference voltage vector is located in the outer region a within sector 3, the switching sequence is designed as follows:
[NON]-[NOO]-[NPN]-[NPP]-[OPO]-[OPP]-[OPO]-[NPP]-[NPN]-[NOO]-[NON]；
when the reference voltage vector is located in the inner region B within sector 3, the switching sequence is designed as follows:
[NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON]；
when the reference voltage vector is located in the outer region a within sector 4, the switching sequence is designed as follows:
[NNO]-[NOO]-[NNP]-[NPP]-[OOP]-[OPP]-[OOP]-[NPP]-[NNP]-[NOO]-[NNO]；
when the reference voltage vector is located in the inner region B within the sector 4, the switching sequence is designed as follows:
[NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO]；
when the reference voltage vector is located in the outer region a within sector 5, the switching sequence is designed as follows:
[NNO]-[ONO]-[NNP]-[PNP]-[OOP]-[POP]-[OOP]-[PNP]-[NNP]-[ONO]-[NNO]；
when the reference voltage vector is located in the inner region B within the sector 5, the switching sequence is designed as follows:
[NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO]；
when the reference voltage vector is located in the outer region a within sector 6, the switching sequence is designed as follows:
[ONN]-[ONO]-[PNN]-[PNP]-[POO]-[OPO]-[POO]-[PNP]-[PNN]-[OON]-[ONN]；
when the reference voltage vector is located in the inner region B within the sector 6, the switching sequence is designed as follows:
[ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN]。
7. the method of claim 6, wherein when the reference voltage is sector switched, the instantaneous zero sequence voltages of the initial small vectors in the switching sequence are the same, and the instantaneous zero sequence voltages of the basic voltage vectors have the same change rule in each switching cycle.
8. A control system for modular parallel low-cost three-level inverters, wherein dc-side neutral points of each parallel low-cost three-level inverter are connected to each other, comprising:
a small vector duty cycle initial value calculation module configured to: determining a sector and a region where a reference voltage vector is located, selecting a basic voltage vector to synthesize the reference voltage vector, and calculating a small vector duty ratio initial value;
a small vector duty cycle first division factor correction value determination module configured to: inputting the tracking error of the zero sequence loop current to a zero sequence loop current controller based on limited time adjustment to obtain a small vector duty ratio first distribution factor correction value;
a small vector duty cycle second division factor correction value determination module configured to: the direct-current side capacitor voltage deviation of the low-cost three-level inverter is input to a midpoint voltage balance controller based on proportion adjustment, and a small vector duty ratio second distribution factor correction value is obtained;
a small vector duty cycle correction module configured to: correcting the small vector duty cycle according to the small vector duty cycle first distribution factor correction value, the small vector duty cycle second distribution factor correction value and the small vector duty cycle initial value;
PWM drive control module: and designing a switching sequence according to the corrected small vector duty ratio, the sector and the area where the reference voltage vector is located, and generating a corresponding PWM driving signal according to the designed switching sequence to control the on and off of the switching tube.
9. A computer device, comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory in communication via the bus when the computer device is running, the machine-readable instructions when executed by the processor performing a method of controlling a modular parallel low cost three level inverter as claimed in any one of claims 1 to 7.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs a method of controlling a modular parallel low cost three level inverter according to any of claims 1 to 7.
CN202310785899.1A 2023-06-29 2023-06-29 Control method and system for modularized parallel low-cost three-level inverter Pending CN116865585A (en)

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