CN116864524A - Transistor with asymmetric structure and manufacturing method thereof - Google Patents

Transistor with asymmetric structure and manufacturing method thereof Download PDF

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Publication number
CN116864524A
CN116864524A CN202310812142.7A CN202310812142A CN116864524A CN 116864524 A CN116864524 A CN 116864524A CN 202310812142 A CN202310812142 A CN 202310812142A CN 116864524 A CN116864524 A CN 116864524A
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gate
layer
silicon wafer
length
doped region
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申靖浩
李南照
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Shenzhen Yucan Technology Co ltd
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Shenzhen Yucan Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application relates to the technical field of transistors, in particular to a transistor with an asymmetric structure, which comprises the following steps: a silicon wafer, and a gate structure, a source structure, and a drain structure disposed on the silicon wafer, with the gate structure between the source structure and the drain structure; the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, wherein the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is larger than the length of the first gate layer. The transistor realizes an asymmetric structure, simplifies an impurity injection process in a manufacturing process, forms a refined transistor, achieves the high-voltage characteristic of the transistor, and can also meet the manufacturing requirement of an SOC semiconductor.

Description

Transistor with asymmetric structure and manufacturing method thereof
Technical Field
The present application relates to the field of transistor technologies, and in particular, to a transistor with an asymmetric structure and a method for manufacturing the same.
Background
Transistors have various functions such as detection, rectification, amplification, switching, voltage regulation, signal modulation, etc., and are used for various digital and analog functions, so that transistors are also used in various industries. In order to realize transistors with different characteristics, in the existing scheme, impurities with the concentration corresponding to the characteristics are injected into a substrate by adopting an impurity injection process corresponding to the characteristics of the transistors to form a layer in the process of manufacturing the transistors with different characteristics, so that the transistors are manufactured, the characteristic effect of the transistors is achieved, and different voltages of the transistors are realized.
Therefore, the existing scheme aims at the manufacturing process of the transistor, and the impurity injection process needs to be strictly controlled, so that the problem of low manufacturing efficiency of the transistor is caused.
Disclosure of Invention
The transistor with the asymmetric structure and the manufacturing method thereof solve the technical problem of low manufacturing efficiency of the transistor in the prior art, and realize the technical effects of simplifying the impurity injection process in the manufacturing process of the transistor, quickly forming the transistor, achieving the high-voltage characteristic of the transistor, improving the manufacturing efficiency of the transistor, meeting the manufacturing requirements of SOC (SystemOnaChip) semiconductors and the like through the asymmetric structure of the transistor.
In a first aspect, an embodiment of the present application provides a transistor having an asymmetric structure, including:
a silicon wafer, and a gate structure, a source structure, and a drain structure disposed on the silicon wafer, with the gate structure between the source structure and the drain structure;
the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, wherein the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is larger than the length of the first gate layer.
Preferably, the gate structure further includes: the insulation film layer is positioned above the silicon wafer, the insulation film layer is positioned below a designated area of the second gate layer, and the insulation film layer is positioned on one side of the first gate layer, wherein the designated area is an area where the second gate layer is not contacted with the first gate layer, the sum of the length of the first gate layer and the length of the insulation film layer is equal to the length of the second gate layer, and the thickness of the insulation film layer is equal to the sum of the thickness of the first gate layer and the thickness of the gate oxide layer.
Preferably, the gate structure further includes: a silicon source layer, a first gate sidewall and a second gate sidewall, the silicon source layer being located over the second gate layer;
the first gate side wall is positioned above the silicon wafer and on the same side of the gate oxide layer, the first gate layer and the second gate layer, wherein the thickness of the first gate side wall is not smaller than the sum of the thickness of the gate oxide layer, the thickness of the first gate layer and the thickness of the second gate layer;
the second gate side wall is located on the silicon wafer and located on the same side of the insulating film layer and the second gate layer, wherein the thickness of the second gate side wall is not smaller than the sum of the thickness of the insulating film layer and the thickness of the second gate layer, and the length of the first gate side wall is consistent with the length of the second gate side wall.
Preferably, the source structure includes: a first active layer, a first heavily doped region and a first doped region; the first doped region; the first doped region is positioned in the silicon wafer, is positioned at one side of the grid structure and is positioned in a region corresponding to the side wall of the first grid; the first heavily doped region is positioned in the upper surface of the silicon wafer, in the first doped region and at one side of the gate structure; the first active layer is located above the first heavily doped region.
Preferably, the drain structure includes: a second active layer, a second heavily doped region and a second doped region; the second doped region is positioned in the silicon wafer, on the other side of the grid structure, and in the region corresponding to the side wall of the second grid and the insulating film layer; the second heavily doped region is positioned in the upper surface of the silicon wafer, in the second doped region and on the other side of the gate structure; the second active layer is located over the second heavily doped region.
Based on the same inventive concept, the present application also provides a method of manufacturing a transistor having an asymmetric structure, including:
forming a gate structure on a silicon wafer, wherein the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is greater than the length of the first gate layer;
and forming a source electrode structure and a drain electrode structure on two sides of the gate electrode structure respectively.
Preferably, in the process of forming the gate structure on the silicon wafer, the method further includes:
forming an insulating film above the silicon wafer and below a designated area of the second gate layer and on one side of the first gate layer, wherein the designated area is an area where the second gate layer is not in contact with the first gate layer, the sum of the length of the first gate layer and the length of the insulating film layer is equal to the length of the second gate layer, and the thickness of the insulating film layer is equal to the sum of the thickness of the first gate layer and the thickness of the gate oxide layer.
Preferably, in the process of forming the gate structure on the silicon wafer, the method further includes:
forming a first gate sidewall on the silicon wafer and on the same side of the gate oxide layer, the first gate layer and the second gate layer, wherein the thickness of the first gate sidewall is not less than the sum of the thickness of the gate oxide layer, the thickness of the first gate layer and the thickness of the second gate layer;
and forming a second gate side wall on the silicon wafer and on the same side of the insulating film layer and the second gate layer, wherein the thickness of the second gate layer side wall is not smaller than the sum of the thickness of the insulating film layer and the thickness of the second gate layer, and the length of the first gate side wall is consistent with the length of the second gate side wall.
Preferably, in the process of forming the source electrode structure, the method further includes:
forming a first doped region in the silicon wafer at one side of the gate structure and in a region corresponding to the side wall of the first gate;
forming a first heavily doped region in the first doped region and on one side of the gate structure on the upper surface of the silicon wafer;
a first active layer is formed over the first heavily doped region.
Preferably, in the process of forming the drain structure, the method further includes:
forming a second doping region in the silicon wafer at the other side of the gate structure and in a region corresponding to the second gate side wall and the insulating film layer;
forming a second heavily doped region on the upper surface of the silicon wafer in the second doped region and on the other side of the gate structure;
a second active layer is formed over the second heavily doped region.
One or more technical solutions in the embodiments of the present application at least have the following technical effects or advantages:
the embodiment of the application provides a transistor with an asymmetric structure, which comprises the following components: a silicon wafer, and a gate structure, a source structure, and a drain structure disposed on the silicon wafer, with the gate structure between the source structure and the drain structure; the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, wherein the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is larger than the length of the first gate layer. Therefore, the gate structure realizes an asymmetric structure through inconsistent lengths of the first gate layer and the second gate layer, can realize any asymmetric structure and the distance between the source electrode and the drain electrode by randomly adjusting the length difference of the first gate layer and the second gate layer, ensures the high-voltage characteristic of the transistor, can also meet the semiconductor manufacturing requirement of the SOC, and achieves the effects of refining the transistor structure, reducing the size of a transistor device and the like.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also throughout the drawings, like reference numerals are used to designate like parts. In the drawings:
fig. 1 shows a schematic structural diagram of a transistor having an asymmetric structure in an embodiment of the present application;
fig. 2 is a schematic structural diagram showing a distance from a gate structure to a source structure and a distance from a gate structure to a drain structure in an embodiment of the present application;
fig. 3 is a schematic view showing a structure of a field region forming a transistor in an embodiment of the present application;
fig. 4 is a schematic diagram showing a structure of a gate oxide layer and a first gate layer forming a transistor in an embodiment of the present application;
fig. 5 shows a schematic structural diagram of a first doped region and a second doped region forming a transistor in an embodiment of the present application;
fig. 6 is a schematic view showing the structure of an insulating film layer and a second gate layer forming a transistor in the embodiment of the present application;
fig. 7 is a schematic structural diagram of forming a first gate sidewall, a second gate sidewall, a first heavily doped region, and a second heavily doped region of a transistor in an embodiment of the present application;
fig. 8 is a schematic step flow diagram of a method for manufacturing a transistor having an asymmetric structure according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example 1
A first embodiment of the present application provides a transistor having an asymmetric structure, as shown in fig. 1, including: a silicon wafer 110, and a gate structure 120, a source structure 130, and a drain structure 140 disposed on the silicon wafer 110, with the gate structure 120 between the source structure 130 and the drain structure 140;
the gate structure 120 includes a gate oxide layer 121, a first gate layer 122 and a second gate layer 123, the gate oxide layer 121 is located above the silicon wafer 110, the first gate layer 122 is located above the gate oxide layer 121, the second gate layer 123 is located above the first gate layer 122, wherein a length of the first gate layer 122 is consistent with a length of the gate oxide layer 121, and a length of the second gate layer 123 is greater than a length of the first gate layer 122.
It should be noted that the material of the silicon wafer 110 includes, but is not limited to, monocrystalline silicon or polycrystalline silicon. The gate structure 120 includes a gate oxide layer 121, a first gate layer 122 and a second gate layer 123, wherein the material of the gate oxide layer 121 includes, but is not limited to, silicon dioxide, silicon oxynitride, hafnium oxide or a high-K material or a low-K material according to practical requirements, and K is the dielectric constant of the material. The material of the first gate layer 122 and the material of the second gate layer 123 include, but are not limited to, polysilicon or metal-based materials, and the material of the first gate layer 122 is the same as the material of the second gate layer 123. The thickness of the gate oxide layer 121, the thickness of the first gate layer 122 and the thickness of the second gate layer 123 may be set according to practical requirements.
The gate structure 120 further includes: the insulating film 124 is made of an electrically insulating material, and the diagonal grid shown in fig. 1 is the insulating film 124. The insulating film layer 124 is located above the silicon wafer 110, the insulating film layer 124 is located below a designated area of the second gate layer 123, and the insulating film layer 124 is located at one side of the first gate layer 122, wherein the designated area is an area where the second gate layer 123 is not in contact with the first gate layer 122, a sum of a length of the first gate layer 122 and a length of the insulating film layer 124 is equal to a length of the second gate layer 123, and a thickness of the insulating film layer 124 is equal to a sum of a thickness of the first gate layer 122 and a thickness of the gate oxide layer 121.
The gate structure 120 further includes: a silicon source layer 125, a first gate sidewall 126, and a second gate sidewall 127. The silicon source layer 125 is located above the second gate layer 123. The first gate sidewall 126 is located above the silicon wafer 110 and on the same side of the gate oxide layer 121, the first gate layer 122 and the second gate layer 123, wherein the thickness of the first gate sidewall 126 is not less than the sum of the thickness of the gate oxide layer 121, the thickness of the first gate layer 122 and the thickness of the second gate layer 123. The second gate sidewall 127 is located on the silicon wafer 110 and on the same side of the insulating film layer 124 and the second gate layer 123, wherein the thickness of the second gate layer 123 sidewall is not less than the sum of the thickness of the insulating film layer 124 and the thickness of the second gate layer 123, and the length of the first gate sidewall 126 is identical to the length of the second gate sidewall 127.
It should be noted that the material of the first gate sidewall 126 and the material of the second gate sidewall 127 may be the same as or different from the material of the insulating film, and the material of the first gate sidewall 126 and the material of the second gate sidewall 127 are both electrically insulating materials. The material of the silicon source layer 125 includes, but is not limited to, polysilicon or various films that may be used as the gate structure 120.
As shown in fig. 1, one end of the gate oxide layer 121 and one end of the first gate layer 122 are aligned with one end of the second gate layer 123, and since the length of the second gate layer 123 is greater than that of the first gate layer 122 and the length of the first gate layer 122 is identical to that of the gate oxide layer 121, the second gate layer 123 completely covers the first gate layer 122 and the gate oxide layer 121. The insulating film layer 124 is located above the silicon wafer 110 and below a designated area of the second gate layer 123, and the insulating film layer 124 is located at the other end of the first gate layer 122 and at the other end of the gate oxide layer 121, and the sum of the length of the first gate layer 122 and the length of the insulating film layer 124 is equal to the length of the second gate layer 123, meaning that the length remaining from the length of the second gate layer 123 excluding the length of the first gate layer 122 is the length of the insulating film layer 124. And, the thickness of the insulating film layer 124 is equal to the sum of the thickness of the first gate layer 122 and the thickness of the gate oxide layer 121.
A silicon source layer 125 is located over the second gate layer 123. The first gate sidewall 126 serves as one side of the gate structure 120 and the second gate sidewall 127 serves as the other side of the gate structure 120. The first gate sidewall 126 is located on the silicon wafer 110 and is located at the same end of the gate oxide layer 121, the first gate layer 122, the second gate layer 123 and the silicon source layer 125, which means that the first gate sidewall 126 is located at one end of the gate oxide layer 121, one end of the first gate layer 122, one end of the second gate layer 123 and one end of the silicon source layer 125. The second gate sidewall 127 is located on the silicon wafer 110 and is located at the same end of the insulating film layer 124, the second gate layer 123 and the silicon source layer 125, which means that the second gate sidewall 127 is located at one end of the insulating film layer 124, the other end of the second gate layer 123 and the other end of the silicon source layer 125.
Since the insulating film layer 124 is present in the gate structure 120 of the present embodiment, and the insulating film layer 124 is located under the designated area of the second gate layer 123, above the silicon wafer 110 and on one side of the first gate layer 122 based on the position structure of the insulating film layer 124, i.e. the length of the second gate layer 123 is greater than the length of the first gate layer 122, the gate structure 120 of the present embodiment forms an asymmetric structure. As shown in fig. 2, the length of the first gate sidewall 126 is denoted as a, the length of the second gate sidewall 127 is also denoted as a, and the length of the insulating film 124 is denoted as B. The distance W1 from the source structure 130 to the gate structure 120 of the present embodiment is equal to the length a of the first gate sidewall 126, i.e. w1=a; the distance W2 from the drain structure 140 to the gate structure 120 is equal to the sum of the length of the second gate sidewall 127 and the length of the insulating film layer 124, i.e., w2=a+b. Since W1 and W2 are not identical, the gate structure 120 or the transistor of the present embodiment forms an asymmetric structure. Therefore, by the gate structure 120 of the present embodiment, any asymmetric structure and the distance between the source and the drain can be realized, the high voltage characteristic of the transistor can be ensured, the semiconductor manufacturing requirement of the SOC can be satisfied, and the effects of refining the transistor structure, reducing the size of the transistor device and the like can be achieved.
The source structure 130 includes: a first active layer 131, a first heavily doped region 132, and a first doped region 133; the first doped region 133; the first doped region 133 is located in the silicon wafer 110, on one side of the gate structure 120, and in a region corresponding to the first gate sidewall 126; the first heavily doped region 132 is located in the upper surface of the silicon wafer 110, in the first doped region 133, and on one side of the gate structure 120; the first active layer 131 is located above the first heavily doped region 132.
The drain structure 140 includes: a second active layer 141, a second heavily doped region 142, and a second doped region 143; the second doped region 143 is located in the silicon wafer 110 and on the other side of the gate structure 120, and is located in a region corresponding to the second gate sidewall 127 and the insulating film layer 124; the second heavily doped region 142 is located in the upper surface of the silicon wafer 110 and in the second doped region 143 and on the other side of the gate structure 120; the second active layer 141 is located over the second heavily doped region 142.
It should be noted that, the first doped region 133 and the second doped region 143 are formed by implanting dopants into the silicon wafer 110 at both sides of the gate oxide layer 121, and thus, the region of the first doped region 133 is a region in the silicon wafer 110 corresponding to one side of the gate structure 120 and the first gate sidewall 126, and the region of the second doped region 143 is a region in the silicon wafer 110 corresponding to the other side of the gate structure 120, the second gate sidewall 127 and the insulating film layer 124. Since the first doped region 133 is implanted with the dopant having a higher concentration after the first doped region 133 is formed, the first heavily doped region 132 is formed in the first doped region 133, and the ion concentration of the first heavily doped region 132 is greater than that of the first doped region 133. Similarly, since the dopant with higher concentration is implanted into the second doped region 143 after the second doped region 143 is formed, the second heavily doped region 142 is formed in the second doped region 143, and the ion concentration of the second heavily doped region 142 is greater than that of the second doped region 143. The dopant concentration of the first doped region 133 is consistent with the dopant concentration of the second doped region 143, and the dopant concentration of the first heavily doped region 132 is consistent with the dopant concentration of the second heavily doped region 142. The material of the first active layer 131 includes, but is not limited to, polysilicon or other film materials. The material of the second active layer 141 includes, but is not limited to, polysilicon or other film materials. The material of the first active layer 131 may be the same as or different from the material of the second active layer 141.
The transistor of this embodiment further includes a field region 150 formed by a shallow trench isolation process, the field region being located at the periphery of the entire transistor. Firstly forming a groove through a shallow groove isolation process, and then filling isolation materials into the groove to form a field region.
In the present embodiment, the transistor of the present embodiment is formed into an asymmetric structure by forming an insulating film under a designated region of the second gate layer 123 in the gate structure 120 and on one side of the first gate layer 122 and the gate oxide layer 121, the sum of the length of the insulating film and the length of the first gate layer 122 being equal to the length of the second gate layer 123. Through the transistor with the asymmetric structure, any asymmetric structure and the distance between the source electrode and the drain electrode can be realized, the effects of refining the transistor structure, reducing the size of a transistor device and the like are achieved, the transistor is rapidly formed, the high-voltage characteristic of the transistor is achieved, the manufacturing efficiency of the transistor is improved, and the SOC (SystemOnaChip) semiconductor manufacturing requirement can be met.
Next, a manufacturing process of the transistor of the present embodiment will be described in detail based on the transistor structure of the present embodiment:
first, as shown in fig. 3, a trench is formed on a silicon wafer 110 by a shallow trench isolation process, and then a field region is formed by filling a corresponding material into the trench according to actual requirements.
In the second step, as shown in fig. 4, a gate oxide film and a gate film are sequentially coated on the upper surface of the silicon wafer 110, and then a gate oxide layer 121 and a first gate layer 122 having the same length are formed.
In the third step, as shown in fig. 5, the first doped region 133 and the second doped region 143 are formed by implanting dopants into the silicon wafer 110 at both sides of the gate oxide layer 121.
Third, as shown in fig. 6, a gate film is coated on the first gate layer 122, then a second gate layer 123 is formed, and an ILD insulating film layer 124 is formed on the silicon wafer 110 and on one side of the first gate layer 122 under the second gate layer 123 by ILD (InterLayerDielectrics) process and CMP (chemical mechanical polishing) to form an asymmetric structure for the gate structure 120 and the transistor device of this embodiment. Wherein the sum of the length of the insulating film layer 124 and the length of the first gate layer 122 is equal to the length of the second gate layer 123, and the thickness of the insulating film layer 124 is equal to the sum of the thickness of the first gate layer 122 and the thickness of the gate oxide layer 121.
Fourth, as shown in fig. 7, a first gate sidewall 126 is formed on the silicon wafer 110 and on the same side of the gate oxide layer 121, the first gate layer 122 and the second gate layer 123 by a Spacer process. A second gate sidewall 127 is formed over the silicon wafer 110 on the same side of the insulating film layer 124 and the second gate layer 123 to form a complete gate structure 120. High-concentration dopants are implanted into the two sides of the gate structure 120, respectively, to form a first heavily doped region 132 and a second heavily doped region 142.
Fifth, as shown in fig. 2, a silicon source layer 125 is formed over the second gate layer 123, a first active layer 131 is formed over the first heavily doped region 132, and a second active layer 141 is formed over the second heavily doped region 142.
In the manufacturing process of the transistor of this embodiment, required process means include, but are not limited to, deposition and diffusion processes, photon processes, etching processes, polishing processes and integration processes, and the process forces required in the manufacturing process are set according to actual requirements. In the manufacturing process of the transistor of the embodiment, the same manufacturing process as that of a common transistor is physically used, the impurity injection process in the manufacturing process of the transistor is simplified, an asymmetric structure is rapidly and efficiently realized, the channel length between a source electrode and a drain electrode is arbitrarily adjusted, the high-voltage characteristic of the transistor is achieved, the manufacturing efficiency of the transistor is improved, a circuit is refined, the size of a device is reduced, and the manufacturing requirement of a SOC (SystemOnaChip) semiconductor can be met.
Example two
Based on the same inventive concept, the second embodiment of the present application also provides a method for manufacturing a transistor having an asymmetric structure, as shown in fig. 8, including:
s101, forming a gate structure on a silicon wafer, wherein the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is larger than the length of the first gate layer;
s102, forming a source electrode structure and a drain electrode structure on two sides of the gate electrode structure respectively.
As an alternative embodiment, in the process of forming the gate structure on the silicon wafer, the method further includes:
forming an insulating film above the silicon wafer and below a designated area of the second gate layer and on one side of the first gate layer, wherein the designated area is an area where the second gate layer is not in contact with the first gate layer, the sum of the length of the first gate layer and the length of the insulating film layer is equal to the length of the second gate layer, and the thickness of the insulating film layer is equal to the sum of the thickness of the first gate layer and the thickness of the gate oxide layer.
As an alternative embodiment, in the process of forming the gate structure on the silicon wafer, the method further includes:
forming a first gate sidewall on the silicon wafer and on the same side of the gate oxide layer, the first gate layer and the second gate layer, wherein the thickness of the first gate sidewall is not less than the sum of the thickness of the gate oxide layer, the thickness of the first gate layer and the thickness of the second gate layer;
and forming a second gate side wall on the silicon wafer and on the same side of the insulating film layer and the second gate layer, wherein the thickness of the second gate layer side wall is not smaller than the sum of the thickness of the insulating film layer and the thickness of the second gate layer, and the length of the first gate side wall is consistent with the length of the second gate side wall.
As an optional embodiment, in forming the source electrode structure, the method further includes:
forming a first doped region in the silicon wafer at one side of the gate structure and in a region corresponding to the side wall of the first gate;
forming a first heavily doped region in the first doped region and on one side of the gate structure on the upper surface of the silicon wafer;
a first active layer is formed over the first heavily doped region.
As an alternative embodiment, in the process of forming the drain structure, the method further includes:
forming a second doping region in the silicon wafer at the other side of the gate structure and in a region corresponding to the second gate side wall and the insulating film layer;
forming a second heavily doped region on the upper surface of the silicon wafer in the second doped region and on the other side of the gate structure;
forming a second active layer over the second heavily doped region
Since the method for manufacturing the transistor with the asymmetric structure described in this embodiment is a method for implementing the transistor with the asymmetric structure described in the first embodiment of the present application, those skilled in the art will be able to understand the specific implementation of the method for manufacturing the transistor with the asymmetric structure and various modifications thereof, so how to implement the transistor in the first embodiment of the present application will not be described in detail herein. Any method adopted by those skilled in the art to implement the transistor having the asymmetric structure in the first embodiment of the present application falls within the scope of protection of the present application.
It will be apparent to those skilled in the art that while preferred embodiments of the present application have been described, additional variations and modifications may be made to these embodiments once the basic inventive concepts are known to those skilled in the art. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A transistor having an asymmetric structure, comprising:
a silicon wafer, and a gate structure, a source structure, and a drain structure disposed on the silicon wafer, with the gate structure between the source structure and the drain structure;
the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, wherein the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is larger than the length of the first gate layer.
2. The transistor of claim 1, wherein the gate structure further comprises: the insulation film layer is positioned above the silicon wafer, the insulation film layer is positioned below a designated area of the second gate layer, and the insulation film layer is positioned on one side of the first gate layer, wherein the designated area is an area where the second gate layer is not contacted with the first gate layer, the sum of the length of the first gate layer and the length of the insulation film layer is equal to the length of the second gate layer, and the thickness of the insulation film layer is equal to the sum of the thickness of the first gate layer and the thickness of the gate oxide layer.
3. The transistor of claim 2, wherein the gate structure further comprises: a silicon source layer, a first gate sidewall and a second gate sidewall, the silicon source layer being located over the second gate layer;
the first gate side wall is positioned above the silicon wafer and on the same side of the gate oxide layer, the first gate layer and the second gate layer, wherein the thickness of the first gate side wall is not smaller than the sum of the thickness of the gate oxide layer, the thickness of the first gate layer and the thickness of the second gate layer;
the second gate side wall is located on the silicon wafer and located on the same side of the insulating film layer and the second gate layer, wherein the thickness of the second gate side wall is not smaller than the sum of the thickness of the insulating film layer and the thickness of the second gate layer, and the length of the first gate side wall is consistent with the length of the second gate side wall.
4. The transistor of claim 3, wherein the source structure comprises: a first active layer, a first heavily doped region and a first doped region; the first doped region; the first doped region is positioned in the silicon wafer, is positioned at one side of the grid structure and is positioned in a region corresponding to the side wall of the first grid; the first heavily doped region is positioned in the upper surface of the silicon wafer, in the first doped region and at one side of the gate structure; the first active layer is located above the first heavily doped region.
5. The transistor of claim 3, wherein the drain structure comprises: a second active layer, a second heavily doped region and a second doped region; the second doped region is positioned in the silicon wafer, on the other side of the grid structure, and in the region corresponding to the side wall of the second grid and the insulating film layer; the second heavily doped region is positioned in the upper surface of the silicon wafer, in the second doped region and on the other side of the gate structure; the second active layer is located over the second heavily doped region.
6. A method of manufacturing a transistor having an asymmetric structure, comprising:
forming a gate structure on a silicon wafer, wherein the gate structure comprises a gate oxide layer, a first gate layer and a second gate layer, the gate oxide layer is positioned on the silicon wafer, the first gate layer is positioned on the gate oxide layer, the second gate layer is positioned on the first gate layer, the length of the first gate layer is consistent with the length of the gate oxide layer, and the length of the second gate layer is greater than the length of the first gate layer;
and forming a source electrode structure and a drain electrode structure on two sides of the gate electrode structure respectively.
7. The method of claim 6, wherein during forming the gate structure on the silicon wafer, further comprising:
forming an insulating film above the silicon wafer and below a designated area of the second gate layer and on one side of the first gate layer, wherein the designated area is an area where the second gate layer is not in contact with the first gate layer, the sum of the length of the first gate layer and the length of the insulating film layer is equal to the length of the second gate layer, and the thickness of the insulating film layer is equal to the sum of the thickness of the first gate layer and the thickness of the gate oxide layer.
8. The method of claim 7, wherein during forming the gate structure on the silicon wafer, further comprising:
forming a first gate sidewall on the silicon wafer and on the same side of the gate oxide layer, the first gate layer and the second gate layer, wherein the thickness of the first gate sidewall is not less than the sum of the thickness of the gate oxide layer, the thickness of the first gate layer and the thickness of the second gate layer;
and forming a second gate side wall on the silicon wafer and on the same side of the insulating film layer and the second gate layer, wherein the thickness of the second gate layer side wall is not smaller than the sum of the thickness of the insulating film layer and the thickness of the second gate layer, and the length of the first gate side wall is consistent with the length of the second gate side wall.
9. The method of claim 8, further comprising, during forming the source structure:
forming a first doped region in the silicon wafer at one side of the gate structure and in a region corresponding to the side wall of the first gate;
forming a first heavily doped region in the first doped region and on one side of the gate structure on the upper surface of the silicon wafer;
a first active layer is formed over the first heavily doped region.
10. The method of claim 8, further comprising, during forming the drain structure:
forming a second doping region in the silicon wafer at the other side of the gate structure and in a region corresponding to the second gate side wall and the insulating film layer;
forming a second heavily doped region on the upper surface of the silicon wafer in the second doped region and on the other side of the gate structure;
a second active layer is formed over the second heavily doped region.
CN202310812142.7A 2023-07-04 2023-07-04 Transistor with asymmetric structure and manufacturing method thereof Pending CN116864524A (en)

Priority Applications (1)

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CN202310812142.7A CN116864524A (en) 2023-07-04 2023-07-04 Transistor with asymmetric structure and manufacturing method thereof

Applications Claiming Priority (1)

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Publication Number Publication Date
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