CN116864475A - Package and packaging method - Google Patents

Package and packaging method Download PDF

Info

Publication number
CN116864475A
CN116864475A CN202310801605.XA CN202310801605A CN116864475A CN 116864475 A CN116864475 A CN 116864475A CN 202310801605 A CN202310801605 A CN 202310801605A CN 116864475 A CN116864475 A CN 116864475A
Authority
CN
China
Prior art keywords
chip
layer board
pcb
package
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310801605.XA
Other languages
Chinese (zh)
Inventor
张伟宏
罗树荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Baonasheng Shenzhen Technology Co ltd
Original Assignee
Baonasheng Shenzhen Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Baonasheng Shenzhen Technology Co ltd filed Critical Baonasheng Shenzhen Technology Co ltd
Priority to CN202310801605.XA priority Critical patent/CN116864475A/en
Publication of CN116864475A publication Critical patent/CN116864475A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards

Abstract

The invention discloses a packaging body and a packaging method, wherein the packaging body comprises a PCB chip and a reinforcing plate, the PCN chip comprises an ultrathin PCB board, the ultrathin PCB board is provided with a first surface and a second surface which are opposite, a packaging area is formed on the first surface, the packaging area is stacked with chips and peripheral resistance-capacitance elements of an adaptive chip, the reinforcing plate is arranged on the first surface of the ultrathin PCB board, and the middle part of the reinforcing plate is hollowed out to form a dispensing slot corresponding to the position of the packaging area. According to the invention, the peripheral resistance-capacitance element is selected according to the performance requirement of the chip, and the chip and the peripheral resistance-capacitance element are packaged on the ultrathin PCB, so that the performance of the chip can be exerted to the maximum extent, meanwhile, the electromagnetic interference noise related to the chip is effectively reduced, the chip and the peripheral element can be protected from factors such as physical vibration and the like through the reinforcing plate, so that the stability and the long-term reliability of the chip are ensured, the chip and the peripheral element can be accurately positioned and protected by the adhesive dispensing groove arranged on the reinforcing plate, and the damage of the chip and the peripheral element from the external environment is effectively prevented.

Description

Package and packaging method
Technical Field
The present invention relates to the field of chip packaging technologies, and in particular, to a package and a packaging method.
Background
With the progress of global technology, industrial automation artificial intelligence and robot technology will develop rapidly, the requirements for chips will be higher and higher, and the requirements for the chips are higher and higher from 140nm, 90nm and 45nm before to 28nm, 14nm, 12nm, 7nm and 5nm which are the current high-end main stream, wherein the high-end main stream chip process is limited by foreign equipment and technology locking, domestic development and application are limited to a certain extent, and meanwhile, due to the improvement of the performance of the high-end chips, EIM, power supply, noise floor, power consumption, signal integrity and high-frequency signals are higher and higher for engineers, the research period and research and development cost and risk are greatly increased.
The existing packaging body for a single chip or a plurality of chips is usually large in size, and if the size is small, the structural stability and the anti-interference performance of the packaging body are low, and interconnection and intercommunication among the plurality of chips are inconvenient.
Disclosure of Invention
The invention mainly aims to provide a packaging body and a packaging method, which aim to reduce the volume of the packaging body and ensure the stability and anti-interference performance of the packaging body.
In order to achieve the above object, the present invention provides a package, comprising:
the PCB chip comprises an ultrathin PCB board, wherein the ultrathin PCB board is provided with a first surface and a second surface which are opposite, a packaging area is formed on the first surface, and the packaging area is stacked with the chip and a peripheral resistance-capacitance element which is matched with the chip; the method comprises the steps of,
the reinforcing plate is arranged on the first surface of the ultrathin PCB, and the middle part of the reinforcing plate is hollowed out to form a dispensing slot corresponding to the packaging area;
the ultrathin PCB board is formed by stacking a first layer board, a second layer board, a third layer board, a fourth layer board and a fifth layer board, the first layer board and the fifth layer board respectively form the first surface and the second surface, the second layer board and the fourth layer board are provided with signal wires for chip signal connection and power supply, and the third layer board is made of flame-retardant resin so as to form a base layer of the ultrathin PCB.
Optionally, the first surface and the second surface of the ultrathin PCB are treated in black.
Optionally, the ultrathin PCB and the reinforcing plate are attached through glue.
Optionally, the material of the reinforcing plate is flame-retardant resin.
Optionally, the second and fourth laminates are signal connected by metallized vias.
Optionally, the second layer plate and the fourth layer plate are made of copper sheets.
Optionally, the material of the first layer plate and the fifth layer plate is epoxy resin.
Optionally, green oil is laid on the first layer board and the fifth layer board to form a first solder mask layer and a second solder mask layer respectively, and the first solder mask layer and the second solder mask layer are provided with windows for exposing copper points.
Optionally, the second surface of the ultrathin PCB is provided with an interface for connecting signals to the chip.
The invention also provides a packaging method, which comprises the following steps:
carrying out circuit layout design on the first layer board, the second layer board, the third layer board, the fourth layer board and the fifth layer board according to the functional requirement of the chip, and sequentially stacking the fifth layer board, the fourth layer board, the third layer board, the second layer board and the first layer board to form an ultrathin PCB board;
selecting an adaptive peripheral resistance-capacitance element according to the functional requirement of the chip, and attaching the chip and the peripheral resistance-capacitance element to an ultrathin PCB;
hollowing the middle part of the reinforcing plate to form a dispensing groove;
pasting the reinforcing plate on the ultrathin PCB through anti-corrosion glue so that the chip and the peripheral resistance-capacitance element are positioned in the glue dispensing groove;
and dispensing the adhesive to the adhesive dispensing groove through an adhesive dispenser.
According to the invention, the peripheral resistance-capacitance element is selected according to the performance requirement of the chip, and the chip and the peripheral resistance-capacitance element are packaged on the ultrathin PCB, so that the performance of the chip can be exerted to the maximum extent, meanwhile, the electromagnetic interference noise related to the chip is effectively reduced, the use of the ultrathin PCB effectively saves space, the PCB chip is more compact, the chip and the peripheral element can be protected from the influence of factors such as physical vibration and the like by the reinforcing plate, the stability and the long-term reliability of the chip are ensured, and the chip and the peripheral element can be accurately positioned and protected by the adhesive dispensing groove provided by the reinforcing plate, so that the chip and the peripheral element are effectively prevented from being damaged by the external environment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a top view of the present invention;
FIG. 2 is a rear view of the present invention;
fig. 3 is a schematic diagram of an ultra-thin PCB layer of the present invention.
Reference numerals illustrate:
1. a PCB chip; 2. a reinforcing plate; 101. an ultra-thin PCB; 102. a packaging region; 103. a chip; 104. a peripheral resistance-capacitance element; 105. an interface; 201. a dispensing groove; 1011. a first laminate; 1012. a second laminate; 1013. a third laminate; 1014. a fourth laminate; 1015. and a fifth laminate.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, if the meaning of "and/or" is presented throughout this document, it is intended to include three schemes in parallel, taking "a and/or B" as an example, including a scheme, or B scheme, or a scheme where a and B meet simultaneously. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
At present, the size of a package body for a single chip or a plurality of chips is usually large, if the size is small, the stability and the anti-interference performance of the package body are low, and the interconnection and the intercommunication among the plurality of chips are inconvenient.
In order to solve the above-mentioned problems, the present invention provides a package and a packaging method, and fig. 1 to 3 are specific embodiments of the package and the packaging method provided by the present invention.
Referring to fig. 1 to 3, the package includes a PCB chip and a stiffener 2, the PCB chip includes an ultra-thin PCB board 101, the ultra-thin PCB board 101 is formed by stacking a first layer board 1011, a second layer board 1012, a third layer board 1013, a fourth layer board 1014 and a fifth layer board 1015, in order to improve stability and structural reliability of the package, and facilitate connection and fixation of components of the chip 103.
Further, the ultra-thin PCB 101 has a first surface and a second surface opposite to each other, and a packaging region 102 is formed on the first surface of the PCB chip, and the packaging region 102 is stacked with a chip 103 and a peripheral resistor-capacitor element 104 adapted to the chip 103. The reinforcing plate 2 is disposed on the first surface of the ultra-thin PCB 101, and is used for reinforcing the mechanical strength of the PCB chip and supporting the chip 103 and the attachment element. In order to facilitate fixing the chip 103 and the peripheral resistor-capacitor element 104, the middle portion of the stiffening plate 2 is hollowed out to form a dispensing slot 201 corresponding to the position of the packaging region 102, and a professional packaging tool is used for dispensing the dispensing slot 201 to ensure the stability and the firmness of connection.
The invention can realize interconnection and intercommunication among stacked chips, more efficient communication and data transmission, and greatly improves communication speed and bandwidth, thereby improving performance, and simultaneously, functional verification and test can be completed in the package body, and the workload of testing the EMI and EMC in the later period is correspondingly reduced.
In order to make the appearance of the ultra-thin PCB 101 more attractive, improve its oxidation resistance and improve its optical properties, the first and second surfaces of the ultra-thin PCB 101 are black-treated, and the black color has an endothermic effect, and heat generated from the chip 103 may be absorbed to reduce the temperature of the chip 103.
Further, the first layer 1011 and the fifth layer 1015 are laid with green oil to form a first solder mask and a second solder mask respectively, the first solder mask and the second solder mask are provided with windows for exposing copper points, the solder mask is a protective layer applied on the circuit board, which can help to maintain the stability of the circuit board and prolong the service life thereof, for example, the solder mask can prevent the surface of the circuit board from oxidizing corrosion and contacting with pollutants in the air, thereby maintaining the integrity of the circuit board, and can also improve the heat resistance of the circuit board, so that the circuit board can bear the high temperature welding process and other processing technologies, the solder mask can reduce the flow of solder, thereby avoiding the problems of unnecessary connection or short circuit, and the like, and improving the welding quality, and the solder mask can help workers to identify the positions of components and circuit layouts on the circuit board.
The ultra-thin PCB 101 is attached to the stiffening plate 2 through anti-corrosion glue, wherein the total thickness of the ultra-thin PCB 101 is between 0.22 mm and 0.28mm, and the ultra-thin PCB 101 is subjected to a gold plating process to improve the oxidation resistance and the welding degree.
The material of the reinforcing plate 2 is flame-resistant resin, the thickness of the flame-resistant resin is between 0.35 and 0.41mm, the flame-resistant resin is also called flame-retardant resin, the flame-resistant resin is a special resin with the performance of preventing the material from burning, the flame-resistant resin generally has higher thermal stability, can keep the basic structure and the performance of the flame-resistant resin in a high-temperature environment, the flame-resistant resin also has flame retardance, can effectively prevent the material from burning, reduces the occurrence and the diffusion of fire, and the flame-resistant resin is generally high in mechanical strength and rigidity, can provide the required supporting and protecting functions in use and has chemical resistance: the flame-retardant resin generally has good chemical resistance and can be kept stable in various environments such as acid, alkali, solvent and the like, and furthermore, the flame-retardant resin can be processed and molded by molding, injection molding, extrusion and the like, and the reinforcing plate 2 has the functions of tensile resistance, fracture resistance and the like, and the overall strength of the package body can be enhanced in the present invention.
The signal connection mode of the metallized via hole is commonly used in the design of the multilayer PCB circuit board, the signal communication between the multilayer boards can be realized, the signal connection of the metallized via hole is one of the signal transmission modes commonly used for the printed circuit board, the signal transmission reliability of the metallized via hole is high, the problems of blocking or signal loss and the like in the signal transmission process can be effectively avoided, the signal transmission reliability and stability are improved, the method is suitable for the design of the multilayer PCB circuit board, the signal transmission can be realized through the connection of the metallized via hole, the mechanical strength of the PCB board can be enhanced, the problems of falling off, breakage and the like of the PCB board are avoided, and compared with other signal transmission modes, the metallized via hole connection has the advantage of lower cost. In the present invention, the second plate 1012 and the fourth plate 1014 are signal connected by metallized vias.
The second layer 1012 and the fourth layer 1014 are made of copper, wherein the thick bottoms of the second layer 1012 and the fourth layer 1014 are 18 μm.
The material of the first laminate 1011 and the fifth layer 1015 is epoxy, and the thickness of the first laminate 1011 and the fifth layer 1015 is 20 μm.
The second surface of the ultra-thin PCB 101 is provided with an interface for connecting signals to the chip 103, and the interface is disposed on the second surface of the ultra-thin PCB 101, and functions similar to pins of the chip 103, so that the chip 103 is conveniently connected with external signals.
The packaging method of the packaging body comprises the following steps:
performing circuit layout design on the first layer board 1011, the second layer board 1012, the third layer board 1013, the fourth layer board 1014 and the fifth layer board 1015 according to the functional requirement of the chip 103, and stacking the fifth layer board 1015, the fourth layer board 1014, the third layer board 1013, the second layer board 1012 and the first layer board 1011 in sequence to form an ultrathin PCB board 101;
selecting an adaptive peripheral resistance-capacitance element 104 according to the functional requirement of the chip 103, and attaching the chip 103 and the peripheral resistance-capacitance element 104 to the ultrathin PCB 101;
the middle part of the reinforcing plate 2 is hollowed out to form a dispensing groove 201;
the reinforcing plate 2 is stuck on the ultrathin PCB 101 through the anti-corrosion glue, so that the chip 103 and the peripheral resistance-capacitance element 104 are positioned in the glue dispensing groove 201;
and dispensing the adhesive in the adhesive dispensing groove 201 by an adhesive dispenser.
In the step of sequentially stacking the first layer 1011, the second layer 1012, the third layer 1013, the fourth layer 1014, and the fifth layer 1015 according to the functional requirements of the chip 103 to form the ultra-thin PCB 101, parameters such as the positions and the sizes of copper foil interfaces between the layers in the stacking process of the first layer 1011, the second layer 1012, the third layer 1013, the fourth layer 1014, and the fifth layer 1015 need to be paid attention to in order to ensure smooth signal transmission between the layers.
In the step of selecting the adaptive peripheral resistor-capacitor element 104 according to the functional requirement of the chip 103 and attaching the chip 103 and the peripheral resistor-capacitor element 104 to the ultra-thin PCB 101, the peripheral resistor-capacitor element 104 is fixed by solder, and the mounting direction and position of the peripheral resistor-capacitor element 104 need to be noted to ensure the correct connection between the chip and the chip 103.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the invention.

Claims (10)

1. A package, comprising:
the PCB chip comprises an ultrathin PCB board, wherein the ultrathin PCB board is provided with a first surface and a second surface which are opposite, a packaging area is formed on the first surface, and the packaging area is stacked with the chip and a peripheral resistance-capacitance element which is matched with the chip; the method comprises the steps of,
the reinforcing plate is arranged on the first surface of the ultrathin PCB, and the middle part of the reinforcing plate is hollowed out to form a dispensing slot corresponding to the packaging area;
the ultrathin PCB board is formed by stacking a first layer board, a second layer board, a third layer board, a fourth layer board and a fifth layer board, the first layer board and the fifth layer board respectively form the first surface and the second surface, the second layer board and the fourth layer board are provided with signal wires for chip signal connection and power supply, and the third layer board is made of flame-retardant resin so as to form a base layer of the ultrathin PCB.
2. The package of claim 1, wherein the first and second surfaces of the ultra-thin PCB are black treated.
3. The package of claim 1, wherein the ultra-thin PCB and the stiffener are attached by glue.
4. The package of claim 1, wherein the stiffener is made of a flame-retardant resin.
5. The package of claim 1, wherein the second tier and the fourth tier are signal connected by metallized vias.
6. The package of claim 1, wherein the second and fourth layers are copper sheets.
7. The package of claim 1, wherein the material of the first and fifth laminates is epoxy.
8. The package of claim 1, wherein the first and fifth layers of board are clad with green oil to form a first solder mask and a second solder mask, respectively, the first and second solder masks having windows exposing copper points.
9. The package of claim 1, wherein the second surface of the ultra-thin PCB is provided with an interface for signal connection to the chip.
10. A packaging method for the package according to any one of claims 1 to 9, comprising the steps of:
carrying out circuit layout design on the first layer board, the second layer board, the third layer board, the fourth layer board and the fifth layer board according to the functional requirement of the chip, and sequentially stacking the fifth layer board, the fourth layer board, the third layer board, the second layer board and the first layer board to form an ultrathin PCB board;
selecting an adaptive peripheral resistance-capacitance element according to the functional requirement of the chip, and attaching the chip and the peripheral resistance-capacitance element to an ultrathin PCB;
hollowing the middle part of the reinforcing plate to form a dispensing groove;
pasting the reinforcing plate on the ultrathin PCB through anti-corrosion glue so that the chip and the peripheral resistance-capacitance element are positioned in the glue dispensing groove;
and dispensing the adhesive to the adhesive dispensing groove through an adhesive dispenser.
CN202310801605.XA 2023-06-30 2023-06-30 Package and packaging method Pending CN116864475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310801605.XA CN116864475A (en) 2023-06-30 2023-06-30 Package and packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310801605.XA CN116864475A (en) 2023-06-30 2023-06-30 Package and packaging method

Publications (1)

Publication Number Publication Date
CN116864475A true CN116864475A (en) 2023-10-10

Family

ID=88224522

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310801605.XA Pending CN116864475A (en) 2023-06-30 2023-06-30 Package and packaging method

Country Status (1)

Country Link
CN (1) CN116864475A (en)

Similar Documents

Publication Publication Date Title
KR970003991B1 (en) Double sided memory board and memory module using the board
JP2011035345A (en) Semiconductor device module, electronic circuit unit, electronic device, and method of manufacturing semiconductor device module
US6321443B1 (en) Connection substrate
CN116782506B (en) Circuit board assembly, processing method thereof, circuit board stacking structure and electronic equipment
CN116864475A (en) Package and packaging method
US7492985B2 (en) Flexible printed circuits capable of transmitting electrical and optical signals
JP2007128959A (en) Semiconductor memory card and circuit board
JPS6386491A (en) Metallic core printed wiring board
KR100467844B1 (en) Rigid flexible printed circuit board for mobile phone, and manufacturing method thereof
JP2005150490A (en) Sheet component between ic and printed wiring board
US5877545A (en) Encapsulated printed circuit assembly and method and manufacturing the same
JPH11298153A (en) Multilayered printed circuit board
CN212393046U (en) Flexible circuit board and semiconductor packaging structure
KR20090102119A (en) Embedded printed circuit board and manufacturing method thereof
US8124879B2 (en) Printed board
CN210298205U (en) Rigid-flex BGA solder mask circuit board
KR20180020524A (en) A printed circuit board having coverlay and Package of battery protection circuits with the same
CN113853059B (en) Rigid-flex printed circuit board and circuit connector
CN216218256U (en) Corrosion-resistant protection circuit board
CN215871967U (en) Anti-falling and anti-winding flexible circuit board
Fjelstad Flexible circuitry‐technology background and important fundamental issues
CN210075683U (en) Novel multilayer circuit board structure
CN214592113U (en) Semi-rigid flexible circuit board, antenna board and base station
CN114126205B (en) Printed wiring board, memory system, and method for manufacturing printed wiring board
CN210575937U (en) Circuit board structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination