CN116861843A

CN116861843A - Verification method, device, equipment and medium of chip simulation model

Info

Publication number: CN116861843A
Application number: CN202210312911.2A
Authority: CN
Inventors: 刘建斌; 马茂松
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2023-10-10

Abstract

The invention discloses a verification method, a device, equipment and a medium of a chip simulation model, which are applied to the field of electronic design and are used for solving the problem that the chip simulation model cannot be automatically verified, wherein the method comprises the following steps: firstly, selecting a target model, and acquiring data to be detected in the target model; then substituting the resistor to be measured and the voltage to be measured in the data to be measured into a verification model to obtain a measured voltage; and then judging whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model, if so, confirming that the verification of the target model is passed, and if not, determining that the target model is wrong. The resistance to be measured and the voltage to be measured in the data to be measured in the target model are substituted into the verification model to obtain the measured voltage, and then whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model is judged, so that automatic verification of the chip simulation model is realized, and the efficiency of verifying the chip simulation model is improved.

Description

Verification method, device, equipment and medium of chip simulation model

Technical Field

The present invention relates to the field of circuit simulation, and in particular, to a method, an apparatus, a device, and a medium for verifying a chip simulation model.

Background

The Input/output buffer information specification (IBIS) model is a simulation model type mainly used in current simulation, and compared with a simulation circuit simulator (Simulation program with integrated circuit emphasis, SPICE) model, the IBIS model has the advantages of high simulation efficiency, short time (the simulation time can be shortened by at least one order of magnitude compared with the SPICE model), no leakage of design details inside a chip and the like, and is a preferred model of a simulation engineer.

The IBIS model that the chip manufacturer will produce often verifies the accuracy of the model before it is made available to the customer. The IBIS model of the chip is characterized in that the IBIS model internally comprises tens to hundreds of models, and the problem of how to improve the verification efficiency of the chip simulation model is a urgent need of the technicians in the field.

Disclosure of Invention

The invention provides a verification method, device, equipment and medium for a chip simulation model, which are used for solving the problem of how to improve the efficiency of verifying the chip simulation model in the prior art.

In a first aspect, an embodiment of the present invention provides a method for verifying a chip simulation model, where the method includes:

Selecting a target model, and acquiring data to be detected in the target model;

substituting the resistor to be measured and the voltage to be measured in the data to be measured into a verification model to obtain a measured voltage;

and judging whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model, if so, confirming that the target model passes verification, and if not, determining that the target model is wrong.

In one possible implementation, the target model includes a plurality of driving models and a plurality of receiving models.

In one possible implementation, the driving models are driving performance data tables, and each driving model includes a pull-up resistance value, a pull-down resistance value, and a driving voltage value;

the receiving models are receiving performance data tables, and each receiving model comprises a termination resistance value and a termination voltage value.

In one possible implementation manner, the verification model includes a first resistor and a second resistor, a first end of the first resistor is connected to a power supply end, the power supply end is used for inputting the voltage to be tested, a second end of the first resistor is connected to a first end of the second resistor, and the first end of the second resistor is grounded as a voltage measurement end.

In one possible embodiment, the method further comprises:

when the target model is the driving model, the first resistor is the resistor to be measured, the second resistor is a standard resistor, and a pull-up resistor in the driving model is used as the resistor to be measured;

when the target model is the receiving model, the first resistor is the standard resistor, the second resistor is the resistor to be measured, and the terminating resistor in the receiving model is used as the resistor to be measured.

In one possible implementation manner, substituting the resistor to be measured and the voltage to be measured in the data to be measured into a verification model, and obtaining the measured voltage includes:

when the target model is a driving model, acquiring a pull-down resistance value, a pull-up resistance value and a driving voltage value in the driving model;

adjusting the resistance value of the second resistor in the verification model to be the same as the pull-down resistance value, adjusting the resistance value of the first resistor of the verification model to be the same as the pull-down resistance value, adjusting the voltage of the power supply end of the verification model to be the driving voltage value, and measuring the voltage value of the second end of the first resistor;

when the target model is a receiving model, acquiring a termination resistance value and a termination voltage value in the receiving model;

Selecting a driving model corresponding to the receiving model from a model library, and acquiring a pull-up resistance value in the driving model;

adjusting the resistance value of a first resistor of the verification model to be the pull-up resistance value, adjusting the resistance value of a second resistor of the verification model to be the termination resistance value, adjusting the voltage of a power supply end of the verification model to be the termination voltage value, and measuring the voltage value of a first end of the second resistor;

the driving model corresponding to the receiving model is a driving model with the same pull-up resistance value as the termination resistance value, which is arbitrarily selected from the model library according to the termination resistance value.

In one possible embodiment, the relation between the voltage to be measured and the resistance to be measured is determined by:

calculating the ratio of the resistance value of the second resistor to the total resistance value;

taking the product of the ratio and the voltage value of the voltage to be measured as the relation between the voltage to be measured and the resistance value to be measured;

the total resistance value is the sum of the resistance value of the first resistor and the resistance value of the second resistor.

In one possible implementation, the voltage to be measured includes a low voltage value, a standard voltage value, and a high voltage value;

And when the verification model verifies the low voltage value, the standard voltage value and the high voltage value, the resistance value to be tested is the same.

In a second aspect, an embodiment of the present invention provides a verification apparatus for a chip simulation model, including:

the first acquisition module is used for selecting a target model and acquiring data to be detected in the target model;

the second acquisition module is used for substituting the resistor to be measured and the voltage to be measured in the data to be measured into a verification model to obtain a measured voltage;

and the judging module is used for judging whether the measured voltage accords with the relation between the voltage to be tested and the resistance value to be tested in the verification model, if so, confirming that the target model passes verification, and if not, the target model is wrong.

In one possible embodiment, the apparatus further comprises:

In one possible implementation manner, the second obtaining module is specifically configured to:

In a third aspect, an embodiment of the present invention provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor implements the steps of the method of any of the first aspects by executing the executable instructions.

In a fourth aspect, embodiments of the present invention provide a computer readable storage medium having stored thereon computer instructions which when executed by a processor implement the steps of the method of any of the first aspects.

The invention has the following beneficial effects:

the invention discloses a verification method, a device, equipment and a medium of a chip simulation model, wherein the verification method comprises the following steps: firstly, selecting a target model, and acquiring data to be detected in the target model; then substituting the resistor to be measured and the voltage to be measured in the data to be measured into a verification model to obtain a measured voltage; and then judging whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model, if so, confirming that the verification of the target model is passed, and if not, determining that the target model is wrong. The resistance to be measured and the voltage to be measured in the data to be measured in the target model are substituted into the verification model to obtain the measured voltage, and then whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model is judged, so that automatic verification of the chip simulation model is realized, and the efficiency of verifying the chip simulation model is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a verification method of a chip simulation model according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an internal structure of a verification model according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a specific flow chart of a verification method for a chip simulation model according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a verification device for a chip simulation model according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a verification device for a chip simulation model according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a verification medium of a chip simulation model according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

At present, in the field of circuit simulation, a signal integrity simulation technology is often used to predict hardware circuit performance or speed up debugging progress. The premise of using the signal integrity simulation technique is to obtain an accurate device model, and the most widely used is SPICE model and IBIS model. Compared with SPICE model, IBIS model has the advantages of high simulation efficiency, short time, no leakage of design details inside the chip, and the like, and is the preferred model of current circuit simulation.

Because the data models of the IBIS model are numerous, different working states of the chip need to be simulated, and therefore, the produced IBIS model needs to be verified for accuracy before being provided for customers. The IBIS model of the chip can comprise a plurality of models, each model also has different application conditions, and the IBIS model of the DRAM chip is characterized by comprising dozens of models, each model has 3 application conditions, so that the verification of the whole IBIS model is very time-consuming.

Based on the above problems, the embodiments of the present invention provide a method, an apparatus, a device, and a medium for verifying a chip simulation model, so as to solve the problem of how to automatically verify the chip simulation model in the prior art.

The chip simulation model verification method provided by the exemplary embodiment of the present application will be described below with reference to the accompanying drawings in conjunction with the above-described application scenario, and it should be noted that the above-described application scenario is only shown for the convenience of understanding the spirit and principle of the present application, and the embodiment of the present application is not limited in any way in this respect.

As shown in fig. 1, a flow chart of a verification method of a chip simulation model according to an embodiment of the present application is shown, where the method includes:

step 101, selecting a target model, acquiring data to be detected in the target model, and executing step 102;

step 102, substituting the resistor to be tested and the voltage to be tested in the data to be tested into a verification model to obtain a measured voltage, and executing step 103;

and step 103, judging whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model, if so, confirming that the verification of the target model is passed, and if not, determining that the target model is wrong.

According to the verification method of the chip simulation model, the resistance to be tested and the voltage to be tested in the data to be tested in the target model are substituted into the verification model, the verification model automatically obtains the measured voltage, and then whether the measured voltage accords with the relation between the voltage to be tested and the resistance value to be tested in the verification model is judged, so that the automatic verification of the chip simulation model is realized, and the efficiency of verifying the chip simulation model is improved.

It should be noted that the target model includes a plurality of driving models and a plurality of receiving models, so as to correspond to the working states of the chip as the driving end and the receiving end. For the IBIS driving model when the chip is used as the driving end in the embodiment of the present invention, as shown in table 1, each IBIS driving model includes a pull-up resistance value Rup, a pull-down resistance value Rdown, and a driving voltage value Vd, where the driving voltage value Vd includes a low voltage value Vmin, a standard voltage value Vtyp, and a high voltage value Vmax, and dq_pu40_pd40 is taken as an example, and represents that the pull-up resistance value of the driving model is 40ohm and the pull-down resistance value is 40ohm.

TABLE 1

For the IBIS receiving models IN the embodiment of the present invention, as shown IN table 2, each receiving model includes a terminating resistance value Rodt and a terminating voltage value Vodt, where the terminating voltage value Vodt includes a low voltage value Vmin, a standard voltage value Vtyp and a high voltage value Vmax, and dq_in_odt40 is taken as an example to represent the terminating resistance value of the receiving model as 40ohm.

TABLE 2

In one possible embodiment, as shown in fig. 2, an internal structure schematic diagram of a verification model is provided in an embodiment of the present invention, where the verification model includes a first resistor R1 and a second resistor R2, and the connection relationship between the first resistor R1 and the second resistor R2 is as follows:

The first end of the first resistor R1 is connected with a power supply end Vin, the power supply end Vin is used for inputting voltage to be measured, the second end of the first resistor R1 is connected with the first end of the second resistor R2, and the second end of the second resistor R2 is grounded as a voltage measuring end Vm.

In one possible embodiment, referring to fig. 2, when the target model is a driving model, the first resistor R1 is a resistor to be measured, the second resistor R2 is a standard resistor, and the pull-up resistor value in the driving model is taken as the resistance value of the resistor to be measured.

The standard resistor refers to a resistor having ideal electrical characteristics, and the resistance is only related to the material and the size.

In one possible embodiment, referring to fig. 2, when the target model is a receiving model, the first resistor R1 is a standard resistor, the second resistor R2 is a resistor to be measured, and the terminating resistor value in the receiving model is the resistor to be measured.

The verification method of the chip simulation model is described in detail below in combination with the above description:

as shown in fig. 3, a specific flow diagram of a verification method of a chip simulation model according to an embodiment of the present invention is shown, where the method includes:

step 301, selecting a target model, obtaining data to be tested in the target model, if the target model is a driving model, executing step 302, and if the target model is a receiving model, executing step 303;

The method for acquiring the data to be detected in the target model comprises the following steps: and sequentially selecting one IBIS model from a plurality of IBIS models, and verifying the model.

Step 302, obtaining a pull-down resistance value, a pull-up resistance value and a driving voltage value in a driving model, adjusting the resistance value of a second resistor in a verification model to be the same as the pull-down resistance value, adjusting the resistance value of a first resistor of the verification model to be the same as the pull-down resistance value, adjusting the voltage of a power supply end of the verification model to be the driving voltage value, and measuring the voltage value of a second end of the first resistor, and executing step 304;

the pull-down resistance value, the pull-up resistance value and the driving voltage value in the driving model are obtained specifically according to the pull-down resistance value and the field value corresponding to the pull-up resistance value in the IBIS model, the field value corresponding to the pull-up resistance value is PU or pull up, the field value corresponding to the pull-down resistance value is PD or pull down, the driving voltage value is obtained according to the voltage unit in the IBIS model, and meanwhile the driving voltage value does not need to change at any time, so that the driving voltage value can be set in advance.

The resistance value R2 of the second resistor in the verification model is adjusted to be the same as the pull-down resistance value, the resistance value of the first resistor R1 of the verification model is adjusted to be the same as the pull-down resistance value, and the voltage of the power supply end of the verification model is adjusted to be the driving voltage value, specifically:

The extracted pull-down resistance value is input into the resistance value to be set of the second resistor R2, the extracted pull-up resistance value is input into the resistance value to be set of the first resistor R1, and the driving voltage value is input into the power supply terminal voltage.

Step 303, acquiring a termination resistance value and a termination voltage value in the receiving model; selecting a driving model corresponding to the receiving model from the model library, and acquiring a pull-up resistance value in the driving model; adjusting the resistance value of the first resistor of the verification model to be a pull-up resistance value, adjusting the resistance value of the second resistor of the verification model to be a termination resistance value, adjusting the voltage of the power supply end of the verification model to be a termination voltage value, measuring the voltage value of the first end of the second resistor, and executing the step 304;

it should be noted that, the driving model corresponding to the receiving model is a driving model with a pull-up resistance value and a termination resistance value that are arbitrarily selected from the model library according to the termination resistance value, for example, for dq_in_odt40, the termination resistance value is 40ohm, and the corresponding driving model may be dq_pu40_pd40 with a pull-up resistance value of 40 ohm.

The field value corresponding to the termination resistance value is 'ODT', and the termination voltage value can be directly obtained from the IBIS model and set in advance. And inputting the final voltage value into the power supply terminal voltage according to the obtained summary resistance value and the to-be-set resistance value of the second resistor R2.

Step 304, judging whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model, if so, executing step 305, otherwise, executing step 306;

step 305, the target model is correct;

step 306, the target model is incorrect.

It should be noted that the voltage to be measured includes a low voltage value Vmin, a standard voltage value Vtyp, and a high voltage value Vmax. When an IBIS model is verified, after the first resistor R1 and the second resistor R2 of the verification model are determined, the voltage value of the power supply voltage end of the verification model can be replaced according to the low voltage value Vmin, the standard voltage value Vtyp and the high voltage value Vmax in sequence.

In one possible embodiment, the above-mentioned manner of determining whether the measured voltage meets the relationship between the voltage to be measured and the resistance to be measured in the verification model is as follows:

calculating the ratio of the resistance value of the second resistor R2 to the total resistance value;

taking the product of the ratio and the voltage value of the voltage to be measured as the relation between the voltage to be measured and the resistance value to be measured.

The total resistance value is the sum of the resistance value of the first resistor R1 and the resistance value of the second resistor R2; the ratio can be set according to the resistance value and the total resistance value of the second resistor R2 in an ideal state and the voltage division condition of the circuit in the specific verification model, for example, the ratio is set to be one half.

When the verification model verifies the low voltage value min, the standard voltage value Vtyp and the high voltage value Vmax, the internal resistance values to be tested are the same, for example, when the DQ_PU40_PD40 is tested, different driving voltages Vd are input, and the resistance values to be tested of the verification resistor are all 40 ohms.

The above method is described in detail with reference to specific examples below:

specifically, selecting a target model, when the tested target model is a driving model, acquiring a pull-up resistance value, a pull-down resistance value and a driving voltage value in a driving performance data table, for example, DQ_PU40_PD40, adjusting the resistance value of a first resistor R1 of a verification model and the resistance value of a pull-down resistor Rdown to be 40 ohms, adjusting the driving voltage Vd of a power supply end to be equal to a low voltage value Vmin, and judging whether the measuring voltage of a measuring voltage end Vm is equal to one half of Vmin; adjusting the power supply voltage of the power supply terminal Vd to be equal to a standard voltage value Vtyp, and judging whether the measured voltage of the measured voltage terminal Vm is equal to one half of the Vtyp; the power supply voltage of the power supply terminal Vd is adjusted to be equal to the high voltage value Vmax, and whether the measured voltage of the measured voltage terminal Vm is equal to one half of Vmax is judged.

If the measured voltages are equal to one half of the driving voltage value Vd, confirming that the target model passes verification;

The above test is repeated for the next drive pattern, e.g., DQ_PU40_PD48, until all drive patterns are tested.

Specifically, selecting a target model, when the tested target model is a receiving model, acquiring a termination resistance value and a termination voltage value IN the receiving model, for example, DQ_IN_ODT40, selecting a driving model corresponding to the receiving model, namely DQ_PU40_PD40, IN a model library, acquiring a pull-up resistance value IN the driving model, namely 40 ohms, adjusting the resistance value of a first resistor R1 of a verification model to be the pull-up resistance value, namely 40 ohms, adjusting the resistance value of a second resistor R2 of the verification model to be the termination resistance value, namely 40 ohms, adjusting the z termination voltage value Vodt of a power supply end to be equal to a low voltage value Vmin, and judging whether the measurement voltage of a measurement voltage end Vm is equal to one half of the low voltage value Vmin; adjusting the power supply voltage of the power supply terminal Vd to be equal to the standard voltage value Vtyp, and judging whether the measured voltage of the measured voltage terminal Vm is equal to one half of the standard voltage value Vtyp; the power supply voltage of the power supply terminal Vd is adjusted to be equal to the high voltage value Vmax, and whether the measured voltage of the measured voltage terminal Vm is equal to one half of the high voltage value Vmax is judged.

If the measured voltages are equal to one half of the final voltage value Vodt, confirming that the target model passes verification;

The above test is repeated for the next receive pattern, e.g., DQ_IN_ODT48, until all receive patterns have been tested.

Based on the same inventive concept, the embodiment of the invention also provides a verification device for a chip simulation model, and because the device is the device in the method in the embodiment of the invention, and the principle of the device for solving the problem is similar to that of the method, the implementation of the device can refer to the implementation of the method, and the repetition is omitted.

As shown in fig. 4, a schematic structural diagram of a verification device for a chip simulation model according to an embodiment of the present invention includes a first obtaining module 401, a second obtaining module 402, and a judging module 403:

a first obtaining module 401, configured to select a target model, and obtain data to be tested in the target model;

a second obtaining module 402, configured to substitute a resistor to be measured and a voltage to be measured in the data to be measured into a verification model to obtain a measured voltage;

and a judging module 403, configured to judge whether the measured voltage meets the relationship between the voltage to be tested and the resistance value to be tested in the verification model, if yes, confirm that the verification of the target model is passed, and if not, make the target model incorrect.

Optionally, the target model includes a plurality of driving models and a plurality of receiving models.

Optionally, the driving models are driving performance data tables, and each driving model includes a pull-up resistance value, a pull-down resistance value and a driving voltage value;

Optionally, the verification model includes a first resistor and a second resistor, a first end of the first resistor is connected with a power supply end, the power supply end is used for inputting the voltage to be tested, a second end of the first resistor is connected with a first end of the second resistor, the second end is used as a voltage measurement end, and a first end of the second resistor is grounded.

Optionally, when the target model is the driving model, the first resistor is the resistor to be measured, the second resistor is a standard resistor, and a pull-up resistor in the driving model is used as the resistor to be measured;

Optionally, the second obtaining module 402 is specifically configured to:

Optionally, the relationship between the voltage to be measured and the resistance to be measured is determined by:

Optionally, the voltage to be measured includes a low voltage value, a standard voltage value and a high voltage value;

Based on the same inventive concept, the embodiment of the invention also provides an electronic device for verifying a chip simulation model, and because the electronic device is the electronic device in the method in the embodiment of the invention, and the principle of solving the problem of the electronic device is similar to that of the method, the implementation of the electronic device can refer to the implementation of the method, and the repetition is omitted.

An electronic device 50 according to this embodiment of the invention is described below with reference to fig. 5. The electronic device 50 shown in fig. 5 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.

As shown in fig. 5, the electronic device 50 may be embodied in the form of a general purpose computing device, which may be a terminal device, for example. Components of electronic device 50 may include, but are not limited to: the at least one processor 51, the at least one memory 52 storing processor-executable instructions, and a bus 53 connecting the various system components, including the memory 52 and the processor 51.

The processor 51 implements the verification method of the chip simulation model described above by executing the executable instructions.

Bus 53 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, and a local bus using any of a variety of bus architectures.

Memory 52 may include readable media in the form of volatile memory, such as Random Access Memory (RAM) 521 and/or cache memory 522, and may further include Read Only Memory (ROM) 523.

Memory 52 may also include a program/utility 525 having a set (at least one) of program modules 524, such program modules 524 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

Electronic device 50 may also communicate with one or more external devices 54 (e.g., keyboard, pointing device, etc.), one or more devices that enable a user to interact with electronic device 50, and/or any devices (e.g., routers, modems, etc.) that enable electronic device 50 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 115. Also, the electronic device 50 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through a network adapter 56. As shown, the network adapter 56 communicates with other modules of the electronic device 50 over the bus 53. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 50, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

In some possible embodiments, the aspects of the present invention may also be implemented in the form of a program product, which includes a program code for causing a terminal device to execute the steps of each module in a resource treatment analysis apparatus according to various exemplary embodiments of the present invention described in the above "exemplary method" section of the present specification, when the program product is run on the terminal device, for example, the terminal device may be used to select a target model, and obtain data to be measured in the target model; substituting the resistor to be measured and the voltage to be measured in the data to be measured into a verification model to obtain a measured voltage; judging whether the measured voltage accords with the relation between the voltage to be measured and the resistance value to be measured in the verification model, if so, confirming that the target model passes verification, and if not, determining that the target model is wrong and the like.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

As shown in fig. 6, a program product 60 of an authentication method for a chip emulation model according to an embodiment of the present invention is described, which may employ a portable compact disc read only memory (CD-ROM) and comprise program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The method adjusts the resistance value and the power supply end voltage in the verification model to obtain the measured voltage by acquiring the pull-down resistance value, the pull-up resistance value and the driving voltage value in the target model to be tested, judges whether the measured voltage accords with the relation between the voltage to be tested and the resistance value to be tested in the verification model, and determines whether the resistance value in the target model in the chip simulation model meets the verification standard of the verification model, so that the driving model and the receiving model in the chip simulation model are automatically verified one by one, and the verification efficiency of the model is improved.

It should be noted that while several modules or sub-modules of the system are mentioned in the detailed description above, such partitioning is merely exemplary and not mandatory. Indeed, the features and functions of two or more modules described above may be embodied in one module in accordance with embodiments of the present invention. Conversely, the features and functions of one module described above may be further divided into a plurality of modules to be embodied.

Furthermore, while the operations of the various modules of the inventive system are depicted in a particular order in the drawings, this is not required to either imply that the operations must be performed in that particular order or that all of the illustrated operations be performed to achieve desirable results. Additionally or alternatively, certain operations may be omitted, multiple operations combined into one operation execution, and/or one operation decomposed into multiple operation executions.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims

1. A method for verifying a chip simulation model, the method comprising:

2. The method of claim 1, wherein the target model comprises a plurality of driving models and a plurality of receiving models.

3. The method of claim 2, wherein the driving models are driving performance data tables, each of the driving models including a pull-up resistance value, a pull-down resistance value, and a driving voltage value;

4. A method according to claim 3, wherein the verification model comprises a first resistor and a second resistor, the first end of the first resistor is connected to a power supply end, the power supply end is used for inputting the voltage to be measured, the second end of the first resistor is connected to the first end of the second resistor, and the first end of the second resistor is grounded as a voltage measurement end.

5. The method of claim 4, wherein the method further comprises:

6. The method of claim 5, wherein substituting the resistance under test and the voltage under test in the data under test into a verification model to obtain the measured voltage comprises:

7. The method of claim 4, wherein the relationship of the voltage under test to the resistance value under test is determined by:

8. The method of claim 1, wherein the voltage to be measured comprises a low voltage value, a standard voltage value, and a high voltage value;

9. A verification device for a chip simulation model, the device comprising:

10. The apparatus of claim 9, wherein the target model comprises a plurality of driving models and a plurality of receiving models.

11. The apparatus of claim 10, wherein the driving models are driving performance data tables, each of the driving models comprising a pull-up resistance value, a pull-down resistance value, and a driving voltage value;

12. The apparatus of claim 11, wherein the verification model comprises a first resistor and a second resistor, a first end of the first resistor is connected to a power supply end, the power supply end is used for inputting the voltage to be measured, a second end of the first resistor is connected to a first end of the second resistor, and the first end of the second resistor is grounded as a voltage measurement end.

13. The apparatus of claim 12, wherein the apparatus further comprises:

14. The apparatus of claim 13, wherein the second acquisition module is specifically configured to:

15. The apparatus of claim 12, wherein the relationship of the voltage to be measured to the resistance value to be measured is determined by:

16. The apparatus of claim 9, wherein the voltage to be measured comprises a low voltage value, a standard voltage value, and a high voltage value;

17. An electronic device, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor implements the steps of the method of any one of claims 1 to 8 by executing the executable instructions.

18. A computer readable and writable storage medium, on which computer instructions are stored which when executed by a processor implement the steps of the method of any one of claims 1 to 8.