CN116860429A

CN116860429A - Memory management method and electronic equipment

Info

Publication number: CN116860429A
Application number: CN202210314876.8A
Authority: CN
Inventors: 季柯丞; 杨文飞; 王绪; 王琳
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2023-10-10

Abstract

A memory management method and electronic equipment relate to the technical field of terminals, and can comprehensively and comprehensively determine the access history of a memory according to the access condition of the process to the memory in the whole process life cycle in history, thereby accurately performing memory management. The method is applied to electronic equipment, the electronic equipment comprises a first linked list, the first linked list comprises a plurality of pages, and the method comprises the following steps: acquiring access times and/or access intervals of a first page in the first linked list in a first period; the first period is the life cycle of the process associated with the first page; the plurality of pages includes the first page; and according to the access times and/or the access intervals, migrating the first page.

Description

Memory management method and electronic equipment

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a memory management method and an electronic device.

Background

Currently, with the popularization of electronic devices such as mobile phones, the fluency demands of users for applications are increasing. In electronic devices, memory is one of the very important system resources. If the system has insufficient idle memory, the smoothness of the application can be greatly reduced, so that the application is blocked, and the use experience is affected. Therefore, it is needed to propose an efficient memory management method for improving the performance of the electronic device.

Disclosure of Invention

In order to solve the technical problems described above, an embodiment of the present application provides a memory management method and an electronic device. The technical scheme provided by the embodiment of the application can reduce the system overhead in the memory management process.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

in a first aspect, a memory management method is provided, where the method is applied to an electronic device or a component (such as a chip system) capable of implementing a function of the electronic device, where the electronic device includes a first linked list, and the first linked list includes a plurality of pages, and the method includes: acquiring access times and/or access intervals of a first page in the first linked list in a first period; the first period is the life cycle of the process associated with the first page; the plurality of pages includes the first page; and according to the access times and/or the access intervals, migrating the first page.

According to the scheme, the electronic equipment can comprehensively and comprehensively determine the access history of the memory according to the access condition of the process to the memory in the whole process life cycle in history, and further can accurately manage the memory according to the accurate memory access history. For example, in some scenarios, the probability of memory being recycled by mistake can be avoided or reduced, so that the system overhead caused by memory recycling by mistake is reduced, and the memory management efficiency is improved.

In one possible design, the process associated with the first page is one or more.

In one possible design, the first period includes a period in which the process is running in the background and/or a period in which the process is running in the foreground.

The electronic device can acquire the access times and the access intervals of the pages accessed by the background process, and manage the pages according to the access times and the access intervals of the pages accessed by the background process. Thus, important memory pages frequently accessed by the background process can be prevented from being erroneously recovered. Furthermore, since the important memory pages can be prevented from being recycled by mistake, or the probability of recycling the important memory pages by mistake is reduced, the normal operation of the background process can be ensured as much as possible, and the functions of the electronic equipment can be realized to the greatest extent.

Or the electronic device can acquire the access times and the access intervals of the pages accessed by the foreground process, and manage the pages according to the access times and the access intervals of the pages accessed by the foreground process.

Or the electronic equipment acquires the access times and the access intervals of the pages accessed by the foreground process and the background process, and manages the pages according to the access times and the access intervals of the pages accessed by the foreground process and the background process.

In one possible design, the obtaining the access times and/or access intervals of the first page in the first linked list in the first period includes: at a first moment, acquiring access times and/or access intervals of a first page in a first linked list in a first period;

in the case that the process is one, the first period starts from the starting time of the process to the closing time of the process; or, the first period starts from the starting time of the process to the end of the first time.

and when the number of the processes is multiple, the first period starts from the starting time of the process started earliest in the multiple processes to the closing time of the process closed latest in the multiple processes, or the first period starts from the starting time of the process started earliest in the multiple processes to the closing time of the process started earliest in the multiple processes.

In one possible design, the migrating the first page according to the access times and/or the access intervals includes:

in the case where the first linked list is an active linked list,

if the access times and/or the access intervals meet a first condition, migrating the first page to the head of the first linked list; otherwise, the first page is migrated from the first linked list to the head of a second linked list;

wherein the second linked list is an inactive linked list.

Therefore, the important pages in the active linked list can be prevented from being wrongly migrated into the inactive linked list.

in the case where the first linked list is an inactive linked list,

if the access times and/or the access intervals meet a first condition, migrating the first page from the first linked list to the head of a second linked list; otherwise, the first page is migrated from the first linked list to a memory recycling area;

the second linked list is an active linked list, and the memory recovery area comprises the following areas: compression space, disk space, free space.

Therefore, important pages in the inactive linked list can be prevented from being mistakenly recycled into the memory recycling area.

In one possible design, the first condition includes any one or more of the following:

the access times are larger than a first threshold, the access interval is smaller than a second threshold, and the ratio of the access times to the access interval is larger than a third threshold.

In one possible design, the obtaining the access times and/or access intervals of the first page in the first linked list in the first period includes:

and obtaining the access times and/or access intervals corresponding to the virtual addresses of the first page.

In one possible design, the migrating the first page according to the access times and/or the access intervals includes: and under the condition that the first page is positioned at the tail part of the first linked list, migrating the first page according to the access times and/or the access intervals.

In one possible design, the access interval is used to characterize a time interval between two adjacent accesses to the first page, or a time interval between two adjacent accesses to the first page.

In a second aspect, an electronic device is provided, the electronic device including a first linked list, the first linked list including a plurality of pages, the electronic device including:

The processing unit is used for acquiring the access times and/or access intervals of the first page in the first linked list in the first period; the first period is the life cycle of the process associated with the first page; the plurality of pages includes the first page;

the processing unit is further configured to migrate the first page according to the access times and/or the access intervals.

if the access times and/or the access intervals meet a first condition under the condition that the first linked list is an active linked list, migrating the first page to the head of the first linked list; otherwise, the first page is migrated from the first linked list to the head of a second linked list;

wherein the second linked list is an inactive linked list.

If the access times and/or the access intervals meet a first condition under the condition that the first linked list is an inactive linked list, migrating the first page from the first linked list to the head of a second linked list; otherwise, the first page is migrated from the first linked list to a memory recycling area;

In a third aspect, an embodiment of the present application provides an electronic device having a function of implementing the method as described in any of the above aspects and any one of the possible implementations; alternatively, the electronic device has functionality to implement the method as described in any of the aspects and any one of the possible implementations. The functions may be implemented by hardware, or by corresponding software executed by hardware. The hardware or software includes one or more modules corresponding to the functions described above.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium. The computer readable storage medium stores a computer program (which may also be referred to as instructions or code) which, when executed by an electronic device, causes the electronic device to perform the method of the first aspect or any implementation of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer program product for causing an electronic device to perform the method of the first aspect or any one of the embodiments of the first aspect when the computer program product is run on the electronic device.

In a sixth aspect, an embodiment of the application provides circuitry comprising processing circuitry configured to perform the first aspect or the method of any one of the embodiments of the first aspect.

In a seventh aspect, an embodiment of the present application provides a chip system, including at least one processor and at least one interface circuit, where the at least one interface circuit is configured to perform a transceiver function and send an instruction to the at least one processor, and when the at least one processor executes the instruction, the at least one processor performs the method of the first aspect or any implementation manner of the first aspect.

Drawings

FIG. 1A is a schematic diagram of a page reclamation mechanism according to an embodiment of the present application;

FIG. 1B is a schematic diagram of a refault phenomenon according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a schematic software structure of an electronic device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 5 and fig. 6 are schematic diagrams of a memory management method according to an embodiment of the present application;

fig. 7-11 are schematic diagrams illustrating a memory management method under different life cycle conditions according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a method for determining the number of accesses according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a method for determining access intervals according to an embodiment of the present application;

fig. 14-15 are schematic diagrams illustrating a memory management method according to an embodiment of the present application;

FIG. 16A is a diagram illustrating a memory management method according to an embodiment of the present application;

FIG. 16B is a diagram illustrating a memory management method according to an embodiment of the present application;

fig. 17 to 19 are schematic diagrams of a memory management method according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of a memory management device according to an embodiment of the present application.

Detailed Description

In the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

First, some terms related to embodiments of the present application will be described:

1. memory paging mechanism

Currently, memory management may be implemented based on memory cells. Memory cells include, but are not limited to, memory pages (pages). In some aspects, the memory may be partitioned into memory pages according to a certain size (e.g., 4K). Through a memory paging mechanism, the efficiency of accessing the memory can be improved.

It should be noted that, as technology evolves, the memory unit may be implemented in other ways, and is not limited to a memory page. It should be understood that the memory page is used as a memory cell in the embodiment of the present application, but this should not be construed as limiting the memory cell.

2. Anonymous pages and file pages

The user-mode memory includes an anonymous page (anonymous page) and a file page (file-blocked page).

The file page refers to a memory page (may be simply referred to as a memory page or a page) having a source backup page in an external storage space (such as a disk), where the file page has a mapping relationship with the source backup page in the external storage space. As one possible implementation, a program may read a file from a disk through basic operations, such as read/map (read/mmap), and the system may apply for pages to store content read from the disk, where the pages used to store the content of the disk file may be considered a file page.

Anonymous pages, which means that there is no memory page in the external storage space with its corresponding file, such as a heap, stack, etc. of processes, the pages used may be anonymous pages.

Wherein, the external storage space refers to a storage space except a memory.

3. Anonymous page recycling method

For anonymous pages, the electronic device may compress the anonymous pages currently in use into a compressed space (or swap space, swap partition, etc., such as zram) during the memory reclamation process. Such a memory reclamation scheme may be referred to as a page swap scheme.

For some anonymous pages that are not currently in use, such as free pages, the electronic device may discard them into free space of the buddy (buddy) system, and subsequently, the free pages may be retrieved from the buddy system when they are reused. Such a memory reclamation scheme may be referred to as a page discard scheme.

4. File page recycling mode

For a file page, during the memory reclamation process, the electronic device screens out some file pages which are not frequently used, if the content of the file page is consistent with the content of a corresponding file in the disk, the file page is a clean file page, and then the electronic device does not need to write the file page back to the disk, but can directly take the file page as a free page, and discard the file page into the free (free) space of the partner system. Such a memory reclamation scheme may be referred to as a page discard scheme.

If the data stored in the file page is inconsistent with the data stored in the corresponding file in the disk, the file page is a dirty page, and then the electronic device needs to write back the content of the file page to the corresponding file in the disk, and then release the file page as a free page to the partner system. Such a memory reclamation scheme may be referred to as a page write-back scheme.

5. Synchronous memory reclamation

For user state memory, the kernel may perform synchronous memory reclamation and/or asynchronous memory reclamation.

The synchronous memory recovery means that when a process calls a page allocation function to apply for allocating physical memory, the system is in shortage of residual memory and cannot meet the memory allocation requirement, and the system tries to acquire the memory page through recovering the memory so as to meet the memory allocation requirement. In this memory reclamation method, the system needs to reclaim part of the memory first, and then can allocate the memory for the process.

6. Asynchronous memory reclamation

As a possible implementation manner, when receiving the memory allocation request, the system detects the amount of the remaining memory, and if the remaining memory is lower than a set low (low) water level threshold, wakes up an asynchronous recovery thread (kswapd) to implement asynchronous memory recovery, so as to maintain the remaining amount of the system memory and meet the memory allocation requirement.

In some aspects, asynchronous memory reclamation and synchronous memory reclamation may be performed concurrently.

7. Linked list and memory management mechanism based on linked list

In some implementations, the kernel may manage user state memory through a least recently used (least recently used, LRU) linked list. According to the active state of the linked list, the linked list can be divided into two stages: active and inactive linked lists. Wherein, the active linked list includes: an active anonymous page linked list and an active file page linked list, the inactive linked list comprising: an inactive anonymous page linked list and an inactive file page linked list.

The linked list based memory management process, as in fig. 1A, is described below in conjunction with fig. 1A, and includes the steps of:

(1) As in (a) of fig. 1A, the process applies for a memory page, the allocator allocates the memory page for the process, and the electronic device adds the allocated memory page to the head of the active linked list.

(2) When there is memory pressure, memory reclamation is triggered. As one possible implementation, the electronic device scans the active linked list first, and determines whether to recycle the memory pages in the active linked list. When the active linked list is recycled, the memory pages at the tail part of the active linked list are recycled preferentially.

In some examples, as shown in fig. 1A (b), if a memory page at the end of the active linked list meets a reclaimable requirement, such as a time period from the memory page being added to the linked list to the time of the reclaiming (such as a time period between two memory reclaims), the memory page is not accessed (reference) and then the memory page is triggered to be reclaimed and migrated from the end of the active linked list to the head of the inactive linked list. In this process, the memory page added from the head is equivalent to moving to the tail of the linked list, that is, when a certain memory page is deleted from the linked list, other memory pages are equivalent to moving to the tail in the linked list, and the electronic device can continue to determine whether to recycle the memory page located at the tail.

Pages are accessed, which may also be referred to as pages being accessed for use, pages being used, pages being mapped, etc.

In other examples, when the memory page at the tail of the active linked list is reclaimed, as shown in (c) of fig. 1A, the memory page to be reclaimed is accessed in a period from being added to the linked list to being reclaimed, or the state of the memory page is changed, the memory page is not reclaimed, and the memory page is migrated from the tail of the active linked list to the head of the active linked list again.

(3) After judging whether the memory pages in the active linked list are recycled and executing the recycling of the corresponding memory pages, the electronic equipment judges whether the memory pages in the inactive linked list are recycled. When the memory pages in the inactive linked list are reclaimed, as a possible implementation manner, the memory pages at the tail of the inactive linked list are preferentially reclaimed.

In some examples, as in (d) of fig. 1A, reclamation of a memory page is triggered if the memory page at the tail meets memory reclamation requirements, such as the memory page has not been accessed after entering the linked list. Optionally, for anonymous pages, recycling is achieved by way of page swapping or page discarding; for file pages, reclamation is performed by page discard or page write-back.

In other examples, as in (e) of fig. 1A, if a memory page does not meet the reclaimable requirement, such as the memory page has been accessed during the period of time that the memory page is added to the inactive linked list until the time of reclaiming, or the state of the memory page changes, it is determined that the memory page is in an active state, and the memory page is migrated back from the tail of the inactive linked list to the head of the active linked list, i.e., the page is not reclaimed.

It will be appreciated that with the reclamation of the tail memory pages in the inactive linked list, other memory pages on the inactive linked list correspond to migration from the head of the inactive linked list to the tail of the inactive linked list. The electronic device can judge and recycle the memory page newly migrated to the tail.

In summary, the memory reclamation process can be simplified as follows: memory pages in the active linked list can move to the tail of the active linked list, and in some cases, memory pages meeting the conditions at the tail of the active linked list can migrate to the head of the inactive linked list, so that migration of the memory pages among the linked lists is realized. Memory pages in the inactive linked list can be migrated to the tail of the inactive linked list, and the electronic device can recover memory pages meeting the conditions from the tail of the inactive linked list.

Wherein, the migration of the page from the active linked list to the inactive linked list may be referred to as reclaiming the page in the active linked list. Migrating (freeing) pages from the inactive linked list into, for example, compressed space or disk space or free space, may be referred to as reclaiming pages in the inactive linked list.

In high load devices or low memory devices, it is easy for the memory pages to be recycled and used immediately after being recycled, and the phenomenon of secondary page loading caused by recycling is called as a refault phenomenon. Illustratively, as shown in FIG. 1B, the refault phenomenon may occur in two flows:

(1) After the page is migrated from the active linked list to the inactive linked list, the condition that the page is used (reference) occurs, in this case, when the page in the inactive linked list is recovered, the used page is judged to be in an active state, and the page is migrated back to the active linked list again, so that a page refetch is generated, the memory recovery or migration is invalid, the cost of the memory recovery is increased, and the performance is affected.

(2) If the anonymous page is reclaimed to the compression space or the file page is written back to the disk space and then the page is immediately used, the memory application triggers a missing page exception (do_page_fault) flow, resulting in the reclaimed memory page (e.g., the anonymous page reclaimed to the compression space or the file page written back to the disk space) being replaced in the active linked list, thereby generating the page refault. The page refault of the type can generate input-output (IO) operation, and the access speed of the IO is far lower than that of a memory, so that high access delay is caused.

From the memory reclamation perspective, page reclamation may result in invalid scanning and reclamation of the memory during the memory reclamation process, thereby resulting in increased memory reclamation overhead. From the perspective of memory application, page refault causes that the memory page in the memory is recovered, when the memory page is accessed again next time, the memory page cannot be found in the memory, and thus the page-missing exception processing flow is triggered to acquire the memory, so that the steps of the memory access application are increased, the memory application flow is prolonged, high time delay is generated in memory access, and simultaneously, more processing steps cause larger processing cost. In summary, page refault can result in reduced memory management performance.

In order to solve the above technical problems, an embodiment of the present application provides a memory management method, which obtains an access history of a memory in a life cycle of an associated process, and manages the memory according to the access history. Wherein the access history comprises access times and/or access intervals. On the one hand, according to the access condition of the process to the memory in the whole process life cycle historically, the access history of the memory can be comprehensively and comprehensively determined, and further, according to the accurate memory access history, the memory management can be accurately performed. For example, in some scenarios, the probability of memory being recycled by mistake can be avoided or reduced, that is, the probability of producing refault can be avoided or reduced, so that the management overhead caused by refault is reduced, and the memory management efficiency is improved.

The memory management method of the embodiment of the application can be applied to electronic equipment. For example, the electronic device may be a mobile phone, a tablet computer, a personal computer (personal computer, PC), a netbook, or the like, which needs to perform memory optimization, and the specific form of the electronic device is not particularly limited in the present application.

Taking an electronic device as an example of a mobile phone, fig. 2 shows a schematic hardware structure of the electronic device 100 a. The structure of the other electronic device can be seen from the structure of the electronic device 100 a.

The electronic device 100A may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity module (subscriber identification module, SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 100 a. In other embodiments of the application, electronic device 100a may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The USB interface 130 is an interface conforming to the USB standard, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 130 may be used to connect a charger to charge the electronic device 100a, or may be used to transfer data between the electronic device 100a and a peripheral device. And can also be used for connecting with a headset, and playing audio through the headset. The interface may also be used to connect other electronic devices, such as AR devices, etc.

It should be understood that the interfacing relationship between the modules illustrated in the embodiment of the present application is only illustrative, and does not limit the structure of the electronic device 100 a. In other embodiments of the present application, the electronic device 100a may also use different interfacing manners in the above embodiments, or a combination of multiple interfacing manners.

The charge management module 140 is configured to receive a charge input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charge management module 140 may receive a charging input of a wired charger through the USB interface 130. In some wireless charging embodiments, the charge management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100 a. The charging management module 140 may also supply power to the terminal through the power management module 141 while charging the battery 142.

The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 may also be configured to monitor battery capacity, battery cycle number, battery health (leakage, impedance) and other parameters. In other embodiments, the power management module 141 may also be provided in the processor 110. In other embodiments, the power management module 141 and the charge management module 140 may be disposed in the same device.

The wireless communication function of the electronic device 100a can be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100a may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G, etc., applied on the electronic device 100 a. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 150 may receive electromagnetic waves from the antenna 1, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 150 can amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 1 to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be provided in the same device as at least some of the modules of the processor 110.

The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or video through the display screen 194. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be provided in the same device as the mobile communication module 150 or other functional module, independent of the processor 110.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc., applied to the electronic device 100 a. The wireless communication module 160 may be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 2.

In some embodiments of the present application, the electronic device 100a may establish a wireless connection with other terminals or servers through the wireless communication module 160 (such as a WLAN module) and the antenna 2 to enable communication between the electronic device 100a and the other terminals or servers.

In some embodiments, antenna 1 and mobile communication module 150 of electronic device 100a are coupled, and antenna 2 and wireless communication module 160 are coupled, such that electronic device 100a may communicate with a network and other devices through wireless communication techniques. The wireless communication techniques may include the Global System for Mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).

The electronic device 100a implements display functions through a GPU, a display screen 194, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 194 is used to display images, videos, and the like. The display 194 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), a mini, a Micro led, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the electronic device 100a may include 1 or N display screens 194, N being a positive integer greater than 1.

The electronic device 100a may implement photographing functions through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.

The ISP is used to process data fed back by the camera 193. For example, when photographing, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electric signal, and the camera photosensitive element transmits the electric signal to the ISP for processing and is converted into an image visible to naked eyes. ISP can also optimize the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 193.

The camera 193 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV, or the like format. In some embodiments, electronic device 100a may include 1 or N cameras 193, N being a positive integer greater than 1.

The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the electronic device 100a selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.

Video codecs are used to compress or decompress digital video. The electronic device 100a may support one or more video codecs. Thus, the electronic device 100a may play or record video in a variety of encoding formats, such as: dynamic picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent cognition of the electronic device 100a may be implemented through the NPU, for example: image recognition, face recognition, speech recognition, text understanding, etc.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 100 a. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.

The internal memory 121 may be used to store computer executable program code including instructions. The internal memory 121 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the electronic device 100a (e.g., audio data, phonebook, etc.), and so on. In addition, the internal memory 121 may include a high-speed random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like. The processor 110 performs various functional applications of the electronic device 100a and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The electronic device 100A may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

The audio module 170 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal. The audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be disposed in the processor 110, or a portion of the functional modules of the audio module 170 may be disposed in the processor 110.

The speaker 170A, also referred to as a "horn," is used to convert audio electrical signals into sound signals. The electronic device 100A may listen to music, or to hands-free conversations, through the speaker 170A.

A receiver 170B, also referred to as a "earpiece", is used to convert the audio electrical signal into a sound signal. When the electronic device 100a picks up a phone call or voice message, the voice can be picked up by placing the receiver 170B close to the human ear.

Microphone 170C, also referred to as a "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or transmitting voice information, the user can sound near the microphone 170C through the mouth, inputting a sound signal to the microphone 170C. The electronic device 100a may be provided with at least one microphone 170C. In other embodiments, the electronic device 100a may be provided with two microphones 170C, and may implement a noise reduction function in addition to collecting sound signals. In other embodiments, the electronic device 100a may also be provided with three, four, or more microphones 170C to enable collection of sound signals, noise reduction, identification of sound sources, directional recording, etc.

The earphone interface 170D is used to connect a wired earphone. The earphone interface 170D may be a USB interface 130 or a 3.5mm open terminal platform (open mobile terminal platform, OMTP) standard interface, a american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

The keys 190 include a power-on key, a volume key, etc. The keys 190 may be mechanical keys. Or may be a touch key. The electronic device 100a may receive key inputs, generating key signal inputs related to user settings and function controls of the electronic device 100 a.

The motor 191 may generate a vibration cue. The motor 191 may be used for incoming call vibration alerting as well as for touch vibration feedback. For example, touch operations acting on different applications (e.g., photographing, audio playing, etc.) may correspond to different vibration feedback effects. The motor 191 may also correspond to different vibration feedback effects by touching different areas of the display screen 194. Different application scenarios (such as time reminding, receiving information, alarm clock, game, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect may also support customization.

The indicator 192 may be an indicator light, may be used to indicate a state of charge, a change in charge, a message indicating a missed call, a notification, etc.

The SIM card interface 195 is used to connect a SIM card. The SIM card may be inserted into the SIM card interface 195, or removed from the SIM card interface 195 to effect contact and separation with the electronic device 100 a. The electronic device 100a may support 1 or N SIM card interfaces, N being a positive integer greater than 1. The SIM card interface 195 may support Nano SIM cards, micro SIM cards, and the like. The same SIM card interface 195 may be used to insert multiple cards simultaneously. The types of the plurality of cards may be the same or different. The SIM card interface 195 may also be compatible with different types of SIM cards. The SIM card interface 195 may also be compatible with external memory cards. The electronic device 100a interacts with the network through the SIM card to realize functions such as communication and data communication. In some embodiments, the electronic device 100a employs esims, namely: an embedded SIM card. The eSIM card can be embedded in the electronic device 100a and cannot be separated from the electronic device 100 a.

Alternatively, the software system of the electronic device 100a may employ a layered architecture, an event driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture. Embodiments of the invention are configured in a layered manner The system is an example illustrating the software architecture of the electronic device 100 a.

Fig. 3 is a software block diagram of the electronic device 100a according to the embodiment of the present invention.

The layered architecture divides the software into several layers, each with distinct roles and branches. The layers communicate with each other through a software interface. In some embodiments, the Android system is divided into four layers, from top to bottom, an application layer, an application framework layer, an Zhuoyun row (Android run) and system libraries, and a kernel layer, respectively.

The application layer may include a series of application packages.

As shown in fig. 3, the application package may include applications for cameras, gallery, calendar, phone calls, maps, navigation, WLAN, bluetooth, music, video, short messages, etc.

The application framework layer provides an application programming interface (application programming interface, API) and programming framework for application programs of the application layer. The application framework layer includes a number of predefined functions.

As shown in FIG. 3, the application framework layer may include a window manager, a content provider, a view system, a telephony manager, a resource manager, a notification manager, and the like.

The window manager is used for managing window programs. The window manager can acquire the size of the display screen, judge whether a status bar exists, lock the screen, intercept the screen and the like. The content provider is used to store and retrieve data and make such data accessible to applications. The data may include video, images, audio, calls made and received, browsing history and bookmarks, phonebooks, etc. The view system includes visual controls, such as controls to display text, controls to display pictures, and the like. The view system may be used to build applications. The display interface may be composed of one or more views. For example, a display interface including a text message notification icon may include a view displaying text and a view displaying a picture. The telephony manager is used to provide the communication functions of the electronic device 100 a. Such as the management of call status (including on, hung-up, etc.). The resource manager provides various resources for the application program, such as localization strings, icons, pictures, layout files, video files, and the like. The notification manager allows the application to display notification information in a status bar, can be used to communicate notification type messages, can automatically disappear after a short dwell, and does not require user interaction. Such as notification manager is used to inform that the download is complete, message alerts, etc. The notification manager may also be a notification in the form of a chart or scroll bar text that appears on the system top status bar, such as a notification of a background running application, or a notification that appears on the screen in the form of a dialog window. For example, a text message is prompted in a status bar, a prompt tone is emitted, the terminal vibrates, and an indicator light blinks.

Android run time includes a core library and virtual machines. Android run time is responsible for scheduling and management of the Android system. The core library consists of two parts: one part is a function which needs to be called by java language, and the other part is a core library of android. The application layer and the application framework layer run in a virtual machine. The virtual machine executes java files of the application program layer and the application program framework layer as binary files. The virtual machine is used for executing the functions of object life cycle management, stack management, thread management, security and exception management, garbage collection and the like.

The system library may include a plurality of functional modules. For example: surface manager (surface manager), media Libraries (Media Libraries), three-dimensional graphics processing Libraries (e.g., openGL ES), 2D graphics engines (e.g., SGL), etc. The surface manager is used to manage the display subsystem and provides a fusion of 2D and 3D layers for multiple applications. Media libraries support a variety of commonly used audio, video format playback and recording, still image files, and the like. The media library may support a variety of audio and video encoding formats, such as MPEG4, h.264, MP3, AAC, AMR, JPG, PNG, etc. The three-dimensional graphic processing library is used for realizing three-dimensional graphic drawing, image rendering, synthesis, layer processing and the like. The 2D graphics engine is a drawing engine for 2D drawing.

The kernel layer is a layer between hardware and software. The inner core layer at least comprises a display driver, a camera driver, an audio driver and a sensor driver.

In some embodiments of the present application, the kernel layer may include a memory management module for managing the memory of a process.

Memory management includes, but is not limited to, memory release (which may also be referred to as memory reclamation).

The memory management module is used for acquiring whether the process runs in the foreground or the background through the process management module of the framework layer, and recording the times and the access intervals of the process for accessing the page when the process runs in the foreground and/or in the background. Subsequently, the memory management module can manage the page according to the access times and access intervals of the page.

The judging process of the foreground process and the background process can refer to the related technology, and will not be repeated here.

It should be noted that the structure of the electronic device may refer to the structure shown in fig. 4, and the electronic device may have more or less components than the structure shown in fig. 4, or may combine some components, split some components, or may have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

For example, as shown in fig. 4, the electronic device may include a processor 401 (optionally including a processor 408), a memory 403, a transceiver 404, and the like.

Wherein, a passage can be included between the components for transmitting information between the components.

A transceiver 404 for communicating with other devices or communication networks using protocols such as ethernet, WLAN, etc.

For details of the processor and the memory, please refer to the description of the related structure in the electronic device of fig. 2, and details thereof are omitted herein.

The following describes the technical scheme provided by the embodiment of the application in detail. The technical scheme of the embodiment of the application is suitable for the electronic equipment adopting the linked list to carry out memory management. Alternatively, the physical memory in the electronic device may be divided into a plurality of memory units. Alternatively, the memory cells include, but are not limited to, memory pages. Multiple memory units may be added to each linked list. The following embodiments mainly take a memory page as a memory unit as an example for illustration, but the technical solution of the embodiments of the present application is not limited thereto.

And when the memory is recovered, the electronic equipment acquires the access times and the time intervals between the accesses of the memory pages in the active linked list in the life cycle, and determines whether to migrate the memory pages to the inactive linked list according to the access times and the access intervals. The electronic device may further obtain the number of accesses to the memory page in the inactive linked list and a time interval between accesses, and determine whether to recycle the memory page according to the number of accesses and the access interval.

Taking the migration of the memory page at the tail of the active linked list as an example, as shown in fig. 5 (a), the electronic device obtains the access times and access intervals in the whole life cycle of the memory page at the tail of the active linked list, and determines whether to migrate the memory page out of the active linked list according to the access times and the access intervals.

Optionally, in some embodiments, the electronic device calculates the activity level of the memory page in the whole life cycle according to the access times and the access intervals of the memory page in the tail of the active linked list in the whole life cycle. If the activity level is higher than the third threshold, as shown in fig. 5 (a), indicating that the memory page at the tail is frequently accessed, the memory page is migrated to the head of the active linked list so as to avoid the memory page being reclaimed in a short time. Otherwise, as shown in fig. 5 (b), if the activity level of the tail memory page is lower than the third threshold value, which indicates that the memory page is not accessed frequently, the tail memory page is migrated to the inactive linked list.

Alternatively, in other embodiments, if the electronic device determines that the number of accesses to a memory page at the end of the active linked list is greater than the first threshold value and the access interval of the memory page throughout the life cycle is less than the fourth threshold value, indicating that the memory page is frequently accessed, the electronic device migrates the memory page to the head of the active linked list. Otherwise, if the electronic device determines that the number of accesses of the memory page in the whole life cycle is less than or equal to the first threshold value and the access interval of the memory page in the whole life cycle is greater than or equal to the fourth threshold value, the electronic device migrates the memory page to the head of the inactive linked list.

Alternatively, in other embodiments, if the electronic device determines that the number of accesses to a memory page at the end of the active linked list is greater than the first threshold throughout the lifecycle, indicating that the memory page is frequently accessed, the electronic device migrates the memory page to the head of the active linked list. Otherwise, if the electronic device determines that the number of accesses to the memory page in the whole life cycle is less than or equal to the first threshold, the electronic device migrates the memory page to the head of the inactive linked list.

Alternatively, in other embodiments, if the electronic device determines that the access interval of a memory page at the end of the active linked list is less than the fourth threshold throughout the lifecycle, the electronic device migrates the memory page to the head of the active linked list. Otherwise, if the electronic device determines that the access interval of the memory page in the whole life cycle is greater than or equal to the fourth threshold, the electronic device migrates the memory page to the head of the inactive linked list.

It can be appreciated that for migration of other memory pages in the active linked list, the above-mentioned migration process of the tail memory page can be referred to, for example, for a memory page in the active linked list with an activity level higher than the third threshold, the memory page is migrated higher than the head of the active linked list. And for the memory pages with the activity degree lower than the third threshold value in the active linked list, migrating the memory pages into the inactive linked list.

Thus, for memory pages in the active linked list, only memory pages with low activity are migrated to the inactive linked list, and memory pages with high activity remain in the active linked list. Because the memory page with high activity is more likely to be repeatedly accessed, the probability of generating the page refault can be avoided or reduced without migrating the memory page to an inactive linked list.

After migrating the memory pages in the active linked list, the electronic device manages the memory pages in the inactive linked list. For example, taking management of the memory page at the tail of the inactive linked list as shown in fig. 6 (a), the electronic device obtains the access times and access intervals of the memory page at the tail of the inactive linked list in the life cycle, and calculates the activity degree of the memory page in the whole life cycle according to the access times and the access intervals. If the activity level is higher than the third threshold, the memory page is migrated to the head of the active linked list as in fig. 6 (a).

Otherwise, as shown in fig. 6 (b), if the activity level of the tail memory page is lower than the third threshold value, which indicates that the memory page is not accessed frequently, the tail memory page is reclaimed.

According to the scheme, the access history of the memory can be determined by acquiring the access times and the access intervals of the memory page, and then the importance of the memory page can be predicted according to the access history. In general, memory pages with historically greater numbers of accesses and smaller access intervals are typically more important memory pages, and then it is considered that the important memory pages are not reclaimed when memory is reclaimed. Therefore, through obtaining the parameters which can represent the multiple dimensions of the access history, the activity degree or the importance degree of the identification page can be more accurate and refined, and the accuracy and the efficiency of memory recovery are improved.

The life cycle of a memory page is related to the duration of time that the memory page is accessed by a process. Alternatively, in the case where a memory page is accessed by only one process, the life cycle of the memory page accessed by the process, i.e., the life cycle of the process. Specifically, the lifecycle of the process refers to the period of time between the start of the process and the time the process is killed (kill). In some examples, a process may access multiple memory pages during the life of the process, and the life of the process may then be referred to as the life of the multiple memory pages.

Illustratively, as shown in fig. 7 (a), at time t1, process a starts. Between times t1 and t2, process A accesses memory page A and memory page B multiple times. At time t2, the system memory is insufficient, memory reclamation is triggered, and at time t3, process A is killed. At time t4, the system memory is insufficient, and memory reclamation is triggered again. The time period between the times t1 and t3, i.e., the life cycle of the process a, can also be regarded as the life cycle of the memory page A, B.

Taking the example that the memory page a is currently at the tail of the active linked list and the memory page a is recycled, in the embodiment of the present application, the electronic device obtains the access times and the access intervals of the memory page a in the whole life cycle (i.e. the time period between t1 and t3 shown in fig. 7), and calculates the activity degree of the memory page a in the time period between t1 and t3 according to the access times and the access intervals. After calculating that the activity level of the memory page a is higher than the third threshold, which indicates that the memory page a is a frequently accessed memory page, as shown in (b) of fig. 7, the electronic device migrates the memory page a to the head of the active linked list, so as to avoid that the memory page a is reclaimed in a short time. As can be seen, in comparison with the related art shown in fig. 7 (c), once the memory page a is not accessed between two memory reclaims (i.e., between t2-t 4), the memory page a is migrated from the active linked list to the inactive linked list, i.e., the frequently accessed memory page a is mismigrated due to not being accessed in a short period, so that the memory page a is likely to be migrated from the inactive linked list back to the active linked list in a short period later, and an ineffective migration is generated.

Alternatively, the life cycle of a memory page may refer to the period of time from the start of a process accessing the memory page to the current memory reclamation.

Illustratively, as shown in fig. 8 (a), at time t1, process a starts. Between times t1 and t2, process A accesses memory page A and memory page B multiple times. At time t2, the system memory is insufficient, memory reclamation is triggered, and at time t3, process A is killed. At time t4, the system memory is insufficient, and memory reclamation is triggered again. The time period (i.e., time period t1-t 4) from the start of the process a to the current memory reclamation can be used as the life cycle of the memory page a and the memory page B.

As shown in fig. 8 (b), the electronic device obtains the access times and access intervals of the memory page a in the whole life cycle (i.e., the time period t1-t 4), and calculates the activity level of the memory page a in the time period t1-t4 according to the access times and the access intervals. After calculation, if the activity level of the memory page a is higher than the third threshold, the electronic device migrates the memory page a to the head of the active linked list, so as to prevent the memory page a from being recovered in a short time.

Further exemplary, as shown in fig. 9 (a), at time t1, process a starts. Between times t1 and t2, process A accesses memory page A and memory page B multiple times. At time t2, the system memory is insufficient, memory reclamation is triggered, and at time t3, the system memory is insufficient, and memory reclamation is triggered again. At time t4, process A is killed. The time period (i.e., time period t1-t 3) from the start of the process a to the current memory reclamation can be used as the life cycle of the memory page a and the memory page B.

As shown in fig. 9 (b), the electronic device obtains the access times and access intervals of the memory page a in the whole life cycle (i.e., the time period t1-t 3), and calculates the activity level of the memory page a in the time period t1-t3 according to the access times and the access intervals. After calculation, if the activity level of the memory page a is higher than the third threshold, the electronic device migrates the memory page a to the head of the active linked list, so as to prevent the memory page a from being recovered in a short time.

Optionally, in a case where a memory page is accessed by a plurality of processes, the life cycle of the memory page is related to the life cycles of the plurality of processes.

Alternatively, the time period from the start of the first process of the plurality of processes to the time when the last process of the plurality of processes is killed may be used as the life cycle of the memory page. Illustratively, as shown in fig. 10 (a), process a starts at time t1 and process B starts at time t 2. At time t3, the system memory is insufficient, triggering memory reclamation. At time t4, process A is killed and at time t5, process B is killed. At time t6, the system memory is insufficient, and memory reclamation is triggered again. After the process A and the process B are started, the memory page A and the memory page B are accessed for multiple times. The time period from the start of process A to the time process B is killed (i.e., time period t1-t 5) may be referred to as the life cycle of memory page A.

When judging whether to recycle the memory page A or not at this time, the electronic device can acquire the access times and the access intervals of the memory page A in the whole life cycle (namely, the time period t1-t 3), and calculate the activity degree of the memory page A in the time period t1-t3 according to the access times and the access intervals. After calculation, if the activity level of the memory page a is higher than the third threshold, the electronic device migrates the memory page a to the head of the active linked list, so as to prevent the memory page a from being recovered in a short time.

Alternatively, the time period from the start of the first process of the multiple processes to the current memory reclamation can be used as the life cycle of the memory page. For example, as shown in fig. 10 (b), the time period from the start of the process a to the current memory reclamation (i.e., time period t1-t 6) can be used as the life cycle of the memory page a. When judging whether to recycle the memory page A, the electronic device can acquire the access times and the access intervals of the memory page A in the whole life cycle (namely the time period t1-t 6), and calculate the activity degree of the memory page A in the time period t1-t6 according to the access times and the access intervals. After calculation, if the activity level of the memory page a is higher than the third threshold, the electronic device migrates the memory page a to the head of the active linked list, so as to prevent the memory page a from being recovered in a short time.

As shown in fig. 10 (c), the time period from the start of the process a to the current memory reclamation (i.e., time period t1-t 6) can be used as the life cycle of the memory page a. Unlike fig. 10 (B), in fig. 10 (c), the process B is not killed at this time of memory reclamation.

As shown in fig. 10 (d), the time period from the start of the process a to the current memory reclamation (i.e., time period t1-t 6) can be used as the life cycle of the memory page a. Unlike fig. 10 (B), in fig. 10 (c), neither process B nor process a is killed at this time of memory reclamation.

7-10 above mainly illustrate the meaning of the life cycle by taking the memory pages in the active linked list, the meaning of the life cycle of the memory pages in the inactive linked list can be referred to the related description of the life cycle of the memory pages in the active linked list, and the recovery process of the memory pages in the inactive linked list can be referred to the recovery process of the memory pages in the active linked list. Illustratively, as shown in fig. 11 (a), at time t1, process a starts. At time t2, the system memory is insufficient, triggering memory reclamation. At time t3, process A is killed. At time t4, the system memory is insufficient, and memory reclamation is triggered again. The life cycle of the memory page is assumed to be the time period between the times t1 and t3, and the memory page a is currently at the tail of the inactive linked list. In the embodiment of the application, the electronic device acquires the access times and the access intervals of the memory page A in the whole life cycle (namely, the time period t1-t3 shown in FIG. 11), and calculates the activity degree of the memory page A in the time period t1-t3 according to the access times and the access intervals. After calculating that the activity level of the memory page a is higher than the third threshold, which indicates that the memory page a is a frequently accessed memory page, as shown in (b) of fig. 11, the electronic device migrates the memory page a from the tail of the inactive linked list to the head of the active linked list, so as to avoid that the memory page a is reclaimed in a short time.

The method for calculating the activity level is described as follows. The electronic device may implement memory management based on virtual memory (virtual memory), and the electronic device may allocate virtual memory and physical memory to a process, where a mapping relationship (or called an association relationship) exists between a virtual address of the virtual memory of the process and a physical address of the physical memory. As a possible implementation manner, when the process applies to access a memory page, the access request carries a virtual address a 'of the memory page to be accessed, where the virtual address a' includes an offset (offset). The electronic equipment obtains the base address of the physical address A corresponding to the virtual address A 'by searching a page table, calculates the physical address A according to the base address and the offset in the virtual address A', addresses the physical address A of the memory page and accesses the memory page in the physical address A.

In the embodiment of the present application, the electronic device may record the access times of the virtual address a 'in the physical memory, as shown in fig. 12, where a variable x for representing the access times of the virtual address a' is stored in the physical memory corresponding to the physical address B, and the process applies to access the memory page in the physical memory corresponding to the physical address a each time, where the value of the variable x is increased by one.

In addition to recording the number of accesses to each virtual address, in the embodiment of the present application, the electronic device may also record an access period or an access interval of each virtual address. Alternatively, for a certain virtual address, the access interval of the virtual address may refer to the number of accesses that access the interval between the virtual address this time and the virtual address last time.

Illustratively, as in FIG. 13, the electronic device increments the total number of accesses by one each time a process is detected to access a memory page. Specifically, (1) detecting that a process accesses a virtual address a', wherein the total access times is n; (2) detecting a process access virtual address B', wherein the total access times are increased by one, and are n+ … (3), and the process access virtual address N is detected, and the total access times are increased by one, and are m-1; (4) the access virtual address a' is detected, and the total number of accesses is increased by one to m. In one example, the electronic device may use the interval m-n of times between two adjacent accesses to the same page as the access interval of the virtual address a'.

Alternatively, the access interval of a virtual address may refer to the time interval between two adjacent accesses to the virtual address. Illustratively, and still referring to FIG. 13, each time a process is detected to access a memory page, the electronic device records the timestamp of the access. Specifically, (1) detecting that a process accesses the virtual address A', and recording a time stamp t1 of the access; (2) detecting a process access virtual address B', recording a timestamp t2 … (3) of the current access, detecting a process access virtual address N, and recording a timestamp t3 of the current access; (4) the access virtual address a' is detected and the timestamp t4 of this access is recorded.

In one example, the electronic device may treat t4-t1 as the access interval (i.e., the time interval) of the virtual address A'.

In further examples, the electronic device may also count a plurality of time intervals and determine the access interval for the virtual address based on the plurality of time intervals. For example, the memory page is accessed M times during the entire life cycle, wherein the time interval between every two adjacent accesses is t ₁ 、t ₂ ，…，t _m-1 Then, the access interval Gap may be determined according to the following formula:

meaning that the access interval to the virtual address may be an average of the above-mentioned plurality of time intervals. Alternatively, in other examples, the access interval to the virtual address may be a maximum or minimum of the plurality of time intervals described above. Alternatively, the access interval to the virtual address may be other values determined by the plurality of time intervals described above.

Optionally, after the electronic device calculates the access times and the access intervals of the memory pages, the access times and/or the access intervals of the memory pages may be stored in a specific physical memory (for example, stored in the parameter storage space), so that the electronic device may read the access times and the access intervals of the memory pages from the specific physical memory. As a possible implementation manner, for a certain memory page, the electronic device may store the access times and access intervals of the memory page in a physical memory adjacent to the memory page, so as to facilitate subsequent reading of parameters. Alternatively, the electronic device may open up a single physical memory for storing the access times and access intervals of all memory pages.

After the electronic device obtains the above parameters (access times and/or access intervals) of the memory page, the electronic device may determine the activity level of the memory page according to the access times and access intervals of the memory page, and manage the memory page according to the activity level of the memory page. Illustratively, as shown in fig. 14, the electronic device obtains virtual addresses of memory pages on the inactive linked list by querying the page table. And then, according to the virtual addresses of the memory pages, inquiring the access times of the virtual addresses and the access intervals of the virtual addresses. Optionally, the electronic device may read the access times and the access intervals of each virtual address from the specific physical memory, and determine the activity level of each memory page according to the access times and the access intervals of each memory page. Alternatively, the Activity level Activity may be determined according to the following formula:

where time represents the number of accesses to the memory page over the life cycle and Gap represents the access interval.

After the activity degree of each memory page in the inactive linked list is calculated, the electronic device determines the memory page to be recycled based on the activity degree of each memory page. Optionally, the electronic device determines to reclaim memory pages having an activity level below a threshold. Or, alternatively, the electronic device determines to reclaim L (L is a positive integer) memory pages with the lowest activity.

Alternatively, L may be determined according to the following formula:

l=length; wherein length represents the length of the inactive linked list (which can be represented by the number of included memory pages), k represents a scaling factor smaller than 1, and the value of k can be flexibly adjusted according to the use scene.

The embodiment of the application also provides a memory recycling method, in which the electronic device determines the recyclable candidate memory pages (which can be simply called candidate recycling pages) first, and then determines the memory pages to be recycled and the memory pages not to be recycled from the candidate memory pages. The manner in which the electronic device determines the candidate recycle page may refer to other related techniques, for example, a memory page that is not accessed between two memory recycle, or a memory page that has a reduced access frequency is used as the candidate recycle page.

Illustratively, as shown in fig. 15 (a), at time t1, process a starts. At time t2, the system memory is insufficient, triggering memory reclamation. At time t3, process A is killed. At time t4, the system memory is insufficient, and memory reclamation is triggered again. Assume that the life cycle of memory page A, B is time period t1-t3.

As shown in fig. 15 (b), when memory reclaiming is performed at time t3, the electronic device may determine candidate memory pages that can be reclaimed according to the related art. Optionally, the electronic device uses the memory pages (including, for example, the memory page a and the memory page B) that are not accessed in the period of t2-t4 as candidate recycle pages. The electronic device may add the candidate memory pages to a temporary linked list.

Then, the electronic device calculates the activity degree of each candidate recycle page in the life cycle (namely, in t1-t 3), and inserts the candidate recycle page with the activity degree higher than a third threshold value into the head of the active linked list so as to prevent the false recycle of the candidate recycle page. Conversely, if the activity level of a certain candidate recycle page is lower than the fourth threshold value, the candidate recycle page is inserted into the head of the inactive linked list, which helps to accelerate the recycle progress of the candidate recycle page.

Wherein the third threshold is greater than or equal to the fourth threshold.

It should be noted that the electronic device may also determine the candidate memory page in other manners, which is not limited in this embodiment of the present application.

The embodiment of the application also provides a memory management method, wherein the electronic equipment can acquire the times and/or intervals of the memory pages accessed by the background process, and manage the memory pages according to the times and/or intervals of the memory pages accessed by the background process.

The background process refers to a process running in the background. For a process, it runs in the background for some period of time, during which the process may be referred to as a background process. During certain periods, where it is running in the foreground, the process may be referred to as a foreground process.

Optionally, if the number of times the memory page is accessed by the background process is greater than the fifth threshold and/or the interval between the memory page accesses by the background process is less than the sixth threshold, the electronic device uses the memory page as an important memory page, and does not recycle the memory page.

In some examples, if the memory page is a memory page in the inactive linked list and the number of times the memory page is accessed by the background process is greater than the fifth threshold, the electronic device does not migrate the memory page out of the inactive linked list, but may migrate the memory page to the head of the active linked list. Illustratively, as shown in fig. 16A (a) and (b), memory page a is at the end of the inactive linked list. In the period of t5-t3, the background process A calls the memory page A for a plurality of times (larger than a fifth threshold value), which means that the memory page A is an important memory page, and the electronic device does not recycle the memory page A, but can migrate the memory page A to the head of the active linked list so as to prevent the important memory page A from being recycled by mistake. Furthermore, since the important memory pages can be prevented from being recycled by mistake, or the probability of recycling the important memory pages by mistake is reduced, the normal operation of the background process can be ensured as much as possible, and the functions of the electronic equipment can be realized to the greatest extent.

In other examples, if the memory page is a memory page in the active linked list and the number of times the memory page is accessed by the background process is greater than the fifth threshold, the electronic device may not migrate the memory page to the inactive linked list, but may migrate the memory page to the head of the active linked list to prevent the memory page from being reclaimed in a short period of time.

Optionally, the electronic device may further calculate an activity level of the memory page according to the number of times and the interval that the memory page is accessed by the background process, and manage the memory page according to the activity level. For example, if the activity level of the memory page is less than the seventh threshold, the electronic device reclaims the memory page, and if the activity level of the memory page is greater than or equal to the seventh threshold, the electronic device does not reclaim the memory page.

It should be noted that, in fig. 16A, only one background process is illustrated as an example, and in other embodiments, multiple background processes may access the same or multiple memory pages during a period of time. Then, the electronic device may obtain the access times and/or intervals of the multiple background processes to the memory pages, and manage the memory pages according to the access times and/or intervals.

The embodiment of the application also provides a memory management method, wherein the electronic equipment can acquire the times and/or intervals of the memory pages accessed by the foreground process and manage the memory pages according to the times and/or intervals of the memory pages accessed by the foreground process.

Optionally, if the number of times the memory page is accessed by the foreground process is greater than the eighth threshold and/or the interval between the memory pages accessed by the foreground process is less than the ninth threshold, the electronic device uses the memory page as an important memory page, and does not recycle the memory page.

In some examples, if the memory page is a memory page in the inactive linked list and the number of times the memory page is accessed by the foreground process is greater than the eighth threshold, the electronic device may not migrate the memory page out of the inactive linked list, but may migrate the memory page to the head of the active linked list. Illustratively, as in (b) of FIG. 17, memory page A is at the end of the inactive linked list. In the period of t1-t5, the foreground process A calls the memory page A for a plurality of times (greater than an eighth threshold value), which means that the memory page A is an important memory page, and the electronic device does not recycle the memory page A, but can migrate the memory page A to the head of the active linked list so as to prevent the important memory page A from being recycled by mistake.

In other examples, if the memory page is a memory page in the active linked list and the number of times the memory page is accessed by the foreground process is greater than the eighth threshold, the electronic device may not migrate the memory page to the inactive linked list, but may migrate the memory page to the head of the active linked list to prevent the memory page from being reclaimed in the time that it needs to be accessed.

Optionally, the electronic device may further calculate the activity/jump level of the memory page according to the number and interval of access of the memory page by the foreground process, and manage the memory page according to the activity level. For example, if the activity level of the memory page is less than the tenth threshold, the electronic device reclaims the memory page, and if the activity level of the memory page is greater than or equal to the tenth threshold, the electronic device does not reclaim the memory page.

Optionally, the electronic device may also calculate candidate recycle pages before calculating the number of times and interval that the memory pages are accessed by the background process. For example, as shown in fig. 16B, the electronic device calculates candidate recycle pages according to the related art, and may add the candidate recycle pages to the temporary linked list. In general, memory pages in the candidate recycle page are memory pages used or accessed by a background process with a high probability, or, because the importance of the background process is not high, memory pages associated with the background process are recycled preferentially in memory recycling. And then, aiming at the candidate recovery pages in the temporary linked list, the electronic equipment calculates the times and/or intervals of the candidate recovery pages accessed by the background process, and manages the corresponding memory pages according to the access times and/or intervals. For example, for memory page a, in t5-t3, the number of times memory page a is accessed by a background process (e.g., background process a) is greater than a fifth threshold, indicating that memory page a is an important memory page for the operation of background process a. Then the electronic device migrates memory page a to the head of the active linked list, helping to delay important memory page a from being reclaimed. For memory page B, in t5-t3, the number of times memory page B is accessed by a background process (e.g., background process a) is less than a fifth threshold, indicating that memory page B is not a significant memory page for the operation of one or more background processes. Then the electronic device migrates the memory page B to the head of the inactive linked list, helping to expedite the reclamation of the non-important memory page B.

Optionally, before calculating the number of times and interval that the memory page is accessed by the foreground process, the electronic device may further calculate a candidate recycle page, and add the candidate recycle page to the temporary linked list. And then, aiming at the candidate recovery pages in the temporary linked list, the electronic equipment calculates the times and/or intervals of the candidate recovery pages accessed by the foreground process, and manages the corresponding memory pages according to the access times and/or intervals.

The embodiment of the application also provides a memory management method, wherein the electronic equipment can acquire the times and/or intervals of the memory pages accessed by the foreground process and the times and/or intervals of the memory pages accessed by the background process, and manage the memory pages according to the times and/or intervals of the memory pages accessed by the foreground process and the times and/or intervals of the memory pages accessed by the background process.

Optionally, if the number of times and/or the interval of the memory page accessed by the foreground process satisfies the second condition and the number of times and/or the interval of the memory page accessed by the background process satisfies the third condition, the electronic device takes the memory page as an important memory page, and does not recycle the memory page. Otherwise, the electronic device retrieves the memory page.

Optionally, the second condition includes: the number of times the memory page is accessed by the foreground process is greater than an eighth threshold, and the interval between the memory page accesses by the foreground process is less than a ninth threshold.

The third condition includes: the number of times the memory pages are accessed by the background process is greater than a fifth threshold, and the interval between the memory pages accessed by the background process is less than a sixth threshold.

Optionally, the electronic device may further calculate a first activity level of the memory page according to the number of times and the interval that the memory page is accessed by the foreground process, calculate a second activity level of the memory page according to the number of times and the interval that the memory page is accessed by the background process, and manage the memory page according to the first activity level and the second activity level. For example, if the first activity level of the memory page is less than the eleventh threshold and the second activity level of the memory page is less than the twelfth threshold, the electronic device reclaims the memory page, otherwise, the electronic device does not reclaim the memory page.

Illustratively, as in FIGS. 18 (a) and (b), memory page A is at the end of the inactive linked list. In the period of t1-t5, the foreground process A calls the memory page A for a plurality of times (more than an eighth threshold value), and in the period of t5-t3, the background process A calls the memory page A for a plurality of times (more than a fifth threshold value), which indicates that the memory page A is an important memory page, the electronic device does not recycle the memory page A, but can migrate the memory page A to the head of the active linked list so as to prevent the important memory page A from being recycled by mistake.

Optionally, before calculating the number of times and interval of access of the memory page by the foreground process and the number of times and interval of access of the memory page by the background process, the electronic device may further calculate the candidate recycle page, and add the candidate recycle page to the temporary linked list. And then, aiming at the candidate recovery pages in the temporary linked list, the electronic equipment calculates the times and intervals of the candidate recovery pages accessed by the foreground process and the times and intervals of the candidate recovery pages accessed by the background process, and manages the corresponding memory pages according to the access times and/or intervals.

The memory management method of the embodiment of the application can be applied to the process of recovering anonymous pages, and can be applied to the process of recovering other types of pages, and the embodiment of the application is not limited to the process.

Fig. 19 shows a further process of the memory management method according to the embodiment of the present application. The method is applied to the electronic equipment, the electronic equipment comprises a first linked list, the first linked list comprises a plurality of pages, and the method comprises the following steps:

s101, the electronic device acquires the access times and/or access intervals of the first page in the first linked list in the first period.

Wherein the first period is a lifecycle of a process associated with the first page; the plurality of pages includes the first page.

Optionally, the processes associated with the first page are one or more.

Optionally, in the case that the process is one, the first period starts from a start time of the process to a closing time of the process; or, the first period starts from the starting time of the process to the end of the first time.

Illustratively, as in (a) of FIG. 7, process A accesses memory page A, i.e., the process associated with memory A is process A. The first cycle starts from the start time (t 1) of the process a to the end of the shutdown time (t 3) of the process a.

As another example, as shown in fig. 8 (a), the first cycle starts from the start time (t 1) of the process a to the end of the present memory reclamation time (first time t 4).

Optionally, when the processes are plural, the first period starts from a start time of a process started earliest among the plural processes to a close time of a process closed latest among the plural processes, or the first period starts from a start time of a process started earliest among the plural processes to the first time.

Illustratively, as in (a) of FIG. 10, process A, B accesses memory page A, i.e., the process associated with memory also A is process A, B. The first cycle starts from the start time (t 1) of the earliest started process a to the end of the shut down time (t 5) of the latest shut down process B.

As another example, as shown in fig. 10 b, the first cycle starts from the start time (t 1) of the process a to the end of the present memory reclamation time (first time t 6).

Optionally, the first period includes a period in which the process runs in the background and/or a period in which the process runs in the foreground.

Illustratively, as in (a) of FIG. 16A, the first cycle is the background run period (t 5-t 3) of process A.

Illustratively, as in (a) of FIG. 17, the first cycle is the foreground run period (t 1-t 5) of process A.

As a possible implementation manner, obtaining the access times and/or access intervals of the first page in the first linked list in the first period includes: and at a first moment, acquiring the access times and/or access intervals of the first page in the first linked list in the first period.

S102, the electronic equipment migrates the first page according to the access times and/or the access intervals.

As a possible implementation manner, in the case that the first linked list is an active linked list, if the access times and/or the access intervals meet a first condition, migrating the first page to a head of the first linked list; otherwise, the first page is migrated from the first linked list to the head of a second linked list; wherein the second linked list is an inactive linked list.

If the access times and/or the access intervals meet a first condition under the condition that the first linked list is an inactive linked list, migrating the first page from the first linked list to the head of a second linked list; otherwise, the first page is migrated from the first linked list to a memory recycling area; the second linked list is an active linked list, and the memory recovery area comprises the following areas: compression space, disk space, free space.

Optionally, the first condition includes any one or more of the following conditions:

In some aspects, various embodiments of the application may be combined and the combined aspects implemented. Optionally, some operations in the flow of method embodiments are optionally combined, and/or the order of some operations is optionally changed. The order of execution of the steps in each flow is merely exemplary, and is not limited to the order of execution of the steps, and other orders of execution may be used between the steps. And is not intended to suggest that the order of execution is the only order in which the operations may be performed. Those of ordinary skill in the art will recognize a variety of ways to reorder the operations described herein. In addition, it should be noted that details of processes involved in a certain embodiment herein apply to other embodiments as well in a similar manner, or that different embodiments may be used in combination.

Moreover, some steps in method embodiments may be equivalently replaced with other possible steps. Alternatively, some steps in method embodiments may be optional and may be deleted in some usage scenarios. Alternatively, other possible steps may be added to the method embodiments.

Moreover, the method embodiments may be implemented alone or in combination.

It will be appreciated that, in order to implement the above-mentioned functions, the electronic device in the embodiment of the present application includes corresponding hardware structures and/or software modules for performing the respective functions. The various illustrative units and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or a combination of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application, but such implementation is not to be considered as beyond the scope of the embodiments of the present application.

The embodiment of the application can divide the functional units of the electronic device according to the method example, for example, each functional unit can be divided corresponding to each function, and two or more functions can be integrated in one processing unit. The integrated units may be implemented in hardware or in software functional units. It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice.

Fig. 20 is a schematic block diagram of a memory management device according to an embodiment of the present application, where the device may be the first electronic device or a component with a corresponding function. The apparatus 1700 may exist in the form of software or as a chip that may be used in a device. The apparatus 1700 includes: a processing unit 1702. The processing unit 1702 may be used to support S101, S102, etc. shown in fig. 19, and/or for other processes of the schemes described herein.

Optionally, the apparatus 1700 may further comprise a communication unit 1703. Alternatively, the communication unit 1703 may be further divided into a transmission unit (not shown in fig. 20) and a reception unit (not shown in fig. 20). The sending unit is configured to enable the apparatus 1700 to send information to other electronic devices. A receiving unit for supporting the apparatus 1700 to receive information from other electronic devices.

Optionally, the apparatus 1700 may further include a storage unit 1701 for storing program codes and data of the apparatus 1700, and the data may include, but is not limited to, raw data or intermediate data, etc.

In one possible approach, the processing unit 1702 may be a controller or the processors 401 and/or 408 shown in fig. 4, such as a central processing unit (Central Processing Unit, CPU), general purpose processor, digital signal processing (Digital Signal Processing, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, transistor logic device, hardware components, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules and circuits described in connection with this disclosure. A processor may also be a combination that performs computing functions, e.g., including one or more microprocessors, a combination of a DSP and a microprocessor, and so forth.

In one possible implementation, the communication unit 1703 may include the transceiver 404 shown in fig. 4, and may also include transceiver circuitry, radio frequency devices, and the like.

In one possible approach, the memory unit 1701 may be the memory 403 shown in fig. 4.

The embodiment of the application also provides electronic equipment which comprises one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, the one or more memories being operable to store computer program code comprising computer instructions that, when executed by the one or more processors, cause the electronic device to perform the relevant method steps described above to implement the methods of the embodiments described above.

The embodiment of the application also provides a chip system, which comprises: a processor coupled to a memory for storing programs or instructions which, when executed by the processor, cause the system-on-a-chip to implement the method of any of the method embodiments described above.

Alternatively, the processor in the system-on-chip may be one or more. The processor may be implemented in hardware or in software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, or the like. When implemented in software, the processor may be a general purpose processor, implemented by reading software code stored in a memory.

Alternatively, the memory in the system-on-chip may be one or more. The memory may be integral with the processor or separate from the processor, and the application is not limited. The memory may be a non-transitory processor, such as a ROM, which may be integrated on the same chip as the processor, or may be separately provided on different chips, and the type of memory and the manner of providing the memory and the processor are not particularly limited in the present application.

The system-on-chip may be, for example, a field programmable gate array (field programmable gatearray, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a central processing unit (central processorunit, CPU), a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip.

It should be understood that the steps in the above-described method embodiments may be accomplished by integrated logic circuitry in hardware in a processor or instructions in the form of software. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on an electronic device, cause the electronic device to perform the related method steps described above to implement the method in the embodiments described above.

Embodiments of the present application also provide a computer program product which, when run on a computer, causes the computer to perform the above-described relevant steps to implement the methods of the above-described embodiments.

In addition, embodiments of the present application also provide an apparatus, which may be a component or module in particular, which may include a processor and a memory connected; the memory is configured to store computer-executable instructions, and when the apparatus is running, the processor may execute the computer-executable instructions stored in the memory, so that the apparatus performs the methods in the method embodiments described above.

The electronic device, the computer readable storage medium, the computer program product or the chip provided by the embodiments of the present application are used to execute the corresponding method provided above, so that the beneficial effects thereof can be referred to the beneficial effects in the corresponding method provided above, and will not be described herein.

It will be appreciated that in order to achieve the above-described functionality, the electronic device comprises corresponding hardware and/or software modules that perform the respective functionality. The present application can be implemented in hardware or a combination of hardware and computer software, in conjunction with the example algorithm steps described in connection with the embodiments disclosed herein. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application in conjunction with the embodiments, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The present embodiment may divide the functional modules of the electronic device according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules described above may be implemented in hardware. It should be noted that, in this embodiment, the division of the modules is schematic, only one logic function is divided, and another division manner may be implemented in actual implementation.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.

In the several embodiments provided in the present application, it should be understood that the disclosed method may be implemented in other manners. For example, the above-described embodiments of the terminal device are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via interfaces, modules or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in whole or in part in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) or a processor to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.

The foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory management method, wherein the method is applied to an electronic device, the electronic device includes a first linked list, the first linked list includes a plurality of pages, and the method includes:

acquiring access times and/or access intervals of a first page in the first linked list in a first period; the first period is the life cycle of the process associated with the first page; the plurality of pages includes the first page;

and according to the access times and/or the access intervals, migrating the first page.

2. The method of claim 1, wherein the processes associated with the first page are one or more.

3. The method according to claim 1 or 2, wherein the first period comprises a period in which the process is running in the background and/or a period in which the process is running in the foreground.

4. The method according to claim 1 or 2, wherein obtaining the number of accesses and/or the access interval of the first page in the first linked list in the first period comprises: at a first moment, acquiring access times and/or access intervals of a first page in a first linked list in a first period;

5. The method according to claim 1 or 2, wherein obtaining the number of accesses and/or the access interval of the first page in the first linked list in the first period comprises: at a first moment, acquiring access times and/or access intervals of a first page in a first linked list in a first period;

6. The method according to any one of claims 1-5, wherein migrating the first page according to the number of accesses and/or the access interval comprises:

in the case where the first linked list is an active linked list,

wherein the second linked list is an inactive linked list.

7. The method according to any one of claims 1-5, wherein migrating the first page according to the number of accesses and/or the access interval comprises:

in the case where the first linked list is an inactive linked list,

8. The method of claim 6 or 7, wherein the first condition comprises any one or more of the following conditions:

9. The method according to any one of claims 1-8, wherein obtaining the number of accesses and/or the access interval of the first page in the first linked list in the first period comprises:

10. The method according to any of claims 1-9, wherein migrating the first page according to the number of accesses and/or the access interval comprises: and under the condition that the first page is positioned at the tail part of the first linked list, migrating the first page according to the access times and/or the access intervals.

11. The method according to any of claims 1-10, wherein the access interval is used to characterize a time interval between two adjacent accesses to the first page or a time interval between two adjacent accesses to the first page.

12. An electronic device, comprising: a processor and a memory coupled to the processor, the memory for storing computer program code, the computer program code comprising computer instructions, the processor reading the computer instructions from the memory to cause the electronic device to perform the method of any of claims 1-11.

13. A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of claims 1-11.

14. A computer program product, characterized in that the computer program product, when run on an electronic device, causes the electronic device to perform the method of any of claims 1-11.