CN116860329A - Compiling optimization method based on logical operation linear reconstruction - Google Patents

Abstract

The invention discloses a compiling optimization method based on logical operation linear reconstruction, which comprises the following steps: the compiler generates a plurality of intermediate expressions with logic operation marks; detecting whether the current basic block has an intermediate expression or not, and optimizing the current basic block; completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization; the invention aims at complex logic operation scene, when effective operands meet a certain number of constraints, the complex logic operation sequence is changed into a group of simplified logic recombination operation sequence by combining logic recombination instructions provided by a processor, and the automatic combination and optimization of the whole basic block logic instructions are realized. The method greatly saves the performance overhead caused by frequent logic operation, thereby improving the performance of related scenes.

Description

Compiling optimization method based on logical operation linear reconstruction

Technical Field

The invention belongs to the technical field of logic operation of a computer compiler, and particularly relates to a compiling optimization method based on linear reconstruction of logic operation.

Background

Logical operations are quite common in programs, and currently mainstream processors have a certain support for conventional logical operations, such as and, or, not, and the like. The compiler can identify the logic operation scene in the program through lexical and grammatical analysis to generate intermediate expression, and then generate corresponding AND, OR, NOT etc. logic operation instructions through the middle end and the back end for processing.

The conventional logic operation optimization method for the compiler mainly comprises the following steps: firstly, redundant deletion, namely eliminating redundant logic operation by utilizing a conventional peeping hole optimization technology, and eliminating logic operation which has no influence on the result by analyzing the logic relation among programs, so as to optimize the locality of the logic operation; based on simple logic combination instructions supported by a processor, such as NAND, NOR and the like, a compiler combines the simple logic combination instructions into the simple logic combination instructions by identifying logic operations conforming to a plurality of single functions under the condition that conditions are met; and thirdly, replacing instructions, and realizing logic operation combination aiming at certain special functions by adopting other efficient instructions.

With the increasing complexity of applications, especially the increasing complexity of algorithms in related fields, the combination of logic operations is more and more diversified, and in the prior art, a large number of linear logic operation combinations exist in applications in fields of security encryption and decryption, data storage and the like. When the number of the operands is relatively large, on the one hand, the optimization method of redundancy deletion and simple combination is adopted, and when the algorithm logic does not have redundancy operation, the original operation amount cannot be greatly reduced only by simple logic operation combination, and the optimization effect is limited; on the other hand, instruction substitution is effective only for specific scenes, and the optimization surface is relatively narrow; furthermore, the conventional peeping hole optimization technology has a certain limitation, the optimization range is only local, and an efficient compiling strategy is difficult to find through a complex dependency relationship, so that the performance optimization space is limited.

Disclosure of Invention

The invention aims to provide a compiling optimization method based on linear reconstruction of logical operation, which aims to solve the technical problem that in the prior art, when redundant operation does not exist in arithmetic logic, the original operation amount cannot be greatly reduced only by simple logical operation combination.

In order to achieve the above purpose, the present invention provides the following technical solutions:

the invention provides a compiling optimization method based on logical operation linear reconstruction, which comprises the following steps:

the compiler generates a plurality of intermediate expressions with logic operation marks;

detecting whether the current basic block has an intermediate expression or not, and optimizing the current basic block;

completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization;

and continuing to execute the subsequent optimization, and finally outputting the optimized reorganization instruction.

Optionally, the compiler optimizes according to the following steps, specifically including:

step S1: detecting whether an intermediate expression with a logic operation mark exists in the current basic block;

if so, the process proceeds to step S2, and if not, the process proceeds to step S9.

Optionally, the step S2 specifically includes:

step S2: saving source and destination operands and logical operators of the operation;

optionally, the step S2: storing source and destination operands and a logical operator of the operation, and continuing to step S3 after proceeding to step S2, wherein step S3 specifically includes:

step S3: detecting whether an intermediate expression with a logic operation mark exists in the next strip;

if so, the process proceeds to step S4, and if not, the process proceeds to step S9.

Optionally, the step S4 specifically includes:

step S4: detecting whether a source operand of the logic operation is the same as a destination operand of the previous logic operation;

if the two are the same, the process proceeds to step S5, and if the two are not the same, the process returns to step S3.

Optionally, the step S5 specifically includes:

step S5: detecting whether a correlation exists in an intermediate expression between the logical operation and a previous logical operation;

if yes, go to step S6, if no, return to step S3.

Optionally, the step S6 specifically includes:

step S6: calculating an 8-bit result parameter of the logic reorganization instruction, and merging two logic operations into an intermediate expression of a bit-stripe logic reorganization mark;

after entering step S6, the method continues to step S7, where step S7 specifically includes:

step S7: detecting whether other operations related to the intermediate expression with the logic recombination mark do not exist;

if not, finishing logic reorganization optimization of the current group of logic operation, entering step S8, and if so, returning to step S6.

Optionally, the step S8 specifically includes:

step S8: detecting whether other intermediate expressions with logic operation marks do not exist;

if not, the process proceeds to step S9, and if so, the process returns to step S2.

Optionally, the step S9 specifically includes:

step S9: completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization;

step 10 is performed in the next basic block, where step 10 specifically includes:

step 10: detecting whether the next basic block which is currently entered is empty;

if the signal is empty, the process proceeds to step S11, and if the signal is not empty, the process returns to step S1.

Optionally, the step 11 specifically includes:

step 11: and continuing to execute the subsequent optimization, and finally outputting the optimized logic reorganization instruction.

The invention has the beneficial effects and advantages that:

the compiling optimization method based on the logical operation linear reconstruction generates a plurality of intermediate expressions with logical operation marks through a compiler, and enters the next basic block for optimization after detecting and optimizing the intermediate expressions until all optimization is completed. The method greatly saves the performance overhead caused by frequent logic operation, thereby improving the performance of related scenes.

Drawings

FIG. 1 is a schematic flow chart of a compiling optimization method according to the present invention;

FIG. 2 is a flowchart of the compile optimization step of the present invention;

FIG. 3 is a schematic diagram of the conversion process from a multi-element operation expression to a binary operation expression according to the present invention;

FIG. 4 is a graph of the results of an operation with three operands according to the present invention;

FIG. 5 is a schematic diagram of a truth table transformation process according to the present invention;

FIG. 6 is a graph showing the results of instruction optimization according to the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.

An embodiment, as shown in fig. 1 and fig. 2, provides a compiling optimization method based on logical operation linear reconstruction, which includes: the compiler generates a plurality of intermediate expressions with logic operation marks; detecting whether the current basic block has an intermediate expression or not, and optimizing the current basic block; completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization; and continuing to execute the subsequent optimization, and finally outputting the optimized reorganization instruction.

Referring to fig. 1, 2 and 3, in this embodiment, the front end of the compiler generates a plurality of intermediate expressions with logic operation marks according to the method and the logic operation scene in the syntax analysis program, and then enters a logic recombination optimization pass, wherein the conversion process is shown in fig. 2, and the compiler performs step S1 according to the generated intermediate expressions: detecting whether an intermediate expression with a logical operation mark exists in the current basic block: wherein the intermediate expression also includes and, or, not, exclusive or, etc.;

in this embodiment, if in step S1, the current basic block has an intermediate expression with a logic operation flag, the step S2 is entered, and if not, the step S9 is entered;

step S2 and step S9 are respectively expressed as:

step S2: saving source and destination operands and logical operators of the operation;

step S9: completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization;

in this embodiment, after step S2 is completed, step S3 is performed, where step S3 specifically includes:

step S3: detecting whether an intermediate expression with a logic operation mark exists in the next strip;

if yes, the step S4 is carried out, and if not, the step S9 is carried out;

step S4: detecting whether a source operand of the logic operation is the same as a destination operand of the previous logic operation;

if the two types of information are the same, the step S5 is carried out, and if the two types of information are not the same, the step S3 is returned to;

step S5: detecting whether a correlation exists in an intermediate expression between the logical operation and a previous logical operation;

if yes, the step S6 is carried out, and if no, the step S3 is returned to;

referring to fig. 3, in this embodiment, the front end of the compiler recognizes the logic operation scene in the program according to lexical and grammatical analysis, and splits the multi-element operation expression into binary operation expressions.

Referring to fig. 4 and 5, in the present embodiment, 8 operation results (truth tables) of three operands are calculated according to different logical operators, wherein the truth tables are calculated as follows:

taking two logical operations, or ' and ' exclusive or ', as an example: (a|b)/(c);

because of bitwise operation, one of the truth tables of result bits is arranged from high order to low order to be 0x56, and ternary logic operation is only needed to find the result corresponding to the immediate 0x56 (86) according to the combination of 1 bit of each parameter;

the conversion process of the truth table is as follows, according to the total value 86 (decimal, hexadecimal is 0x 56) of all possible operation results of a.0_1, b.1_2 and c.2_4 in the truth table, the 86 is used as a parameter to generate a logic recombination built-in function with a table look-up function, and then a corresponding conversion result is obtained;

step S6: combining the result as an operand of a relogxx (logic reorganization instruction) to generate an intermediate expression with a logic reorganization mark;

after the step S6 is finished, the process proceeds to a step S7, where the step S7 specifically includes:

step S7: detecting whether other operations related to the intermediate expression with the logic recombination mark do not exist;

if not, finishing logic reorganization optimization of the current group of logic operation, entering step S8, and if so, returning to step S6;

step S8: detecting whether other intermediate expressions with logic operation marks do not exist;

if not, the step S9 is carried out, and if so, the step S2 is returned to;

step S9: completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization;

step 10 is performed in the next basic block, where step 10 specifically includes:

step 10: detecting whether the next basic block which is currently entered is empty;

if the air is empty, the method proceeds to step S11, and if the air is not empty, the method returns to step S1;

step S11: and continuing to execute the subsequent optimization, and finally outputting the optimized logic reorganization instruction.

Referring to fig. 6, in this embodiment, an optimized logic reorganization instruction is finally output, and the instruction optimization change is shown in fig. 6, and in this embodiment, for a complex logic operation scene, when the effective operand satisfies a certain number of constraints, a complex logic operation sequence is changed into a group of simplified logic reorganization operation sequences by combining with a logic reorganization instruction provided by a processor, so as to realize automatic combination and optimization of the logic instruction of the whole basic block. The method greatly saves the performance overhead caused by frequent logic operation, thereby improving the performance of related scenes.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are all within the protection of the present invention.

Claims (10)

1. A compiling optimization method based on logical operation linear reconstruction is characterized by comprising the following steps:

the compiler generates a plurality of intermediate expressions with logic operation marks;

detecting whether the current basic block has an intermediate expression or not, and optimizing the current basic block;

completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization;

and continuing to execute the subsequent optimization, and finally outputting the optimized reorganization instruction.

2. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 1, wherein: the compiler realizes optimization according to the following steps:

step S1: detecting whether an intermediate expression with a logic operation mark exists in the current basic block;

if so, the process proceeds to step S2, and if not, the process proceeds to step S9.

3. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 2, wherein: the step S2 specifically includes:

step S2: the source and destination operands of the operation and the logical operator are saved.

4. A compiling optimization method based on logical operation linear reconstruction according to claim 3, wherein: the step S2: storing source and destination operands and a logical operator of the operation, and continuing to step S3 after proceeding to step S2, wherein step S3 specifically includes:

step S3: detecting whether an intermediate expression with a logic operation mark exists in the next strip;

if so, the process proceeds to step S4, and if not, the process proceeds to step S9.

5. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 4, wherein: the step S4 specifically includes:

step S4: detecting whether a source operand of the logic operation is the same as a destination operand of the previous logic operation;

if the two are the same, the process proceeds to step S5, and if the two are not the same, the process returns to step S3.

6. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 5, wherein: the step S5 specifically includes:

step S5: detecting whether a correlation exists in an intermediate expression between the logical operation and a previous logical operation;

if yes, go to step S6, if no, return to step S3.

7. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 6, wherein: the step S6 specifically includes:

step S6: calculating an 8-bit result parameter of the logic reorganization instruction, and merging two logic operations into an intermediate expression of a bit-stripe logic reorganization mark;

after entering step S6, the method continues to step S7, where step S7 specifically includes:

step S7: detecting whether other operations related to the intermediate expression with the logic recombination mark do not exist;

if not, finishing logic reorganization optimization of the current group of logic operation, entering step S8, and if so, returning to step S6.

8. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 7, wherein: the step S8 specifically includes:

step S8: detecting whether other intermediate expressions with logic operation marks do not exist;

if not, the process proceeds to step S9, and if so, the process returns to step S2.

9. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 8, wherein: the step S9 specifically includes:

step S9: completing all logic operation linear reconstruction compiling optimization of the current basic block, and entering the next basic block optimization;

step 10 is performed in the next basic block, where step 10 specifically includes:

step 10: detecting whether the next basic block which is currently entered is empty;

if the signal is empty, the process proceeds to step S11, and if the signal is not empty, the process returns to step S1.

10. The compiling optimization method based on the linear reconstruction of the logical operation according to claim 9, wherein: the step 11 specifically includes:

step 11: and continuing to execute the subsequent optimization, and finally outputting the optimized logic reorganization instruction.