CN116860323A - P4-based compiling and FPGA configuration method - Google Patents
P4-based compiling and FPGA configuration method Download PDFInfo
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Abstract
The invention discloses a P4-based compiling and FPGA configuration method, which comprises the following steps: the compiling configuration tool (P4-fpga-combo-config) integrates a compiling module (P4-fpga-combo) and a configuration module set (P4-fpga-config-xxx); the compiling module compiles the p4 source file into three configuration data of a state path, a matching operation and field modification which can be identified by the FPGA, and generates a transmitting configuration data linked list; compiling a configuration tool to support a plurality of physical channel configuration modes, and calling corresponding configuration modules in a configuration module set according to the configuration channels; the configuration module reads the configuration data and sends the configuration data to the FPGA, and after the configuration data is completely and successfully sent, the configuration module sends a message to inform the FPGA that the configuration data takes effect; the configuration data transmission and message interaction between the configuration module and the FPGA need to be conducted through escape coding and decoding and CRC checking.
Description
Technical Field
The invention belongs to the field of computer networks, and particularly relates to a P4-based compiling and FPGA configuration method.
Background
In the era of requiring faster network speed, larger storage space and stronger data processing, the computing power and flexibility of use of the conventional network card are becoming weaker in terms of service requirements. In order to meet the demands of storage, calculation and data center network processing, intelligent network equipment capable of reducing the load of a CPU, improving the calculation efficiency, having calculation capability and flexible and programmable functions is generated.
At present, the design of the intelligent network card mainly comprises two modes; 1. a multi-core intelligent network card based on an Application Specific Integrated Circuit (ASIC) comprising a plurality of CPU cores; 2. an intelligent network card based on a Field Programmable Gate Array (FPGA). However, the multi-core intelligent network card is limited by at least two constraints: 1. based on software programmable processors, they are slower when used for network processing due to lack of processor parallelism; 2. the lack of programmability and flexibility of the intelligent network card in the data plane is caused by the fixed function hardware engine. These two points are the advantages specific to the FPGA, so the intelligent network card based on the FPGA will be the mainstream in the future.
The university of Stenford study team of Nick McKeown leaded in 2014 proposes a P4 network programming language, and the protocol independent forwarding technology represented by P4 (Programming Protocol-Independent Packet Processors, programmable protocol independent data packet processor) realizes definition of forwarding resources, which is mainly used on network devices such as network cards, switches, routers and the like, and allows user programming to control forwarding behavior of messages in a data plane. Over the last 10 years of development, P4 has become a virtually standard programming language in the field of web applications. P4 is an open source, and the development efficiency of P4 for network application business is improved by orders of magnitude compared with the programming language of the circuit behavior level such as Verilog/VHDL or the general-purpose computing programming language such as C/C++ aiming at the special programming language of the network behavior level.
At present, most of network data forwarding functions of intelligent network cards based on FPGA are fixed during encoding, recoding and downloading are needed during function modification, and the intelligent network cards have certain limitation in flexible programmable playing. The functions of analyzing real-time configuration information and forwarding network data according to the configuration information are realized in the FPGA, and the problems can be solved. Therefore, designing a set of practical and effective tools for compiling and configuring the P4 source file to the FPGA is a key point for realizing the flexible programmable function based on the FPGA intelligent network card.
Disclosure of Invention
In view of the above, the present invention aims to provide a compiling and FPGA configuration method based on P4, defining a network data forwarding rule by P4, compiling a binary configuration file identifiable by an FPGA by a specific compiler, supporting a multi-channel issuing mode, and issuing the configuration file to the FPGA to realize a flexible and variable programmable function.
In order to achieve the above object, the method for compiling and configuring an FPGA based on P4 provided by the embodiment of the present invention includes the following steps:
(1) The P4-fpga-common-config compiling and configuring tool integrates a P4-fpga-common compiling module and a P4-fpga-config-xxx configuring module set, and receives a P4 source file and configuration parameters to be compiled and configured;
(2) The P4-FPGA-common compiling module compiles the P4 source file into three types of configuration data including a state path which can be identified by the FPGA, matching operation and field modification, and generates a transmitting configuration data linked list according to a designated configuration mode;
(3) The P4-fpga-config compiling and configuring tool supports a multi-physical channel configuration mode, and corresponding configuration modules are called in the P4-fpga-config-xxx configuration module set according to the designated configuration channels;
(4) The configuration module reads the configuration data in the configuration data link list and sends the configuration data to the FPGA, the FPGA successfully receives the configuration data and stores the configuration data in the cache link list, and the configuration module sends a message to inform the FPGA that the configuration data is effective after the configuration data is completely and successfully sent, wherein both the configuration data sending and the message interaction of the configuration module and the FPGA need escape encoding and decoding and CRC check processing.
Further, the P4-fpga-config-xxx configuration module set comprises five configuration modules, namely P4-fpga-config-usb, P4-fpga-config-pcie, P4-fpga-config-uart, P4-fpga-config-i2c and P4-fpga-config-spi, corresponding to the configuration methods of the five physical channels of usb, PCIe, uart, i c and spi respectively.
Further, the received configuration parameters include:
A forced configuration flag parameter, wherein a forced configuration flag parameter of 1 indicates a forced full configuration mode, and a forced configuration flag parameter of 0 indicates an incremental configuration mode;
the configuration channel between the configuration module and the FPGA, wherein the configuration channel is 1, a usb device configuration channel is required to be input simultaneously, the configuration channel is 2, a PCIe device configuration channel is required to be input simultaneously, the configuration channel is 3, a uart device configuration channel is required to be input simultaneously, the configuration channel is 4, an i2c device configuration channel is required to be input simultaneously, an i2c device number and an i2c address are required to be input simultaneously, the configuration channel is 5, a spi device configuration channel is required to be input simultaneously, and the spi device number is required to be input simultaneously.
Further, the step (2) comprises the following specific steps:
(2.1) the front-end and middle-end compiling functions of the P4-fpga-common compiling module compile the P4 source file into intermediate representation layer information and store the intermediate representation layer information in a tree structure cache;
(2.2) traversing intermediate representation layer information of a tree structure cache by an FPGA (field programmable gate array) rear-end compiling function of the P4-FPGA-common compiling module, carrying out data extraction according to the functional module, generating three types of configuration data including a state path, a matching operation and field modification, wherein the state path type represents the configuration data of all state paths of a network message, the matching operation type represents the configuration data for executing corresponding operation according to a keyword matched with the network message to achieve a message forwarding function, and the field modification type represents the configuration data for executing field insertion and/or deletion operation at a designated position of the network message;
(2.3) the P4-fpga-common compiling module calls the incremental configuration function module to generate the three types of configuration data into a transmission configuration data linked list.
Further, the step (2.3) comprises the following specific steps:
(2.3.1) creating a save send configuration data linked list, and executing steps (2.3.2) -2.3.8) on the three types of configuration data of the state path, the matching operation and the field modification generated by compiling respectively;
(2.3.2) applying for storing the current cache of the current configuration data, and storing the compiled configuration data to the current cache by the P4-fpga-common compiling module, and obtaining the length of the current configuration data;
(2.3.3) judging whether the forced configuration flag parameter is 1, if not, executing the step (2.3.4), and if yes, executing the step (2.3.7);
(2.3.4) traversing a folder for storing the previous configuration data, searching whether the configuration file corresponding to the configuration data exists or not, if yes, executing the step (2.3.5), otherwise, executing the step (2.3.7);
(2.3.5) obtaining a configuration file corresponding to the configuration data and the configuration data length thereof, comparing whether the configuration data length is equal to the current configuration data length obtained in the step (2.3.2), if yes, executing the step (2.3.6), otherwise, executing the step (2.3.7);
(2.3.6) applying for storing another cache of the configuration file, reading the data content of the configuration file, storing the data content in the other cache, comparing whether the cache content of the other cache is equal to the cache content of the current cache in the step (2.3.2), otherwise, executing the step (2.3.7), and releasing the current cache and the other cache and exiting the configuration data transmission;
(2.3.7) inserting the current buffer into the transmission configuration data linked list, and releasing the other buffer;
(2.3.8) generating corresponding configuration files from the cached content of the current cache, and storing or replacing the corresponding configuration files in the folder, wherein three types of configuration data are stored in the folder in a classified mode.
Further, in the step (4), the configuration data transmission and message processing of the configuration module side includes the following specific steps:
(4.1.1) the configuration module polls the transmission configuration data linked list and judges whether the configuration data in the configuration data linked list is transmitted completely, if yes, the step (4.1.3) is executed, otherwise, the step (4.1.2) is executed;
(4.1.2) the configuration module obtains the current polling to the current buffer memory of the configuration data from the linked list of the transmission configuration data, processes the buffer memory data therein and then transmits the processed buffer memory data to the FPGA, and then executes the step (4.1.4);
(4.1.3) the configuration module sending a message validating the FPGA configuration data, and then performing step (4.1.4);
(4.1.4) defining the timeout time of waiting for the FPGA message, enabling the configuration module to enter a state of waiting for the FPGA message to return, judging whether the FPGA message is received within the timeout time of waiting for the FPGA message, if yes, executing the step (4.1.5), otherwise, executing the step (4.1.7);
(4.1.5) the configuration module receives the FPGA message, judges whether the message receiving process is wrong, if yes, executes the step (4.1.7), otherwise, executes the step (4.1.6);
the configuration module analyzes the received FPGA message, and the step (4.1.7) is executed when the received FPGA message is judged to be an invalid message, an FPGA receiving data error message or an FPGA configuration validation failure message, the step (4.1.1) is executed when the received configuration data message is judged to be successful, and the step (4.1.8) is executed when the received configuration data message is judged to be successful;
(4.1.7) the configuration module exits abnormally, and returns a configuration error prompt to the P4-fpga-common-config compiling configuration tool;
and (4.1.8) the configuration module successfully completes the configuration data transmission and takes the FPGA configuration into effect, and simultaneously returns a configuration success prompt to the P4-FPGA-combole-config compiling configuration tool.
Further, in the step (4), the configuration data receiving and message processing on the FPGA side includes the following specific steps:
(4.2.1) the FPGA applies for receiving a cache list of configuration data, and defines the overtime of the configuration module to send the data;
(4.2.2) the FPGA acquires the data sent by the configuration module, judges whether the data is received within a time-out time shorter than the sending data, if yes, executes the step (4.2.3), otherwise, executes the step (4.2.7);
(4.2.3) after the FPGA receives and obtains the complete data or the message, judging whether an error occurs in the receiving process, if so, executing the step (4.2.8), otherwise, executing the step (4.2.4);
(4.2.4) the FPGA analyzes the received data or information, and the step (4.2.5) is executed if the FPGA configuration validation information is judged, the step (4.2.8) is executed if the FPGA configuration validation information is judged, and the step (4.2.7) is executed if the FPGA configuration validation information is judged to be invalid;
(4.2.5) the FPGA sends the successfully received configuration data message to the configuration module, and inserts the received configuration data into a cache linked list;
(4.2.6) the FPGA judges whether the cache linked list is empty, if yes, the step (4.2.2) is executed, otherwise, the step (4.2.7) is executed;
(4.2.7) the FPGA sends a data error message to the FPGA, clears the cache linked list and executes the step (4.2.2);
(4.2.8) the FPGA polls the buffer linked list to assign configuration data to the corresponding functional module, and the module is restarted to enable the configuration to be effective, and the buffer linked list is emptied, if yes, the step (4.2.9) is executed, and if no, the step (4.2.10) is executed;
(4.2.9) the FPGA sends a configuration validation failure message to a configuration module, and the step (4.2.2) is executed;
(4.2.10) the FPGA sends a configuration validation success message to the configuration module, and the step (4.2.2) is executed.
Further, in step (4), the configuration module or FPGA processes the escape codec and CRC check of the configuration data, including the following sub-steps:
(4.3.1) performing CRC (cyclic redundancy check) calculation on the effective data of the configuration data or the information by the configuration module or the FPGA to obtain a first check value, inserting the first check value into the tail part of the effective data, and then performing escape coding on the effective data inserted with the first check value;
(4.3.2) the configuration module or the FPGA receives data, performing escape decoding processing on the data to obtain complete data, removing a first check value at the tail of the complete data to obtain effective data, performing CRC check calculation on the effective data to obtain a second check value, and comparing the second check value with the first check value, wherein the second check value and the first check value are equal, the two are used for indicating that the received data are correct, and the inequality is used for indicating that the received data are wrong.
Further, in the step (4), rules to be followed for escape encoding of the configuration data are: the method comprises the specific steps of respectively inserting a start code and an end code of 0xFF into the start code and the end code of data, and performing escape coding on the contents of the start code and the end code of the data, wherein the specific steps comprise:
(4.4.1) applying for the coded data buffer, wherein the first byte of the buffer is assigned to 0xFF, and the original data buffer is defined;
(4.4.2) circularly reading bytes of the original data cache, judging whether the original data cache is read completely, if yes, executing the step (4.4.7), otherwise, executing the step (4.4.3);
(4.4.3) obtaining the current byte read from the original data cache, comparing the value of the current byte, performing the step (4.4.4) if the current byte is equal to 0xFF, performing the step (4.4.5) if the current byte is equal to 0xFE, and performing the step (4.4.6) if the current byte is other values than 0xFE and 0 xFF;
(4.4.4) the current byte is converted into two bytes of 0xFE and 0xFE, the two bytes are stored in an encoded data cache, and the step (4.4.2) is executed in a skip mode;
(4.4.5) the current byte is converted into two bytes of 0xFE and 0x00, the two bytes are stored in an encoded data cache, and the step (4.4.2) is executed in a skip mode;
(4.4.6) keeping the current byte unchanged, storing the current byte in a coded data cache, and executing the step (4.4.2) in a jumping manner;
(4.4.7) escape encoding is completed, and a 0xFF byte is added to the tail of the valid data of the encoded data buffer.
Further, in the step (4), the configuration data is subjected to escape decoding, and the specific steps include:
(4.5.1) polling to read data from the configuration channel, wherein the read byte is a first byte, judging whether the value of the first byte is 0xFF, if so, applying for decoding data caching and executing the step (4.5.2), otherwise, discarding the read byte, and executing the step (4.5.1);
(4.5.2) reading data from the configuration channel, judging whether the data is successfully read, if so, executing the step (4.5.3), otherwise, executing the step (4.5.10);
(4.5.3) obtaining the read byte as the current byte, comparing the value of the current byte, executing the step (4.5.11) if the current byte is equal to 0xFF, executing the step (4.5.4) if the current byte is equal to 0xFE, and executing the step (4.5.8) if the current byte is other values than 0xFE and 0 xFF;
(4.5.4) reading data from the configuration channel, judging whether the data is successfully read, if so, executing the step (4.5.5), otherwise, executing the step (4.5.10);
(4.5.5) obtaining the read byte as the next byte, comparing the value of the next byte, executing step (4.5.6) if the next byte is equal to 0xFE, executing step (4.5.7) if the next byte is equal to 0x00, and executing step (4.5.10) if the next byte is other values than 0xFE and 0x 00;
(4.5.6) escape decoding the current byte and the next byte into one byte 0xFF and saving to the decoded data buffer, performing step (4.5.9);
(4.5.7) escape decoding the current byte and the next byte into one byte 0xFE and saving the byte 0xFE to a decoded data cache, and executing the step (4.5.9);
(4.5.8) keeping the current byte unchanged, storing the current byte in a decoded data buffer, and executing the step (4.5.9);
(4.5.9) judging whether the decoded data buffer is full, if yes, executing step (4.5.10), otherwise, executing step (4.5.2);
(4.5.10) escape decoding failure to obtain configuration data or message, release decoded data cache, and exit abnormally;
(4.5.11) successfully escape decoding a complete configuration data or message and exit normally.
Compared with the prior art, the invention has the beneficial effects that at least the following steps are included:
1. the P4 source file compiling and configuring tool provided by the invention integrates the P4 source file compiling and configuring data transmitting functions, simplifies the FPGA configuring process, realizes compiling and configuring integration, and improves the efficiency of the whole compiling and configuring process;
2. According to the invention, the P4 source file is compiled and then subjected to modularized treatment, and is divided into three types of configuration data including a state path, a matching operation and field modification, and an incremental generation mode is adopted when a transmission configuration data linked list is generated, so that the generation of the transmission configuration data is reduced as much as possible, the repeated transmission of the configuration data is reduced, and the configuration efficiency is improved;
3. the configuration sending mode of the multiple physical channels of USB, PCIe, UART, I C and SPI is supported, the sending mode appointed by a user during compiling configuration is supported, the corresponding configuration module is intensively called in the configuration module to finish the sending of configuration data, the portability of the method on multiple platforms can be effectively improved, and the application range of the method is improved;
4. according to the invention, the escape coding and CRC value calculation processing are carried out when the configuration data is sent, the FPGA carries out escape decoding and CRC on the configuration data, the integrity and the correctness of the configuration data are ensured, and the FPGA function configuration failure caused by transmission errors can be effectively avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a P4-based compiling and FPGA configuration method provided by the invention;
FIG. 2 is a flow chart of compiling configuration data provided by the present invention;
FIG. 3 is a flow chart of an incremental configuration function module provided by the present invention;
FIG. 4 is a diagram of a configuration data multi-channel transmission function provided by the present invention;
FIG. 5 is a flow chart of configuration data encoding and decoding and verification transmission provided by the invention;
FIG. 6 is a flow chart of configuration data or message escape encoding provided by the present invention;
fig. 7 is a flow chart of configuration data or message escape decoding provided by the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description is presented by way of example only and is not intended to limit the scope of the invention.
Fig. 1 is a flowchart of a P4-based compiling and FPGA configuration method provided by the present invention. As shown in fig. 1, the P4-based compiling and FPGA configuration method provided by the embodiment includes the following steps:
and (1) integrating a P4-fpga-common compiling module and a P4-fpga-common-xxx configuration module set by a P4-fpga-common compiling and configuring tool, and receiving a P4 source file and configuration parameters to be compiled and configured.
In an embodiment, the P4-fpga-config-xxx configuration module set includes five configuration modules, namely P4-fpga-config-usb, P4-fpga-config-pcie, P4-fpga-config-uart, P4-fpga-config-i2c and P4-fpga-config-spi, corresponding to the configuration methods of the five physical channels usb, PCIe, uart, i c and spi respectively.
In an embodiment, the received configuration parameters include a mandatory configuration flag parameter force_config_flag, and the specific values are defined as: force_config_flag=1 indicates that the forced full configuration is adopted, and force_config_flag=0 indicates that the incremental configuration is adopted.
The received configuration parameters also comprise a configuration channel config_channel between the configuration module and the FPGA, and the specific numerical values are defined as follows: config_channel=1 indicates that the usb device is adopted to configure the channel, and the usb device number needs to be input at the same time; config_channel=2 indicates that PCIe device number is required to be input simultaneously when PCIe device configuration channel is adopted; config_channel=3 indicates that the channel is configured by using the uart device, and the uart device number needs to be input at the same time; config_channel=4 indicates that the channel is configured by using the i2c device, and the i2c device number and the i2c address need to be input at the same time; config_channel=5 indicates that the channel is configured by the spi device, and the spi device number needs to be input at the same time.
And (2) compiling the P4 source file into three types of configuration data, namely state-path, match-operation and field-add-delete, which can be identified by the FPGA by the P4-FPGA-common compiling module, and generating a transmitting configuration data linked list according to a specified configuration mode.
In an embodiment, as shown in fig. 2, the step (2) includes the following specific steps:
(2.1) inputting a P4 source file and a signature configuration flag, and compiling the P4 source file into IR information (intermediate presentation layer information) by a front-end compiling function and a middle-end compiling function of a P4-fpga-common compiling module, and storing the IR information in a tree structure cache;
(2.2) traversing IR information cached in a tree structure by an FPGA rear-end compiling function of a P4-FPGA-command compiling module, extracting data according to the functional module, and generating binary configuration data of three types of FPGA, namely state-path, match-operation and field-add-delete, wherein the state-path type represents configuration data of all state paths of a network message, the match-operation type represents configuration data for executing corresponding operation actions according to keywords matched with the network message to achieve a message forwarding function, and the field-add-delete type represents configuration data for executing field inserting and/or deleting operations at a designated position of the network message;
(2.3) the P4-fpga-common compiling module calls the incremental configuration function module to generate a sending configuration data linked list from three types of configuration data, namely state-path, match-operation and field-add-delete.
As shown in fig. 3, the incremental configuration function module generates a transmission configuration data linked list from three types of configuration data, namely state-path, match-operation and field-add-delete, and specifically includes the following steps:
(2.3.1) creating a save send configuration data linked list send_config_list, and executing steps (2.3.2) -2.3.8) on three types of configuration data of state-path, match-operation and field-add-delete generated by compiling respectively;
(2.3.2) applying for saving the current configuration data, saving the compiled configuration data to the current buffer by a P4-fpga-rule compiling module, and obtaining the length cur_data_length of the current configuration data;
(2.3.3) judging whether the forced configuration flag parameter force_config_flag is 1, namely whether the forced configuration flag parameter force_config_flag is set, if not, executing the step (2.3.4), otherwise, executing the step (2.3.7);
(2.3.4) traversing a folder config_file for storing the previous configuration data, searching whether a configuration file corresponding to the configuration data exists, if so, executing the step (2.3.5), otherwise, executing the step (2.3.7);
(2.3.5) obtaining a configuration file pre_data_file and a configuration data length pre_data_length thereof corresponding to the configuration data, comparing whether the configuration data length pre_data_length is equal to the current configuration data cur_data_length obtained in the step (2.3.2), if yes, executing the step (2.3.6), otherwise, executing the step (2.3.7);
(2.3.6) applying for storing another buffer pre_data_buffer of the configuration file pre_data_file, reading the data content of the configuration file pre_data_file and storing the data content to the other buffer pre_data_buffer, comparing whether the buffer content of the other buffer pre_data_buffer is equal to the buffer content of the current buffer cur_data_buffer in the step (2.3.2), otherwise, executing the step (2.3.7), if yes, releasing the current buffer cur_data_buffer and the other buffer pre_data_buffer, and exiting the configuration data transmission;
(2.3.7) inserting the current buffer cur_data_buffer into the sending configuration data linked list send_config_list, and releasing the other buffer pre_data_buffer;
(2.3.8) generating a corresponding configuration file from the cache content of the current cache cur_data_buffer, and saving or replacing a corresponding configuration file config_file in a folder, wherein three types of configuration data are saved in the folder in a classified manner, specifically, three types of configuration data, namely state-path, match-operation and field-add-delete, are respectively saved as state-path, match-operation, bin and field-add-delete.
And (3) supporting a multi-physical channel configuration mode by the P4-fpga-common-config compiling configuration tool, and calling corresponding configuration modules in the P4-fpga-config-xxx configuration module set according to the designated configuration channels.
In the embodiment, as shown in fig. 4, according to a configuration channel config_channel between a configuration module and an FPGA, a corresponding configuration model is called from five configuration modules included in a P4-FPGA-config-xxx configuration module set to perform configuration work.
And (4) reading the configuration data in the configuration data link list by the configuration module and sending the configuration data to the FPGA, storing the configuration data in the cache link list after the FPGA successfully receives the configuration data, and sending a message to inform the FPGA of the configuration data to take effect after the configuration data is completely and successfully sent by the configuration module, wherein both the configuration data sending and the message interaction of the configuration module and the FPGA need to be subjected to escape coding and decoding and CRC check processing.
In an embodiment, as shown in fig. 5, the configuration data sending and message processing on the configuration module side includes the following specific steps:
(4.1.1) the configuration module polls the send configuration data linked list send_config_list and judges whether the configuration data in the send_config_list is sent completely, if yes, the step (4.1.3) is executed, otherwise, the step (4.1.2) is executed;
(4.1.2) the configuration module obtains the current buffer cur_config_buffer currently polled to the configuration data from the sending configuration data linked list send_config_list, processes the buffer data in the cur_config_buffer and sends the processed buffer data to the FPGA, and then performs the step (4.1.4);
(4.1.3) the configuration module sending a message validating the FPGA configuration data, and then performing step (4.1.4);
(4.1.4) defining a wait FPGA message timeout time wait_fpga_timeout, wherein the configuration module enters a wait FPGA message return state, judges whether the FPGA message is received within the wait FPGA message timeout time wait_fpga_timeout or not, if yes, executes the step (4.1.5), otherwise, executes the step (4.1.7);
(4.1.5) the configuration module receives the FPGA message, judges whether the message receiving process is wrong, if yes, executes the step (4.1.7), otherwise, executes the step (4.1.6);
the configuration module analyzes the received FPGA message, and the step (4.1.7) is executed when the received FPGA message is judged to be an invalid message, an FPGA receiving data error message or an FPGA configuration validation failure message, the step (4.1.1) is executed when the received configuration data message is judged to be successful, and the step (4.1.8) is executed when the received configuration data message is judged to be successful;
(4.1.7) the configuration module exits abnormally, and returns a configuration error prompt to the P4-fpga-common-config compiling configuration tool;
and (4.1.8) the configuration module successfully completes the configuration data transmission and takes the FPGA configuration into effect, and simultaneously returns a configuration success prompt to the P4-FPGA-combole-config compiling configuration tool.
In an embodiment, as shown in fig. 5, the configuration data receiving and message processing on the FPGA side includes the following specific steps:
(4.2.1) the FPGA applies for receiving a cache list recv_config_list of configuration data, and defines the overtime time wait_config_timeout of the configuration module to send the data;
(4.2.2) the FPGA acquires the data sent by the configuration module, judges whether the data is received in the period less than wait_config_timeout, if yes, the step (4.2.3) is executed, otherwise, the step (4.2.7) is executed;
(4.2.3) after the FPGA receives and obtains the complete data or the message, judging whether an error occurs in the receiving process, if so, executing the step (4.2.8), otherwise, executing the step (4.2.4);
(4.2.4) the FPGA analyzes the received data or information, and the step (4.2.5) is executed if the FPGA configuration validation information is judged, the step (4.2.8) is executed if the FPGA configuration validation information is judged, and the step (4.2.7) is executed if the FPGA configuration validation information is judged to be invalid;
(4.2.5) the FPGA sends the successfully received configuration data message to the configuration module, and inserts the received configuration data into a cache linked list recv_config_list;
(4.2.6) the FPGA judges whether the cache chain list recv_config_list is empty, if yes, the step (4.2.2) is executed, otherwise, the step (4.2.7) is executed;
(4.2.7) the FPGA sends a data receiving error message to the FPGA, clears the cache chain list recv_config_list and executes the step (4.2.2);
(4.2.8) the FPGA polls the cache chain list recv_config_list to assign configuration data to the corresponding functional module, and the module is restarted to enable the configuration to be effective, and the cache chain list recv_config_list is cleared, so that whether an error occurs in the process is judged, if yes, the step (4.2.9) is executed, otherwise, the step (4.2.10) is executed;
(4.2.9) the FPGA sends a configuration validation failure message to a configuration module, and the step (4.2.2) is executed;
(4.2.10) the FPGA sends a configuration validation success message to the configuration module, and the step (4.2.2) is executed.
In an embodiment, the escape codec and CRC check processing of configuration data by the configuration module or FPGA comprises the following sub-steps:
(4.3.1) performing CRC (cyclic redundancy check) calculation on the effective data of the configuration data or the information by using the configuration module or the FPGA to obtain a first check value send_crc_check_value, inserting the first check value send_crc_check_value into the tail part of the effective data, and performing escape coding on the effective data inserted with the first check value send_crc_check_value, wherein the length of the effective data is 4 bytes;
and (4.3.2) the configuration module or the FPGA receives data, performing escape decoding processing on the data to obtain complete data, removing a first check value represented by 4 bytes at the tail of the complete data to obtain effective data, performing CRC (cyclic redundancy check) calculation on the effective data to obtain a second check value recv_crc_check_value, and comparing the second check value recv_crc_check_value with the first check value send_crc_check_value, wherein the two values are equal and represent that the received data is correct, and the inequality represents that the received data is wrong.
In an embodiment, rules followed for escape encoding of configuration data are: the start and end of the data are inserted with a start code and end code of 0xFF, respectively. After the start code and the end code are added to the data, in order to ensure the uniqueness of the code words, so that both communication parties can correctly identify the start and end boundaries of the message, the contents of the start code and the end code of the data are required to be subjected to escape coding, and the rule is that a 0xFF field in the data is replaced by two bytes of 0xFE and 0xFE, and a 0xFE field is replaced by two bytes of 0xFE and 0x 00. As shown in fig. 6, the specific steps of escape encoding configuration data include:
(4.4.1) applying for a code data buffer, wherein the first byte of the buffer is assigned to 0xFF, and an original data buffer orig_buffer is defined;
(4.4.2) circularly reading bytes of the original data buffer, judging whether the original data buffer is completely read, if yes, executing the step (4.4.7), otherwise, executing the step (4.4.3);
(4.4.3) obtaining the current byte cur_byte read from the original data buffer, comparing the value of the current byte cur_byte, performing the step (4.4.4) if the current byte cur_byte is equal to 0xFF, performing the step (4.4.5) if the current byte cur_byte is equal to 0xFE, and performing the step (4.4.6) if the current byte cur_byte is other values than 0xFE and 0 xFF;
(4.4.4) the current byte cur_byte is converted into two bytes of 0xFE and 0xFE, the two bytes are stored into a code buffer, and the step (4.4.2) is carried out in a skip mode;
(4.4.5) escaping the current byte cur_byte into two bytes of 0xFE and 0x00, storing the two bytes into a code buffer, and jumping to execute the step (4.4.2);
(4.4.6) keeping the current byte cur_byte unchanged, storing the current byte into a code_buffer, and jumping to execute the step (4.4.2);
(4.4.7) completing escape encoding, and adding a 0xFF byte at the tail of the valid data of the encoded data buffer code_buffer.
In an embodiment, as shown in fig. 7, the escape decoding of the configuration data includes the following specific steps:
(4.5.1) polling to read data from the configuration channel, wherein the read byte is a first byte, judging whether the value of the first byte is 0xFF, if so, applying for decoding the data buffer decoder buffer and executing the step (4.5.2), otherwise, discarding the read byte, and executing the step (4.5.1);
(4.5.2) reading data from the configuration channel, judging whether the data is successfully read, if so, executing the step (4.5.3), otherwise, executing the step (4.5.10);
(4.5.3) obtaining the read byte as the current byte cur_byte, comparing the value of the current byte cur_byte, executing the step (4.5.11) if the current byte cur_byte is equal to 0xFF, executing the step (4.5.4) if the current byte cur_byte is equal to 0xFE, and executing the step (4.5.8) if the current byte cur_byte is other values than 0xFE and 0 xFF;
(4.5.4) reading data from the configuration channel, judging whether the data is successfully read, if so, executing the step (4.5.5), otherwise, executing the step (4.5.10);
(4.5.5) obtaining the read byte as a next byte cur_next_byte, comparing the values of the next byte cur_next_byte, performing the step (4.5.6) if the next byte cur_next_byte is equal to 0xFE, performing the step (4.5.7) if the next byte cur_next_byte is equal to 0x00, and performing the step (4.5.10) if the next byte cur_next_byte is other values than 0xFE and 0x 00;
(4.5.6) the current byte cur_ byt and the next byte cur_next_byte are decoded into one byte 0xFF, and stored in a decoded data buffer, and step (4.5.9) is executed;
(4.5.7) the current byte cur_byte and the next byte cur_next_byte are escape decoded into one byte 0xFE and stored in a decoded data buffer decoder_buffer, and step (4.5.9) is executed;
(4.5.8) keeping the current byte cur_byte unchanged, storing the current byte in a decoding data buffer, and executing the step (4.5.9);
(4.5.9) judging whether the decoding data buffer is full, if yes, executing the step (4.5.10), otherwise, executing the step (4.5.2);
(4.5.10) escape decoding to obtain configuration data or information failure, release decoding data buffer, and exit abnormally;
(4.5.11) successfully escape decoding a complete configuration data or message and exit normally.
The foregoing detailed description of the preferred embodiments and advantages of the invention will be appreciated that the foregoing description is merely illustrative of the presently preferred embodiments of the invention, and that no changes, additions, substitutions and equivalents of those embodiments are intended to be included within the scope of the invention.
Claims (10)
1. The P4-based compiling and FPGA configuration method is characterized by comprising the following steps of:
(1) The P4-fpga-common-config compiling and configuring tool integrates a P4-fpga-common compiling module and a P4-fpga-config-xxx configuring module set, and receives a P4 source file and configuration parameters to be compiled and configured;
(2) The P4-FPGA-common compiling module compiles the P4 source file into three types of configuration data including a state path which can be identified by the FPGA, matching operation and field modification, and generates a transmitting configuration data linked list according to a designated configuration mode;
(3) The P4-fpga-config compiling and configuring tool supports a multi-physical channel configuration mode, and corresponding configuration modules are called in the P4-fpga-config-xxx configuration module set according to the designated configuration channels;
(4) The configuration module reads the configuration data in the configuration data link list and sends the configuration data to the FPGA, the FPGA successfully receives the configuration data and stores the configuration data in the cache link list, and the configuration module sends a message to inform the FPGA that the configuration data is effective after the configuration data is completely and successfully sent, wherein both the configuration data sending and the message interaction of the configuration module and the FPGA need escape encoding and decoding and CRC check processing.
2. The P4-based compiling and FPGA configuration method according to claim 1, wherein the P4-FPGA-config-xxx configuration module set comprises five configuration modules P4-FPGA-config-usb, P4-FPGA-config-pcie, P4-FPGA-config-uart, P4-FPGA-config-i2c and P4-FPGA-config-spi, corresponding to the configuration methods of the five physical channels usb, PCIe, uart, i c and spi, respectively.
3. The P4-based compilation and FPGA configuration method of claim 2 wherein the received configuration parameters comprise:
a forced configuration flag parameter, wherein a forced configuration flag parameter of 1 indicates a forced full configuration mode, and a forced configuration flag parameter of 0 indicates an incremental configuration mode;
the configuration channel between the configuration module and the FPGA, wherein the configuration channel is 1, a usb device configuration channel is required to be input simultaneously, the configuration channel is 2, a PCIe device configuration channel is required to be input simultaneously, the configuration channel is 3, a uart device configuration channel is required to be input simultaneously, the configuration channel is 4, an i2c device configuration channel is required to be input simultaneously, an i2c device number and an i2c address are required to be input simultaneously, the configuration channel is 5, a spi device configuration channel is required to be input simultaneously, and the spi device number is required to be input simultaneously.
4. The P4-based compiling and FPGA configuration method according to claim 1, wherein the step (2) comprises the following specific steps:
(2.1) the front-end and middle-end compiling functions of the P4-fpga-common compiling module compile the P4 source file into intermediate representation layer information and store the intermediate representation layer information in a tree structure cache;
(2.2) traversing intermediate representation layer information of a tree structure cache by an FPGA (field programmable gate array) rear-end compiling function of the P4-FPGA-common compiling module, carrying out data extraction according to the functional module, generating three types of configuration data including a state path, a matching operation and field modification, wherein the state path type represents the configuration data of all state paths of a network message, the matching operation type represents the configuration data for executing corresponding operation according to a keyword matched with the network message to achieve a message forwarding function, and the field modification type represents the configuration data for executing field insertion and/or deletion operation at a designated position of the network message;
(2.3) the P4-fpga-common compiling module calls the incremental configuration function module to generate the three types of configuration data into a transmission configuration data linked list.
5. The P4-based compiling and FPGA configuration method according to claim 4, wherein the step (2.3) comprises the following specific steps:
(2.3.1) creating a save send configuration data linked list, and executing steps (2.3.2) -2.3.8) on the three types of configuration data of the state path, the matching operation and the field modification generated by compiling respectively;
(2.3.2) applying for storing the current cache of the current configuration data, and storing the compiled configuration data to the current cache by the P4-fpga-common compiling module, and obtaining the length of the current configuration data;
(2.3.3) judging whether the forced configuration flag parameter is 1, if not, executing the step (2.3.4), and if yes, executing the step (2.3.7);
(2.3.4) traversing a folder for storing the previous configuration data, searching whether the configuration file corresponding to the configuration data exists or not, if yes, executing the step (2.3.5), otherwise, executing the step (2.3.7);
(2.3.5) obtaining a configuration file corresponding to the configuration data and the configuration data length thereof, comparing whether the configuration data length is equal to the current configuration data length obtained in the step (2.3.2), if yes, executing the step (2.3.6), otherwise, executing the step (2.3.7);
(2.3.6) applying for storing another cache of the configuration file, reading the data content of the configuration file, storing the data content in the other cache, comparing whether the cache content of the other cache is equal to the cache content of the current cache in the step (2.3.2), otherwise, executing the step (2.3.7), and releasing the current cache and the other cache and exiting the configuration data transmission;
(2.3.7) inserting the current buffer into the transmission configuration data linked list, and releasing the other buffer;
(2.3.8) generating corresponding configuration files from the cached content of the current cache, and storing or replacing the corresponding configuration files in the folder, wherein three types of configuration data are stored in the folder in a classified mode.
6. The P4-based compiling and FPGA configuration method according to claim 1, wherein in step (4), the configuration data transmission and message processing at the configuration module side comprises the following specific steps:
(4.1.1) the configuration module polls the transmission configuration data linked list and judges whether the configuration data in the configuration data linked list is transmitted completely, if yes, the step (4.1.3) is executed, otherwise, the step (4.1.2) is executed;
(4.1.2) the configuration module obtains the current polling to the current buffer memory of the configuration data from the linked list of the transmission configuration data, processes the buffer memory data therein and then transmits the processed buffer memory data to the FPGA, and then executes the step (4.1.4);
(4.1.3) the configuration module sending a message validating the FPGA configuration data, and then performing step (4.1.4);
(4.1.4) defining the timeout time of waiting for the FPGA message, enabling the configuration module to enter a state of waiting for the FPGA message to return, judging whether the FPGA message is received within the timeout time of waiting for the FPGA message, if yes, executing the step (4.1.5), otherwise, executing the step (4.1.7);
(4.1.5) the configuration module receives the FPGA message, judges whether the message receiving process is wrong, if yes, executes the step (4.1.7), otherwise, executes the step (4.1.6);
the configuration module analyzes the received FPGA message, and the step (4.1.7) is executed when the received FPGA message is judged to be an invalid message, an FPGA receiving data error message or an FPGA configuration validation failure message, the step (4.1.1) is executed when the received configuration data message is judged to be successful, and the step (4.1.8) is executed when the received configuration data message is judged to be successful;
(4.1.7) the configuration module exits abnormally, and returns a configuration error prompt to the P4-fpga-common-config compiling configuration tool;
and (4.1.8) the configuration module successfully completes the configuration data transmission and takes the FPGA configuration into effect, and simultaneously returns a configuration success prompt to the P4-FPGA-combole-config compiling configuration tool.
7. The P4-based compiling and FPGA configuration method according to claim 1, wherein in step (4), the configuration data receiving and message processing at the FPGA side comprises the following specific steps:
(4.2.1) the FPGA applies for receiving a cache list of configuration data, and defines the overtime of the configuration module to send the data;
(4.2.2) the FPGA acquires the data sent by the configuration module, judges whether the data is received within a time-out time shorter than the sending data, if yes, executes the step (4.2.3), otherwise, executes the step (4.2.7);
(4.2.3) after the FPGA receives and obtains the complete data or the message, judging whether an error occurs in the receiving process, if so, executing the step (4.2.8), otherwise, executing the step (4.2.4);
(4.2.4) the FPGA analyzes the received data or information, and the step (4.2.5) is executed if the FPGA configuration validation information is judged, the step (4.2.8) is executed if the FPGA configuration validation information is judged, and the step (4.2.7) is executed if the FPGA configuration validation information is judged to be invalid;
(4.2.5) the FPGA sends the successfully received configuration data message to the configuration module, and inserts the received configuration data into a cache linked list;
(4.2.6) the FPGA judges whether the cache linked list is empty, if yes, the step (4.2.2) is executed, otherwise, the step (4.2.7) is executed;
(4.2.7) the FPGA sends a data error message to the FPGA, clears the cache linked list and executes the step (4.2.2);
(4.2.8) the FPGA polls the buffer linked list to assign configuration data to the corresponding functional module, and the module is restarted to enable the configuration to be effective, and the buffer linked list is emptied, if yes, the step (4.2.9) is executed, and if no, the step (4.2.10) is executed;
(4.2.9) the FPGA sends a configuration validation failure message to a configuration module, and the step (4.2.2) is executed;
(4.2.10) the FPGA sends a configuration validation success message to the configuration module, and the step (4.2.2) is executed.
8. The P4-based compiling and FPGA configuration method according to claim 1, wherein in step (4), the configuration module or the FPGA performs the escape codec and CRC check processing on the configuration data, and the method comprises the following sub-steps:
(4.3.1) performing CRC (cyclic redundancy check) calculation on the effective data of the configuration data or the information by the configuration module or the FPGA to obtain a first check value, inserting the first check value into the tail part of the effective data, and then performing escape coding on the effective data inserted with the first check value;
(4.3.2) the configuration module or the FPGA receives data, performing escape decoding processing on the data to obtain complete data, removing a first check value at the tail of the complete data to obtain effective data, performing CRC check calculation on the effective data to obtain a second check value, and comparing the second check value with the first check value, wherein the second check value and the first check value are equal, the two are used for indicating that the received data are correct, and the inequality is used for indicating that the received data are wrong.
9. The P4-based compiling and FPGA configuring method according to claim 1, wherein in step (4), rules to be followed for escape encoding of the configuration data are: the method comprises the specific steps of respectively inserting a start code and an end code of 0xFF into the start code and the end code of data, and performing escape coding on the contents of the start code and the end code of the data, wherein the specific steps comprise:
(4.4.1) applying for the coded data buffer, wherein the first byte of the buffer is assigned to 0xFF, and the original data buffer is defined;
(4.4.2) circularly reading bytes of the original data cache, judging whether the original data cache is read completely, if yes, executing the step (4.4.7), otherwise, executing the step (4.4.3);
(4.4.3) obtaining the current byte read from the original data cache, comparing the value of the current byte, performing the step (4.4.4) if the current byte is equal to 0xFF, performing the step (4.4.5) if the current byte is equal to 0xFE, and performing the step (4.4.6) if the current byte is other values than 0xFE and 0 xFF;
(4.4.4) the current byte is converted into two bytes of 0xFE and 0xFE, the two bytes are stored in an encoded data cache, and the step (4.4.2) is executed in a skip mode;
(4.4.5) the current byte is converted into two bytes of 0xFE and 0x00, the two bytes are stored in an encoded data cache, and the step (4.4.2) is executed in a skip mode;
(4.4.6) keeping the current byte unchanged, storing the current byte in a coded data cache, and executing the step (4.4.2) in a jumping manner;
(4.4.7) escape encoding is completed, and a 0xFF byte is added to the tail of the valid data of the encoded data buffer.
10. The P4-based compiling and FPGA configuring method according to claim 9, wherein in step (4), the configuration data is decoded in an escape way, and the specific steps include:
(4.5.1) polling to read data from the configuration channel, wherein the read byte is a first byte, judging whether the value of the first byte is 0xFF, if so, applying for decoding data caching and executing the step (4.5.2), otherwise, discarding the read byte, and executing the step (4.5.1);
(4.5.2) reading data from the configuration channel, judging whether the data is successfully read, if so, executing the step (4.5.3), otherwise, executing the step (4.5.10);
(4.5.3) obtaining the read byte as the current byte, comparing the value of the current byte, executing the step (4.5.11) if the current byte is equal to 0xFF, executing the step (4.5.4) if the current byte is equal to 0xFE, and executing the step (4.5.8) if the current byte is other values than 0xFE and 0 xFF;
(4.5.4) reading data from the configuration channel, judging whether the data is successfully read, if so, executing the step (4.5.5), otherwise, executing the step (4.5.10);
(4.5.5) obtaining the read byte as the next byte, comparing the value of the next byte, executing step (4.5.6) if the next byte is equal to 0xFE, executing step (4.5.7) if the next byte is equal to 0x00, and executing step (4.5.10) if the next byte is other values than 0xFE and 0x 00;
(4.5.6) escape decoding the current byte and the next byte into one byte 0xFF and saving to the decoded data buffer, performing step (4.5.9);
(4.5.7) escape decoding the current byte and the next byte into one byte 0xFE and saving the byte 0xFE to a decoded data cache, and executing the step (4.5.9);
(4.5.8) keeping the current byte unchanged, storing the current byte in a decoded data buffer, and executing the step (4.5.9);
(4.5.9) judging whether the decoded data buffer is full, if yes, executing step (4.5.10), otherwise, executing step (4.5.2);
(4.5.10) escape decoding failure to obtain configuration data or message, release decoded data cache, and exit abnormally;
(4.5.11) successfully escape decoding a complete configuration data or message and exit normally.
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