CN116859153A - High-voltage interlocking loop fault detection device - Google Patents

Abstract

The application discloses a high-voltage interlocking loop fault detection device, which is used for detecting through setting two paths of pulse width modulation signals, wherein one path is used for detecting a control end aiming at a high-voltage interlocking loop, and the other path is used for detecting a detection end aiming at the high-voltage interlocking loop. The pulse width modulation signals with the fixed duty ratio are automatically calibrated, and the pulse width modulation signals are transmitted by combining the two paths, so that whether the detection end fails or the control end fails in the high-voltage interlocking loop can be judged according to the complementary condition between the two paths of pulse width signals. The fault detection device can detect faults of the detection end and the control end in the high-voltage interlocking loop, so that the reliability of fault detection of the high-voltage interlocking loop is improved.

Description

A high-voltage interlock circuit fault detection device

This application claims priority to the Chinese patent application submitted to the State Intellectual Property Office on September 13, 2022, with application number 202222422010.7 and titled "A high-voltage interlocking loop fault detection device", the entire content of which is incorporated herein by reference. Applying.

Technical field

The present application relates to the field of digital signal technology, and in particular to a high-voltage interlock circuit fault detection device.

Background technique

With the development of science and technology, new energy electric vehicles are becoming more and more popular. The high-voltage system in electric vehicles is an insulated and closed system. When fault detection is performed on the high-voltage interlock, the high-voltage connector is not functioning properly. High voltage exposure will occur during connection, which may easily cause electric shock to maintenance personnel and affect the personal safety of maintenance personnel. Therefore, there is an urgent need for a simple and efficient high-voltage interlock loop fault detection solution to ensure the integrity and safety of the high-voltage system, thereby ensuring the safety of maintenance personnel.

When detecting a high-voltage interlock loop fault in the existing technology, a single-chip microcomputer I/O port is usually used to output a pulse width modulation signal, and the pulse width modulation signal is transmitted from the end of the high-voltage interlock loop through a series line in the high-voltage interlock loop. The feedback signal is fed back to the microcontroller, and finally the feedback signal is processed by the microcontroller unit (MCU) in the microcontroller to determine whether a fault occurs in the high-voltage interlock circuit.

In the above technical solution, because the microcontroller outputs the pulse width modulation signal through one channel, since the signal passes through the control end and detection end of the high-voltage interlock loop, when a high-voltage interlock fault occurs, it cannot be determined that it is a high-voltage interlock loop. The control terminal fails or the detection terminal of the high-voltage interlock circuit fails. Therefore, the reliability of the detection results is low.

Contents of the invention

Based on the above problems, this application provides a high-voltage interlock circuit fault detection device to solve the problem of low reliability of high-voltage interlock circuit fault detection results.

The embodiments of this application disclose the following technical solutions:

A high-voltage interlock circuit fault detection device, including: a micro-control unit and a high-voltage interlock circuit; the high-voltage interlock circuit includes a voltage dividing circuit; wherein, the output end of the micro-control unit, the first input end and the second The input terminals are all connected to the high-voltage interlock circuit;

The micro-control unit is configured to output an original pulse width modulation signal to the high-voltage interlock circuit through the output terminal;

The voltage dividing circuit is used to decompose the original pulse width modulation signal into a first pulse width modulation signal and a second pulse width modulation signal with different duty cycles;

The high-voltage interlock circuit is used to transmit the first pulse width modulation signal to the first input terminal, and to transmit the second pulse width modulation signal to the second input terminal;

The micro control unit is further configured to receive a duty cycle of the first pulse width modulation signal and a duty cycle of the second pulse width modulation signal from the first input terminal and the second input terminal. The duty cycle and the duty cycle of the original pulse width modulation signal are used to obtain the fault detection result of the high voltage interlock loop. .

Optionally, the microcontrol unit is specifically used for:

If the duty cycle of the original pulse width modulation signal is complementary to the duty cycle of the first pulse width modulation signal, it is determined that the control end of the high voltage interlock loop is normal;

If the duty cycle of the first pulse width modulation signal and the duty cycle of the second pulse width modulation signal are complementary, it is determined that the detection end of the high voltage interlock loop is normal.

Optionally, the voltage dividing circuit specifically includes: a first resistor, a second resistor, a first transistor and a second transistor, and the resistance of the first resistor is smaller than the resistance of the second resistor. , one end of the first transistor is grounded, and the other end is connected in series with the first resistor; one end of the second transistor is grounded, and the other end is connected in series with the second resistor;

The first resistor and the second resistor are used to perform voltage dividing processing on the circuit, so that the first pulse width modulation signal and the second pulse width modulation signal have different and complementary duty cycles.

Optionally, the device further includes: a first filter acquisition module and a second filter acquisition module, the first transistor is connected to the input end of the first filter acquisition module, and the first input end is connected to the first filter acquisition module. The output end of the first filter acquisition module is connected, the second transistor is connected to the input end of the second filter acquisition module, and the second input end is connected to the output end of the second filter acquisition module;

The first filter acquisition module is used to collect the first pulse width modulation signal and transmit it to the first input terminal;

The second filtering acquisition module is used to collect the second pulse width modulation signal and transmit it to the second input terminal.

Optionally, the device further includes: a fault processing module, which is connected to the micro control unit;

The fault processing module is used to take countermeasures according to the mode of the power supply when a fault occurs in the high-voltage interlock circuit.

Optional countermeasures include:

When the power supply is in the discharge mode, the discharge power is limited to the first threshold;

When the power supply is in the charging mode, limiting the charging power to the second threshold;

When the power supply is not in the charging mode and the discharging mode, charging is prohibited.

Optionally, the microcontrol unit is also specifically used for:

When there is no fault in the high-voltage interlock circuit at the current moment or at the previous moment, it is determined that the state of the high-voltage interlock circuit is the first state, and the first state indicates that the high-voltage interlock circuit is in a working state;

When the high-voltage interlock circuit fails at the last moment, the state of the high-voltage interlock circuit is determined to be the second state, and the second state indicates that the high-voltage interlock circuit is closed; When the high-voltage interlock circuit fails and the high-voltage interlock circuit fails at the current moment, it is determined that the state of the high-voltage interlock circuit is a third state, and the third state indicates that the operation of the high-voltage interlock circuit is interrupted. interrupt.

Compared with the existing technology, this application has the following beneficial effects: This application provides a high-voltage interlock circuit fault detection device, which detects by setting two pulse width modulation signals, one of which is used to detect the high-voltage interlock circuit. The control terminal is used for detection, and the other is used for detection of the high-voltage interlock circuit. Through the pulse width modulation signal with a fixed duty cycle calibrated by the user, the pulse width modulation signal is transmitted by combining the two channels. By judging the complementarity between the pulse width signals, it can be judged whether the corresponding detection end or control end has occurred. Fault. Its fault detection device can detect faults at the detection end and control end of the high-voltage interlock loop, thereby improving the reliability of fault detection in the high-voltage interlock loop.

Description of the drawings

In order to explain the embodiments of the present application or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort.

Figure 1 is a schematic structural diagram of a high-voltage interlock circuit fault detection device provided by an embodiment of the present application;

FIG. 2 is a circuit diagram of a high-voltage interlock circuit fault detection device provided by an embodiment of the present application.

Detailed ways

As described above, when detecting high-voltage interlock circuit faults in the current technology, the current technology usually only uses a single-chip I/O port to output a pulse width modulation signal to determine whether the high-voltage interlock circuit is in a fault state. It is impossible to determine whether the high-voltage interlock circuit is in a fault state. Is the detection end of the lock loop faulty or its control end faulty.

Based on this, this application provides a high-voltage interlock circuit fault detection device, which detects by setting two pulse width modulation signals, one of which is used to detect the control end of the high-voltage interlock loop, and the other is used to detect the high-voltage interlock circuit. Detection of the detection end of the interlocking loop. Through the pulse width modulation signal with a fixed duty cycle calibrated by the user, the pulse width modulation signal is transmitted by combining the two channels. By judging the complementarity between the pulse width signals, it can be judged whether the corresponding detection end or control end has occurred. Fault. Its fault detection device can detect faults at the detection end and control end of the high-voltage interlock loop, thereby improving the reliability of fault detection in the high-voltage interlock loop.

In order to enable those in the technical field to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only These are part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

Device embodiment

Refer to Figure 1, which is a schematic structural diagram of a high-voltage interlock circuit fault detection device provided by an embodiment of the present application. FIG. 2 is a circuit diagram of a high-voltage interlock circuit fault detection device provided by an embodiment of the present application.

As shown in Figure 1, this high-voltage interlock circuit fault detection device includes: a micro-control unit 100 and a high-voltage interlock circuit 200; the high-voltage interlock circuit 200 includes a voltage dividing circuit; wherein, the output of the micro-control unit 100 terminal, the first input terminal and the second input terminal are all connected to the high voltage interlock circuit 200 .

The micro control unit 100 is configured to output an original pulse width modulation signal to the high voltage interlock circuit through the output terminal.

The voltage dividing circuit is used to decompose the original pulse width modulation signal into a first pulse width modulation information and a second pulse width modulation signal with different duty ratios.

The voltage dividing circuit is arranged in a high-voltage interlock circuit. A first resistor R1 and a second resistor R2 are arranged in the circuit, and each resistor is connected in series with a corresponding first transistor and a second transistor. The resistor R1 is far away from the Less than resistor R2, the other end of the transistor is connected to ground. Combined with the use of a voltage divider circuit, the original pulse width modulation signal output by the micro control unit can be decomposed into two pulse width modulation signals with different duty cycles.

The high-voltage interlock circuit 200 is used to transmit the first pulse width modulation signal to the first input terminal, and to transmit the second pulse width modulation signal to the second input terminal.

The first pulse width modulation signal and the second pulse width modulation signal are respectively transmitted to the first input terminal and the second input terminal of the micro control unit. The two pulse width modulation signals have different duty cycles. When the micro control unit receives When receiving the above two pulse width modulation signals with different duty ratios, the fault condition at the detection end of the high-voltage interlock loop will be determined based on the complementarity of the duty ratios between them.

The micro-control unit 100 is also configured to, according to the duty cycle of the first pulse width modulation signal received from the first input terminal and the second input terminal, the second pulse width modulation signal The duty cycle and the duty cycle of the original pulse width modulation signal are used to obtain the fault detection result of the high voltage interlock loop.

The duty cycle of the original pulse width modulation signal can be calibrated by the user. The micro control unit can adjust the duty cycle according to the difference between the original pulse width modulation signal (PWM in Figure 2) and the first pulse width modulation signal (PWM1 in Figure 2). situation to determine whether the control end of the high-voltage interlock circuit is faulty.

For example, by calibrating the duty cycle of the original pulse width modulation signal to 70%, after being processed by the voltage divider circuit, the duty cycle of the first pulse width modulation signal is 30%. The first pulse width modulation signal is the same as the original pulse width modulation signal. If the signals are complementary, it is determined that the control end of the high-voltage interlock loop is normal.

If the duty cycle of the original pulse width modulation signal is calibrated to be 70%, and after being processed by the voltage divider circuit, the duty cycle of the first pulse width modulation signal is 20%, then the first pulse width modulation signal and the original pulse width If the modulation signal does not meet the condition of complementary duty cycle, it is determined that the control end of the high-voltage interlock loop is faulty.

In the same way, the micro control unit can also determine the status of the high-voltage interlock loop based on the complementarity of the duty ratio between the first pulse width modulation signal (PWM1 in Figure 2) and the second pulse width modulation signal (PWM2 in Figure 2). Check whether there is a failure at the detection end.

For example, when the first pulse width modulation signal is 30% and the second pulse width modulation signal is 70%, the duty cycles of the first pulse width modulation signal and the second pulse width modulation signal are complementary, determining the high voltage interlock loop The detection end is normal.

If the duty cycle of the first pulse width modulation signal is 60%, and after being processed by the voltage divider circuit, the duty cycle of the second pulse width modulation signal is 30%, then the first pulse width modulation signal and the second pulse If the width modulation signal does not meet the condition of complementary duty cycle, it is determined that the detection end of the high-voltage interlock loop is faulty.

It can be seen that in the high-voltage interlock loop fault detection device provided by the embodiment of the present application, two pulse width modulation signals are set for detection, one of which is used for control end detection of the high-voltage interlock loop, and the other One channel is used for detection of the high-voltage interlock circuit. Through the pulse width modulation signal with a fixed duty cycle calibrated by the user, the pulse width modulation signal is transmitted by combining the two channels. By judging the complementarity between the pulse width signals, it can be judged whether the corresponding detection end or control end has occurred. Fault. Its fault detection device can detect faults at the detection end and control end of the high-voltage interlock loop, thereby improving the reliability of fault detection in the high-voltage interlock loop.

In an optional implementation, the high-voltage interlock circuit fault detection device further includes: a fault processing module, and the fault processing module is connected to the micro control unit.

The fault processing module is used to take countermeasures according to the mode of the power supply when a fault occurs in the high-voltage interlock circuit.

The countermeasures include: when the power supply is in the discharge mode, limiting the discharge power to the first threshold. When the power supply is in the charging mode, the charging power is limited to the second threshold. When the power supply is not in the charging mode and the discharging mode, charging is prohibited.

The first threshold and the second threshold can be set by the user, for example, the first threshold is set to 50% and the second threshold is set to 0%. The countermeasures provided by the fault handling module can flexibly take corresponding measures according to the current power supply mode when the high-voltage interlock circuit fails. This flexibly and efficiently ensures the safety of using the power supply when the high-voltage interlock circuit fails. .

In an optional implementation, the high-voltage interlock circuit fault detection device and the micro-control unit are specifically used for:

When there is no fault in the high-voltage interlock circuit at the current moment or the previous moment, the state of the high-voltage interlock circuit is determined to be the first state, and the first state indicates that the high-voltage interlock circuit is in a working state.

When the high-voltage interlock circuit failed at the last moment, the state of the high-voltage interlock circuit is determined to be the second state, and the second state indicates that the high-voltage interlock circuit is closed.

When the high-voltage interlock circuit fails at the previous moment and the high-voltage interlock circuit fails at the current moment, it is determined that the state of the high-voltage interlock circuit is the third state, and the third state represents the The operation of the above-mentioned high-voltage interlock circuit was interrupted.

By setting different flags to represent different states of the high-voltage interlock circuit, it is more conducive for staff to observe the status of the high-voltage interlock circuit and improves the efficiency of high-voltage interlock circuit fault detection.

In an optional implementation, the high-voltage interlock loop fault detection device further includes: a first filter acquisition module and a second filter acquisition module, and the connection between the first transistor and the first filter acquisition module is The input end is connected, the first input end is connected to the output end of the first filter acquisition module, the second transistor is connected to the input end of the second filter acquisition module, the second input end is connected to The output end of the second filter acquisition module is connected.

The first filter acquisition module is used to collect the first pulse width modulation signal and transmit it to the first input terminal.

The second filtering acquisition module is used to collect the second pulse width modulation signal and transmit it to the second input terminal.

The specific working principle of the circuit diagram shown in Figure 2 is:

Among them, GND represents ground, VCC represents power supply, HVIL _- represents the output channel of the high-voltage interlock circuit, and HVIL ₊ represents the input channel of the high-voltage interlock circuit.

When the high-voltage interlock circuit is normal:

When the original pulse width modulation signal (PWM) is high level, the first transistor (Q1) is turned on, and the first pulse width modulation signal (PWM1) captures the low level signal. When the high-voltage interlock is connected normally, the high-voltage interlock circuit is turned on. Since the resistance value of the first resistor (R1) is much smaller than the resistance value of the second resistor (R2), it can be seen from the voltage division that the value of the voltage (U1) is smaller. The transistor (Q2) fails to conduct, and the second pulse width modulation signal (PWM2) captures a high level signal.

When the PWM input signal is low level, the Q1 transistor is turned off, and PWM1 captures the high level signal. When the high-voltage interlock is connected normally, the high-voltage interlock circuit is turned on. Because Q1 is disconnected, the U1 voltage is the power supply voltage (VCC), the Q2 transistor is turned on, and PWM2 captures the low-level signal.

By calibrating the PWM input signal duty cycle to 70%, the PWM1 duty cycle is 30% and the PWM2 duty cycle is 70% (without considering the error). The PWM1 duty cycle is complementary to the PWM2 duty cycle, and the PWM duty cycle is complementary to the PWM1 duty cycle, which proves that both the detection end and the control end of the high-voltage interlock are in a normal state.

When the high-voltage interlock circuit fails, the circuit is disconnected:

When the PWM input signal is high level, the Q1 transistor is turned on, and PWM1 captures the low level signal. The high-voltage interlock loop is disconnected, the U1 voltage is VCC, the Q2 transistor is turned on, and PWM2 captures the low-level signal.

When the PWM input signal is low level, the Q1 transistor is turned off, and PWM1 captures the high level signal. The high-voltage interlock loop is disconnected, the U1 voltage is VCC, the Q2 transistor is turned on, and PWM2 captures the low-level signal.

When the input PWM duty cycle is 70%, the duty cycle of PWM1 is 30% and the duty cycle of PWM2 is 0%. The duty cycles of PWM1 and PWM2 are not complementary, which indicates that the detection terminal of the high-voltage interlock loop is faulty.

When the input PWM duty cycle is 70%, then the PWM1 duty cycle is 20%, and when the PWM2 duty cycle is 80%, the duty cycles of PWM and PWM1 are not complementary, indicating a fault at the control end of the high-voltage interlock loop.

In the embodiment of this application, two pulse width modulation signal feedback circuits are designed. One circuit is used for self-test of the control terminal. When the duty cycle of the first pulse width modulation signal and the original pulse width modulation signal is complementary, it proves that the control terminal is normal; one circuit is used for self-testing of the control terminal. Detection terminal diagnosis: when the duty ratios of the first pulse width modulation signal and the second pulse width modulation signal are complementary, it proves that the detection terminal of the high-voltage interlock loop is normal. Its fault detection device can detect faults at the detection end and control end of the high-voltage interlock loop, thereby improving the reliability of fault detection in the high-voltage interlock loop.

The above is only a specific implementation mode of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present application. Replacements shall be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (7)

1. A high-voltage interlock circuit fault detection device, characterized in that it includes: a micro-control unit and a high-voltage interlock circuit; the high-voltage interlock circuit includes a voltage dividing circuit; wherein, the output end of the micro-control unit and the third An input terminal and a second input terminal are both connected to the high-voltage interlock circuit; The micro-control unit is configured to output an original pulse width modulation signal to the high-voltage interlock circuit through the output terminal; The voltage dividing circuit is used to decompose the original pulse width modulation signal into a first pulse width modulation signal and a second pulse width modulation signal with different duty cycles; The high-voltage interlock circuit is used to transmit the first pulse width modulation signal to the first input terminal, and to transmit the second pulse width modulation signal to the second input terminal; The micro control unit is further configured to receive a duty cycle of the first pulse width modulation signal and a duty cycle of the second pulse width modulation signal from the first input terminal and the second input terminal. The duty cycle and the duty cycle of the original pulse width modulation signal are used to obtain the fault detection result of the high voltage interlock loop. 2. The device according to claim 1, characterized in that the micro control unit is specifically used for: If the duty cycle of the original pulse width modulation signal is complementary to the duty cycle of the first pulse width modulation signal, it is determined that the control end of the high voltage interlock loop is normal; If the duty cycle of the first pulse width modulation signal and the duty cycle of the second pulse width modulation signal are complementary, it is determined that the detection end of the high voltage interlock loop is normal. 3. The device according to claim 1, wherein the voltage dividing circuit specifically includes: a first resistor, a second resistor, a first transistor and a second transistor, and the first resistor The resistance value is smaller than the resistance value of the second resistor. One end of the first transistor is connected to ground and the other end is connected in series with the first resistor. One end of the second transistor is connected to ground and the other end is connected to the second resistor. series; The first resistor and the second resistor are used to perform voltage dividing processing on the voltage dividing circuit, so that the first pulse width modulation signal and the second pulse width modulation signal have complementary duty cycles. 4. The device according to claim 3, characterized in that the device further includes: a first filter acquisition module and a second filter acquisition module, and the input of the first transistor and the first filter acquisition module terminals are connected, the first input terminal is connected to the output terminal of the first filter acquisition module, the second transistor is connected to the input terminal of the second filter acquisition module, the second input terminal is connected to the The output end of the second filter acquisition module is connected; The first filter acquisition module is used to collect the first pulse width modulation signal and transmit it to the first input terminal; The second filtering acquisition module is used to collect the second pulse width modulation signal and transmit it to the second input terminal. 5. The device according to claim 1, characterized in that the device further includes: a fault processing module, the fault processing module is connected to the micro control unit; The fault processing module is used to take countermeasures according to the mode of the power supply when a fault occurs in the high-voltage interlock circuit. 6. The device according to claim 5, characterized in that the countermeasures include: When the power supply is in discharge mode, limit the discharge power to the first threshold When the power supply is in the charging mode, limiting the charging power to the second threshold; When the power supply is not in the charging mode and the discharging mode, charging is prohibited. 7. The device according to claim 1, characterized in that the micro control unit is also specifically used for: When there is no fault in the high-voltage interlock circuit at the current moment or at the previous moment, it is determined that the state of the high-voltage interlock circuit is the first state, and the first state indicates that the high-voltage interlock circuit is in a working state; When the high-voltage interlock circuit failed at the last moment, the state of the high-voltage interlock circuit is determined to be the second state, and the second state indicates that the high-voltage interlock circuit is closed; At the last moment, the high-voltage interlock circuit did not malfunction and at the current moment, the When the high-voltage interlock circuit fails, the state of the high-voltage interlock circuit is determined to be the third state, The third state indicates that the operation of the high-voltage interlock loop is interrupted.