CN116859153A - High-voltage interlocking loop fault detection device - Google Patents
High-voltage interlocking loop fault detection device Download PDFInfo
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- CN116859153A CN116859153A CN202310785770.0A CN202310785770A CN116859153A CN 116859153 A CN116859153 A CN 116859153A CN 202310785770 A CN202310785770 A CN 202310785770A CN 116859153 A CN116859153 A CN 116859153A
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- 230000000295 complement effect Effects 0.000 claims abstract description 17
- 238000001914 filtration Methods 0.000 claims description 22
- 238000007599 discharging Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/005—Testing of electric installations on transport means
- G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2827—Testing of electronic protection circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2843—In-circuit-testing
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- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The application discloses a high-voltage interlocking loop fault detection device, which is used for detecting through setting two paths of pulse width modulation signals, wherein one path is used for detecting a control end aiming at a high-voltage interlocking loop, and the other path is used for detecting a detection end aiming at the high-voltage interlocking loop. The pulse width modulation signals with the fixed duty ratio are automatically calibrated, and the pulse width modulation signals are transmitted by combining the two paths, so that whether the detection end fails or the control end fails in the high-voltage interlocking loop can be judged according to the complementary condition between the two paths of pulse width signals. The fault detection device can detect faults of the detection end and the control end in the high-voltage interlocking loop, so that the reliability of fault detection of the high-voltage interlocking loop is improved.
Description
The present application claims priority from the national intellectual property agency, application number 202222422010.7, chinese patent application entitled "a high voltage interlock loop fault detection device", filed on month 13 of 2022, the entire contents of which are incorporated herein by reference.
Technical Field
The application relates to the technical field of digital signals, in particular to a high-voltage interlocking loop fault detection device.
Background
Along with the development of science and technology, the popularization degree of new forms of energy electric motor car is higher and higher, and the high voltage system in the electric motor car is an insulating closed system, when carrying out fault detection to high voltage interlocking wherein, its high voltage connector can cause high voltage exposure when not normally connecting, leads to the maintainer to electrocute easily, influences maintainer's personal safety. Therefore, a simple and efficient high-voltage interlock loop fault detection scheme is urgently needed to ensure the integrity and safety of the high-voltage system, thereby ensuring the safety of maintenance personnel.
In the prior art, when the fault detection of the high-voltage interlocking loop is performed, a single-chip microcomputer I/O port is generally adopted to output a pulse width modulation signal, the pulse width modulation signal is fed back to the single-chip microcomputer from the tail end of the high-voltage interlocking loop through a serial circuit in the high-voltage interlocking loop, and finally, a Micro Control Unit (MCU) in the single-chip microcomputer is used for processing the feedback signal to judge whether the fault occurs in the high-voltage interlocking loop.
In the above technical scheme, because the single chip microcomputer outputs the pulse width modulation signal through one path, in view of the fact that the signal passes through the control end and the detection end of the high-voltage interlocking loop, when the high-voltage interlocking fault occurs, whether the control end of the high-voltage interlocking loop fails or the detection end of the high-voltage interlocking loop fails cannot be judged. Therefore, the reliability of the detection result is low.
Disclosure of Invention
Based on the problems, the application provides a high-voltage interlocking loop fault detection device, which aims to solve the problem that the reliability of a high-voltage interlocking loop fault detection result is low.
The embodiment of the application discloses the following technical scheme:
a high voltage interlock loop fault detection device comprising: a micro control unit and a high-voltage interlocking loop; the high-voltage interlocking loop comprises a voltage dividing circuit; the output end, the first input end and the second input end of the micro control unit are all connected with the high-voltage interlocking loop;
the micro control unit is used for outputting an original pulse width modulation signal to the high-voltage interlocking loop through the output end;
the voltage dividing circuit is used for dividing the original pulse width modulation signal into a first pulse width modulation signal and a second pulse width modulation signal with different duty ratios;
the high-voltage interlocking loop is used for transmitting the first pulse width modulation signal to the first input end and transmitting the second pulse width modulation signal to the second input end;
the micro control unit is further configured to obtain a fault detection result of the high-voltage interlock loop according to the duty ratio of the first pwm signal, the duty ratio of the second pwm signal, and the duty ratio of the original pwm signal received from the first input terminal and the second input terminal. .
Optionally, the micro control unit is specifically configured to:
if the duty ratio of the original pulse width modulation signal is complementary with that of the first pulse width modulation signal, judging that the control end of the high-voltage interlocking loop is normal;
and if the duty ratio of the first pulse width modulation signal is complementary with the duty ratio of the second pulse width modulation signal, judging that the detection end of the high-voltage interlocking loop is normal.
Optionally, the voltage dividing circuit specifically includes: the circuit comprises a first resistor, a second resistor, a first triode and a second triode, wherein the resistance value of the first resistor is smaller than that of the second resistor, one end of the first triode is grounded, the other end of the first triode is connected with the first resistor in series, one end of the second triode is grounded, and the other end of the second triode is connected with the second resistor in series;
the first resistor and the second resistor are used for dividing the voltage of the circuit, so that the first pulse width modulation signal and the second pulse width modulation signal have different and complementary duty ratios.
Optionally, the apparatus further includes: the device comprises a first filtering acquisition module and a second filtering acquisition module, wherein a first triode is connected with the input end of the first filtering acquisition module, the first input end is connected with the output end of the first filtering acquisition module, the second triode is connected with the input end of the second filtering acquisition module, and the second input end is connected with the output end of the second filtering acquisition module;
the first filtering and collecting module is used for collecting the first pulse width modulation signal and transmitting the first pulse width modulation signal to the first input end;
the second filtering and collecting module is used for collecting the second pulse width modulation signal and transmitting the second pulse width modulation signal to the second input end.
Optionally, the apparatus further includes: the fault processing module is connected with the micro control unit;
and the fault processing module is used for taking corresponding measures according to the mode of the power supply when the high-voltage interlocking loop fails.
Optionally, the countermeasure includes:
when the power supply is in a discharge mode, limiting discharge power to a first threshold;
limiting charging power to a second threshold when the power supply is in a charging mode;
and when the power supply is not in the charging mode and the discharging mode, the charging is forbidden.
Optionally, the micro control unit is further specifically configured to:
when the high-voltage interlocking loop does not fail at the current moment and the last moment, determining that the state of the high-voltage interlocking loop is a first state, wherein the first state represents that the high-voltage interlocking loop is in a working state;
when the high-voltage interlocking loop fails at the previous moment, determining that the high-voltage interlocking loop state is a second state, wherein the second state represents that the high-voltage interlocking loop is closed; and when the high-voltage interlocking loop fails at the previous moment and the high-voltage interlocking loop fails at the current moment, determining the state of the high-voltage interlocking loop as a third state, wherein the third state indicates that the high-voltage interlocking loop is broken.
Compared with the prior art, the application has the following beneficial effects: the application provides a high-voltage interlocking loop fault detection device, which is used for detecting through setting two paths of pulse width modulation signals, wherein one path is used for detecting a control end aiming at a high-voltage interlocking loop, and the other path is used for detecting a detection end aiming at the high-voltage interlocking loop. The pulse width modulation signals with the fixed duty ratio are automatically calibrated by a user, the pulse width modulation signals are transmitted by combining two paths, and whether the corresponding detection end or control end fails can be judged by judging the complementation condition between the pulse width signals. The fault detection device can detect faults of the detection end and the control end in the high-voltage interlocking loop, so that the reliability of fault detection of the high-voltage interlocking loop is improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a fault detection device for a high-voltage interlocking loop according to an embodiment of the present application;
fig. 2 is a circuit diagram of a fault detection device for a high-voltage interlock loop according to an embodiment of the present application.
Detailed Description
As described above, in the prior art, when the fault detection of the high-voltage interlocking loop is performed, only a single I/O port is generally used to output a pulse width modulation signal to determine whether the high-voltage interlocking loop is in a fault state, and it cannot be determined whether the detection end of the high-voltage interlocking loop fails or the control end of the high-voltage interlocking loop fails.
Based on the detection, the application provides a high-voltage interlocking loop fault detection device, which is used for detecting through setting two paths of pulse width modulation signals, wherein one path is used for detecting a control end aiming at the high-voltage interlocking loop, and the other path is used for detecting a detection end aiming at the high-voltage interlocking loop. The pulse width modulation signals with the fixed duty ratio are automatically calibrated by a user, the pulse width modulation signals are transmitted by combining two paths, and whether the corresponding detection end or control end fails can be judged by judging the complementation condition between the pulse width signals. The fault detection device can detect faults of the detection end and the control end in the high-voltage interlocking loop, so that the reliability of fault detection of the high-voltage interlocking loop is improved.
In order to make the present application better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Device embodiment
Referring to fig. 1, the structure of a high-voltage interlocking loop fault detection device according to an embodiment of the present application is shown. Fig. 2 is a circuit diagram of a fault detection device for a high-voltage interlock loop according to an embodiment of the present application.
As shown in fig. 1, the high-voltage interlock loop fault detection device includes: a micro control unit 100 and a high voltage interlock loop 200; the high voltage interlock circuit 200 includes a voltage divider circuit; wherein the output terminal, the first input terminal and the second input terminal of the micro control unit 100 are all connected with the high voltage interlock circuit 200.
The micro control unit 100 is configured to output an original pulse width modulation signal to the high voltage interlock loop through the output terminal.
The voltage dividing circuit is used for dividing the original pulse width modulation signal into first pulse width modulation information good second pulse width modulation signals with different duty ratios.
The voltage dividing circuit is arranged in the high-voltage interlocking loop, a first resistor R1 and a second resistor R2 are arranged in the circuit, each resistor is connected with a corresponding first triode and a corresponding second triode in series, the resistor R1 is far smaller than the resistor R2, and the other end of each triode is grounded. The original pulse width modulation signal output by the micro control unit can be decomposed into two paths of pulse width modulation signals with different duty ratios by combining the use of the voltage dividing circuit.
The high voltage interlock loop 200 is configured to transmit the first pwm signal to the first input terminal and to transmit the second pwm signal to the second input terminal.
The first pulse width modulation signal and the second pulse width modulation signal are respectively transmitted to a first input end and a second input end of the micro control unit, the two pulse width modulation signals have different duty ratios, and when the micro control unit receives the pulse width modulation signals with the two different duty ratios, the fault condition of the high-voltage interlocking loop detection end can be judged according to the complementary condition of the duty ratios between the pulse width modulation signals.
The micro control unit 100 is further configured to obtain a fault detection result of the high voltage interlock loop according to the duty ratio of the first pwm signal, the duty ratio of the second pwm signal, and the duty ratio of the original pwm signal received from the first input terminal and the second input terminal.
The duty ratio of the original PWM signal may be calibrated by the user, and the micro control unit may determine whether the control end of the high voltage interlock loop fails according to the duty ratio between the original PWM signal (PWM in fig. 2) and the first PWM signal (PWM 1 in fig. 2).
For example, by calibrating the duty ratio of the original pwm signal to be 70%, after the processing of the voltage dividing circuit, the duty ratio of the first pwm signal is 30%, and the first pwm signal is complementary to the original pwm signal, it is determined that the control end of the high-voltage interlock loop is normal.
If the duty ratio of the original pulse width modulation signal is calibrated to be 70%, after the processing of the voltage division circuit, the duty ratio of the first pulse width modulation signal is 20%, and the first pulse width modulation signal and the original pulse width modulation signal do not meet the condition of duty ratio complementation, the control end fault of the high-voltage interlocking loop is determined.
Similarly, the micro control unit can also judge whether the detection end of the high-voltage interlocking loop fails according to the complementary condition of the duty ratio between the first pulse width modulation signal (PWM 1 in fig. 2) and the second pulse width modulation signal (PWM 2 in fig. 2).
For example, when the first pwm signal is 30% and the second pwm signal is 70%, the duty ratios of the first pwm signal and the second pwm signal are complementary, so as to determine that the detection end of the high voltage interlock loop is normal.
If the duty ratio of the first pulse width modulation signal is 60%, and the duty ratio of the second pulse width modulation signal is 30% after the processing of the voltage division circuit, the first pulse width modulation signal and the second pulse width modulation signal do not meet the condition of duty ratio complementation, and then the detection end fault of the high-voltage interlocking loop is determined.
Therefore, in the high-voltage interlocking loop fault detection device provided by the embodiment of the application, two paths of pulse width modulation signals are arranged for detection, one path is used for detecting a control end of the high-voltage interlocking loop, and the other path is used for detecting a detection end of the high-voltage interlocking loop. The pulse width modulation signals with the fixed duty ratio are automatically calibrated by a user, the pulse width modulation signals are transmitted by combining two paths, and whether the corresponding detection end or control end fails can be judged by judging the complementation condition between the pulse width signals. The fault detection device can detect faults of the detection end and the control end in the high-voltage interlocking loop, so that the reliability of fault detection of the high-voltage interlocking loop is improved.
In an alternative embodiment, the high-voltage interlock loop fault detection device further includes: and the fault processing module is connected with the micro control unit.
And the fault processing module is used for taking corresponding measures according to the mode of the power supply when the high-voltage interlocking loop fails.
The countermeasures include: when the power supply is in a discharge mode, the discharge power is limited to a first threshold. When the power supply is in a charging mode, the charging power is limited to a second threshold. And when the power supply is not in the charging mode and the discharging mode, the charging is forbidden.
Wherein the first threshold and the second threshold may be set by the user himself, for example, the first threshold is set to 50% and the second threshold is set to 0%. The countermeasure provided by the fault processing module can flexibly take corresponding measures according to the mode of the current power supply when the high-voltage interlocking loop fails, and flexibly and efficiently ensures the safety of using the power supply when the high-voltage interlocking loop fails.
In an alternative embodiment, the high-voltage interlocking loop fault detection device, the micro control unit is further specifically configured to:
and when the high-voltage interlocking loop does not fail at the current moment and the last moment, determining the state of the high-voltage interlocking loop as a first state, wherein the first state represents that the high-voltage interlocking loop is in a working state.
And when the high-voltage interlocking loop fails at the previous moment, determining that the high-voltage interlocking loop state is a second state, wherein the second state represents that the high-voltage interlocking loop is closed.
And when the high-voltage interlocking loop fails at the previous moment and the high-voltage interlocking loop fails at the current moment, determining the state of the high-voltage interlocking loop as a third state, wherein the third state indicates that the high-voltage interlocking loop is broken.
Different marks are set to represent different states of the high-voltage interlocking loop, so that a worker is more facilitated to observe the states of the high-voltage interlocking loop, and the efficiency of fault detection of the high-voltage interlocking loop is improved.
In an alternative embodiment, the high-voltage interlock loop fault detection device further includes: the first triode is connected with the input end of the first filtering acquisition module, the first input end is connected with the output end of the first filtering acquisition module, the second triode is connected with the input end of the second filtering acquisition module, and the second input end is connected with the output end of the second filtering acquisition module.
The first filtering and collecting module is used for collecting the first pulse width modulation signal and transmitting the first pulse width modulation signal to the first input end.
The second filtering and collecting module is used for collecting the second pulse width modulation signal and transmitting the second pulse width modulation signal to the second input end.
The specific working principle of the circuit diagram shown in fig. 2 is as follows:
wherein GND represents ground, VCC represents power supply, HVIL - Output channel representing high-voltage interlock loop, HVIL + Representing the input path of the high-pressure interlock loop.
When the high-voltage interlock loop is normal:
when the original pulse width modulation signal (PWM) is at a high level, the first triode (Q1) is conducted, and the first pulse width modulation signal (PWM 1) captures a low level signal. When the high-voltage interlocking is normally connected, the high-voltage interlocking circuit is conducted, the resistance value of the first resistor (R1) is far smaller than that of the second resistor (R2), the value of the voltage (U1) is smaller through voltage division, the second triode (Q2) cannot be conducted, and the second pulse width modulation signal (PWM 2)) captures a high-level signal.
When the PWM input signal is low, the Q1 transistor is turned off and PWM1 captures a high signal. When the high-voltage interlocking is normally connected, the high-voltage interlocking circuit is conducted, the Q1 is disconnected, the U1 voltage is the power supply Voltage (VCC), the Q2 triode is conducted, and the PWM2 captures a low-level signal.
By calibrating the PWM input signal duty cycle to be 70%, at this time the PWM1 duty cycle is 30% and the PWM2 duty cycle is 70% (without taking into account errors). The duty ratio of PWM1 is complementary with the duty ratio of PWM2, and the duty ratio of PWM is complementary with the duty ratio of PWM1, prove that the detection end and the control end of high-voltage interlocking are both in a normal state.
When the high-voltage interlock circuit fails, the circuit opens:
when the PWM input signal is at a high level, the Q1 triode is conducted, and the PWM1 captures a low level signal. The high-voltage interlocking loop is disconnected, the voltage of U1 is VCC, the triode Q2 is conducted, and the PWM2 captures a low-level signal.
When the PWM input signal is low, the Q1 transistor is turned off and PWM1 captures a high signal. The high-voltage interlocking loop is disconnected, the voltage of U1 is VCC, the triode Q2 is conducted, and the PWM2 captures a low-level signal.
When the input PWM duty ratio is 70%, the PWM1 duty ratio is 30%, the PWM2 duty ratio is 0%, and the PWM1 duty ratio and the PWM2 duty ratio are not complementary, so that the high-voltage interlocking loop detection end fault is indicated.
When the input PWM duty ratio is 70%, the PWM1 duty ratio is 20% and the PWM2 duty ratio is 80%, the duty ratios of PWM and PWM1 are not complementary, and the high-voltage interlocking loop control end is indicated to be faulty.
The embodiment of the application designs two paths of pulse width modulation signal feedback circuits, one path is used for self-checking of a control end, and when the duty ratio of a first pulse width modulation signal is complementary with that of an original pulse width modulation signal, the control end is proved to be normal; one path is used for detecting end diagnosis, and when the duty ratio of the first pulse width modulation signal is complementary with that of the second pulse width modulation signal, the high-voltage interlocking loop detecting end is proved to be normal. The fault detection device can detect faults of the detection end and the control end in the high-voltage interlocking loop, so that the reliability of fault detection of the high-voltage interlocking loop is improved.
The foregoing is only one specific embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (7)
1. A high voltage interlock loop fault detection device, comprising: a micro control unit and a high-voltage interlocking loop; the high-voltage interlocking loop comprises a voltage dividing circuit; the output end, the first input end and the second input end of the micro control unit are all connected with the high-voltage interlocking loop;
the micro control unit is used for outputting an original pulse width modulation signal to the high-voltage interlocking loop through the output end;
the voltage dividing circuit is used for dividing the original pulse width modulation signal into a first pulse width modulation signal and a second pulse width modulation signal with different duty ratios;
the high-voltage interlocking loop is used for transmitting the first pulse width modulation signal to the first input end and transmitting the second pulse width modulation signal to the second input end;
the micro control unit is further configured to obtain a fault detection result of the high-voltage interlock loop according to the duty ratio of the first pwm signal, the duty ratio of the second pwm signal, and the duty ratio of the original pwm signal received from the first input terminal and the second input terminal.
2. The device according to claim 1, characterized in that said micro-control unit is in particular adapted to:
if the duty ratio of the original pulse width modulation signal is complementary with that of the first pulse width modulation signal, judging that the control end of the high-voltage interlocking loop is normal;
and if the duty ratio of the first pulse width modulation signal is complementary with the duty ratio of the second pulse width modulation signal, judging that the detection end of the high-voltage interlocking loop is normal.
3. The apparatus of claim 1, wherein the voltage divider circuit comprises: the circuit comprises a first resistor, a second resistor, a first triode and a second triode, wherein the resistance value of the first resistor is smaller than that of the second resistor, one end of the first triode is grounded, the other end of the first triode is connected with the first resistor in series, one end of the second triode is grounded, and the other end of the second triode is connected with the second resistor in series;
the first resistor and the second resistor are used for performing voltage division processing on the voltage division circuit, so that the first pulse width modulation signal and the second pulse width modulation signal have complementary duty ratios.
4. A device according to claim 3, characterized in that the device further comprises: the device comprises a first filtering acquisition module and a second filtering acquisition module, wherein a first triode is connected with the input end of the first filtering acquisition module, the first input end is connected with the output end of the first filtering acquisition module, the second triode is connected with the input end of the second filtering acquisition module, and the second input end is connected with the output end of the second filtering acquisition module;
the first filtering and collecting module is used for collecting the first pulse width modulation signal and transmitting the first pulse width modulation signal to the first input end;
the second filtering and collecting module is used for collecting the second pulse width modulation signal and transmitting the second pulse width modulation signal to the second input end.
5. The apparatus of claim 1, wherein the apparatus further comprises: the fault processing module is connected with the micro control unit;
and the fault processing module is used for taking corresponding measures according to the mode of the power supply when the high-voltage interlocking loop fails.
6. The apparatus of claim 5, wherein the countermeasures comprise:
when the power supply is in the discharge mode, limiting the discharge power to a first threshold value
Limiting charging power to a second threshold when the power supply is in a charging mode;
and when the power supply is not in the charging mode and the discharging mode, the charging is forbidden.
7. The device according to claim 1, characterized in that said micro-control unit is further specifically adapted to:
when the high-voltage interlocking loop does not fail at the current moment and the last moment, determining that the state of the high-voltage interlocking loop is a first state, wherein the first state represents that the high-voltage interlocking loop is in a working state;
when the high-voltage interlocking loop fails at the previous moment, determining that the high-voltage interlocking loop state is a second state, wherein the second state represents that the high-voltage interlocking loop is closed;
at the last moment the high-voltage interlocking loop is not failed and at the current moment
When the high-voltage interlocking loop fails, determining the state of the high-voltage interlocking loop as a third state,
the third state indicates that the high-pressure interlock loop operation is interrupted.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2022224220107 | 2022-09-13 | ||
| CN202222422010 | 2022-09-13 |
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| CN116859153A true CN116859153A (en) | 2023-10-10 |
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| CN202310785770.0A Pending CN116859153A (en) | 2022-09-13 | 2023-06-29 | High-voltage interlocking loop fault detection device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118393266A (en) * | 2024-06-27 | 2024-07-26 | 比亚迪股份有限公司 | High-voltage interlock detection method and device, storage medium, electronic equipment and vehicle |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118393266A (en) * | 2024-06-27 | 2024-07-26 | 比亚迪股份有限公司 | High-voltage interlock detection method and device, storage medium, electronic equipment and vehicle |
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