CN116847656A - Flash memory forming method - Google Patents
Flash memory forming method Download PDFInfo
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- CN116847656A CN116847656A CN202310789623.0A CN202310789623A CN116847656A CN 116847656 A CN116847656 A CN 116847656A CN 202310789623 A CN202310789623 A CN 202310789623A CN 116847656 A CN116847656 A CN 116847656A
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- Prior art keywords
- layer
- hard mask
- propylene glycol
- monomethyl ether
- glycol monomethyl
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- 230000015654 memory Effects 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 238000010168 coupling process Methods 0.000 claims abstract description 29
- 238000005859 coupling reaction Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 28
- 230000008878 coupling Effects 0.000 claims abstract description 26
- ARXJGSRGQADJSQ-UHFFFAOYSA-N 1-methoxypropan-2-ol Chemical compound COCC(C)O ARXJGSRGQADJSQ-UHFFFAOYSA-N 0.000 claims abstract description 24
- LLHKCFNBLRBOGN-UHFFFAOYSA-N propylene glycol methyl ether acetate Chemical compound COCC(C)OC(C)=O LLHKCFNBLRBOGN-UHFFFAOYSA-N 0.000 claims abstract description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 13
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 238000011049 filling Methods 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 13
- 230000003667 anti-reflective effect Effects 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 20
- 239000000126 substance Substances 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a flash memory forming method, which comprises the following steps: forming an active region in a substrate, and sequentially forming a coupling oxide layer, a floating gate polysilicon layer, a silicon nitride layer and a hard mask layer which is ethyl silicate silicon dioxide on the substrate; cleaning the surface of the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate; removing the rest propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate; sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer; patterning the photoresist layer and the anti-reflection layer; sequentially dry etching the hard mask layer, the silicon nitride layer, the floating gate polysilicon layer, the coupling oxide layer and the active region according to the patterned photoresist layer and the anti-reflection layer to form a shallow trench; and filling oxide into the shallow trenches to form shallow trench isolation structures. The surface of the hard mask layer is cleaned, so that substances in the hard mask layer are prevented from reacting with the anti-reflection layer, and finally, the situation that the bottom of the shallow trench isolation structure is recessed towards the active region is prevented.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a flash memory.
Background
Flash memory has the advantages of large storage capacity and high erasing speed, and thus has become the mainstream of nonvolatile memory.
The flash memory of the prior art is various, and the manufacturing method thereof is to provide a silicon substrate, form an active region in the substrate, and sequentially form a coupling oxide layer, a floating gate polysilicon layer, a silicon nitride layer and a hard mask layer on the substrate. And forming a groove by etching the hard mask layer, the silicon nitride layer, the floating gate polycrystalline silicon layer, the coupling oxide layer and the active region with partial depth, and filling oxide into the groove to form a shallow groove isolation structure, wherein the shallow groove isolation structure divides the active region into a plurality of devices, so that a plurality of devices are formed on the substrate in a separated mode.
However, the inventors have found that the bottom of the shallow trench isolation structure of a portion of the flash memory is recessed into the active region under the shallow trench isolation structure, thereby possibly degrading the performance of the flash memory.
Disclosure of Invention
The invention aims to provide a method for forming a flash memory, which can prevent the bottom of a shallow trench isolation structure of the formed flash memory from sinking towards an active area below the shallow trench isolation structure, thereby improving the performance of the flash memory.
In order to achieve the above object, the present invention provides a method for forming a flash memory, including:
providing a substrate, forming an active region in the substrate, and sequentially forming a coupling oxide layer, a floating gate polycrystalline silicon layer, a silicon nitride layer and a hard mask layer on the substrate, wherein the hard mask layer is ethyl silicate silicon dioxide;
cleaning the surface of the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate;
removing the rest propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate;
sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer;
patterning the photoresist layer and the anti-reflection layer;
sequentially dry etching the hard mask layer, the silicon nitride layer, the floating gate polycrystalline silicon layer, the coupling oxide layer and the substrate according to the patterned photoresist layer and the anti-reflection layer, and stopping etching in the active region to form a shallow trench;
and filling oxide into the shallow trench to form a shallow trench isolation structure.
Optionally, in the method for forming a flash memory, the substrate includes a wafer.
Optionally, in the method for forming a flash memory, the concentration of propylene glycol monomethyl ether is 70wt%.
Optionally, in the method for forming a flash memory, the concentration of the propylene glycol monomethyl ether acetate is 30wt%.
Optionally, in the method for forming a flash memory, the method for cleaning the surface of the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate includes:
and soaking the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate.
Optionally, in the method for forming a flash memory, the method for removing the remaining propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate includes:
and swinging the hard mask layer to spin-dry the rest propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate.
Optionally, in the method for forming a flash memory, the method for patterning the photoresist layer and the anti-reflection layer includes:
and photoetching the photoresist layer and the anti-reflection layer to form a patterned photoresist layer and an anti-reflection layer, wherein the patterned photoresist layer and the anti-reflection layer expose part of the surface of the hard mask layer.
The invention also provides a flash memory forming method, which comprises the following steps:
providing a substrate, forming an active region in the substrate, and sequentially forming a coupling oxide layer, a floating gate polycrystalline silicon layer, a silicon nitride layer and a hard mask layer on the substrate, wherein the hard mask layer is ethyl silicate silicon dioxide;
ashing the surface of the hard mask layer by using gas;
sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer;
patterning the photoresist layer and the anti-reflection layer;
sequentially dry etching the hard mask layer, the silicon nitride layer, the floating gate polycrystalline silicon layer, the coupling oxide layer and the substrate according to the patterned photoresist layer and the anti-reflection layer, and stopping etching in the active region to form a shallow trench;
and filling oxide into the shallow trench to form a shallow trench isolation structure.
Optionally, in the method for forming a flash memory, the gas includes H 2 N 2 Or CF (compact flash) 4 。
Optionally, in the method for forming a flash memory, the method for patterning the photoresist layer and the anti-reflection layer includes:
and photoetching the photoresist layer and the anti-reflection layer to form a patterned photoresist layer and an anti-reflection layer, wherein the patterned photoresist layer and the anti-reflection layer expose part of the surface of the hard mask layer.
In the method for forming the flash memory, the surface of the hard mask layer is cleaned or ashed by propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate, so that substances in the hard mask layer are prevented from reacting with the anti-reflection layer, the situation that the hard mask layer is sunken is prevented, and finally the situation that the shallow trench isolation structure is sunken towards an active area below the shallow trench isolation structure is prevented, and the performance of the flash memory is improved.
Drawings
FIGS. 1 through 3 are schematic diagrams of prior art flash memories;
FIG. 4 is a flowchart of a method for forming a flash memory according to a first embodiment of the present invention;
fig. 5 to 8 are schematic diagrams illustrating a method for forming a flash memory according to a first embodiment of the invention;
FIG. 9 is a flowchart of a method for forming a flash memory according to a second embodiment of the present invention;
fig. 10 to 13 are schematic diagrams illustrating a method for forming a flash memory according to a second embodiment of the invention;
in the figure: 110-active region, 120-coupling oxide layer, 130-floating gate polysilicon layer, 140-silicon nitride layer, 150-hard mask layer, 160-anti-reflection layer, 170-photoresist layer, 180-shallow trench, 190-shallow trench isolation structure, 210-active region, 220-coupling oxide layer, 230-floating gate polysilicon layer, 240-silicon nitride layer, 250-hard mask layer, 260-anti-reflection layer, 270-photoresist layer, 280-shallow trench, 290-shallow trench isolation structure, 310-active region, 320-coupling oxide layer, 330-floating gate polysilicon layer, 340-silicon nitride layer, 350-hard mask layer, 351-recess, 360-anti-reflection layer, 370-photoresist layer, 380-shallow trench, 390-shallow trench isolation structure.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The inventor has found that the flash memory with the bottom of the shallow trench isolation structure having the recess in the downward active region is mainly an ArF process with a hard mask layer on the surface, and referring to fig. 1, the flash memory has the steps of exposing the hard mask layer 350, the silicon nitride layer 340, the floating gate polysilicon layer 330, the coupling oxide layer 320 and the active region 310 to light before forming the trench, coating the anti-reflection layer 360 and the photoresist layer 370 on the hard mask layer before exposing the hard mask layer, and exposing the photoresist layer 370. Referring to fig. 2, after the hard mask layer 350, the silicon nitride layer 340, the floating gate polysilicon layer 330, the coupling oxide layer 320 and the active region 310 are etched to form the shallow trench 380, a recess extending upward toward the active region 310 is found at the bottom of the shallow trench 380 by dicing. Referring to fig. 3, after the shallow trench 380 is filled with silicon oxide, it is found that the shallow trench isolation structure 390 is recessed toward the underlying active region 310. And, it was found by a plurality of defective flash memories that depressions appear at different places of the bottom of the shallow trench isolation structure, and that there is no regularity in the places where they appear. Such defects are not found in other forms of flash memory such as flash memory structures that do not have ethyl silicate based silicon dioxide as a hard mask layer. Thus, through analysis of the process and flow of flash memory by the inventors, it was found that the surface of the ethyl silicate-based silicon dioxide layer as the hard mask layer had a substance that reacted with the anti-reflective layer. The surface of the hard mask layer is recessed through reaction, so that each layer is recessed downwards due to the characteristic of dry etching in subsequent etching, the recess is formed at the bottom of the shallow trench after the etching is finished, the recess is prolonged towards an active region below the shallow trench, and the shallow trench is filled with silicon oxide to form a shallow trench isolation structure, and then the shallow trench isolation structure is recessed towards the active region below. Thus, in view of this problem, the present invention proposes two embodiments for solving this problem.
Example 1
Referring to fig. 4, the present invention provides a method for forming a flash memory, which includes:
s11: providing a substrate, forming an active region in the substrate, and sequentially forming a coupling oxide layer, a floating gate polycrystalline silicon layer, a silicon nitride layer and a hard mask layer on the substrate, wherein the hard mask layer is ethyl silicate silicon dioxide;
s12: cleaning the surface of the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate;
s13: removing the rest propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate;
s14: sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer;
s15: patterning the photoresist layer and the anti-reflection layer;
s16: etching the hard mask layer, the silicon nitride layer, the floating gate polysilicon layer, the coupling oxide layer and the substrate in sequence according to the patterned photoresist layer and the anti-reflection layer, and stopping etching in the active region to form a shallow trench;
s17: and filling oxide into the shallow trenches to form shallow trench isolation structures.
Specifically, referring to fig. 5, a substrate is provided first, and the substrate may be a silicon substrate, for example, a wafer, and ions are implanted into the substrate to form an active region 110. Next, a coupling oxide layer 120 is formed on the substrate by depositing an oxide, the coupling oxide layer 120 having a thickness of about 90 a. Next, a floating gate polysilicon layer 130 is formed on the coupling oxide layer 120 by depositing polysilicon, and the thickness of the floating gate polysilicon layer 130 is about 300 a. Next, a silicon nitride layer 140 is formed on the floating gate polysilicon layer 130 by depositing silicon nitride, wherein the thickness of the silicon nitride layer 140 is about 800 a. Next, a hard mask layer 150 is formed on the silicon nitride layer 140 by depositing ethyl silicate based silicon dioxide, and the thickness of the hard mask layer 150 is about 450 a.
Next, the entire surface of the hard mask layer 150 is soaked with propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate, at which time the entire structure may be soaked in propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate and then spin-coated on the surface of the hard mask layer 150, and the inventors found that after the anti-reflection layer is coated on the hard mask layer 150, a portion of the anti-reflection layer may react with impurities or other substances on the hard mask layer 150, thereby recessing the anti-reflection layer 160. The entire surface of the hard mask layer 150 is cleaned using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate. And then spin-drying the propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate.
Next, referring to fig. 6, an anti-reflection layer 160 and a photoresist layer 170 are sequentially formed on the hard mask layer 150 by a deposition method.
Next, referring to fig. 7, the photoresist layer 170 and the anti-reflective layer 160 are patterned by photolithography as required to form a patterned photoresist layer and a patterned anti-reflective layer. The hard mask layer 150, the silicon nitride layer 140, the floating gate polysilicon layer 130, the coupling oxide layer 120 and the active region 110 are vertically etched in the direction of the active region 110 using a dry etching method according to the patterned photoresist layer and the patterned anti-reflection layer, and the etching is stopped inside the active region 110 to form the shallow trench 180. Next, referring to fig. 8, an oxide, such as silicon dioxide, is filled into the shallow trench 180 to form a shallow trench isolation structure 190.
Example two
Referring to fig. 9, the present invention provides a method for forming a flash memory, which includes:
s21: providing a substrate, forming an active region in the substrate, and sequentially forming a coupling oxide layer, a floating gate polycrystalline silicon layer, a silicon nitride layer and a hard mask layer on the substrate, wherein the hard mask layer is ethyl silicate silicon dioxide;
s22: ashing the surface of the hard mask layer using a gas;
s23: sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer;
s24: patterning the photoresist layer and the anti-reflection layer;
s25: etching the hard mask layer, the silicon nitride layer, the floating gate polysilicon layer, the coupling oxide layer and the substrate in sequence according to the patterned photoresist layer and the anti-reflection layer, and stopping etching in the active region to form a shallow trench;
s26: and filling oxide into the shallow trenches to form shallow trench isolation structures.
Specifically, referring to fig. 10, a substrate is provided first, and the substrate may be a silicon substrate, for example, a wafer, and ions are implanted into the substrate to form an active region 210. Next, a coupling oxide layer 220 is formed on the substrate by depositing an oxide, the coupling oxide layer 220 having a thickness of about 90 a. Next, a floating gate polysilicon layer 230 is formed on the coupling oxide layer 220 by depositing polysilicon, and the thickness of the floating gate polysilicon layer 230 is about 300 a. Next, a silicon nitride layer 240 is formed on the floating gate polysilicon layer 230 by depositing silicon nitride, the thickness of the silicon nitride layer 240 being approximately 800 a. Next, a hard mask layer 250 is formed on the silicon nitride layer 240 by depositing an ethyl silicate based silicon dioxide, the hard mask layer 250 having a thickness of about 450 a.
Next, the surface of the hard mask layer 250 is ashed with a gas, which may be H 2 N 2 Or CF (compact flash) 4 。
Next, referring to fig. 11, an anti-reflection layer 260 and a photoresist layer 270 are sequentially formed on the hard mask layer 250 by a deposition method.
Next, referring to fig. 12, the photoresist layer 270 and the anti-reflective layer 260 are patterned by photolithography as required to form a patterned photoresist layer and a patterned anti-reflective layer. The hard mask layer 250, the silicon nitride layer 240, the floating gate polysilicon layer 230, the coupling oxide layer 220 and the active region 210 are vertically etched in the direction of the active region 210 using a dry etching method according to the patterned photoresist layer and the patterned anti-reflection layer, and the etching is stopped inside the active region 210 to form the shallow trench 280. Next, referring to fig. 13, shallow trench isolation structures 290 are formed by filling the shallow trenches 280 with an oxide, such as silicon dioxide.
In summary, in the method for forming a flash memory according to the embodiment of the present invention, the surface of the hard mask layer is cleaned or ashed with propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate, so as to prevent some substances in the hard mask layer from reacting with the anti-reflective layer, thereby preventing the hard mask layer from recessing, and finally preventing the shallow trench isolation structure from recessing towards the active area below the shallow trench isolation structure, reducing leakage, and improving the performance of the flash memory.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method for forming a flash memory, comprising:
providing a substrate, forming an active region in the substrate, and sequentially forming a coupling oxide layer, a floating gate polycrystalline silicon layer, a silicon nitride layer and a hard mask layer on the substrate, wherein the hard mask layer is ethyl silicate silicon dioxide;
cleaning the surface of the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate;
removing the rest propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate;
sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer;
patterning the photoresist layer and the anti-reflection layer;
sequentially dry etching the hard mask layer, the silicon nitride layer, the floating gate polycrystalline silicon layer, the coupling oxide layer and the substrate according to the patterned photoresist layer and the anti-reflection layer, and stopping etching in the active region to form a shallow trench;
and filling oxide into the shallow trench to form a shallow trench isolation structure.
2. The method of claim 1, wherein the substrate comprises a wafer.
3. The method of forming a flash memory of claim 1, wherein the propylene glycol monomethyl ether concentration is 70wt%.
4. The method of forming flash memory of claim 1, wherein the propylene glycol monomethyl ether acetate concentration is 30wt%.
5. The method of claim 1, wherein the cleaning the surface of the hard mask layer using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate comprises:
and soaking the hard mask layer by using propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate.
6. The method of forming a flash memory of claim 1, wherein the method of removing the remaining propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate comprises:
and swinging the hard mask layer to spin-dry the rest propylene glycol monomethyl ether or propylene glycol monomethyl ether acetate.
7. The method of forming a flash memory of claim 1, wherein the patterning the photoresist layer and the anti-reflective layer comprises:
and photoetching the photoresist layer and the anti-reflection layer to form a patterned photoresist layer and an anti-reflection layer, wherein the patterned photoresist layer and the anti-reflection layer expose part of the surface of the hard mask layer.
8. A method for forming a flash memory, comprising:
providing a substrate, forming an active region in the substrate, and sequentially forming a coupling oxide layer, a floating gate polycrystalline silicon layer, a silicon nitride layer and a hard mask layer on the substrate, wherein the hard mask layer is ethyl silicate silicon dioxide;
ashing the surface of the hard mask layer by using gas;
sequentially forming an anti-reflection layer and a photoresist layer on the hard mask layer;
patterning the photoresist layer and the anti-reflection layer;
sequentially dry etching the hard mask layer, the silicon nitride layer, the floating gate polycrystalline silicon layer, the coupling oxide layer and the substrate according to the patterned photoresist layer and the anti-reflection layer, and stopping etching in the active region to form a shallow trench;
and filling oxide into the shallow trench to form a shallow trench isolation structure.
9. The method of forming a flash memory of claim 8, wherein the gas comprises H 2 N 2 Or CF (compact flash) 4 。
10. The method of forming a flash memory of claim 8, wherein the patterning the photoresist layer and the anti-reflective layer comprises:
and photoetching the photoresist layer and the anti-reflection layer to form a patterned photoresist layer and an anti-reflection layer, wherein the patterned photoresist layer and the anti-reflection layer expose part of the surface of the hard mask layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310789623.0A CN116847656A (en) | 2023-06-29 | 2023-06-29 | Flash memory forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310789623.0A CN116847656A (en) | 2023-06-29 | 2023-06-29 | Flash memory forming method |
Publications (1)
| Publication Number | Publication Date |
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| CN116847656A true CN116847656A (en) | 2023-10-03 |
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| CN202310789623.0A Pending CN116847656A (en) | 2023-06-29 | 2023-06-29 | Flash memory forming method |
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| CN (1) | CN116847656A (en) |
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- 2023-06-29 CN CN202310789623.0A patent/CN116847656A/en active Pending
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