CN116845103A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

Info

Publication number
CN116845103A
CN116845103A CN202210735355.XA CN202210735355A CN116845103A CN 116845103 A CN116845103 A CN 116845103A CN 202210735355 A CN202210735355 A CN 202210735355A CN 116845103 A CN116845103 A CN 116845103A
Authority
CN
China
Prior art keywords
region
semiconductor
semiconductor region
conductivity type
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210735355.XA
Other languages
Chinese (zh)
Inventor
田中克久
河野洋志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Publication of CN116845103A publication Critical patent/CN116845103A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Abstract

The embodiment provides a semiconductor device capable of improving withstand voltage. The semiconductor device of the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a plurality of fifth semiconductor regions of the second conductivity type, a plurality of sixth semiconductor regions of the second conductivity type, and a second electrode. The first semiconductor region includes a first region and a second region. The fourth semiconductor region is disposed between the first region and the gate electrode. The plurality of fifth semiconductor regions are located around the fourth semiconductor region along the first face, and are separated from each other in a second direction from the first region toward the second region. The plurality of sixth semiconductor regions are located around the second semiconductor region along the first face and are separated from each other in the second direction. Each of the plurality of sixth semiconductor regions has a lower impurity concentration of the second conductivity type than each of the plurality of fifth semiconductor regions.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Related application
The present application enjoys priority based on Japanese patent application No. 2022-46944 (application date: day 23 of 3.2022). The present application includes the entire contents of the basic application by reference to the basic application.
Technical Field
Embodiments of the present application relate to a semiconductor device.
Background
A semiconductor device such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is used for power conversion and the like. The withstand voltage of the semiconductor device is preferable.
Disclosure of Invention
The application provides a semiconductor device capable of improving withstand voltage.
A semiconductor device of an embodiment is provided with: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the first conductivity type; a gate electrode; a fourth semiconductor region of the second conductivity type; a plurality of fifth semiconductor regions of the second conductivity type; a plurality of sixth semiconductor regions of the second conductivity type; and a second electrode. The first semiconductor region is arranged above the first electrode and comprises a first region and a second region arranged around the first region. The second semiconductor region is arranged above the first region. The third semiconductor region is disposed over a portion of the second semiconductor region. The gate electrode faces the second semiconductor region with a gate insulating layer therebetween in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The fourth semiconductor region is disposed between the first region and the gate electrode. The plurality of fifth semiconductor regions are located around the fourth semiconductor region along a first face perpendicular to the first direction, and are separated from each other in a second direction from the first region toward the second region. The plurality of sixth semiconductor regions are located around the second semiconductor region along the first face, separated from each other in the second direction. Each of the plurality of sixth semiconductor regions has a lower impurity concentration of the second conductivity type than each of the plurality of fifth semiconductor regions. The second electrode is arranged on the second semiconductor region and the third semiconductor region.
Drawings
Fig. 1 is a plan view showing a semiconductor device according to a first embodiment.
Fig. 2 is a sectional view of A1-A2 of fig. 1 and 3.
Fig. 3 is a plan view showing the semiconductor device according to the first embodiment.
Fig. 4 is a sectional view of B1-B2 of fig. 1 and 3.
Fig. 5 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the first embodiment.
Fig. 6 (a) and (b) are plan views showing a part of a semiconductor device according to a first modification of the first embodiment.
Fig. 7 is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.
Fig. 8 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the second embodiment.
Fig. 9 is a cross-sectional view showing a part of the semiconductor device according to the third embodiment.
Fig. 10 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the third embodiment.
Fig. 11 is a cross-sectional view showing a part of a semiconductor device according to a second modification of the third embodiment.
Fig. 12 is a cross-sectional view showing a part of a semiconductor device according to a third modification of the third embodiment.
Fig. 13 is a cross-sectional view showing a part of a semiconductor device according to a fourth modification of the third embodiment.
Detailed Description
Hereinafter, embodiments of the present application will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, and the like are not necessarily the same as those in reality. Even when the same portions are shown, the dimensions and ratios of the portions may be different from each other according to the drawings.
In the following description and the accompanying drawings, n + ，n，n － And p + ，p，p － The reference sign of (2) indicates the relative level of each impurity concentration. That is, the impurity concentration of the mark labeled with "+" is relatively higher than the impurity concentration of any mark not labeled with "+" or "-" and the impurity concentration of the mark labeled with "-" is relatively lower than the impurity concentration of any mark not labeled. These marks show the relative levels of the substantial impurity concentrations of the impurities after mutual compensation in the case where both the p-type impurity and the n-type impurity are contained in the respective regions.
For each embodiment described below, the p-type and n-type of each semiconductor region may be inverted to implement each embodiment.
(first embodiment)
Fig. 1 and 3 are plan views showing a semiconductor device according to a first embodiment. Fig. 2 is a sectional view of A1-A2 of fig. 1 and 3. Fig. 4 is a sectional view of B1-B2 of fig. 1 and 3. In FIG. 3, n is omitted + Source regions 3, p + A contact region 9b, a gate electrode 10, an insulating layer 15, a source electrode 22, and the like.
The semiconductor device of the first embodiment is a MOSFET. As shown in fig. 1 to 4, a semiconductor device 100 according to a first embodiment includes: n is n － A type (first conductivity type) drift region 1 (first semiconductor region); a p-type (second conductivity type) base region 2 (second semiconductor region); n is n + A source region 3 (third semiconductor region); p is p + A semiconductor region 4 (fourth semiconductor region); p is p + A type semiconductor region 5 (an example of a fifth semiconductor region); p is p － A type semiconductor region 6 (an example of a sixth semiconductor region); a p-type semiconductor region 7 (an example of a seventh semiconductor region); n is n + A drain region 9a; p is p + A pattern contact region 9b; n is n + A semiconductor region 9c; a gate electrode 10; a drain electrode 21 (first electrode) and a source electrode 22 (second electrode).
In the description of the embodimentsAn XYZ orthogonal coordinate system is used. Will be directed from the drain electrode 21 toward n － The direction of the type drift region 1 is set to the Z direction (first direction). One direction orthogonal to the Z direction is referred to as the X direction. The direction orthogonal to the X direction and the Z direction is referred to as the Y direction. Further, here, the drain electrode 21 is directed toward n － The direction of the type drift region 1 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the drain electrodes 21 and n － The direction of the relative positional relationship of the type drift region 1 is independent of the direction of gravity.
As shown in fig. 1, a source electrode 22 is provided on the upper surface of the semiconductor device 100. The periphery of the source electrode 22 is covered with an insulating layer 15.
As shown in fig. 2 and 4, a drain electrode 21 is provided on the lower surface of the semiconductor device 100. n is n + The drain region 9a is provided on the drain electrode 21 and electrically connected to the drain electrode 21.n is n － The drift region 1 is arranged at n + Over the drain region 9 a. n is n － The type drift region 1 is via n + The drain region 9a is electrically connected to the drain electrode 21.
As shown in fig. 1 to 4, n － The type drift region 1 includes a first region R1 and a second region R2. The second region R2 is provided around the first region R1 along the X-Y plane (first plane). The first region R1 corresponds to an element region of the semiconductor device 100. The second region R2 corresponds to a terminal region of the semiconductor device 100.
As shown in fig. 2, the p-type base region 2 is provided over the first region R1. n is n + Source region 3 and p + The type contact region 9b is selectively provided over the p-type base region 2.
The gate electrode 10 faces the p-type base region 2 through the gate insulating layer 11 in the X direction. In the illustrated example, the gate electrode 10 is further formed by a gate insulating layer 11 and n － Part of a type drift region 1 and n + A portion of the source region 3 is facing. P is p + The semiconductor region 4 is provided in the Z direction with n － Between the type drift region 1 and the gate electrode 10. P is p + The p-type impurity concentration of the type semiconductor region 4 is higher than that of the p-type base region 2High. P is p + The type semiconductor region 4 is separated from the p-type base region 2.
As illustrated in the figure, n － The type drift region 1 may include portions 1a and 1b having different n-type impurity concentrations. The portion 1b is provided between the portion 1a and the p-type base region 2 in the Z direction and juxtaposed with the gate electrode 10 in the X direction. The n-type impurity concentration of the portion 1b is higher than that of the portion 1 a.
Portions 1b, n + Source regions 3, p + Semiconductor regions 4, p + The plurality of contact regions 9b and the plurality of gate electrodes 10 extend along the Y direction and are provided in the X direction. As shown in fig. 2 to 4, the p-type base region 2 is provided between the gate electrodes 10 and around the plurality of gate electrodes 10.
As shown in fig. 1 and 2, the source electrode 22 is disposed on the first region R1 and is located at a plurality of n + Source region 3 and a plurality of p-type + Over the shaped contact area 9 b. Source electrode 22 and a plurality of n + Source region 3 and a plurality of p-type + The pattern contact regions 9b are electrically connected. The p-type base region 2 is formed by p + The pattern contact region 9b is electrically connected to the source electrode 22. The gate electrode 10 is electrically separated from the source electrode 22 by an insulating layer 15.
As shown in FIG. 4, p + The type semiconductor region 5 is provided in the second region R2. As shown in fig. 3 and 4, p － Semiconductor regions 6, n + The type semiconductor region 9c is provided above the second region R2. P is p － The type semiconductor region 6 is located around the p-type base region 2 along the X-Y plane. P is p － The p-type impurity concentration of the type semiconductor region 6 is lower than that of the p-type base region 2.P is p － The plurality of the semiconductor regions 6 are provided in a direction from the first region R1 toward the second region R2 (radial direction: second direction). Radially parallel to the X-Y plane. Each p － The semiconductor regions 6 are separated from each other, adjacent p － The intervals between the semiconductor regions 6 are increased as they are oriented in the radial direction.
p + The semiconductor regions 5 are located at a plurality of p-type along the X-Y plane + Around the shaped semiconductor region 4. P is p + P-type impurity of semiconductor region 5Concentration and p + The p-type impurity concentration of the type semiconductor region 4 may be the same or different. P is p + The p-type impurity concentration of the p-type semiconductor region 5 is higher than that of the p-type base region 2, and is higher than that of the p-type base region 2 － The p-type impurity concentration of the type semiconductor region 6 is high. P is p + Semiconductor regions 5 and p － The semiconductor region 6 is likewise provided in plurality in the radial direction. Each p + The semiconductor regions 5 are separated from each other, adjacent p + The interval between the semiconductor regions 5 increases as the interval extends in the radial direction. In addition, a plurality of p － Semiconductor region 6 and a plurality of p-type + The semiconductor regions 5 are separated in the Z direction.
n + The semiconductor regions 9c are located at a plurality of p-s along the X-Y plane － Around the semiconductor region 6. n is n + Semiconductor region 9c and a plurality of p-type semiconductor regions － The shaped semiconductor regions 6 are separated and arranged along the outer periphery of the semiconductor device 100. n is n + The n-type impurity concentration of the type semiconductor region 9c is higher than that of the portion 1b. In a part of the part 1b, a plurality of p － Semiconductor region 6 and n + An insulating layer 15 is provided on the semiconductor region 9 c. That is, in the second region R2, a part of the portion 1b and a plurality of p － Semiconductor region 6 and n + The type semiconductor region 9c is covered with an insulating layer 15.
As shown in FIG. 4, a plurality of p + P at the end in the X direction among the semiconductor regions 4 + The type semiconductor region 4a may also meet the p-type base region 2. In this case, p is + The electrode 10a surrounded by the semiconductor region 4a may or may not function as a gate electrode (for example, a floating electrode). The electrode 10a may be electrically connected to the gate electrode 10 or may be electrically separated from the gate electrode 10. Multiple p + Among the semiconductor regions 5, p nearest to the first region R1 + The semiconductor region 5a may be p-type + The shaped semiconductor regions 4a meet. In this case, p + The semiconductor region 5a is connected to the semiconductor layer via p + The type semiconductor region 4a and the p-type base region 2 are electrically connected to the source electrode 22. Multiple p － Semiconductor regionP of 6 closest to the first region R1 － The type semiconductor region 6a may be in contact with the p-type base region 2 or may be separated from the p-type base region 2.
The operation of the semiconductor device 100 will be described below.
In a state where a positive voltage is applied to the drain electrode 21 with respect to the source electrode 22, a voltage equal to or higher than a threshold value is applied to the gate electrode 10. Thus, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 22 through the channel to n － The type drift region 1 moves toward the drain electrode 21. Thereby, a current flows through the first region R1. If the voltage applied to the gate electrode 10 is lower than the threshold value, the channel of the p-type base region 2 is extinguished, and the semiconductor device 100 is turned off.
An example of the materials of each constituent element of the semiconductor device 100 will be described below.
n － Type drift region 1, p-type base region 2, n + Source regions 3, p + Semiconductor regions 4, p + Semiconductor region 5, p － Semiconductor regions 6, n + Drain regions 9a, p + Contact regions 9b and n + The type semiconductor region 9c contains a semiconductor material. Silicon carbide, silicon, gallium nitride, or gallium arsenide may be used as the semiconductor material. Arsenic, phosphorus, or antimony may be used as the n-type impurity. Boron may be used as the p-type impurity.
The gate electrode 10 includes a conductive material such as polysilicon. The gate electrode 10 may be doped with an n-type or p-type impurity. The gate insulating layer 11 and the insulating layer 15 contain an electrically insulating material. For example, the gate insulating layer 11 and the insulating layer 15 include silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and the source electrode 22 include a metal such as titanium, tungsten, or aluminum.
The advantages of the first embodiment will be described below.
In the semiconductor device 100, at n － P is arranged between the drift region 1 and the gate electrode 10 + A type semiconductor region 4. By setting p + The semiconductor region 4 can alleviate electric field concentration near the lower end of the gate insulating layer 11 when the semiconductor device 100 is turned off, and suppress damage to the gate insulating layer 11. On the other hand, in setting p + In the case of the semiconductor region 4, n － Type drift regions 1 and p + An electric field concentration will be generated between the type semiconductor regions 4. In order to improve the withstand voltage of the semiconductor device 100, it is preferable that p can be relaxed as well + The electric field is concentrated near the type semiconductor region 4.
In particular, in the semiconductor device 100 including silicon carbide in each semiconductor region, the dielectric breakdown field is higher than that of an insulating material such as silicon oxide. Thus, if p is not set + In the semiconductor region 4, when a high voltage is applied to the semiconductor device 100 at the time of turn-off, an excessive voltage is applied to the gate insulating layer 11, and there is a possibility that the gate insulating layer 11 may be damaged by insulation. Therefore, in the semiconductor device 100 using silicon carbide, it is more desirable to set p than the semiconductor device 100 using silicon + A type semiconductor region 4.
In the semiconductor device 100 according to the first embodiment, p is + A plurality of p-type semiconductor regions 4 are arranged around + A semiconductor region 5. By setting p in the second region R2 of the termination region + The semiconductor region 5 can expand the electric field distribution toward the outer periphery of the semiconductor device 100, and can alleviate p + The electric field is concentrated near the type semiconductor region 4. In addition, a plurality of p-type base regions 2 are formed around the p-type base region 2 by forming a plurality of p-type base regions on the second region R2 － The semiconductor region 6 can also alleviate the electric field concentration at the outer periphery of the p-type base region 2.
In particular, in the semiconductor device 100, p + P-type impurity concentration ratio p of the type semiconductor region 5 － The p-type impurity concentration of the type semiconductor region 6 is high. By increasing p + The p-type impurity concentration of the semiconductor region 5 is set to be p + The position of the shaped semiconductor region 4 can further expand the electric field distribution toward the outer periphery of the semiconductor device 100. As a result, the electric field concentration can be further relaxed, and the withstand voltage of the semiconductor device 100 can be further improved.
Furthermore, p + The type semiconductor region 5 is located inside the semiconductor layer instead of on the surface of the semiconductor layer and is not fully depleted when the semiconductor device 100 is turned off. Therefore, when the semiconductor device 100 is turned off, the voltage is p + An electric field concentration occurs in the vicinity of the type semiconductor region 5. In other words, after the semiconductor region (p － The electric field concentration occurs at the position of the interface between the shaped semiconductor region 6, the portion 1 b) and the insulating layer 15.
At the interface between the semiconductor region and the insulating layer 15, there is a trap level of carriers. If electric field concentration is generated near the interface, carriers accelerated by the electric field are trapped, and there is a possibility that the electric field distribution of the second region R2 is affected. By setting p + The semiconductor region 5 can suppress electric field concentration in the vicinity of the interface between the semiconductor region and the insulating layer 15. Can pass a plurality of p － The electric field distribution of the semiconductor region 6, which expands toward the outer periphery of the semiconductor device 100, is stable, and the fluctuation of the withstand voltage of the semiconductor device 100 can be suppressed.
(first modification)
Fig. 5 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the first embodiment.
The semiconductor device 110 of the first modification differs from the semiconductor device 100 in that the semiconductor device further includes a p-type semiconductor region 7. As shown in fig. 5, the p-type semiconductor region 7 is provided in the second region R2 around the gate electrode 10 on the X-Y plane. The p-type semiconductor region 7 is located at a specific p + The semiconductor region 5 is located above the p-type semiconductor region － The semiconductor region 6 is located below. p-type semiconductor region 7 and p + Semiconductor region 5 and p － The plurality of semiconductor regions 6 are similarly provided in the X direction and the Y direction. The p-type semiconductor regions 7 are separated from each other.
p-type impurity concentration ratio p of p-type semiconductor region 7 + The p-type impurity concentration of the type semiconductor region 5 is low, being lower than p － The p-type impurity concentration of the type semiconductor region 6 is high. The p-type impurity concentration of the p-type semiconductor region 7 may also be the same as the p-type impurity concentration of the p-type base region 2,or may be different. At least any one of the plurality of p-type semiconductor regions 7 may be connected to the p-type base region 2. Any one of the plurality of p-type semiconductor regions 7 may be connected to a plurality of p-type semiconductor regions + Any one or more p of the semiconductor regions 5 － The semiconductor regions 6 are connected to each other.
According to the first modification, by providing the plurality of p-type semiconductor regions 7, the depletion layer is more likely to expand along the Z direction on the outer periphery of the p-type base region 2. The electric field strength in the Z direction of the outer periphery of the p-type base region 2 can be further reduced as compared with the semiconductor device 100, and the withstand voltage of the semiconductor device 110 can be further improved.
Fig. 6 (a) and 6 (b) are plan views showing a part of a semiconductor device according to a first modification of the first embodiment.
Fig. 6 (a) and 6 (b) are plan views showing positions where the p-type semiconductor regions 7 are provided. As shown in fig. 6 (a), each of the plurality of p-type semiconductor regions 7 may be provided continuously around the plurality of gate electrodes 10. As shown in fig. 6 (b), the p-type semiconductor regions 7 may be arranged around the plurality of gate electrodes 10 in a plurality of circumferential directions. Furthermore, p + The same applies to the semiconductor region 5, a plurality of p + Each p of the semiconductor regions 5 + The semiconductor region may be continuously provided around the plurality of gate electrodes 10. Around a plurality of gate electrodes 10, p + The semiconductor regions 5 may be arranged in plurality in the circumferential direction.
In the case of the structure shown in fig. 6 (a), the electric field distribution in the second region R2 can be stabilized more than in the structure shown in fig. 6 (b), and the withstand voltage of the semiconductor device 110 can be stabilized more. In the case of the configuration shown in fig. 6 (b), by changing the density of the p-type semiconductor region 7 according to the electric field intensity of the second region R2, the length of the second region R2 in the radial direction can be shortened as compared with the configuration shown in fig. 6 (a). For example, near the corner of the p-type base region 2 when viewed from the Z direction shown in fig. 6 (b), the electric field intensity tends to be higher than that of other regions. By increasing the density of the p-type semiconductor region 7 in the vicinity of the corner to be higher than that of the p-type semiconductor region 7 in the other region, the withstand voltage of the semiconductor device 110 can be improved while suppressing an increase in the length of the second region R2.
(second embodiment)
Fig. 7 is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.
The semiconductor device 200 of the second embodiment shown in fig. 7 replaces p in the case of comparison with the semiconductor device 100 － Semiconductor region 6 containing p － The type semiconductor region 6b (another example of the sixth semiconductor region). P is p － The p-type semiconductor region 6b is provided around the p-type base region 2 along the X-Y plane, and contacts the p-type base region 2.P is p － The shaped semiconductor region 6b comprises a first portion 6b1 and a second portion 6b2. The p-type impurity concentration of the first portion 6b1 is higher than that of the second portion 6b2. The first portions 6b1 and the second portions 6b2 are alternately provided in the radial direction.
The p-type impurity concentration of each of the first portion 6b1 and the second portion 6b2 is lower than that of the p-type base region 2, and is lower than that of p + The p-type impurity concentration of the type semiconductor region 5 is low. In the illustrated example, the width of each first portion 6b1 is narrower in the radial direction so as to include p of the first portion 6b1 and the second portion 6b2 － The p-type impurity concentration per unit area of the type semiconductor region 6b decreases toward the outer periphery of the semiconductor device 200. "width" corresponds to the length in the radial direction.
If p is － The p-type impurity concentration per unit area of the type semiconductor region 6b decreases toward the outer periphery of the semiconductor device 200, and the width of the second portion 6b2 may also be narrowed toward the outer periphery of the semiconductor device 200.
In order to improve the withstand voltage of the semiconductor device 200, it is effective to suppress an increase in the local electric field strength of the second region R2. The flatter the gradient of the p-type impurity concentration in the radial direction in the region around the p-type base region 2, the more the local electric field concentration can be relaxed, and the more the electric field intensity at the position where the electric field is concentrated can be reduced. In the semiconductor device 200, the width of the first portion 6b1 having a relatively high p-type impurity concentration is directed more towardThe less the radial direction. Due to the reduced width of the first portion 6b1, p － The p-type impurity concentration per unit area of the type semiconductor region 6b becomes smaller as it goes toward the radial direction. By increasing the number of the first portions 6b1 and reducing the difference in width between adjacent first portions 6b1, the gradient of the p-type impurity concentration per unit area can be further smoothed. According to the second embodiment, the withstand voltage of the semiconductor device 200 can be improved while suppressing an increase in the electric field strength of the second region R2.
In addition, there is a method of varying the p-type impurity concentration of each first portion 6b1 in order to vary the p-type impurity concentration per unit area. However, in this method, the number of ion implantation steps of the first portions 6b1 having different p-type impurity concentrations is required. The plurality of first portions 6b1 having different widths from each other may be formed by one ion implantation using a mask. The width of each first portion 6b1 can be controlled by adjusting the opening width of the mask. Also, the plurality of second portions 6b2 may be formed by one ion implantation using a mask. By changing the width of each first portion 6b1 and adjusting the p-type impurity concentration per unit area, p with a gentle impurity concentration gradient can be formed more easily － A type semiconductor region 6b.
(first modification)
Fig. 8 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the second embodiment.
The semiconductor device 210 of the second modification shown in fig. 8 replaces a plurality of p in comparison with the semiconductor device 200 + Semiconductor region 5 containing p － The type semiconductor region 5b (another example of the fifth semiconductor region). P is p － The semiconductor region 5b is arranged along the X-Y plane at a plurality of p-type + Around the shaped semiconductor region 4. P is p － P-type impurity concentration ratio p of the type semiconductor region 5b + The p-type impurity concentration of the type semiconductor region 4 is low.
p － The type semiconductor region 5b includes a plurality of portions 5b1 and 5b2 having p-type impurity concentrations different from each other. The portion 5b2 is located around the portion 5b1 along the X-Y plane. Concentration of p-type impurity of portion 5b2The degree is lower than the p-type impurity concentration of the portion 5b 1. The thickness of the portion 5b2 is smaller than the thickness of the portion 5b 1. The "thickness" corresponds to the length in the Z direction. In the illustrated example, p － The type semiconductor region 5b includes two portions 5b1 and 5b2 having p-type impurity concentrations and thicknesses different from each other. P is p － The type semiconductor region 5b may include more portions having different p-type impurity concentrations and thicknesses.
Even when p is substituted + P is provided in the semiconductor region 5 － In the case of the semiconductor region 5b, p can be provided + The position of the semiconductor region 4 expands the electric field distribution toward the outer periphery of the semiconductor device 210, and can alleviate p + The electric field is concentrated near the type semiconductor region 4. This can improve the withstand voltage of the semiconductor device 210.
However, to further alleviate at p + Electric field concentration in the vicinity of the semiconductor region 4, and p － The semiconductor region 5b is preferably provided at p of the semiconductor device 100 or 110, compared with p of the semiconductor device 100 or 110 + A semiconductor region 5. Further, as described above, by providing p + The semiconductor region 5 can suppress electric field concentration in the vicinity of the interface between the semiconductor region and the insulating layer 15, and can stabilize the withstand voltage of the semiconductor device 100.
(third embodiment)
Fig. 9 is a cross-sectional view showing a part of the semiconductor device according to the third embodiment.
In the semiconductor device 300 according to the third embodiment shown in fig. 9, p is provided in the second region R2 － Semiconductor regions 5b, p － Semiconductor region 6c (another example of the sixth semiconductor region) and p + The type semiconductor region 7a (another example of the seventh semiconductor region).
P with semiconductor device 210 － Similarly, the semiconductor region 5b is p of the semiconductor device 300 － The semiconductor region 5b is located along the X-Y plane at p + A plurality of the semiconductor regions 4 are provided around. P is p + The type semiconductor region 7a is located around the gate electrode 10 on the X-Y plane. P is p + Semiconductor regionDomain 7a to p + The semiconductor region 5 is located at an upper position. P is p + The p-type impurity concentration of the p-type semiconductor region 7a is higher than that of the p-type base region 2, and is higher than that of the p-type base region 2 － The p-type impurity concentration of the type semiconductor region 5b is high. P is p + The semiconductor region 7a is provided in plurality in the X direction and the Y direction. Each p + The semiconductor regions 7a are separated from each other.
Multiple p + One or more of the semiconductor regions 7a may be connected to p － The type semiconductor region 5b or the p-type base region 2 meets. Multiple p + The semiconductor region 7a may be also connected to p － The type semiconductor region 5b and the p-type base region 2 are separated.
p － The p-type semiconductor region 6c is provided around the p-type base region 2 along the X-Y plane, and contacts the p-type base region 2.P is p － The semiconductor region 6c is larger than a plurality of p-type + The type semiconductor region 7a is located at an upper position. P is p － The semiconductor region 6c may be connected to a plurality of p-type semiconductor regions + More than one contact of the type semiconductor region 7a may be separated from the plurality of p-type semiconductor regions 7. P is p － The p-type impurity concentration of the p-type semiconductor region 6c is lower than that of the p-type base region 2 and lower than that of the p-type semiconductor region 7.
p － The type semiconductor region 6c includes a plurality of portions 6c1 and 6c2 having p-type impurity concentrations different from each other. The portion 6c2 is located around the portion 6c1 along the X-Y plane. The p-type impurity concentration of the portion 6c2 is lower than that of the portion 6c 1. The thickness of the portion 6c2 is smaller than the thickness of the portion 6c 1. In comparison with the illustrated example, p － The type semiconductor region 6c may include more portions having different p-type impurity concentrations and thicknesses.
In the semiconductor device 300, at p － Semiconductor regions 5b and p － A plurality of p-type semiconductor regions 6c are provided between + The p-type impurity concentration of the type semiconductor region 7a is higher than that of these semiconductor regions. By setting p + The type semiconductor region 7a, thereby the depletion layer can be more easily expanded in the Z direction in the second region R2. Can reduce the number of the first regions R2 in the Z directionThe electric field strength can further improve the withstand voltage of the semiconductor device 300.
(first modification)
Fig. 10 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the third embodiment.
The semiconductor device 310 of the first modification shown in fig. 10 replaces p in the case of comparison with the semiconductor device 300 － The semiconductor region 5b includes a plurality of p-type + A semiconductor region 5. P for semiconductor device 310 + Specific structure of semiconductor region 5 can be applied to p of semiconductor device 100, 110, or 200 + A specific configuration of the type semiconductor region 5.
p + The p-type impurity concentration of the type semiconductor region 7a may be equal to that of p + The p-type impurity concentration of the type semiconductor region 5 may be the same or different. Multiple p + More than one semiconductor region 7a may be used in combination with a plurality of p + More than one semiconductor region 5 may be connected to a plurality of p-type semiconductor regions + The semiconductor regions 5 are separated.
At substitution p － A plurality of p-type semiconductor regions 5b + In the case of the semiconductor region 5, as described above, concentration of an electric field in the vicinity of the interface between the semiconductor region and the insulating layer 15 can be suppressed, and the withstand voltage of the semiconductor device 310 can be further stabilized.
(second modification)
Fig. 11 is a cross-sectional view showing a part of a semiconductor device according to a second modification of the third embodiment.
The semiconductor device 320 of the second modification shown in fig. 11 replaces p in the case of comparison with the semiconductor device 300 － Semiconductor region 6c containing p + The type semiconductor region 6d (another example of the sixth semiconductor region).
p + The type semiconductor region 6d is located around the p-type base region 2 along the X-Y plane. P is p + The p-type impurity concentration of the type semiconductor region 6d is higher than that of the p-type base region 2.P is p + The p-type impurity concentration of the type semiconductor region 6d may be equal to p + The p-type impurity concentration of the type semiconductor region 7a may be the same or different. P is p + The plurality of semiconductor regions 6d are provided in the X direction and the Y direction. Each p + The semiconductor regions 6d are separated from each other, adjacent p + The interval between the shaped semiconductor regions 6d increases as the interval extends in the radial direction.
Multiple p + P in the semiconductor region 6d closest to the first region R1 + The type semiconductor region 6d may be in contact with the p-type base region 2 or may be separated from the p-type base region 2. Multiple p + One or more of the semiconductor regions 6d may be connected to a plurality of p + One or more of the semiconductor regions 7a may be connected to a plurality of p + The type semiconductor region 7a is separated.
p + The p-type impurity concentration of the p-type semiconductor region 6d is higher than that of the p-type base region 2, and is higher than that of the p-type base region 2 － The p-type impurity concentration of the type semiconductor region 5b is high. For example, p + The semiconductor region 6d is not completely depleted when the semiconductor device 320 is turned off. Therefore, at p when the semiconductor device 320 is turned off + An electric field concentration occurs near the bottom of the semiconductor region 6d, and avalanche breakdown is likely to occur. By easily generating avalanche breakdown at a specific position, it is possible to suppress the semiconductor device 320 from being damaged by avalanche breakdown generated at an undesired position.
(third modification)
Fig. 12 is a cross-sectional view showing a part of a semiconductor device according to a third modification of the third embodiment.
The semiconductor device 330 of the third modification shown in fig. 12 replaces p in the case of comparison with the semiconductor device 310 － Semiconductor region 6c containing p － A type semiconductor region 6b. P for semiconductor device 330 － Specific structure of the semiconductor region 6b can be applied to p of the semiconductor device 200 － A specific configuration of the type semiconductor region 6b.
(fourth modification)
Fig. 13 is a cross-sectional view showing a part of a semiconductor device according to a fourth modification of the third embodiment.
The semiconductor device 340 of the fourth modification shown in fig. 13 further includes p in comparison with the semiconductor device 300 － And a pillar region 8 (eighth semiconductor region). P is p － The pillar regions 8 are provided in n － In the type drift region 1, is located at a ratio p + Semiconductor region 4 and p － The mold semiconductor region 5b is located below. P is p － Pillar regions 8 and p + Semiconductor region 4 or p － The shaped semiconductor regions 5b meet. n is n － The type drift region 1 further comprises p and p in the X direction － N column regions 8 are juxtaposed － A post region 1c. n is n － Pillar regions 1c and p － The column regions 8 are alternately arranged in the X direction. Each n － Column regions 1c and p － The column regions 8 extend along the gate electrode 10 in the Y direction.
Through n － Pillar regions 1c and p － The pillar regions 8 are alternately arranged in the X direction, and can be formed from n when the semiconductor device 340 is turned off － Column regions 1c and p － The pn junction of the pillar region 8 expands the depletion layer in the X direction. This can improve the withstand voltage of the semiconductor device 340.
Here, it is described that a plurality of p are further provided in the structure of the semiconductor device 300 － Examples of the post region 8. The present application is not limited to this example, and a plurality of p may be further provided in any one of the semiconductor devices 100, 110, 200, 210, or 310 to 330 － And a post region 8. In any semiconductor device, by providing a plurality of p － The column region 8 can improve the withstand voltage.
While the present application has been described with reference to several embodiments, these embodiments are presented by way of example and are not intended to limit the scope of the application. These novel embodiments can be implemented in various other modes, and various omissions, substitutions, modifications, and the like can be made without departing from the scope of the application. These embodiments and modifications thereof are included in the scope and gist of the application, and are included in the application described in the claims and their equivalents. The above embodiments can be combined with each other.

Claims (9)

1. A semiconductor device is characterized by comprising:
a first electrode;
a first semiconductor region of a first conductivity type provided over the first electrode, including a first region and a second region provided around the first region;
a second semiconductor region of a second conductivity type disposed over the first region;
a third semiconductor region of the first conductivity type provided over a portion of the second semiconductor region;
a gate electrode facing the second semiconductor region with a gate insulating layer therebetween in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region;
a fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode;
a plurality of fifth semiconductor regions of a second conductivity type provided in the second region, located around the fourth semiconductor region along a first surface perpendicular to the first direction, and separated from each other in a second direction, the second direction being a direction from the first region toward the second region;
a plurality of sixth semiconductor regions of a second conductivity type provided on the second region, located around the second semiconductor region along the first surface, separated from each other in the second direction, and having a lower impurity concentration of the second conductivity type than each of the plurality of fifth semiconductor regions; and
and a second electrode disposed over the second semiconductor region and the third semiconductor region.
2. The semiconductor device according to claim 1, wherein,
the impurity concentration of the second conductivity type of each of the plurality of sixth semiconductor regions is lower than the impurity concentration of the second conductivity type of the second semiconductor region.
3. The semiconductor device according to claim 1, wherein,
a plurality of seventh semiconductor regions of the second conductivity type are provided along the first surface at the periphery of the gate electrode,
the plurality of seventh semiconductor regions are located above the plurality of fifth semiconductor regions and below the plurality of sixth semiconductor regions.
4. The semiconductor device according to claim 3, wherein,
the impurity concentration of the second conductivity type of each of the plurality of seventh semiconductor regions is lower than the impurity concentration of the second conductivity type of each of the plurality of fifth semiconductor regions and higher than the impurity concentration of the second conductivity type of each of the plurality of sixth semiconductor regions.
5. A semiconductor device is characterized by comprising:
a first electrode;
a first semiconductor region of a first conductivity type provided over the first electrode, including a first region and a second region provided around the first region;
a second semiconductor region of a second conductivity type disposed over the first region;
a third semiconductor region of the first conductivity type provided over a portion of the second semiconductor region;
a gate electrode facing the second semiconductor region with a gate insulating layer therebetween in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region;
a fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode;
a fifth semiconductor region of a second conductivity type provided in the second region and located around the fourth semiconductor region along a first surface perpendicular to the first direction;
a sixth semiconductor region of a second conductivity type provided over the second region, the sixth semiconductor region being located around the second semiconductor region along the first surface, the sixth semiconductor region including first portions and second portions alternately provided in a second direction from the first region toward the second region, an impurity concentration of the second conductivity type of the first portion being lower than an impurity concentration of the second conductivity type of the second portion, and lengths of the first portions being reduced toward the second direction; and
and a second electrode disposed over the second semiconductor region and the third semiconductor region.
6. The semiconductor device according to claim 5, wherein,
a plurality of seventh semiconductor regions of the second conductivity type located around the gate electrode along the first surface;
the plurality of seventh semiconductor regions are separated from each other in the second direction,
the plurality of seventh semiconductor regions are located above the fifth semiconductor region and below the sixth semiconductor region.
7. The semiconductor device according to claim 5, wherein,
the impurity concentration of the second conductivity type of each of the plurality of seventh semiconductor regions is higher than the impurity concentration of the second conductivity type of the first portion and higher than the impurity concentration of the second conductivity type of the second portion.
8. A semiconductor device is characterized by comprising:
a first electrode;
a first semiconductor region of a first conductivity type provided over the first electrode, including a first region and a second region provided around the first region;
a second semiconductor region of a second conductivity type disposed over the first region;
a third semiconductor region of the first conductivity type provided over a portion of the second semiconductor region;
a gate electrode facing the second semiconductor region with a gate insulating layer therebetween in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region;
a fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode;
a fifth semiconductor region of a second conductivity type provided in the second region and located around the fourth semiconductor region along a first surface perpendicular to the first direction;
a sixth semiconductor region of a second conductivity type provided over the second region, around the second semiconductor region along the first surface;
a plurality of seventh semiconductor regions of a second conductivity type located around the gate electrode along the first surface, separated from each other in a second direction from the first region toward the second region, located above the fifth semiconductor region, and located below the sixth semiconductor region; and
and a second electrode disposed over the second semiconductor region and the third semiconductor region.
9. The semiconductor device according to any one of claims 1 to 8, wherein,
the semiconductor device further includes a plurality of eighth semiconductor regions of the second conductivity type provided in the first semiconductor region and separated from each other in the vertical direction.
CN202210735355.XA 2022-03-23 2022-06-27 Semiconductor device with a semiconductor device having a plurality of semiconductor chips Pending CN116845103A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022046944A JP2023140891A (en) 2022-03-23 2022-03-23 Semiconductor device
JP2022-046944 2022-03-23

Publications (1)

Publication Number Publication Date
CN116845103A true CN116845103A (en) 2023-10-03

Family

ID=88096519

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210735355.XA Pending CN116845103A (en) 2022-03-23 2022-06-27 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Country Status (3)

Country Link
US (1) US20230307535A1 (en)
JP (1) JP2023140891A (en)
CN (1) CN116845103A (en)

Also Published As

Publication number Publication date
JP2023140891A (en) 2023-10-05
US20230307535A1 (en) 2023-09-28

Similar Documents

Publication Publication Date Title
US10763359B2 (en) Semiconductor device
US7074681B2 (en) Semiconductor component and method of manufacturing
US11495679B2 (en) Semiconductor device and method for manufacturing the same
US20220093728A1 (en) Semiconductor device
KR101297440B1 (en) Pn junction and mos capacitor hybrid resurf transistor
KR100674987B1 (en) Method of operating transistor formed in bulk wafer substrate
US8482060B2 (en) Semiconductor device
US11430885B2 (en) Semiconductor device
CN116845103A (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
CN116711080A (en) Semiconductor power device having multiple gate trenches and method of forming the same
US20220285488A1 (en) Superjunction semiconductor device having floating region and method of manufacturing same
JP7013606B1 (en) Semiconductor devices and methods for manufacturing semiconductor devices
JP7381425B2 (en) Semiconductor device and its manufacturing method
KR100694327B1 (en) Semiconductor device
US20230290820A1 (en) Semiconductor device and method for manufacturing the same
US20230070381A1 (en) Vertical field-effect transistor and method for forming same
EP4160693A1 (en) Transistor device a method for producing a transistor device
US20230299178A1 (en) Semiconductor device and method for manufacturing
US20240096962A1 (en) Semiconductor device and method for the same
CN116457945A (en) Vertical semiconductor component and method for producing the same
KR100277680B1 (en) Improved LGI Power Devices
JP2023039219A (en) Semiconductor device
KR20010034433A (en) Mos field effect transistor with an auxiliary electrode
JP2023140026A (en) Semiconductor device
JP2023170953A (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination