CN116844973A - Manufacturing method of chip packaging structure and chip packaging structure - Google Patents
Manufacturing method of chip packaging structure and chip packaging structure Download PDFInfo
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- CN116844973A CN116844973A CN202310815390.7A CN202310815390A CN116844973A CN 116844973 A CN116844973 A CN 116844973A CN 202310815390 A CN202310815390 A CN 202310815390A CN 116844973 A CN116844973 A CN 116844973A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 title abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 163
- 239000010410 layer Substances 0.000 claims abstract description 142
- 239000011241 protective layer Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000001746 injection moulding Methods 0.000 claims abstract description 23
- 238000007789 sealing Methods 0.000 claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims description 24
- 239000012790 adhesive layer Substances 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 20
- 239000012778 molding material Substances 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 230000032798 delamination Effects 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The embodiment of the application provides a chip packaging structure manufacturing method and a chip packaging structure, and relates to the technical field of packaging, wherein the method comprises the following steps: providing at least one substrate, wherein the substrate comprises a first wiring layer, and a first protective layer and a second protective layer which are respectively positioned at two opposite sides of the first wiring layer; attaching at least one side of the substrate provided with the first protection layer to a carrier plate; arranging a chip on one side of the substrate far away from the carrier plate, and enabling pins of the chip to be electrically connected with the first wiring layer through the first ball mounting holes; a plastic sealing layer which wraps the chip and the substrate is arranged on the carrier plate; and cutting at least part of the substrate on the edge of the substrate and the plastic sealing layer corresponding to the original position of the substrate to separate the packaged chips from each other. Therefore, layering phenomenon is not easy to occur between the injection molding layer and the substrate, and the quality of the chip packaging structure can be improved.
Description
Technical Field
The application relates to the technical field of packaging, in particular to a chip packaging structure manufacturing method and a chip packaging structure.
Background
The technological process of semiconductor manufacturing comprises wafer manufacturing, wafer testing, chip packaging, testing, later finished product warehousing and the like, and the chip packaging structure is needed for chip packaging, so that the chip packaging structure can protect the chip.
However, in some chip packaging structures, there is a risk of delamination between the plastic layer and the substrate, which affects the packaging quality.
Disclosure of Invention
In order to overcome the technical problems mentioned in the background of the technology, the embodiment of the application provides a chip packaging structure manufacturing method and a chip packaging structure.
In a first aspect of the present application, a method for manufacturing a chip package structure is provided, the method comprising:
providing at least one substrate, wherein the substrate comprises a first wiring layer, a first protective layer and a second protective layer which are respectively positioned at two opposite sides of the first wiring layer, and the second protective layer is provided with a first ball mounting hole exposing the first wiring layer;
attaching at least one side of the substrate provided with the first protection layer to a carrier plate;
arranging a chip on one side of the substrate far away from the carrier plate, and enabling pins of the chip to be electrically connected with the first wiring layer through the first ball mounting holes;
a plastic sealing layer which wraps the chip and the substrate is arranged on the carrier plate;
and cutting at least part of the substrate along the direction perpendicular to the substrate, so that the packaged chips are separated from each other.
In one possible implementation manner, before the step of cutting at least part of the substrate along the direction perpendicular to the substrate, the edge of the substrate and the plastic sealing layer corresponding to the original position of the substrate, so as to separate the packaged chips from each other, the method further includes:
removing the carrier plate to expose the first protection layer;
a second ball planting hole is formed in the first protective layer;
and a first solder ball is arranged on one side, far away from the first wiring layer, of the first protective layer, and the first solder ball is in electrical contact with the first wiring layer through the second ball implantation hole.
In one possible implementation, before the step of providing at least one substrate, the method further comprises:
providing a conductive plate; the conductive plate comprises a first wiring layer, a first protective layer and a second protective layer, wherein the first protective layer and the second protective layer are respectively positioned on two opposite sides of the first wiring layer;
the conductive plate is cut into a plurality of the substrates.
In one possible implementation, after the step of disposing a plastic layer on the carrier plate, the method further includes:
and grinding one side of the plastic sealing layer, which is far away from the carrier plate, so as to expose one side of the chip, which is far away from the carrier plate.
In one possible implementation manner, after the step of attaching the side of at least one of the substrates provided with the first protective layer to a carrier, the method further includes:
and setting filling glue at the gap between the substrate and the chip so that the filling glue fills the gap between the substrate and the chip.
In one possible implementation manner, the step of attaching the side, on which the first protective layer is disposed, of at least one substrate to a carrier plate includes:
providing a carrier plate;
an adhesive layer is arranged on one side of the carrier plate;
and attaching at least one side of the substrate provided with the first protective layer to the adhesive layer.
In one possible implementation manner, the step of disposing an adhesive layer on one side of the carrier board includes:
selecting an adhesive material based on the material of the carrier plate;
and arranging the bonding material on one side of the carrier plate and forming a bonding layer.
In one possible implementation manner, before the step of disposing the chip on a side of the substrate away from the carrier plate, and electrically connecting pins of the chip with the first wiring layer through the first ball-mounting hole, the method further includes:
manufacturing a second wiring layer on one side of the pins of the chip, and leading out the pins of the chip to be electrically connected with the second wiring layer;
arranging a second tin ball on one side of the second wiring layer far away from the chip so as to electrically connect a pin of the chip with the second tin ball;
the step of arranging the chip on the side of the substrate away from the carrier plate, and electrically connecting pins of the chip with the first wiring layer through the first ball-implanting holes comprises the following steps:
and arranging the chip on one side of the substrate far away from the carrier plate, and enabling the second tin balls to be electrically connected with the first wiring layer through the first ball implantation holes.
In one possible implementation manner, the step of disposing a plastic layer on the carrier plate, where the plastic layer wraps the chip and the substrate, includes:
providing an injection mold, wherein the injection mold comprises an upper mold and a lower mold, and the lower mold comprises an injection groove;
adding injection molding materials into the injection molding grooves, and heating and melting the injection molding materials;
mounting one side of the carrier plate far away from the chip on the upper die, and clamping the upper die and the lower die so as to immerse the chip and the substrate in molten injection molding material;
and removing the injection mold to form a plastic sealing layer which wraps the chip and the substrate on the carrier plate.
In a second aspect, the application further provides a chip packaging structure, which is manufactured by the manufacturing method of the chip packaging structure.
Compared with the prior art, the application has at least the following beneficial effects:
according to the chip packaging structure manufacturing method and the chip packaging structure provided by the embodiment of the application, the size of the provided substrate is designed to be larger than that of the substrate in the final chip packaging structure, and after the chip is subjected to plastic packaging, the size of the substrate of the reserved part and the corresponding plastic packaging layer are cut off. Therefore, the side surface of the substrate and the plastic sealing layer are not contacted any more, and the cutting edge formed when the conductive plate is cut into the substrate can not cause layering risk between the substrate and the plastic sealing layer, so that the quality of the chip packaging structure can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates a schematic cross-sectional view of a prior art conductive plate of the present application;
FIG. 2 illustrates a schematic cross-sectional view of a prior art substrate of the present application;
FIG. 3 illustrates a partial cross-sectional view of a prior art substrate having its lower end flush with the lower end of the molding layer;
fig. 4 illustrates a flow chart of a method for manufacturing a chip package structure according to the present application;
FIG. 5 illustrates a schematic cross-sectional view of a substrate provided by the present application;
FIG. 6 illustrates a schematic cross-sectional view of the present application with a substrate disposed on a carrier plate;
FIG. 7 illustrates a schematic cross-sectional view of the present application with a chip disposed on a substrate;
FIG. 8 illustrates a schematic cross-sectional view of the present application with a plastic layer on a carrier plate that encapsulates a substrate and a chip;
FIG. 9 illustrates a schematic cross-sectional view of a chip package structure after cutting away portions of the substrate and the molding layer in accordance with the present application;
FIG. 10 illustrates a flow chart of a method further included prior to step 14 of the present application;
FIG. 11 illustrates a schematic cross-sectional view of the application with the carrier plate removed;
FIG. 12 is a schematic cross-sectional view illustrating the present application in which a second ball-mounting hole is formed in the first protective layer;
FIG. 13 illustrates a schematic cross-sectional view of the present application with a first solder ball disposed in a second ball placement hole;
FIG. 14 is a schematic cross-sectional view of the application after the plastic layer on the side of the chip away from the carrier has been polished away;
FIG. 15 illustrates a flow chart of a method of the present application further included prior to step 12;
FIG. 16 illustrates a schematic cross-sectional view of the present application with a second wiring layer and a second solder ball disposed on one side of the chip;
FIG. 17 illustrates a schematic cross-sectional view of the present application with a filler layer disposed between the chip and the substrate;
FIG. 18 illustrates a schematic cross-sectional view of the present application with an adhesive layer disposed on one side of the carrier plate;
FIG. 19 illustrates a schematic cross-sectional view of a chip package structure of the present application having an adhesive layer disposed on one side of a carrier plate;
fig. 20 illustrates a flowchart of a specific implementation method of step S15 of the present application;
FIG. 21 illustrates a schematic cross-sectional view of an injection mold of the present application;
FIG. 22 illustrates a schematic cross-sectional view of the present application after injection molding material is introduced into the injection groove of the lower mold;
FIG. 23 illustrates a schematic cross-sectional view of the present application after the upper die has moved the substrate and die into engagement with the lower die.
Reference numerals: 1. a conductive plate; 2. a second protective layer; 3. a first wiring layer; 4. a first protective layer; 5. the first ball planting hole; 6. a second ball-planting hole; 7. a substrate; 8. a plastic sealing layer; 9. a carrier plate; 10. a chip; 101. pins; 11. a first solder ball; 12. a second solder ball; 13. a second wiring layer; 14. filling a glue layer; 15. an adhesive layer; 16. a lower die; 161. injection molding the groove; 17. an upper die; 18. and (5) injection molding materials.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put in use of the product of the application, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application.
It should be noted that, in the case of no conflict, different features in the embodiments of the present application may be combined with each other.
In some chip package fabrication processes, a substrate is required, and the substrate is obtained by cutting a conductive plate. Referring to fig. 1, the conductive plate 1 includes a first wiring layer 3, a first protection layer 4 and a second protection layer 2 respectively located on opposite sides of the first wiring layer 3, a plurality of first ball mounting holes 5 are formed in the second protection layer 2, and then the conductive plate 1 is cut into a plurality of substrates 7 as shown in fig. 2. However, when the conductive plate 1 is cut into the substrate 7 as shown in fig. 2, cutting chipping is likely to occur on the side surface of the substrate 7. Referring to fig. 3, after the substrate 7 shown in fig. 2 is molded, the first protective layer 4 of the substrate 7 is flush with the lower end of the molding layer 8, and under the influence of the cutting edge breakage of the substrate 7, a delamination risk is easily generated between the substrate 7 and the molding layer 8, thereby affecting the quality of the chip packaging structure.
In order to solve the above technical problems. The inventor has innovatively devised the following technical solutions, and a detailed description of specific embodiments of the present application will be given below with reference to the accompanying drawings.
Referring to fig. 4, in one aspect, the present application provides a method for manufacturing a chip package structure, where the method includes:
s10: at least one substrate 7 is provided, the substrate 7 comprises a first wiring layer 3, and a first protection layer 4 and a second protection layer 2 which are respectively positioned on two opposite sides of the first wiring layer 3, and the second protection layer 2 is provided with a first ball mounting hole 5 exposing the first wiring layer 3.
In the present embodiment, referring to fig. 5, the substrate 7 includes a first wiring layer 3 for conducting electricity, and the first protective layer 4 and the second protective layer 2 protecting the first wiring layer 3, the first protective layer 4 and the second protective layer 2 can make the first wiring layer 3 not electrically conducted with unnecessary devices, and damage to the first wiring layer 3 at the time of soldering can be prevented.
S11: at least one side of the substrate 7 provided with the first protective layer 4 is attached to a carrier 9.
In this embodiment, referring to fig. 6, the carrier supports and fixes the substrate 7, the carrier plate 9 may be made of metal or glass, the thickness of the carrier plate 9 may be matched according to the substrate 7, and in general, the thickness of the carrier plate 9 is 1 mm-3 mm.
At least one of the substrate 7 which is processed in advance can be arranged on one side provided with the first protection layer 4 to be attached to a carrier plate 9, and the carrier plate 9 is fixedly connected with the carrier plate, the first protection layer 4 of the substrate 7 is tightly attached to the carrier plate 9, and the carrier plate 9 plays a role in protecting the first protection layer 4 of the substrate 7.
S12: the chip 10 is disposed on a side of the substrate 7 away from the carrier 9, so that the pins 101 of the chip 10 are electrically connected to the first wiring layer 3 through the first ball mounting holes 5.
In this embodiment, referring to fig. 7, the chip 10 is an unpackaged chip, the chip 10 is disposed on a side of the substrate 7 away from the carrier 9, and the leads 101 of the chip 10 are electrically connected to the first wiring layer 3 through the first ball mounting holes 5.
It is also required that the front projection of the chip 10 on the carrier 9 is located in the front projection of the substrate 7 on the carrier 9, i.e. a stepped structure with the chip 10 retracted can be formed between the carrier 9 and the chip 10 as shown in fig. 7, which is more beneficial for packaging the chip 10.
S13: a plastic layer 8 is provided on the carrier 9 to encapsulate the chip 10 and the substrate 7.
In this embodiment, referring to fig. 8, a plastic layer 8 that encapsulates both the chip 10 and the substrate 7 may be disposed on the carrier 9 by using an associated injection mold, where the plastic layer 8 extends to a step structure formed between the substrate 7 and the carrier 9, and fills the step structure. In this way, the chip 10 can be packaged more stably by the plastic layer 8.
S14: and cutting at least part of the substrate 7 along the direction perpendicular to the substrate 7, so as to separate the packaged chips 10 from each other, wherein the edge of the substrate 7 and the plastic layer 8 corresponding to the original position of the substrate 7 are cut.
In the case that the substrate 7 does not need to be wrapped by the plastic layer 8, the size of the substrate 7 provided may be larger than the size of the substrate 7 in the final chip package structure, for example, the length and width of the substrate 7 required finally are 40mm, and the length and width of the substrate 7 designed may be 40.1mm, that is, 0.1mm is reserved for more than the length and width of the substrate 7.
After the chip packaging structure shown in fig. 8 is formed, the reserved edge portion of the substrate 7 is cut along the direction perpendicular to the substrate 7, for example, the reserved edge portion of the substrate 7 is cut in a size of 0.1mm in length and width, so that the packaged chips 10 are separated from each other, and the chip packaging structure shown in fig. 9 is formed.
The plastic layer 8 contacting the edge of the substrate 7 may be cut together while the reserved edge of the substrate 7 is cut. Therefore, the side surface of the substrate 7 and the plastic sealing layer 8 are not contacted any more, so that the cutting edge formed when the conductive plate 1 is cut into the substrate 7 can not cause delamination risk between the substrate 7 and the plastic sealing layer 8, thereby improving the quality of the chip packaging structure.
Based on the above design, the size of the substrate 7 provided in this embodiment is designed to be larger than the size of the substrate 7 in the final chip package structure, and after the 10-chip is molded, the size of the substrate 7 of the reserved portion and the corresponding molding layer 8 are cut off. Therefore, the side surface of the substrate 7 and the plastic sealing layer 8 are not contacted any more, so that the cutting edge formed when the conductive plate 1 is cut into the substrate 7 can not cause delamination risk between the substrate 7 and the plastic sealing layer 8, thereby improving the quality of the chip packaging structure.
Referring to fig. 1 again, in the related art, a plurality of second ball mounting holes 6 are further formed in the first protective layer 4, and then the conductive plate 1 is cut into a plurality of substrates 7 as shown in fig. 2. However, the second ball-implanting hole 6 is formed in the first protective layer 4 in advance, and in the manufacturing process of the chip packaging structure in the later stage, the second ball-implanting hole 6 is easily polluted, so that the quality of implanting solder balls into the second ball-implanting hole 6 is affected, and finally the packaging quality of the chip 10 is affected.
In order to solve the above problem of affecting the quality of the solder ball implantation, in one possible implementation, please refer to fig. 10, before step S14, the method further includes:
s20: the carrier 9 is removed to expose the first protective layer 4.
In this embodiment, referring to fig. 11, the carrier 9 is removed, and the first protection layer 4 is exposed. In this way, a structure in which the substrate 7 and the chip 10 are wrapped by the plastic layer 8 can be formed.
S21: and a second ball-planting hole 6 is formed in the first protective layer 4.
In this embodiment, referring to fig. 12, a plurality of second ball-planting holes 6 may be formed in the first protection layer 4 by laser, and the depth of the second ball-planting holes 6 is equal to the thickness of the first protection layer 4, so as to expose the first wiring layer 3.
S22: a first solder ball 11 is disposed on a side of the first protection layer 4 away from the first wiring layer 3, and the first solder ball 11 is electrically contacted with the first wiring layer 3 through the second ball-implanting hole 6.
In this embodiment, referring to fig. 13, a first solder ball 11 is disposed on a side of the first protection layer 4 away from the first wiring layer 3, so that a portion of the first solder ball 11 is located in the second ball mounting hole 6, so that the first solder ball 11 is electrically connected with the first wiring layer 3, and finally, the lead 101 of the chip 10 is electrically connected with the first solder ball 11 through the first wiring layer 3, and the chip package structure can be soldered on a circuit board through the first solder ball 11.
Compared with the prior art, the method for manufacturing the chip package structure provided by the embodiment of the application has the advantages that the plastic layer 8 wrapping the chip 10 and the substrate 7 is arranged on the carrier 9, and the carrier 9 is removed to expose the first protection layer 4, and then the second ball-planting hole 6 is arranged on the first protection layer 4. In this way, the first ball-implanting hole 5 is not easy to be polluted in the packaging process, so that the quality of the first solder ball 11 implanted into the second ball-implanting hole 6 is higher, and the packaging quality of the chip 10 can be improved.
In a possible implementation, before the step of providing at least one substrate 7, the method further comprises: providing a conductive plate 1; the conductive plate 1 comprises a first wiring layer 3, a first protective layer 4 and a second protective layer 2 which are respectively positioned on two opposite sides of the first wiring layer 3; the conductive plate 1 is cut into a plurality of the substrates 7.
The substrate 7 is cut from the conductive plate 1, and the size of the substrate 7 may be determined according to the size of the chip 10. Specifically, cutting lines may be provided on the conductive plate 1 according to the size of the chip 10, and the substrate 7 may be cut into a plurality of substrates 7 along the cutting lines.
In a possible implementation, after the step of disposing a plastic layer 8 on the carrier 9, which encapsulates the chip 10 and the substrate 7, the method further includes: the side of the plastic layer 8 remote from the carrier plate 9 is ground to expose the side of the chip 10 remote from the carrier plate 9.
The plastic sealing layer 8 in fig. 8 may be ground away from the carrier plate 9 by using a grinding device, so as to form a structure in which the chip 10 is exposed away from the carrier plate 9 as shown in fig. 14. In this way, the chip 10 can dissipate heat through the exposed side, so that the service life of the chip 10 can be improved.
In one possible implementation, referring to fig. 15, before step S12, the method further includes:
s30: a second wiring layer 13 is formed on the side of the chip 10 where the leads 101 are located, and the leads 101 of the chip 10 are led out to be electrically connected to the second wiring layer 13.
In this embodiment, the second wiring layer 13 has conductivity, referring to fig. 16, the second wiring layer 13 is fabricated on the side where the leads 101 of the chip 10 are located, and the leads 101 of the chip 10 are electrically connected to the second wiring layer 13.
S31: a second solder ball 12 is disposed on a side of the second wiring layer 13 away from the chip 10, so that the lead 101 of the chip 10 is electrically connected to the second solder ball 12.
In this embodiment, a second solder ball 12 is disposed on a side of the second wiring layer 13 away from the chip 10, and a portion of the second solder ball 12 is located in the first ball mounting hole 5, so that the second solder ball 12 is electrically connected to both the first wiring layer 3 and the leads 101 of the chip 10. In this way, the chip 10 is disposed on the side of the substrate 7 away from the carrier 9, so that the second solder balls 12 are electrically connected to the first wiring layer 3 through the first ball mounting holes 5, and finally, it is more convenient to electrically connect the pins 101 of the chip 10 to the first wiring layer 3.
In a possible implementation, after the step of attaching the side of at least one substrate 7 provided with the first protective layer 4 to a carrier 9, the method further comprises: and a filling glue is arranged at the gap between the substrate 7 and the chip 10, so that the filling glue fills the gap between the substrate 7 and the chip 10.
Referring to fig. 17, after the chip 10 is fixed on the substrate 7, a gap is formed between the chip 10 and the substrate 7, and a filling glue is disposed at the gap between the chip 10 and the substrate 7, wherein the filling glue has fluidity, and the filling glue can fill the gap between the chip 10 and the substrate 7 to form a filling glue layer 14. The filling glue layer 14 can enable the chip 10 to be firmly fixed on the substrate 7, and plays a role in protecting the chip 10.
In a possible implementation manner, the step of attaching the side of at least one substrate 7 provided with the first protective layer 4 to a carrier 9 includes: providing a carrier plate 9; an adhesive layer 15 is arranged on one side of the carrier plate 9; at least one side of the substrate 7 on which the first protective layer 4 is provided is bonded to the adhesive layer 15. By providing the adhesive layer 15 on one side of the carrier plate 9, the substrate 7 can be more easily fixed to the carrier plate 9.
In a possible implementation manner, the step of disposing the adhesive layer 15 on one side of the carrier plate 9 includes: based on the material of the carrier plate 9, an adhesive material is selected. The adhesive material is provided on one side of the carrier plate 9 and an adhesive layer 15 is formed.
Referring to fig. 18, when the material of the carrier plate 9 is glass, the material of the adhesive layer 15 is a photolytic or pyrolytic material, and when the material of the carrier plate 9 is steel, the material of the adhesive layer 15 is a pyrolytic material. By providing the adhesive layer 15 on one side of the carrier plate 9, the substrate 7 can be more easily fixed to the carrier plate 9.
Referring to fig. 19, when the carrier 9 needs to be removed, a removal manner may be selected according to a material property of the adhesive layer 15, for example, when the material of the adhesive layer 15 is a photolytic material, the adhesive layer 15 is irradiated with a laser to detach the adhesive layer 15 from the substrate 7, and when the material of the adhesive layer 15 is a pyrolysis material, the adhesive layer 15 is detached from the substrate 7 by heating. In this way, it is more convenient to detach the carrier 9 from the substrate 7.
In one possible implementation, referring to fig. 20, step S13 includes:
s131: an injection mold is provided, the injection mold comprising an upper mold 17 and a lower mold 16, the lower mold 16 comprising an injection groove 161.
In this embodiment, referring to fig. 21, the injection mold includes an upper mold 17 and a lower mold 16, the lower mold 16 is provided with an injection groove 161, and the depth and width of the injection groove 161 may be determined according to the dimensions of the chip 10 and the substrate 7, so that the substrate 7 and the chip 10 as a whole may be required to be placed in the injection groove 161.
S132: injection molding material 18 is added into the injection molding groove 161, and the injection molding material 18 is melted by heating.
In this embodiment, referring to fig. 22, a liquid or powder injection molding material 18 is added into the injection molding groove 161, and the injection molding material 18 is heated until the injection molding material 18 is melted.
S133: the side of the carrier plate 9 remote from the chip 10 is mounted on the upper die 17 and the upper die 17 is clamped with the lower die 16 so that the chip 10 and the substrate 7 are immersed in the melted injection molding material 18.
In this embodiment, referring to fig. 23, the carrier 9 is fixed to one side of the upper mold 17 in a conventional manner, and then the upper mold 17 and the lower mold 16 are clamped so that the chip 10 and the substrate 7 are completely immersed in the melted injection molding material 18.
S134: the injection mould is removed to form a plastic layer 8 on the carrier plate 9, which encapsulates the chip 10 and the substrate 7.
In this embodiment, the injection mold is removed, and finally a plastic layer 8 is formed on the carrier 9 to encapsulate the chip 10 and the substrate 7 as shown in fig. 8.
In this way, since the melted injection molding material 18 has fluidity, the melted injection molding material 18 can fill the steps formed by the chip 10 and the substrate 7, etc., and finally the plastic layer 8 can better encapsulate the chip 10 and the substrate 7, thereby being more beneficial to improving the quality of the finally fabricated chip package structure.
In a possible implementation manner, the step of forming cutting grooves on the first protective layer 4 and the second protective layer 2 includes: cutting grooves are formed in the first protective layer 4 and the second protective layer 2 by using an exposure machine. The cutting grooves can be formed on the first protective layer 4 and the second protective layer 2 more efficiently and more accurately by the exposure machine.
In summary, the size of the substrate 7 provided by the application is designed to be larger than the size of the substrate 7 in the final chip packaging structure, and after the chip is packaged, the size of the substrate 7 of the reserved part and the corresponding plastic layer 8 are cut off. Therefore, the side surface of the substrate 7 and the plastic sealing layer 8 are not contacted any more, so that the cutting edge formed when the conductive plate 1 is cut into the substrate 7 can not cause delamination risk between the substrate 7 and the plastic sealing layer 8, thereby improving the quality of the chip packaging structure.
In a second aspect, the application further provides a chip packaging structure, which is manufactured by the manufacturing method of the chip packaging structure. The chip packaging structure has higher tin ball implantation quality, and the layering risk is not easy to generate between the plastic sealing layer 8 and the substrate 7, so that the chip packaging structure manufactured by the manufacturing method of the chip packaging structure has higher quality.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method for manufacturing a chip package structure, the method comprising:
providing at least one substrate, wherein the substrate comprises a first wiring layer, a first protective layer and a second protective layer which are respectively positioned at two opposite sides of the first wiring layer, and the second protective layer is provided with a first ball mounting hole exposing the first wiring layer;
attaching at least one side of the substrate provided with the first protection layer to a carrier plate;
arranging a chip on one side of the substrate far away from the carrier plate, and enabling pins of the chip to be electrically connected with the first wiring layer through the first ball mounting holes;
a plastic sealing layer which wraps the chip and the substrate is arranged on the carrier plate;
and cutting at least part of the substrate along the direction perpendicular to the substrate, so that the packaged chips are separated from each other.
2. The method of manufacturing a chip package structure according to claim 1, wherein, before the step of separating each packaged chip from each other by cutting at least a part of the substrate along the direction perpendicular to the substrate and the edge of the substrate and the molding layer corresponding to the original position of the substrate, the method further comprises:
removing the carrier plate to expose the first protection layer;
a second ball planting hole is formed in the first protective layer;
and a first solder ball is arranged on one side, far away from the first wiring layer, of the first protective layer, and the first solder ball is in electrical contact with the first wiring layer through the second ball implantation hole.
3. The method of manufacturing a chip package structure of claim 1, wherein prior to the step of providing at least one substrate, the method further comprises:
providing a conductive plate; the conductive plate comprises a first wiring layer, a first protective layer and a second protective layer, wherein the first protective layer and the second protective layer are respectively positioned on two opposite sides of the first wiring layer;
the conductive plate is cut into a plurality of the substrates.
4. The method of manufacturing a chip package structure according to claim 1, wherein after the step of disposing a molding layer on the carrier plate, the method further comprises:
and grinding one side of the plastic sealing layer, which is far away from the carrier plate, so as to expose one side of the chip, which is far away from the carrier plate.
5. The method of claim 1, wherein after the step of attaching the side of the at least one substrate provided with the first protective layer to a carrier, the method further comprises:
and setting filling glue at the gap between the substrate and the chip so that the filling glue fills the gap between the substrate and the chip.
6. The method of claim 1, wherein the step of attaching the side of the at least one substrate provided with the first protective layer to a carrier comprises:
providing a carrier plate;
an adhesive layer is arranged on one side of the carrier plate;
and attaching at least one side of the substrate provided with the first protective layer to the adhesive layer.
7. The method of manufacturing a chip package structure according to claim 6, wherein the step of disposing an adhesive layer on one side of the carrier comprises:
selecting an adhesive material based on the material of the carrier plate;
and arranging the bonding material on one side of the carrier plate and forming a bonding layer.
8. The method of manufacturing a chip package structure according to claim 1, wherein before the step of disposing the chip on a side of the substrate away from the carrier, and electrically connecting the leads of the chip with the first wiring layer through the first ball mounting holes, the method further comprises:
manufacturing a second wiring layer on one side of the pins of the chip, and leading out the pins of the chip to be electrically connected with the second wiring layer;
arranging a second tin ball on one side of the second wiring layer far away from the chip so as to electrically connect a pin of the chip with the second tin ball;
the step of arranging the chip on the side of the substrate away from the carrier plate, and electrically connecting pins of the chip with the first wiring layer through the first ball-implanting holes comprises the following steps:
and arranging the chip on one side of the substrate far away from the carrier plate, and enabling the second tin balls to be electrically connected with the first wiring layer through the first ball implantation holes.
9. The method of manufacturing a chip package structure according to claim 1, wherein the step of disposing a molding layer on the carrier plate, the molding layer wrapping the chip and the substrate, comprises:
providing an injection mold, wherein the injection mold comprises an upper mold and a lower mold, and the lower mold comprises an injection groove;
adding injection molding materials into the injection molding grooves, and heating and melting the injection molding materials;
mounting one side of the carrier plate far away from the chip on the upper die, and clamping the upper die and the lower die so as to immerse the chip and the substrate in molten injection molding material;
and removing the injection mold to form a plastic sealing layer which wraps the chip and the substrate on the carrier plate.
10. A chip package structure, characterized in that the chip package structure is manufactured by the manufacturing method of the chip package structure according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310815390.7A CN116844973A (en) | 2023-07-04 | 2023-07-04 | Manufacturing method of chip packaging structure and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310815390.7A CN116844973A (en) | 2023-07-04 | 2023-07-04 | Manufacturing method of chip packaging structure and chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116844973A true CN116844973A (en) | 2023-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310815390.7A Pending CN116844973A (en) | 2023-07-04 | 2023-07-04 | Manufacturing method of chip packaging structure and chip packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN116844973A (en) |
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2023
- 2023-07-04 CN CN202310815390.7A patent/CN116844973A/en active Pending
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