CN116825836A - Gate commutated thyristor - Google Patents
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- CN116825836A CN116825836A CN202310953328.4A CN202310953328A CN116825836A CN 116825836 A CN116825836 A CN 116825836A CN 202310953328 A CN202310953328 A CN 202310953328A CN 116825836 A CN116825836 A CN 116825836A
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- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 34
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- 238000010586 diagram Methods 0.000 description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
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Abstract
The invention discloses a gate commutated thyristor, comprising: the first conductive type base region comprises a convex part positioned at the center and a horizontal part positioned at the periphery of the convex part, and the convex part penetrates through the first conductive type base region; a plurality of second conductivity type short circuit emitter regions disposed in the first conductivity type base region, a first surface of the second conductivity type short circuit emitter regions facing away from the first conductivity type conductive layer being uncovered by the first conductivity type base region; at least one amplifying gate electrode arranged on the first surface of the second conductive type short-circuit emission region; and the thyristor functional layer is arranged on the first surface of the first conductive type base region opposite to the first conductive type conductive layer and the first surface of the first conductive type conductive layer opposite to the second conductive type base region. The invention solves the technical problem that the maximum electric field in the chip body is distributed at the terminal of the chip table top in the prior art, and blocking failure is easy to cause.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a gate commutated thyristor.
Background
IGCT (Integrated Gate-Commutated Thyristor) is used as a fully-controlled power semiconductor device, and has great potential for application in the field of direct-current power grids in the future due to the advantages of high blocking capacity, low on-state loss, high power capacity and the like. One of the application requirements in the field is that the IGCT device can be quickly turned into an on-state function under the working condition that the rated blocking value is exceeded, and the IGCT device is required to have a reliable short-circuit failure function when the device possibly fails.
When the GCT (Gate Commutated Thyristors, gate commutated thyristor) chip is in a blocking state, a reverse bias voltage (or short circuit) within-20V must be applied to the gate-cathode of the device to avoid the significant reduction of the device withstand voltage due to the positive bias injection effect of the gate-cathode junction. The positive-negative electrode is applied with a positive voltage, the device is in a positive blocking state, and the blocking voltage is mainly borne by a reverse biased blocking voltage main junction. At this time, the maximum electric field in the chip body is distributed at the terminal of the chip table surface, and when the voltage applied from the outside exceeds the chip bearing capacity, avalanche phenomenon occurs at the place, and blocking failure may be caused. And secondly, a dynamic avalanche generating position in the blocking state is positioned at the terminal, so that most blocking failure positions are also positioned at the terminal, and the blocking state can be possibly generated when the device fails.
Disclosure of Invention
In view of the above, the embodiment of the invention provides a gate commutated thyristor, which solves the technical problem that the maximum electric field in a chip body is distributed at the terminal of a chip table top in the prior art, and blocking failure is easy to cause.
The technical scheme provided by the embodiment of the invention is as follows:
a first aspect of an embodiment of the present invention provides a gate commutated thyristor, including: the semiconductor device comprises a first conductive type conductive layer, a second conductive type base region and a first conductive type base region which are sequentially arranged, wherein the second conductive type base region comprises a convex part positioned at the center and a horizontal part positioned at the periphery of the convex part, and the convex part penetrates through the first conductive type base region; a plurality of second conductivity type short circuit emitter regions disposed within the first conductivity type base region, a first surface of the second conductivity type short circuit emitter regions facing away from the first conductivity type conductive layer being uncovered by the first conductivity type base region; the amplifying gates are arranged on the first surface of the second conductivity type short-circuit emission area, and the plurality of second conductivity type short-circuit emission areas and the amplifying gates are located in the periphery preset range of the protruding part; and the thyristor functional layer is arranged on the first surface of the first conductive type base region, which is opposite to the first conductive type conductive layer, and the first surface of the first conductive type conductive layer, which is opposite to the second conductive type base region.
Optionally, the first conductivity type base region includes: the first conductive type lightly doped base region and the first conductive type heavily doped base region are sequentially arranged, the plurality of second conductive type short circuit emitter regions are arranged in the first conductive type heavily doped base region, and the first conductive type lightly doped base region and the second conductive type short circuit emitter regions are in contact or not in contact.
Optionally, a first surface of the protruding portion facing away from the first conductivity type conductive layer is not covered by the first conductivity type base region, and a lateral width of the first surface of the protruding portion is determined according to an avalanche turn voltage of the gate commutated thyristor.
Optionally, the first surface of the protruding portion is provided with a protective layer.
Optionally, the radial width of the second conductivity type short-circuit emission regions, the number of the second conductivity type short-circuit emission regions and the distance between any two second conductivity type short-circuit emission regions are determined according to the turn-on capability of the device.
Optionally, the peripheral preset range of the protruding portion includes a range with the center of the gate commutated thyristor as the center and the radius smaller than or equal to 20 mm.
Optionally, the gate commutated thyristor further comprises: and a second conductivity type buffer layer disposed between the second conductivity type base region and the first conductivity type conductive layer.
Optionally, the second conductivity type base region further includes: and the concave part penetrates through the first conductive type conductive layer, and is arranged in a preset range of the periphery of the convex part.
Optionally, the first conductivity type conductive layer includes: the first conductive type heavily doped conductive layer and the first conductive type lightly doped conductive layer are sequentially arranged.
Optionally, the thyristor functional layer includes: an anode arranged on a first surface of the first conductive type conductive layer opposite to the second conductive type base region, and a gate electrode, a cathode and a second conductive type emitter arranged on a first surface of the first conductive type base region opposite to the first conductive type conductive layer; the gate electrode, the cathode and the second conductive type emitter region are arranged outside the preset range of the periphery of the protruding portion, the gate electrode and the second conductive type emitter region are respectively contacted with the first surface of the first conductive type base region, and the cathode is contacted with the second conductive type emitter region.
The technical scheme of the invention has the following advantages:
according to the gate commutated thyristor provided by the embodiment of the invention, the raised part penetrating through the base region of the first conductivity type is formed by the base region of the second conductivity type to form a PNP structure, so that the dynamic avalanche generation position in the blocking state is adjusted to the center. Thus, on the one hand, the function of triggering the thyristor to turn on again when the rated blocking voltage is exceeded; on the other hand, a high-density current channel is formed at the center, and if the gate pole converter thyristor fails in a blocking way, the gate pole converter thyristor is ensured to fail at the center of the chip to be in a reliable short circuit state, so that the problem that the blocking state of the existing gate pole converter thyristor is in a blocking state when the terminal of the table board fails is solved. Meanwhile, the structural design does not occupy the effective utilization area of the thyristor, so that the on-state, off-state and other characteristics of the thyristor are not reduced. In addition, the gate commutated thyristor structure is easy to integrate in process, high in chip area utilization rate and reliable in short-circuit failure mode.
When the gate commutated thyristor provided by the embodiment of the invention is applied to the inverse gate commutated thyristor, the high-temperature blocking characteristic of the inverse gate commutated thyristor can be improved by forming the concave part penetrating through the first conductive layer by the second conductive base region.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a gate commutated thyristor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a gate commutated thyristor according to another embodiment of the invention;
FIG. 3 is a schematic diagram of a gate commutated thyristor according to another embodiment of the invention;
FIG. 4 is a schematic top view of a BOD zone according to an embodiment of the present invention;
FIG. 5 is a schematic top view of a BOD zone according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a prior art gate commutated thyristor;
FIG. 7 is a schematic top view of a cathode face of a prior art gate commutated thyristor;
FIG. 8 is a schematic diagram of a gate commutated thyristor according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a gate commutated thyristor according to another embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
An embodiment of the present invention provides a gate commutated thyristor, as shown in fig. 1, including: the semiconductor device comprises a first conductive type conductive layer 1, a second conductive type base region 2 and a first conductive type base region 3 which are sequentially arranged, wherein the second conductive type base region 2 comprises a convex part 21 positioned at the center and a horizontal part 22 positioned at the periphery of the convex part 21, and the convex part 21 penetrates through the first conductive type base region 3; at least one second conductivity-type short-circuit emitter region 4 disposed within said first conductivity-type base region 3, a first surface of said second conductivity-type short-circuit emitter region 4 facing away from said first conductivity-type conductive layer 1 being uncovered by said first conductivity-type base region 3; at least one amplifying gate 5 disposed on the first surface of the second conductive type short circuit emission region 4, the at least one second conductive type short circuit emission region 4 and the amplifying gate 5 being located within a preset range of the periphery of the protruding portion 21; and the thyristor functional layer is arranged on the first surface of the first conductive type base region 3 opposite to the first conductive type conductive layer 1 and the first surface of the first conductive type conductive layer 1 opposite to the second conductive type base region 2.
Wherein the first conductivity type may be a P-type semiconductor, and the second conductivity type is an N-type semiconductor; alternatively, the first conductivity type may be an N-type semiconductor and the second conductivity type may be a P-type semiconductor. In the following embodiments, a P-type semiconductor is used as the first conductivity type and an N-type semiconductor is used as the second conductivity type.
Specifically, the raised portion formed by the second conductivity type base region and the first conductivity type base regions on both sides thereof constitute a PNP structure. I.e. corresponds to a BOD (Break Over Diode) parallel connected in the centre of the gate commutated thyristor. Meanwhile, the PNP structure, the second conduction type short circuit emission region and the amplifying gate electrode form a high-density current channel together, so that the dynamic avalanche generation position in the blocking state is adjusted to the center, the thyristor will first occur at the center when the blocking failure occurs, and the reliable short circuit state caused by the failure at the center when the gate electrode current conversion thyristor fails. In addition, when dynamic avalanche occurs at the central PNP structure, avalanche current is generated to flow laterally through the amplifying gate to the gate of the thyristor functional layer, triggering the gate commutated thyristor, thereby acting as voltage protection. In addition, it should be noted that, a plurality of GCT functional areas may be disposed on the outer periphery of the BOD area, that is, the outer periphery of the GCT functional area in fig. 1 is continuously disposed with the GCT functional area, or a plurality of GCT functional areas are sequentially disposed on the outer periphery of the BOD area, and each of the functional areas has the same function, and each layer structure of the plurality of functional areas and the BOD area may be formed simultaneously. Note that, the gate commutated thyristor may also be referred to as a gate commutated thyristor chip (hereinafter referred to as a chip).
According to the gate commutated thyristor provided by the embodiment of the invention, the raised part penetrating through the base region of the first conductivity type is formed by the base region of the second conductivity type to form a PNP structure, so that the dynamic avalanche generation position in the blocking state is adjusted to the center. Thus, on the one hand, the function of triggering the thyristor to turn on again when the rated blocking voltage is exceeded; on the other hand, a high-density current channel is formed at the center, and if the gate pole converter thyristor fails in a blocking way, the gate pole converter thyristor is ensured to fail at the center of the chip to be in a reliable short circuit state, so that the problem that the blocking state of the existing gate pole converter thyristor is in a blocking state when the terminal of the table board fails is solved. Meanwhile, the structural design does not occupy the effective utilization area of the thyristor, so that the on-state, off-state and other characteristics of the thyristor are not reduced. In addition, the gate commutated thyristor structure is easy to integrate in process, high in chip area utilization rate and reliable in short-circuit failure mode.
In one embodiment, as shown in fig. 1, the first conductivity type base region 3 includes: the first conductive type lightly doped base region and the first conductive type heavily doped base region are sequentially arranged, the at least one second conductive type short circuit emitter region is arranged in the first conductive type heavily doped base region, and the first conductive type lightly doped base region and the second conductive type short circuit emitter region are in contact or not in contact. Wherein, when the first conductive type lightly doped base region and the first conductive type short circuit emitter region are contacted, the first conductive type lightly doped base region may be arranged in a polygonal shape, a circular spot shape or a circular ring shape.
It should be noted that, when the second conductivity type short circuit emitter is connected with the first conductivity type heavily doped base, or is connected with the first conductivity type lightly doped base and the first conductivity type heavily doped base, a shorted PN junction is formed, and the current flows transversely, so that the shorted PN junction is in forward amplification, and the amplification of avalanche current is realized through the amplifying gate structure.
Wherein the second conductivity type short-circuits the emitter regionIs defined by the radial width DeltaR n The number n of the second conductivity type short-circuit emission regions and the distance L between any two second conductivity type short-circuit emission regions n-(n-1) The current amplification factor of the amplifying gate can be regulated and controlled, and the current amplification factor can be determined according to the turn-on capability of the device. The second conductivity type short-circuit emission area and the cathode in the thyristor functional layer are positioned on the same surface, and the second conductivity type short-circuit emission area is in a circular ring-shaped, circular spot-shaped or polygonal structure. In addition, the second conductive type short-circuit emission region is in short-circuit connection with the first conductive type lightly doped base region and the first conductive type heavily doped base region on the outer side of the second conductive type short-circuit emission region through the amplifying electrode, wherein the opening capacity of the gate electrode current-converting thyristor can be changed by controlling the width of the contact surface between the amplifying gate electrode and the second conductive type short-circuit emission region, namely the short-circuit connection distance.
Specifically, as shown in fig. 1, a schematic structure of the first conductivity type lightly doped base region and the second conductivity type short circuit emitter region is not contacted, and fig. 2 and fig. 3 are schematic structures of the first conductivity type lightly doped base region and the second conductivity type short circuit emitter region contacted. As shown in fig. 4, when the first conductivity type lightly doped base region contacts with the second conductivity type short circuit emitter region, the first surface of the protruding portion is circular, and the second conductivity type short circuit emitter region is a structural schematic diagram corresponding to the circular ring, i.e. a top schematic diagram of the structure corresponding to fig. 2. As shown in fig. 5, when the first conductive type lightly doped base region contacts with the second conductive type short circuit emitter region, the first surface of the protruding portion is circular, and the second conductive type short circuit emitter region is a structural schematic diagram corresponding to the circular spot shape, that is, a top view schematic diagram of a structure corresponding to fig. 3.
In an embodiment, a first surface of the protruding portion facing away from the first conductivity type conductive layer is not covered by the first conductivity type base region, and a lateral width of the first surface of the protruding portion is determined according to an avalanche turn voltage of the gate commutated thyristor. The first surface of the protruding portion is provided with a protective layer. Specifically, as shown in fig. 1, the first surface of the protruding portion is exposed outside the first conductivity type base region, and the lateral width W of the first surface of the protruding portion, i.e., the top lateral width of the PNP structure, depends on the avalanche breakdown voltageV BOD . Namely, the BOD protection voltage value can be determined by designing the top transverse width of the PNP structure. In addition, the passivation protection of the protruding portion can be realized by designing the protection layer 10 on the first surface of the protruding portion, and the protection layer can adopt structures such as an oxide layer or other passivation layers.
In one embodiment, a conventional gate commutated thyristor structure is shown in fig. 6 and 7, in which a plurality of "strip cathodes", commonly referred to as cathode bars, are arranged radially from a lateral perspective. The cathode strips are uniformly distributed in a wafer by adopting sector arcs or circumferences. According to the magnitude of the GCT turn-off current, the GCT gate electrode leading-out part is arranged at the center of the wafer, namely called a center gate electrode, or arranged at the center or the periphery of the wafer, namely called a middle annular gate electrode or an edge annular gate electrode. And at the extreme edge terminal of the chip, a mesa modeling design is used, and then a passivation material is used for protecting the terminal surface, so that the blocking capability of the chip is ensured. The structure adopted in the embodiment of the invention can be designed on the basis of the existing structure, wherein the table surface design and the cathode sliver arrangement are kept unchanged under the condition of not influencing other parameters of a chip, as shown in fig. 1, the peripheral preset range of the gate commutated thyristor comprises a range with the center of a convex part as the center of a circle and the radius R less than or equal to 20mm, wherein the radius can be determined as 4mm, 5mm, 10mm, 15mm or 20mm and the like according to actual needs. The preset range of the periphery of the protruding part is used as the BOD area of the gate commutated thyristor.
In one embodiment, as shown in fig. 1, the gate commutated thyristor further comprises: a second conductivity-type buffer layer 11 disposed between the second conductivity-type base region 2 and the first conductivity-type conductive layer 1. The thyristor functional layer comprises: an anode 6 disposed on a first surface of the first conductivity-type conductive layer 1 facing away from the second conductivity-type base region 2, and a gate 7, a cathode 8, and a second conductivity-type emitter region 9 disposed on a first surface of the first conductivity-type base region 3 facing away from the first conductivity-type conductive layer 1; the gate 7, the cathode 8 and the second conductive type emitter 9 are disposed outside the protrusion periphery preset range, the gate 7 and the second conductive type emitter 9 are respectively in contact with the first surface of the first conductive type base region 3, and the cathode 8 and the second conductive type emitter 9 are in contact.
In one embodiment, as shown in FIG. 2, the gate commutated thyristor comprises N in order from cathode to anode + Short-circuit emission region, i.e. second conductivity type short-circuit emission region, P + The base region is a heavily doped base region of a first conductivity type, the P base region is a lightly doped base region of a first conductivity type, and the N is - Base region, i.e. second conductivity type base region, N' buffer layer, i.e. second conductivity type buffer region and P + The transparent emissive anode is the first conductivity type conductive layer. Through N at the center - The convex part of the base region forms a voltage protection region (BOD region), namely a PNP structure designed on the cathode surface, and the BOD region comprises N + Short-circuit emitter region, P + Base region, P base region, N - Base region, N' buffer layer and P + Transparent emitting anode and formed simultaneously with each layer of thyristor outside BOD region, wherein N + The short-circuit emitter region is in short-circuit connection with the P+ base region or the P base region through the amplifying gate electrode to form a multistage amplifying gate electrode. Next, N - Raised part of base region and P on two sides of raised part + The base region and the P base region form a PNP BOD structure.
Wherein P is + The doping concentration of the transparent anode emission area is 1E17cm -3 ～1E18cm -3 The diffusion depth is about 0.2 μm to 5 μm. P (P) + The doping concentration of the base region is 1E15cm -3 ～1E18cm -3 The diffusion depth is about 40 μm to 100 μm. The doping concentration of the P base region is 1E14cm -3 ～2E16cm -3 The diffusion junction depth is typically designed according to the blocking voltage, about 50 μm to 200 μm. N (N) + The doping concentration of the short-circuit emission region is 1E19 cm -3 ～1E21cm -3 The diffusion depth is about 5 μm to 40 μm. The depth of the gate trench is about 0 μm to 40 μm. N (N) ′ The doping concentration of the buffer layer is 1E15cm -3 ～1E17cm -3 The diffusion depth is about 20-90 μm, and the design is adjusted depending on the characteristic trade-off between the chip blocking, on-state and off-state. N (N) - The doping concentration of the base region and its base width depend on the blocking voltage level.
Example 2
The embodiment of the invention provides a gate commutated thyristor, as shown in fig. 8, which is a reverse-resistance gate commutated thyristor, comprising: the semiconductor device comprises a first conductive type conductive layer 1, a second conductive type base region 2 and a first conductive type base region 3 which are sequentially arranged, wherein the second conductive type base region 2 comprises a convex part 21 positioned at the center and a horizontal part 22 positioned at the periphery of the convex part 21, and the convex part 21 penetrates through the first conductive type base region 3; at least one second conductivity-type short-circuit emitter region 4 disposed within said first conductivity-type base region 3, a first surface of said second conductivity-type short-circuit emitter region 4 facing away from said first conductivity-type conductive layer 1 being uncovered by said first conductivity-type base region 3; at least one amplifying gate 5 disposed on the first surface of the second conductive type short circuit emission region 4, the at least one second conductive type short circuit emission region 4 and the amplifying gate 5 being located within a preset range of the periphery of the protruding portion 21; and the thyristor functional layer is arranged on the first surface of the first conductive type base region 3 opposite to the first conductive type conductive layer 1 and the first surface of the first conductive type conductive layer 1 opposite to the second conductive type base region 2. The second conductivity type base region 2 further includes: a recess 23, the recess 23 penetrates through the first conductive type conductive layer 1, and the recess 23 is disposed within a preset range of the periphery of the protrusion 21. At this time, the first conductive type conductive layer 1 includes: a first conductive type heavily doped conductive layer P arranged in sequence + The anode region and the first conductivity type lightly doped conductive layer, i.e., the P-anode region.
As shown in fig. 8, the thyristor functional layer includes: an anode 6 disposed on a first surface of the first conductivity-type conductive layer 1 facing away from the second conductivity-type base region 2, and a gate 7, a cathode 8, and a second conductivity-type emitter region 9 disposed on a first surface of the first conductivity-type base region 3 facing away from the first conductivity-type conductive layer 1; the gate 7, the cathode 8 and the second conductive type emitter 9 are disposed outside the protrusion periphery preset range, the gate 7 and the second conductive type emitter 9 are respectively in contact with the first surface of the first conductive type base region 3, and the cathode 8 and the second conductive type emitter 9 are in contact.
Wherein the first conductivity type may be a P-type semiconductor, and the second conductivity type is an N-type semiconductor; alternatively, the first conductivity type may be an N-type semiconductor and the second conductivity type may be a P-type semiconductor. In the following embodiments, a P-type semiconductor is used as the first conductivity type and an N-type semiconductor is used as the second conductivity type.
Specifically, the recess 23 is formed below the amplifying gate 5, and after the recess 23 penetrates the first conductivity type conductive layer 1, the first surface of the recess 23 opposite to the first conductivity type base region 3 contacts the anode 6, so as to form a short circuit connection between the second conductivity type base region 2 and the anode 6. Meanwhile, the recess 23 and the first conductive type conductive layers 1 on both sides thereof constitute an anode PNP short circuit isolation structure. The first surface of the recess 23 may be circular, polygonal or spot-shaped. The lateral width of the first surface of the recess 23, i.e. the lateral width of the top of the anode of the base region 2 of the second conductivity type, depends on the reverse avalanche breakover voltage and the anode injection efficiency.
When the gate commutated thyristor provided by the embodiment of the invention is applied to the inverse gate commutated thyristor, the high-temperature blocking characteristic of the inverse gate commutated thyristor can be improved by forming the concave part penetrating through the first conductive layer by the second conductive base region.
In one embodiment, as shown in FIG. 9, the gate commutated thyristor comprises N in order from cathode to anode + Short-circuit emission region, i.e. second conductivity type short-circuit emission region, P + The base region is a heavily doped base region of a first conductivity type, the P base region is a lightly doped base region of a first conductivity type, and the N is - The base region is a second conductive type base region, the P anode region is a first conductive type lightly doped conductive layer and P + The anode region is the first conductivity type heavily doped conductive layer. Through N at the center - The convex part of the base region forms a voltage protection region (BOD region), namely a PNP structure designed on the cathode surface, and the BOD region comprises N + Short-circuit emitter region, P + Base region, P base region, N - Base region, P anode region and P + Anode region, and all are formed simultaneously with each layer of structure of thyristor outside BOD regionWherein N is + Short-circuit emission area is formed by amplifying gate electrode and P + The base region or the P base region is connected in a short circuit mode, and a multistage amplifying gate electrode is formed. Next, N - Raised part of base region and P on two sides of raised part + The base region and the P base region form a PNP BOD structure. Meanwhile, an anode PNP short-circuit isolation structure formed by the concave part and the first conductive type conductive layers at two sides of the concave part is arranged below the gate electrode.
Wherein the doping concentration of the P anode region is 1E14cm -3 ～2E16cm -3 The diffusion junction depth is typically designed according to the blocking voltage, about 50 μm to 200 μm. P (P) + The doping concentration of the anode region is 1E15cm -3 ～1E18cm -3 The diffusion depth is about 40 μm to 100 μm, depending on the design of the characteristic compromise between reverse blocking, on-state and reverse recovery. P (P) + The doping concentration of the base region is 1E15cm -3 ～1E18cm -3 The diffusion depth is about 40 μm to 100 μm. The doping concentration of the P base region is 1E14cm -3 ～2E16cm -3 The diffusion junction depth is typically designed according to the blocking voltage, about 50 μm to 200 μm. N (N) + The doping concentration of the short-circuit emission region is 1E19 cm -3 ～1E21cm -3 The diffusion depth is about 5 μm to 40 μm. The depth of the gate trench is about 0 μm to 40 μm. N (N) - The doping concentration of the base region and its base width depend on the blocking voltage level.
In this embodiment, the structural design of the protruding portion and the second conductive type short-circuit emission region is referred to the corresponding structural design of embodiment 1, and will not be described herein.
Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and alterations to these embodiments without departing from the spirit of the invention and the scope of protection as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while remaining within the scope of the present invention.
Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. From the present disclosure, it will be readily understood by those of ordinary skill in the art that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (10)
1. A gate commutated thyristor, comprising:
the semiconductor device comprises a first conductive type conductive layer, a second conductive type base region and a first conductive type base region which are sequentially arranged, wherein the second conductive type base region comprises a convex part positioned at the center and a horizontal part positioned at the periphery of the convex part, and the convex part penetrates through the first conductive type base region;
a plurality of second conductivity type short circuit emitter regions disposed within the first conductivity type base region, a first surface of the second conductivity type short circuit emitter regions facing away from the first conductivity type conductive layer being uncovered by the first conductivity type base region;
the amplifying gates are arranged on the first surface of the second conductivity type short-circuit emission area, and the plurality of second conductivity type short-circuit emission areas and the amplifying gates are located in the periphery preset range of the protruding part;
and the thyristor functional layer is arranged on the first surface of the first conductive type base region, which is opposite to the first conductive type conductive layer, and the first surface of the first conductive type conductive layer, which is opposite to the second conductive type base region.
2. The gate commutated thyristor of claim 1, wherein the first conductivity type base region comprises: the first conductive type lightly doped base region and the first conductive type heavily doped base region are sequentially arranged, the plurality of second conductive type short circuit emitter regions are arranged in the first conductive type heavily doped base region, and the first conductive type lightly doped base region and the second conductive type short circuit emitter regions are in contact or not in contact.
3. The gate commutated thyristor of claim 1, wherein a first surface of the raised portion facing away from the first conductivity type conductive layer is uncovered by the first conductivity type base region, and wherein a lateral width of the first surface of the raised portion is determined from an avalanche breakover voltage of the gate commutated thyristor.
4. A gate commutated thyristor according to claim 3, wherein the first surface of the protruding portion is provided with a protective layer.
5. The gate commutated thyristor of claim 1, wherein the radial width of the second conductivity type short-circuited emitter regions, the number of second conductivity type short-circuited emitter regions, and the distance between any two second conductivity type short-circuited emitter regions are determined according to the turn-on capability of the device.
6. The gate commutated thyristor of claim 1, wherein the predetermined range of the periphery of the boss comprises a range of 20mm or less in radius with the center of the gate commutated thyristor as the center of the circle.
7. The gate commutated thyristor of any one of claims 1-6, further comprising: and a second conductivity type buffer layer disposed between the second conductivity type base region and the first conductivity type conductive layer.
8. The gate commutated thyristor of claim 1, wherein the second conductivity type base region further comprises: and the concave part penetrates through the first conductive type conductive layer, and is arranged in a preset range of the periphery of the convex part.
9. The gate commutated thyristor of claim 8, wherein the first conductivity type conductive layer comprises: the first conductive type heavily doped conductive layer and the first conductive type lightly doped conductive layer are sequentially arranged.
10. The gate commutated thyristor of any one of claims 1-9, wherein the thyristor functional layer comprises: an anode arranged on a first surface of the first conductive type conductive layer opposite to the second conductive type base region, and a gate electrode, a cathode and a second conductive type emitter arranged on a first surface of the first conductive type base region opposite to the first conductive type conductive layer;
the gate electrode, the cathode and the second conductive type emitter region are arranged outside the preset range of the periphery of the protruding portion, the gate electrode and the second conductive type emitter region are respectively contacted with the first surface of the first conductive type base region, and the cathode is contacted with the second conductive type emitter region.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117219666A (en) * | 2023-11-07 | 2023-12-12 | 湖北九峰山实验室 | Gallium oxide heterogeneous thyristor with double trigger gate electrodes and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117219666A (en) * | 2023-11-07 | 2023-12-12 | 湖北九峰山实验室 | Gallium oxide heterogeneous thyristor with double trigger gate electrodes and preparation method thereof |
| CN117219666B (en) * | 2023-11-07 | 2024-01-26 | 湖北九峰山实验室 | Gallium oxide heterogeneous thyristor with double trigger gate electrodes and preparation method thereof |
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