CN116825833A

CN116825833A - Semiconductor device and semiconductor circuit

Info

Publication number: CN116825833A
Application number: CN202210811220.7A
Authority: CN
Inventors: 岩鍜治阳子; 末代知子; 下条亮平
Original assignee: Toshiba Corp; Toshiba Electronic Devices and Storage Corp
Current assignee: Toshiba Corp; Toshiba Electronic Devices and Storage Corp
Priority date: 2022-03-19
Filing date: 2022-07-11
Publication date: 2023-09-29
Also published as: JP2023138192A

Abstract

The embodiment provides a semiconductor device and a semiconductor circuit capable of reducing switching loss. A semiconductor device of an embodiment is provided with: a first trench; a first gate electrode disposed in the first trench; a second trench; a second gate electrode disposed in the second trench; a third trench; a third gate electrode disposed in the third trench; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode, wherein the thickness of the conductive semiconductor region in contact with the third trench and facing the third gate electrode is smaller than the thickness of the conductive semiconductor region in contact with the first trench and facing the first gate electrode, and the thickness of the conductive semiconductor region in contact with the third trench and facing the third gate electrode is smaller than the thickness of the conductive semiconductor region in contact with the second trench and facing the second gate electrode.

Description

Semiconductor device and semiconductor circuit

Related application

The present application claims priority based on Japanese patent application No. 2022-44755 (application day: 19 of 3/2022). The present application refers to the entire content of the basic application by referring to the basic application.

Technical Field

Embodiments of the present invention relate to a semiconductor device and a semiconductor circuit.

Background

As an example of the semiconductor device for electric power, there is an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT). The IGBT includes, for example, a p-type collector region, an n-type drift region, and a p-type base region on the collector electrode. A gate electrode is provided in a trench penetrating the p-type base region and reaching the n-type drift region with a gate insulating film interposed therebetween. An n-type emitter region connected to the emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

In the case of IGBTs, it is desirable to reduce switching losses.

Disclosure of Invention

The invention provides a semiconductor device and a semiconductor circuit capable of reducing switching loss.

A semiconductor device of an embodiment is provided with: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface; a first trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode disposed in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode, wherein the third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with the at least one third trench, a thickness of the third portion in a direction from the first surface toward the second surface is smaller than a thickness of the first portion in the direction, and a thickness of the third portion in a direction from the first surface toward the second surface is smaller than a thickness of the second portion in the direction.

Drawings

Fig. 1 is a schematic diagram of a semiconductor circuit of a first embodiment.

Fig. 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

Fig. 3 is a schematic top view of a part of the semiconductor device of the first embodiment.

Fig. 4 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

Fig. 5 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

Fig. 6 is an explanatory diagram of a driving method of the semiconductor device of the first embodiment.

Fig. 7 is an enlarged schematic cross-sectional view of a part of a semiconductor device according to a modification of the first embodiment.

Fig. 8 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment.

Fig. 9 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the second embodiment.

Fig. 10 is a schematic cross-sectional view of a part of a semiconductor device of the third embodiment.

Fig. 11 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the third embodiment.

Fig. 12 is a schematic cross-sectional view of a part of a semiconductor device of the fourth embodiment.

Fig. 13 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the fourth embodiment.

Fig. 14 is a schematic cross-sectional view of a part of a semiconductor device of the fifth embodiment.

Fig. 15 is a schematic top view of a part of a semiconductor device of the fifth embodiment.

Fig. 16 is a schematic cross-sectional view of a part of a semiconductor device of the fifth embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar components are denoted by the same reference numerals, and the description thereof is omitted as appropriate for the components and the like described once.

In the present specification, there is n ⁺ Type, n ^- In the case of the expression "type", the n-type impurity concentration is represented by n ⁺ Type, n ^- The order of the patterns decreases. In addition, there is p ⁺ Type, p-type, p ^- In the case of the expression of type, this means that the concentration of p-type impurity is expressed as p ⁺ Type, p-type, p ^- The order of the patterns decreases. Has a structure of n ⁺ Type, n ^- The type summary is described only as the case of n-type. In addition, there is a method of converting p ⁺ Type, p-type, p ^- The type summary is described only as the case of p-type.

In the present specification, the n-type impurity concentration does not mean an actual n-type impurity concentration, but means an effective n-type impurity concentration after compensation. Also, the p-type impurity concentration does not represent the actual p-type impurity concentration, but represents the effective p-type impurity concentration after compensation. For example, when the actual n-type impurity concentration is larger than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is referred to as the n-type impurity concentration. The same applies to the p-type impurity concentration.

In this specification, the distribution and absolute value of the impurity concentration in the semiconductor region can be measured by, for example, secondary ion mass spectrometry (Secondary Ion Mass Spectrometry:SIMS). The relative magnitude relation between the impurity concentrations of the two semiconductor regions can be determined by using, for example, a scanning capacitance microscope method (Scanning Capacitance Microscopy:scm). The distribution of the impurity concentration and the absolute value thereof can be measured by, for example, an extended resistance measurement method (Spreading Resistance Analysis:SRA). In SCM and SRA, the absolute value of the relative magnitude relation of the carrier concentration in the semiconductor region is obtained. By assuming the activation rate of the impurity, the relative magnitude relation between the impurity concentrations of the two semiconductor regions, the distribution of the impurity concentrations, and the absolute value of the impurity concentration can be obtained from the measurement results of the SCM and the SRA.

In this specification, a transistor portion which is driven using a first gate electrode in a semiconductor device may be expressed as a "first transistor having a first gate electrode". Similarly, there are cases where a transistor portion driven using the second gate electrode is expressed as "a second transistor having the second gate electrode", and a transistor portion driven using the third gate electrode is expressed as "a third transistor having the third gate electrode".

(first embodiment)

The semiconductor device of the first embodiment includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a first trench provided on a first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode disposed in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode. Further, the third semiconductor region includes: the first portion is connected with the first groove, the second portion is connected with the second groove, and the third portion is connected with at least one third groove, the thickness of the third portion in the direction from the first face to the second face is thinner than that of the first portion, and the thickness of the third portion in the direction from the first face to the second face is thinner than that of the second portion.

The semiconductor circuit of the first embodiment includes a control circuit for driving the semiconductor device.

The semiconductor device of the first embodiment is an IGBT100. The IGBT100 is a trench gate type IGBT including a gate electrode among trenches formed in a semiconductor layer. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The control circuit of the first embodiment is a gate driver circuit 150. The semiconductor circuit of the first embodiment is constituted by a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor component mounted with the IGBT100 and the gate driver circuit 150.

Fig. 1 is a schematic diagram of a semiconductor circuit of a first embodiment.

Fig. 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Fig. 2 is a section AA' of fig. 1.

Fig. 3 is a schematic top view of a part of the semiconductor device of the first embodiment. Fig. 3 is a top view in the first face F1. Fig. 2 is a section AA' of fig. 3.

Fig. 4 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Fig. 4 is a BB' section of fig. 3.

The semiconductor circuit of the first embodiment has the IGBT100 and the gate driver circuit 150. The IGBT100 has a transistor region 101. The transistor region 101 is provided with a plurality of transistors that operate at different timings.

The IGBT100 is an example of a semiconductor device. The gate driver circuit 150 is one example of a control circuit.

The IGBT100 of the first embodiment includes: the semiconductor layer 10, the emitter electrode 12 (first electrode), the collector electrode 14 (second electrode), the first gate insulating film 41, the second gate insulating film 42, the third gate insulating film 43, the first gate electrode 51, the second gate electrode 52, the third gate electrode 53, the interlayer insulating layer 61, the first gate electrode pad 104 (first electrode pad), the second gate electrode pad 105 (second electrode pad), and the third gate electrode pad 106 (third electrode pad).

The semiconductor layer 10 includes a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region).

The base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c. The barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

The semiconductor layer 10 has a first surface F1 and a second surface F2 opposite to the first surface F1. The semiconductor layer 10 is, for example, monocrystalline silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

In the present specification, a direction parallel to the first surface F1 is referred to as a first direction. The direction parallel to the first surface F1 and orthogonal to the first direction is referred to as a second direction. The direction from the first surface F1 toward the second surface F2 is referred to as a third direction.

In the present specification, "depth" is defined as a distance in a direction toward the second surface F2 with reference to the first surface F1.

The emitter electrode 12 is provided on the first surface F1 side of the semiconductor layer 10. At least a portion of the emitter electrode 12 contacts the first surface F1 of the semiconductor layer 10. The emitter electrode 12 is, for example, metal.

The emitter electrode 12 is in contact with the emitter region 29. The emitter electrode 12 is electrically connected to the emitter region 29.

The emitter electrode 12 meets the contact region 30. The emitter electrode 12 is electrically connected to the contact region 30. The emitter electrode 12 is electrically connected to the base region 28 via a contact region 30.

The collector electrode 14 is provided on the second surface F2 side of the semiconductor layer 10. At least a portion of the collector electrode 14 contacts the second surface F2 of the semiconductor layer 10. The collector electrode 14 is, for example, metal.

The collector electrode 14 is connected to the collector region 26. The collector electrode 14 is electrically connected to the collector region 26.

Collector region 26 is p ⁺ A semiconductor region of the type. The collector region 26 meets the second face F2. The collector region 26 is electrically connected to the collector electrode 14. The collector region 26 is connected to the collector electrode 14. The collector region 26 serves as a source of holes in the on state of the IGBT 100.

The drift region 27 is an n-type semiconductor region. The drift region 27 is provided between the collector region 26 and the first surface F1.

The drift region 27 serves as a path for an on current in the on state of the IGBT 100. The drift region 27 has a function of exhausting the IGBT100 in the off state and maintaining the withstand voltage of the IGBT 100.

The base region 28 is a p-type semiconductor region. The base region 28 is provided between the drift region 27 and the first surface F1. The base region 28 sandwiches the drift region 27 with the collector region 26.

The depth of the base region 28 is, for example, 5 μm or less. In the on state of the IGBT100, an n-type inversion layer is formed in the region of the base region 28 facing the first gate electrode 51, the region of the base region 28 facing the second gate electrode 52, and the region of the base region 28 facing the third gate electrode 53. The base region 28 functions as a channel region of the transistor.

The barrier region 31 is an n-type semiconductor region. A barrier region 31 is provided between the drift region 27 and the base region 28. The n-type impurity concentration of the barrier region 31 is higher than that of the drift region 27.

The barrier region 31 has a function of increasing the carrier accumulation amount of the drift region 27 in the on state of the IGBT 100. By providing the barrier region 31, the on-resistance of the IGBT100 is reduced, and the steady-state loss of the IGBT100 is reduced.

Emitter region 29 is n ⁺ A semiconductor region of the type. The emitter region 29 is provided between the base region 28 and the first face F1.

The emitter region 29 is in contact with the first gate insulating film 41, the second gate insulating film 42, and the third gate insulating film 43.

The n-type impurity concentration of the emitter region 29 is higher than that of the drift region 27.

The emitter region 29 is in contact with the emitter electrode 12. The emitter region 29 is electrically connected to the emitter electrode 12. The emitter region 29 serves as a supply source of electrons in the on state of the IGBT 100.

The contact region 30 is p ⁺ A semiconductor region of the type. The contact region 30 is provided between the base region 28 and the first face F1. The contact region 30 is connected to the emitter electrode 12. The contact region 30 is electrically connected to the emitter electrode 12.

The contact region 30 has a higher p-type impurity concentration than the base region 28.

The first gate trench 21 is provided on the first surface F1 side of the semiconductor layer 10. The first gate trench 21 is a trench provided in the semiconductor layer 10. The first gate trench 21 is a portion of the semiconductor layer 10.

As shown in fig. 3, the first gate trench 21 extends in the first plane F1 in a first direction parallel to the first plane F1. The first gate trench 21 has a stripe shape. The plurality of first gate trenches 21 are repeatedly arranged in a second direction orthogonal to the first direction.

The first gate trench 21 is connected to the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The first gate trench 21 penetrates the base region 28 and reaches the drift region 27. The depth of the first gate trench 21 is, for example, 8 μm or less.

The first gate electrode 51 is disposed in the first gate trench 21. The first gate electrode 51 is, for example, a semiconductor or a metal. The first gate electrode 51 contains, for example, n-type impurity or p-type impurity, and is amorphous silicon or polysilicon. The first gate electrode 51 is electrically connected to the first gate electrode pad 104.

The first gate insulating film 41 is provided between the first gate electrode 51 and the semiconductor layer 10. The first gate insulating film 41 is provided between the first gate electrode 51 and the drift region 27, between the first gate electrode 51 and the base region 28, between the first gate electrode 51 and the emitter region 29, and between the first gate electrode 51 and the barrier region 31. The first gate insulating film 41 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The first gate insulating film 41 is, for example, silicon oxide.

The second gate trench 22 is provided on the first surface F1 side of the semiconductor layer 10. The second gate trench 22 is a trench provided in the semiconductor layer 10. The second gate trench 22 is part of the semiconductor layer 10.

As shown in fig. 3, the second gate trench 22 extends in the first plane F1 in a first direction parallel to the first plane F1. The second gate trench 22 has a stripe shape. The plurality of second gate trenches 22 are repeatedly arranged in a second direction orthogonal to the first direction.

The second gate trench 22 is connected to the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The second gate trench 22 penetrates the base region 28 and reaches the drift region 27. The depth of the second gate trench 22 is, for example, 8 μm or less.

The second gate electrode 52 is disposed in the second gate trench 22. The second gate electrode 52 is, for example, a semiconductor or a metal. The second gate electrode 52 is, for example, amorphous silicon or polysilicon containing n-type impurities or p-type impurities. The second gate electrode 52 is electrically connected to the second gate electrode pad 105.

The second gate insulating film 42 is provided between the second gate electrode 52 and the semiconductor layer 10. The second gate insulating film 42 is provided between the second gate electrode 52 and the drift region 27, between the second gate electrode 52 and the base region 28, between the second gate electrode 52 and the emitter region 29, and between the second gate electrode 52 and the barrier region 31. The second gate insulating film 42 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The second gate insulating film 42 is, for example, silicon oxide.

The third gate trench 23 is provided on the first surface F1 side of the semiconductor layer 10. The third gate trench 23 is a trench provided in the semiconductor layer 10. The third gate trench 23 is a portion of the semiconductor layer 10.

As shown in fig. 3, the third gate trench 23 extends on the first face F1 in a first direction parallel to the first face F1. The third gate trench 23 has a stripe shape. The plurality of third gate trenches 23 are repeatedly arranged in a second direction orthogonal to the first direction.

The third gate trench 23 is connected to the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The third gate trench 23 penetrates the base region 28 and reaches the drift region 27. The depth of the third gate trench 23 is, for example, 8 μm or less.

The third gate electrode 53 is provided in the third gate trench 23. The third gate electrode 53 is, for example, a semiconductor or a metal. The third gate electrode 53 contains, for example, an n-type impurity or a p-type impurity, and is amorphous silicon or polycrystalline silicon. The third gate electrode 53 is electrically connected to the third gate electrode pad 106.

The third gate insulating film 43 is provided between the third gate electrode 53 and the semiconductor layer 10. The third gate insulating film 43 is provided between the third gate electrode 53 and the drift region 27, between the third gate electrode 53 and the base region 28, between the third gate electrode 53 and the emitter region 29, and between the third gate electrode 53 and the barrier region 31. The third gate insulating film 43 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The third gate insulating film 43 is, for example, silicon oxide.

An interlayer insulating layer 61 is provided between the first gate electrode 51 and the emitter electrode 12. The interlayer insulating layer 61 electrically separates the first gate electrode 51 from the emitter electrode 12. An interlayer insulating layer 61 is provided between the second gate electrode 52 and the emitter electrode 12.

The interlayer insulating layer 61 electrically separates the second gate electrode 52 from the emitter electrode 12. An interlayer insulating layer 61 is provided between the third gate electrode 53 and the emitter electrode 12. The interlayer insulating layer 61 electrically separates the third gate electrode 53 from the emitter electrode 12. The interlayer insulating layer 61 is, for example, silicon oxide.

The first gate electrode pad 104 is provided on the first surface F1 side of the semiconductor layer 10. The first gate electrode pad 104 is electrically connected to the first gate electrode 51. The first gate electrode pad 104 and the first gate electrode 51 are connected by, for example, a metal wiring not shown.

The first gate electrode pad 104 is applied with a first gate voltage (Vg 1). The first gate electrode pad 104 is applied with, for example, a first on voltage (Von 1), a first off voltage (Voff 1).

The second gate electrode pad 105 is provided on the first surface F1 side of the semiconductor layer 10. The second gate electrode pad 105 is electrically connected to the second gate electrode 52. The second gate electrode pad 105 and the second gate electrode 52 are connected by, for example, a metal wiring not shown.

The second gate electrode pad 105 is applied with a second gate voltage (Vg 2). The second gate electrode pad 105 is applied with, for example, a second on voltage (Von 2), a second off voltage (Voff 2).

The third gate electrode pad 106 is provided on the first surface F1 side of the semiconductor layer 10. The third gate electrode pad 106 is electrically connected to the third gate electrode 53. The third gate electrode pad 106 is connected to the third gate electrode 53 through, for example, a metal wiring not shown.

The third gate electrode pad 106 is applied with a third gate voltage (Vg 3). The third gate electrode pad 106 is applied with, for example, a third on voltage (Von 3), a third off voltage (Voff 3).

The gate driver circuit 150 is provided on the same circuit substrate as the RC-IGBT100 or on another circuit substrate, for example. The gate driver circuit 150 has a function of driving the IGBT 100.

The gate driver circuit 150 has a function of applying a desired first gate voltage (Vg 1), a desired second gate voltage (Vg 2), and a desired third gate voltage (Vg 3) to the first gate electrode pad 104, the second gate electrode pad 105, and the third gate electrode pad 106 at a desired timing.

The gate driver circuit 150 applies a first on voltage (Von 1) to the first gate electrode pad 104, applies a second on voltage (Von 2) to the second gate electrode pad 105, applies a third on voltage (Von 3) to the third gate electrode pad 106, applies the first on voltage (Von 1) to the first gate electrode pad 104, applies the second on voltage (Von 2) to the second gate electrode pad 105, applies a third off voltage (Voff 3) to the third gate electrode pad 106 after applying the third on voltage (Von 3) to the third gate electrode pad 106, applies the second off voltage (Voff 2) to the second gate electrode pad 105 after applying the third off voltage (Voff 3) to the third gate electrode pad 106, and applies the first off voltage (Voff 1) to the first gate electrode pad 104 after applying the second off voltage (Voff 2) to the second gate electrode pad 105.

Fig. 5 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Fig. 5 is an enlarged view of a portion of fig. 2.

As shown in fig. 5, the base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

The first portion 28a is a portion that meets the first gate trench 21 of the base region 28. The first portion 28a is in contact with the first gate insulating film 41. The first portion 28a is opposite to the first gate electrode 51.

The first portion 28a functions as a channel region of the first transistor having the first gate electrode 51, the first gate insulating film 41, and the first portion 28 a. The first transistor is a transistor driven by a first gate voltage (Vg 1) applied to the first gate electrode 51.

The second portion 28b is the portion that meets the second gate trench 22 of the base region 28. The second portion 28b is in contact with the second gate insulating film 42. The second portion 28b is opposite the second gate electrode 52.

The second portion 28b functions as a channel region of the second transistor having the second gate electrode 52, the second gate insulating film 42, and the second portion 28 b. The second transistor is a transistor driven by a second gate voltage (Vg 2) applied to the second gate electrode 52.

The third portion 28c is a portion that meets the third gate trench 23 of the base region 28. The third portion 28c is in contact with the third gate insulating film 43. The third portion 28c is opposite to the third gate electrode 53.

The third portion 28c functions as a channel region of a third transistor having the third gate electrode 53, the third gate insulating film 43, and the third portion 28 c. The third transistor is a transistor driven by a third gate voltage (Vg 3) applied to the third gate electrode 53.

The thickness (t 3 in fig. 5) of the third portion 28c in the third direction is thinner than the thickness (t 1 in fig. 5) of the first portion 28a in the third direction. The thickness t3 of the third portion 28c in the third direction is, for example, 20% or more and 70% or less of the thickness t1 of the first portion 28a in the third direction.

Further, the thickness (t 3 in fig. 5) of the third portion 28c in the third direction is thinner than the thickness (t 2 in fig. 5) of the second portion 28b in the third direction. The thickness t3 of the third portion 28c in the third direction is, for example, 20% or more and 70% or less of the thickness t2 of the second portion 28b in the third direction.

As shown in fig. 5, the barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

The fourth portion 31a is a portion that meets the first gate trench 21 of the barrier region 31. The fourth portion 31a is in contact with the first gate insulating film 41. The fourth portion 31a is opposite to the first gate electrode 51. The fourth portion 31a is provided between the drift region 27 and the first portion 28 a.

The fifth portion 31b is a portion that is in contact with the second gate trench 22 of the barrier region 31. The fifth portion 31b is in contact with the second gate insulating film 42. The fifth portion 31b is opposite to the second gate electrode 52. The fifth portion 31b is provided between the drift region 27 and the second portion 28 b.

The sixth portion 31c is a portion that meets the third gate trench 23 of the barrier region 31. The sixth portion 31c is in contact with the third gate insulating film 43. The sixth portion 31c is opposite to the third gate electrode 53. The sixth portion 31c is provided between the drift region 27 and the third portion 28 c.

The thickness (t 6 in fig. 5) of the sixth portion 31c in the third direction is thicker than the thickness (t 4 in fig. 5) of the fourth portion 31a in the third direction. The thickness t6 of the sixth portion 31c in the third direction is, for example, 150% or more of the thickness t4 of the fourth portion 31a in the third direction.

Further, the thickness (t 6 in fig. 5) of the sixth portion 31c in the third direction is thicker than the thickness (t 5 in fig. 5) of the fifth portion 31b in the third direction. The thickness t6 of the sixth portion 31c in the third direction is, for example, 150% or more of the thickness t5 of the fifth portion 31b in the third direction.

Next, an example of a driving method of the IGBT100 will be described.

Fig. 6 is an explanatory diagram of a driving method of the semiconductor device of the first embodiment. Fig. 6 is a timing chart of a first gate voltage (Vg 1) applied to the first gate electrode pad 104, a second gate voltage (Vg 2) applied to the second gate electrode pad 105, and a third gate voltage (Vg 3) applied to the third gate electrode pad 106.

In the off state of the IGBT100, for example, the emitter electrode 12 is applied with an emitter voltage. The emitter voltage is, for example, 0V. Collector electrode 14 is applied with a collector voltage. The collector voltage is, for example, 200V to 6500V.

In the off state of the IGBT100, the first gate electrode pad 104 is applied with a first off voltage (Voff 1). The first gate voltage (Vg 1) becomes the first off voltage (Voff 1). Thus, the first gate electrode 51 is also applied with the first off voltage (Voff 1).

The first off voltage (Voff 1) is a voltage smaller than a threshold voltage at which the first transistor having the first gate electrode 51 is not turned on, for example, 0V or a negative voltage.

In the off state, an n-type inversion layer is not formed in the base region 28 facing the first gate electrode 51 and in contact with the first gate insulating film 41.

In the off state of the IGBT100, the second gate electrode pad 105 is applied with a second off voltage (Voff 2). The second gate voltage (Vg 2) becomes the second off voltage (Voff 2). Thus, the second gate electrode 52 is also applied with the second off voltage (Voff 2).

The second off voltage (Voff 2) is a voltage smaller than a threshold voltage at which the second transistor having the second gate electrode 52 is not turned on, for example, 0V or a negative voltage.

In the off state, an n-type inversion layer is not formed in the base region 28 facing the second gate electrode 52 and in contact with the second gate insulating film 42.

In the off state of the IGBT100, the third gate electrode pad 106 is applied with a third off voltage (Voff 3). The third gate voltage (Vg 3) becomes the third off voltage (Voff 3). Thus, the third gate electrode 53 is also applied with the third off-voltage (Voff 3).

The third off voltage (Voff 3) is a voltage smaller than a threshold voltage at which the third transistor having the third gate electrode 53 is not turned on, for example, 0V.

In the off state, an n-type inversion layer is not formed in the base region 28 facing the third gate electrode 53 and in contact with the third gate insulating film 43.

At time T1, a first on voltage (Von 1) is applied to the first gate electrode pad 104. The first gate voltage (Vg 1) becomes the first on voltage (Von 1). The first gate electrode 51 is also applied with a first on voltage (Von 1).

The first on voltage (Von 1) refers to a positive voltage exceeding the threshold voltage of the first transistor having the first gate electrode 51. The first switching voltage (Von 1) is, for example, 15V. By applying the first on voltage (Von 1) to the first gate electrode 51, the first transistor having the first gate electrode 51 becomes an on state.

In the on state, an n-type inversion layer is formed in the base region 28 facing the first gate electrode 51 and contacting the first gate insulating film 41.

At time T1, a second on voltage (Von 2) is applied to the second gate electrode pad 105. The second gate voltage (Vg 2) becomes the second on voltage (Von 2). The second gate electrode 52 is also applied with a second on voltage (Von 2).

The second on voltage (Von 2) refers to a positive voltage exceeding the threshold voltage of the second transistor having the second gate electrode 52. The second switching voltage (Von 2) is, for example, 15V. By applying the second on voltage (Von 2) to the second gate electrode 52, the second transistor having the second gate electrode 52 becomes an on state.

In the on state, an n-type inversion layer is formed in the base region 28 facing the second gate electrode 52 and in contact with the second gate insulating film 42.

At time T1, a third on voltage (Von 3) is applied to the third gate electrode pad 106. The third gate voltage (Vg 3) becomes the third on voltage (Von 3). The third gate electrode 53 is also applied with a third on voltage (Von 3).

The third on voltage (Von 3) refers to a positive voltage exceeding the threshold voltage of the third transistor having the third gate electrode 53. The third on-voltage (Von 3) is, for example, 15V. By applying the third on voltage (Von 3) to the third gate electrode 53, the third transistor having the third gate electrode 53 becomes an on state.

In the on state, an n-type inversion layer is formed in the base region 28 facing the third gate electrode 53 and in contact with the third gate insulating film 43.

After time T1, IGBT100 is turned on.

At time T2, a third off voltage (Voff 3) is applied to the third gate electrode pad 106. The third gate voltage (Vg 3) becomes the third off voltage (Voff 3). The third gate electrode 53 is also applied with a third off voltage (Voff 3).

By the application of the third off voltage (Voff 3) to the third gate electrode 53, the third transistor having the third gate electrode 53 becomes an off state.

At time T3, a second off voltage (Voff 2) is applied to the second gate electrode pad 105. The second gate voltage (Vg 2) becomes the second off voltage (Voff 2). The second gate electrode 52 is also applied with a second off voltage (Voff 2).

The second transistor having the second gate electrode 52 becomes an off state by application of the second off voltage (Voff 2) to the second gate electrode 52.

For example, when the second off voltage (Voff 2) is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the second gate insulating film 42. The second off-voltage (Voff 2) is, for example, -15V or more and less than 0V.

At time T4, a first off voltage (Voff 1) is applied to the first gate electrode pad 104. The first gate voltage (Vg 1) becomes the first off voltage (Voff 1). The first gate electrode 51 is also applied with a first off voltage (Voff 1).

The first transistor having the first gate electrode 51 becomes an off state by application of the first off voltage (Voff 1) to the first gate electrode 51.

After time T4, the first transistor having the first gate electrode 51, the second transistor having the second gate electrode 52, and the third transistor having the third gate electrode 53 are all turned off.

Next, the operation and effects of the semiconductor device and the semiconductor circuit according to the first embodiment will be described.

The IGBT100 of the first embodiment includes, in the transistor region 101: a first transistor having a first gate electrode 51, a second transistor having a second gate electrode 52, and a third transistor having a third gate electrode 53. Further, each transistor can be driven independently. With this configuration, the turn-on loss and turn-off loss of the IGBT100 can be reduced.

At time T1, the first transistor having the first gate electrode 51, the second transistor having the second gate electrode 52, and the third transistor having the third gate electrode 53 are all turned on. In the transistor region 101, electrons are injected from the emitter region 29 to the drift region 27 when all of the first transistor having the first gate electrode 51, the second transistor having the second gate electrode 52, and the third transistor having the third gate electrode 53 are in an on state. In response, holes are injected from the collector region 26 into the drift region 27.

For example, compared with the case where the third transistor having the third gate electrode 53 is not provided, the amount of electrons injected from the emitter region 29 to the drift region 27 increases. Thus, the on-time of the IGBT100 can be shortened. This reduces the turn-on loss of the IGBT 100.

At time T2, the third transistor having the third gate electrode 53 is turned off. At time T2, the injection of electrons into the drift region 27 based on the third transistor having the third gate electrode 53 is stopped. After time T2, the third transistor having the third gate electrode 53 functions as a dummy gate (a dock).

By stopping the injection of electrons to the drift region 27 based on the third transistor having the third gate electrode 53, the carrier density on the emitter region 29 side of the drift region 27 is reduced. Thus, the saturation current of the IGBT100 can be suppressed. This improves the short-circuit resistance of the IGBT100, for example.

At time T3, the second transistor having the second gate electrode 52 is turned off. Thereafter, at time T4, the first transistor having the first gate electrode 51 is turned off. At time T4, IGBT100 turns off.

At time T3, the carrier density of drift region 27 decreases by turning off the second transistor having second gate electrode 52. Therefore, after the first transistor having the first gate electrode 51 is turned off, the amount of carriers to be discharged decreases.

Thus, the turn-off time of the IGBT100 can be shortened. Thereby, the turn-off loss of the IGBT100 is reduced.

Particularly, when the second off voltage (Voff 2) applied to the second gate electrode 52 is a negative voltage, a p-type inversion layer is formed in the drift region 27 contacting the second gate insulating film 42. Accordingly, the discharge of holes from the drift region 27 to the emitter electrode 12 is promoted until time T4, and after the first transistor having the first gate electrode 51 is turned off, the amount of carriers to be discharged is further reduced. Thereby, the turn-off loss of the IGBT100 is further reduced.

The thickness (t 3 in fig. 5) of the third portion 28c of the base region 28 of the IGBT100 of the first embodiment is thinner than the thickness (t 1 in fig. 5) of the first portion 28a in the third direction. Thus, the channel length of the third transistor having the third gate electrode 53 is shorter than that of the first transistor having the first gate electrode 51. Thus, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower than the threshold voltage of the first transistor having the first gate electrode 51 due to the short channel effect.

Further, the thickness (t 3 in fig. 5) of the third portion 28c of the base region 28 of the IGBT100 of the first embodiment is thinner than the thickness (t 2 in fig. 5) of the second portion 28b in the third direction. Thus, the channel length of the third transistor having the third gate electrode 53 is shorter than that of the second transistor having the second gate electrode 52. Thus, the threshold voltage of the second transistor having the second gate electrode 52 becomes lower than that of the second transistor having the second gate electrode 52 due to the short channel effect.

The threshold voltage of the third transistor having the third gate electrode 53 is lower than the threshold voltage of the first transistor having the first gate electrode 51 and the threshold voltage of the second transistor having the second gate electrode 52. Therefore, for example, at time T1, when the on voltage is applied to the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 at the same time, the third transistor having the third gate electrode 53 starts the on operation quickly. Thus, the amount of electrons injected into the drift region 27 increases rapidly. Thus, the on-time of the IGBT100 can be further shortened. Thereby, the turn-on loss of the IGBT100 is further reduced.

From the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53, the thickness t3 of the third portion 28c in the third direction is preferably 70% or less, more preferably 50% or less of the thickness t1 of the first portion 28a in the third direction. From the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53, the thickness t3 of the third portion 28c in the third direction is preferably 70% or less, more preferably 50% or less, of the thickness t2 of the second portion 28b in the third direction.

(modification)

Fig. 7 is an enlarged schematic cross-sectional view of a part of a semiconductor device according to a modification of the first embodiment. Fig. 7 is a view corresponding to fig. 5 of the first embodiment.

The semiconductor device according to the modification of the first embodiment is an IGBT101. The IGBT101 according to the modification differs from the IGBT100 according to the first embodiment in the following points: that is, the n-type impurity concentration from the sixth portion 31c of the barrier region 31 is higher than the n-type impurity concentration of the fourth portion 31a, and the n-type impurity concentration of the sixth portion 31c is higher than the n-type impurity concentration of the fifth portion 31 b.

The n-type impurity concentration of the sixth portion 31c is, for example, 120% or more and 200% or less of the n-type impurity concentration of the fourth portion 31 a. The n-type impurity concentration of the fifth portion 31b is, for example, 120% or more and 200% or less of the n-type impurity concentration of the fourth portion 31 a.

By the case where the n-type impurity concentration of the sixth portion 31c is higher than that of the fourth portion 31a, the threshold voltage of the third transistor having the third gate electrode 53 becomes further lower than that of the first transistor having the first gate electrode 51 due to the short channel effect. Further, by the case where the n-type impurity concentration of the sixth portion 31c is higher than that of the fifth portion 31b, the threshold voltage of the third transistor having the third gate electrode 53 becomes further lower than that of the second transistor having the second gate electrode 52 due to the short channel effect.

The third transistor with the third gate electrode 53 further rapidly starts the turn-on action. Thus, the amount of electrons injected into the drift region 27 further increases rapidly. Thus, the on-time of the IGBT101 can be further shortened. Thereby, the turn-on loss of the IGBT101 is further reduced.

As described above, according to the first embodiment and the modification, a semiconductor device and a semiconductor circuit in which the switching loss can be reduced can be realized.

(second embodiment)

The semiconductor device and the semiconductor circuit according to the second embodiment are different from those according to the first embodiment in the following points: that is, the at least one third groove comprises an adjacent pair of third grooves, the third portion being located between the pair of third grooves. Hereinafter, the description of the parts may be omitted for the contents overlapping with those of the first embodiment.

The semiconductor device of the second embodiment is an IGBT200. The IGBT200 is a trench gate type IGBT including a gate electrode among trenches formed in a semiconductor layer. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The control circuit of the second embodiment is a gate driver circuit 150. The semiconductor circuit of the second embodiment is constituted by a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor component mounted with the IGBT200 and the gate driver circuit 150.

Fig. 8 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 8 is a view corresponding to fig. 2 of the first embodiment.

The IGBT200 of the second embodiment includes: the semiconductor layer 10, the emitter electrode 12 (first electrode), the collector electrode 14 (second electrode), the first gate insulating film 41, the second gate insulating film 42, the third gate insulating film 43, the first gate electrode 51, the second gate electrode 52, the third gate electrode 53, the interlayer insulating layer 61, the first gate electrode pad 104 (first electrode pad), the second gate electrode pad 105 (second electrode pad), and the third gate electrode pad 106 (third electrode pad).

A first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region) are provided in the semiconductor layer 10.

The IGBT200 of the second embodiment includes a pair of third gate trenches 23 adjacent in the second direction. The first gate trench 21 and the second gate trench 22 are not present between the adjacent pair of third gate trenches 23.

Fig. 9 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 9 is an enlarged view of a portion of fig. 8. Fig. 9 is a view corresponding to fig. 5 of the first embodiment.

As shown in fig. 9, the base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

The first portion 28a is the portion of the base region 28 that meets the first gate trench 21. The first portion 28a is in contact with the first gate insulating film 41. The first portion 28a is opposite to the first gate electrode 51.

The second portion 28b is the portion of the base region 28 that meets the second gate trench 22. The second portion 28b is in contact with the second gate insulating film 42. The second portion 28b is opposite the second gate electrode 52.

The third portion 28c is the portion of the base region 28 that meets the third gate trench 23. The third portion 28c is in contact with the third gate insulating film 43. The third portion 28c is opposite to the third gate electrode 53.

The third portion 28c is provided between a pair of third gate trenches 23 adjacent in the second direction.

The thickness (t 3 in fig. 9) of the third portion 28c in the third direction is thinner than the thickness (t 1 in fig. 9) of the first portion 28a in the third direction. The thickness t3 of the third portion 28c in the third direction is, for example, 20% or more and 70% or less of the thickness t1 of the first portion 28a in the third direction.

Further, the thickness (t 3 in fig. 9) of the third portion 28c in the third direction is thinner than the thickness (t 2 in fig. 9) of the second portion 28b in the third direction. The thickness t3 of the third portion 28c in the third direction is, for example, 20% or more and 70% or less of the thickness t2 of the second portion 28b in the third direction.

As shown in fig. 9, the barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

The fourth portion 31a is a portion of the barrier region 31 that meets the first gate trench 21. The fourth portion 31a is in contact with the first gate insulating film 41. The fourth portion 31a is opposite to the first gate electrode 51. The fourth portion 31a is provided between the drift region 27 and the first portion 28 a.

The fifth portion 31b is a portion of the barrier region 31 that meets the second gate trench 22. The fifth portion 31b is in contact with the second gate insulating film 42. The fifth portion 31b is opposite to the second gate electrode 52. The fifth portion 31b is provided between the drift region 27 and the second portion 28 b.

The sixth portion 31c is a portion of the barrier region 31 that meets the third gate trench 23. The sixth portion 31c is in contact with the third gate insulating film 43. The sixth portion 31c is opposite to the third gate electrode 53. The sixth portion 31c is provided between the drift region 27 and the third portion 28 c.

The thickness (t 6 in fig. 9) of the sixth portion 31c in the third direction is thicker than the thickness (t 4 in fig. 9) of the fourth portion 31a in the third direction. The thickness t6 of the sixth portion 31c in the third direction is, for example, 150% or more of the thickness t6 of the fourth portion 31a in the third direction.

Further, the thickness (t 6 in fig. 9) of the sixth portion 31c in the third direction is thicker than the thickness (t 5 in fig. 9) of the fifth portion 31b in the third direction. The thickness t6 of the sixth portion 31c in the third direction is, for example, 150% or more of the thickness t5 of the fifth portion 31b in the third direction.

The IGBT200 of the second embodiment reduces switching losses by the same operation as the IGBT100 of the first embodiment.

In addition, in the IGBT200 of the second embodiment, compared to the IGBT100 of the first embodiment, the density of the third gate trenches 23 in the first surface F1 is higher than the density of the first gate trenches 21 and the density of the second gate trenches 22. Thus, the injection amount of electrons at the time of turn-on of the IGBT200 becomes further larger than that of the IGBT 100. Thereby, the turn-on loss is further reduced.

As described above, according to the second embodiment, a semiconductor device and a semiconductor circuit which can reduce switching loss can be realized.

(third embodiment)

The semiconductor device of the third embodiment includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a first trench provided on a first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode disposed in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode. The third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, wherein a first conductivity type impurity concentration of the third portion is lower than a first conductivity type impurity concentration of the first portion, and a first conductivity type impurity concentration of the third portion is lower than a first conductivity type impurity concentration of the second portion.

The semiconductor circuit of the third embodiment includes a control circuit for driving the semiconductor device.

The semiconductor device and the semiconductor circuit according to the third embodiment are different from those according to the first embodiment in the following points: that is, the first-conductivity-type impurity concentration of the third portion is lower than the first-conductivity-type impurity concentration of the first portion, and the first-conductivity-type impurity concentration of the third portion is lower than the first-conductivity-type impurity concentration of the second portion. Hereinafter, description of the contents overlapping with those of the first embodiment may be omitted.

The semiconductor device of the third embodiment is an IGBT300. The IGBT300 is a trench gate type IGBT including a gate electrode among trenches formed in a semiconductor layer. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The control circuit of the third embodiment is a gate driver circuit 150. The semiconductor circuit of the third embodiment is constituted by a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor component mounted with the IGBT300 and the gate driver circuit 150.

Fig. 10 is a schematic cross-sectional view of a part of a semiconductor device of the third embodiment. Fig. 10 is a view corresponding to fig. 2 of the first embodiment.

The IGBT300 according to the third embodiment includes: the semiconductor layer 10, the emitter electrode 12 (first electrode), the collector electrode 14 (second electrode), the first gate insulating film 41, the second gate insulating film 42, the third gate insulating film 43, the first gate electrode 51, the second gate electrode 52, the third gate electrode 53, the interlayer insulating layer 61, the first gate electrode pad 104 (first electrode pad), the second gate electrode pad 105 (second electrode pad), and the third gate electrode pad 106 (third electrode pad).

The base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

Fig. 11 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Fig. 11 is an enlarged view of a portion of fig. 10. Fig. 11 is a view corresponding to fig. 5 of the first embodiment.

As shown in fig. 11, the base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

The third portion 28c has a p-type impurity concentration lower than that of the first portion 28 a. The p-type impurity concentration of the third portion 28c is, for example, 50% or more and 80% or less of the p-type impurity concentration of the first portion 28 a.

Further, the third portion 28c has a p-type impurity concentration lower than that of the second portion 28 b. The p-type impurity concentration of the third portion 28c is, for example, 50% or more and 80% or less of the p-type impurity concentration of the second portion 28 b.

The p-type impurity concentration of the third portion 28c of the IGBT300 of the third embodiment is lower than that of the first portion 28 a. Thus, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower than the threshold voltage of the first transistor having the first gate electrode 51.

Further, the p-type impurity concentration of the third portion 28c of the IGBT300 of the third embodiment is lower than that of the second portion 28 b. Thus, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower than the threshold voltage of the second transistor having the second gate electrode 52.

The threshold voltage of the third transistor having the third gate electrode 53 becomes lower than the threshold voltage of the first transistor having the first gate electrode 51 and the threshold voltage of the second transistor having the second gate electrode 52. Therefore, for example, at time T1 in fig. 6, when the on voltage is applied to the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 at the same time, the third transistor having the third gate electrode 53 starts the on operation quickly. Thus, the amount of electrons injected into the drift region 27 increases rapidly. Thus, the on-time of the IGBT300 can be shortened. Thus, the turn-on loss of the IGBT300 is reduced.

The p-type impurity concentration of the third portion 28c is preferably 80% or less of the p-type impurity concentration of the second portion 28b from the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53. The p-type impurity concentration of the third portion 28c is preferably 80% or less of the p-type impurity concentration of the second portion 28b from the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53.

As described above, according to the third embodiment, a semiconductor device and a semiconductor circuit which can reduce switching loss can be realized.

(fourth embodiment)

The semiconductor device of the fourth embodiment includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a fifth semiconductor region of the second conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the third semiconductor region, and having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region; a first trench provided on a first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, between the first gate electrode and the fourth semiconductor region, and between the first gate electrode and the fifth semiconductor region; a second trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a second gate electrode disposed in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, between the second gate electrode and the fourth semiconductor region, and between the second gate electrode and the fifth semiconductor region; at least one third trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, between the third gate electrode and the fourth semiconductor region, and between the third gate electrode and the fifth semiconductor region; a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode. The fifth semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, wherein a second conductivity type impurity concentration of the third portion is higher than a second conductivity type impurity concentration of the first portion, and a second conductivity type impurity concentration of the third portion is higher than a second conductivity type impurity concentration of the second portion.

The semiconductor circuit of the fourth embodiment includes a control circuit for driving the semiconductor device.

The semiconductor device and the semiconductor circuit according to the fourth embodiment are different from those according to the first embodiment in the following points: that is, the fifth semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, the third portion having a second conductivity type impurity concentration higher than that of the first portion, and the third portion having a second conductivity type impurity concentration higher than that of the second portion. Hereinafter, description of the contents overlapping with those of the first embodiment may be omitted.

The semiconductor device of the fourth embodiment is an IGBT400. The IGBT400 is a trench gate type IGBT including a gate electrode among trenches formed in a semiconductor layer. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The control circuit of the fourth embodiment is a gate driver circuit 150. The semiconductor circuit of the fourth embodiment is constituted by a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor component mounted with the IGBT400 and the gate driver circuit 150.

Fig. 12 is a schematic cross-sectional view of a part of a semiconductor device of the fourth embodiment. Fig. 12 is a view corresponding to fig. 2 of the first embodiment.

The IGBT400 according to the fourth embodiment includes: the semiconductor layer 10, the emitter electrode 12 (first electrode), the collector electrode 14 (second electrode), the first gate insulating film 41, the second gate insulating film 42, the third gate insulating film 43, the first gate electrode 51, the second gate electrode 52, the third gate electrode 53, the interlayer insulating layer 61, the first gate electrode pad 104 (first electrode pad), the second gate electrode pad 105 (second electrode pad), and the third gate electrode pad 106 (third electrode pad).

The barrier region 31 includes a first low-concentration portion 31x (first portion), a second low-concentration portion 31y (second portion), and a high-concentration portion 31z (third portion).

Fig. 13 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the fourth embodiment. Fig. 13 is an enlarged view of a portion of fig. 12.

As shown in fig. 13, the barrier region 31 includes a first low-concentration portion 31x, a second low-concentration portion 31y, and a high-concentration portion 31z.

The first low concentration portion 31x is a portion of the barrier region 31 that meets the first gate trench 21. The first low concentration portion 31x is in contact with the first gate insulating film 41. The first low concentration portion 31x is opposed to the first gate electrode 51.

The second low concentration portion 31y is a portion of the barrier region 31 that meets the second gate trench 22. The second low concentration portion 31y is in contact with the second gate insulating film 42. The second low concentration portion 31y is opposed to the second gate electrode 52.

The high concentration portion 31z is a portion of the barrier region 31 that meets the third gate trench 23. The high concentration portion 31z is in contact with the third gate insulating film 43. The high concentration portion 31z is opposed to the third gate electrode 53.

The n-type impurity concentration of the high concentration portion 31z is higher than that of the first low concentration portion 31 x. The n-type impurity concentration of the high concentration portion 31z is, for example, 120% or more and 200% or less of the n-type impurity concentration of the first low concentration portion 31 x.

The n-type impurity concentration of the high concentration portion 31z is higher than that of the second low concentration portion 31 y. The n-type impurity concentration of the high concentration portion 31z is, for example, 120% or more and 200% or less of the n-type impurity concentration of the second low concentration portion 31 y.

By the case where the n-type impurity concentration of the high concentration portion 31z is higher than that of the first low concentration portion 31x, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower than that of the first transistor having the first gate electrode 51 due to the short channel effect. Further, by the case where the n-type impurity concentration of the high concentration portion 31z is higher than that of the second low concentration portion 31y, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower than that of the second transistor having the second gate electrode 52 due to the short channel effect.

Therefore, at the time of the turn-on operation of the IGBT400, the third transistor having the third gate electrode 53 rapidly starts the turn-on operation. Thus, the amount of electrons injected into the drift region 27 increases rapidly. Thus, the on-time of the IGBT400 can be shortened. This reduces the turn-on loss of the IGBT 400.

As described above, according to the fourth embodiment, a semiconductor device and a semiconductor circuit that can reduce switching loss can be realized.

(fifth embodiment)

The semiconductor device of the fifth embodiment includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a first trench provided on a first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode disposed in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode. Further, the transistor includes a first transistor having a first gate electrode, a second transistor having a second gate electrode, and a third transistor having a third gate electrode, a threshold voltage of the third transistor is lower than that of the first transistor, and a threshold voltage of the third transistor is lower than that of the second transistor.

The semiconductor circuit of the fifth embodiment includes a control circuit for driving the semiconductor device.

The semiconductor device of the fifth embodiment is an IGBT500. The IGBT500 is a trench gate type IGBT including a gate electrode among trenches formed in a semiconductor layer. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The control circuit of the fifth embodiment is the same as the gate driver circuit 150 of the first embodiment. The semiconductor circuit of the fifth embodiment is constituted by a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor component mounted with the IGBT500 and the gate driver circuit 150.

Fig. 15 is a schematic top view of a part of a semiconductor device of the fifth embodiment. Fig. 15 is a plan view of the first surface F1. Fig. 14 is a CC' section of fig. 15.

Fig. 16 is a schematic cross-sectional view of a part of a semiconductor device of the fifth embodiment. Fig. 16 is a DD' section of fig. 15.

The IGBT500 of the fifth embodiment includes: the semiconductor layer 10, the emitter electrode 12 (first electrode), the collector electrode 14 (second electrode), the first gate insulating film 41, the second gate insulating film 42, the third gate insulating film 43, the first gate electrode 51, the second gate electrode 52, the third gate electrode 53, the interlayer insulating layer 61, the first gate electrode pad 104 (first electrode pad), the second gate electrode pad 105 (second electrode pad), and the third gate electrode pad 106 (third electrode pad).

The direction parallel to the first surface F1 is referred to as a first direction. The direction parallel to the first surface F1 and orthogonal to the first direction is referred to as a second direction. The direction from the first surface F1 toward the second surface F2 is referred to as a third direction.

Further, "depth" is defined as a distance in a direction toward the second surface F2 with reference to the first surface F1.

Collector region 26 is p ⁺ A semiconductor region of the type. The collector region 26 meets the second face F2. The collector region 26 is electrically connected to the collector electrode 14. The collector region 26 is connected to the collector electrode 14. The collector region 26 serves as a source of holes in the on state of the IGBT 500.

Drift region 27 is n ^- A semiconductor region of the type. The drift region 27 is provided between the collector region 26 and the first surface F1.

The drift region 27 serves as a path for an on current in the on state of the IGBT 500. The drift region 27 has a function of depleting the IGBT500 in the off state and maintaining the withstand voltage of the IGBT 500.

The depth of the base region 28 is, for example, 5 μm or less. In the on state of the IGBT500, an n-type inversion layer is formed in the region of the base region 28 facing the first gate electrode 51, the region of the base region 28 facing the second gate electrode 52, and the region of the base region 28 facing the third gate electrode 53. The base region 28 functions as a channel region of the transistor.

The barrier region 31 has a function of increasing the carrier accumulation amount of the drift region 27 in the on state of the IGBT 500. By providing the barrier region 31, the on-resistance of the IGBT500 is reduced, and the steady loss of the IGBT500 is reduced.

The emitter region 29 is in contact with the emitter electrode 12. The emitter region 29 is electrically connected to the emitter electrode 12. The emitter region 29 serves as a supply source of electrons in the on state of the IGBT 500.

As shown in fig. 15, the first gate trench 21 extends in the first plane F1 in a first direction parallel to the first plane F1. The first gate trench 21 has a stripe shape. The plurality of first gate trenches 21 are repeatedly arranged in a second direction orthogonal to the first direction.

As shown in fig. 15, the second gate trench 22 extends in the first direction parallel to the first face F1 at the first face F1. The second gate trench 22 has a stripe shape. The plurality of second gate trenches 22 are repeatedly arranged in a second direction orthogonal to the first direction.

The second gate electrode 52 is disposed in the second gate trench 22. The second gate electrode 52 is, for example, a semiconductor or a metal. The second gate electrode 52 contains, for example, n-type impurity or p-type impurity, and is amorphous silicon or polysilicon. The second gate electrode 52 is electrically connected to the second gate electrode pad 105.

As shown in fig. 15, the third gate trench 23 extends in the first direction parallel to the first face F1 at the first face F1. The third gate trench 23 has a stripe shape. The plurality of third gate trenches 23 are repeatedly arranged in a second direction orthogonal to the first direction.

The IGBT500 of the fifth embodiment includes a first transistor having a first gate electrode 51, a second transistor having a second gate electrode 52, and a third transistor having a third gate electrode 53.

The first transistor having the first gate electrode 51 is a transistor driven using the first gate electrode 51. The first transistor includes a first gate electrode 51, a first gate insulating film 41, a base region 28, an emitter region 29, and a barrier region 31, which face the first gate electrode 51. The base region 28 opposite the first gate electrode 51 becomes the channel region of the first transistor. The portions of the emitter region 29 and the barrier region 31 that contact the first gate insulating film 41 serve as source and drain regions of the first transistor.

The second transistor having the second gate electrode 52 is a transistor driven using the second gate electrode 52. The second transistor includes a second gate electrode 52, a second gate insulating film 42, a base region 28, an emitter region 29, and a barrier region 31, which face the second gate electrode 52. The base region 28 opposite the second gate electrode 52 becomes the channel region of the second transistor. The emitter region 29 and the barrier region 31 are connected to the second gate insulating film 42, and serve as source and drain regions of the second transistor.

The third transistor having the third gate electrode 53 is a transistor driven using the third gate electrode 53. The third transistor includes the third gate electrode 53, the third gate insulating film 43, the base region 28, the emitter region 29, and the barrier region 31, which face the third gate electrode 53. The base region 28 opposite the third gate electrode 53 becomes the channel region of the third transistor. The emitter region 29 and the barrier region 31 are connected to the third gate insulating film 43, and serve as source and drain regions of the third transistor.

In the IGBT500 of the fifth embodiment, the threshold voltage of the third transistor is lower than the threshold voltage of the first transistor, and the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

For example, the third gate insulating film 43 of the third transistor has a smaller film thickness than the first gate insulating film 41 of the first transistor. Further, the third gate insulating film 43 of the third transistor is thinner in film thickness than the second gate insulating film 42 of the second transistor. The threshold voltage of the third transistor becomes low by the thin film thickness of the third gate insulating film 43 of the third transistor.

Further, for example, the dielectric constant of the third gate insulating film 43 of the third transistor is higher than the dielectric constant of the first gate insulating film 41 of the first transistor. Further, the dielectric constant of the third gate insulating film 43 of the third transistor is higher than that of the second gate insulating film 42 of the second transistor. By the fact that the dielectric constant of the third gate insulating film 43 of the third transistor is high, the threshold voltage of the third transistor becomes low.

Further, for example, the work function of the third gate electrode 53 of the third transistor is different from the work function of the first gate electrode 51 of the first transistor. Further, the work function of the third gate electrode 53 of the third transistor is different from the work function of the second gate electrode 52 of the second transistor. By the case where the work functions of the third gate electrodes 53 of the third transistors are different, the threshold voltages of the third transistors become low.

For example, the p-type impurity concentration of the base region 28 of the third transistor facing the third gate electrode 53 is lower than the p-type impurity concentration of the base region 28 of the first transistor facing the first gate electrode 51. The base region 28 of the third transistor facing the third gate electrode 53 has a p-type impurity concentration lower than that of the base region 28 of the second transistor facing the second gate electrode 52. By the fact that the p-type impurity concentration of the base region 28 of the third transistor facing the third gate electrode 53 is low, the threshold voltage of the third transistor becomes low.

Next, the operation and effects of the semiconductor device and the semiconductor circuit according to the fifth embodiment will be described.

The IGBT500 of the fifth embodiment operates by the same driving method as the IGBT100 of the first embodiment.

Like the IGBT100 of the first embodiment, the IGBT500 of the fifth embodiment includes, in the transistor region 101: a first transistor having a first gate electrode 51, a second transistor having a second gate electrode 52, and a third transistor having a third gate electrode 53. Further, each transistor can be driven independently. With this configuration, the turn-on loss and turn-off loss of the IGBT500 can be reduced.

The threshold voltage of the third transistor of the IGBT500 of the fifth embodiment is lower than the threshold voltage of the first transistor, and the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

The threshold voltage of the third transistor of the IGBT500 of the fifth embodiment becomes lower than the threshold voltage of the first transistor and the threshold voltage of the second transistor. Therefore, for example, at time T1 in fig. 6, when the on voltage is applied to the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 at the same time, the third transistor having the third gate electrode 53 starts the on operation quickly. Thus, the amount of electrons injected into the drift region 27 increases rapidly. Thus, the on-time of the IGBT500 can be further shortened. Thereby, the turn-on loss of the IGBT500 is further reduced.

As described above, according to the fifth embodiment, a semiconductor device and a semiconductor circuit which can reduce switching loss can be realized.

In the first to fifth embodiments, the case where the semiconductor layer is single crystal silicon is described as an example, but the semiconductor layer is not limited to single crystal silicon. For example, single crystal silicon carbide and other single crystal semiconductors may be used.

In the first to fifth embodiments, the case where the semiconductor device includes the first gate trench, the second gate trench, and the third gate trench is described as an example, but the potential of the conductive layer in the trench may be, for example, a dummy trench in which a fixed potential or a floating potential is further set.

In the first to fifth embodiments, the case of stripe shapes in which grooves are arranged in parallel was described as an example, but the present invention can also be applied to grid-shaped grooves or dot-shaped grooves in which grooves intersect.

In the first to fifth embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type has been described as an example, but the first conductivity type may be n-type and the second conductivity type may be p-type.

While the present invention has been described with reference to several embodiments, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other modes, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. For example, the constituent elements of one embodiment may be replaced or modified with those of another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device is characterized by comprising:

a semiconductor layer having a first surface and a second surface opposite to the first surface;

A first semiconductor region of a first conductivity type provided in the semiconductor layer;

a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface;

a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface;

a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface;

a first trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region;

a first gate electrode disposed in the first trench;

a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region;

a second trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region;

A second gate electrode disposed in the second trench;

a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region;

at least one third trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region;

a third gate electrode disposed in the at least one third trench;

a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region;

a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region;

a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region;

a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode;

A second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and

a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode,

the third semiconductor region includes a first portion contiguous with the first trench, a second portion contiguous with the second trench, and a third portion contiguous with the at least one third trench,

the thickness of the third portion in a direction from the first face toward the second face is thinner than the thickness of the first portion in the direction,

the third portion has a thickness in a direction from the first face toward the second face that is thinner than a thickness in the direction of the second portion.

2. The semiconductor device according to claim 1, wherein,

a fifth semiconductor region of a second conductivity type provided in the semiconductor layer and between the second semiconductor region and the third semiconductor region, the second conductivity type impurity concentration being higher than the second conductivity type impurity concentration of the second semiconductor region,

the fifth semiconductor region includes: a fourth portion connected to the first trench and provided between the second semiconductor region and the first portion; a fifth portion connected to the second trench and provided between the second semiconductor region and the second portion; and a sixth portion contiguous with the at least one third trench and disposed between the second semiconductor region and the third portion,

The thickness of the sixth portion in the direction from the first face toward the second face is thicker than the thickness of the fourth portion in the direction,

the thickness of the sixth portion in a direction from the first face toward the second face is thicker than the thickness of the fifth portion in the direction.

3. The semiconductor device according to claim 1, wherein,

the second conductive type impurity concentration of the sixth portion is higher than the second conductive type impurity concentration of the fourth portion, and the second conductive type impurity concentration of the sixth portion is higher than the second conductive type impurity concentration of the fifth portion.

4. The semiconductor device according to claim 1, wherein,

the at least one third groove includes an adjacent pair of third grooves, the third portion being located between the pair of third grooves.

5. The semiconductor device according to claim 1, wherein,

the thickness of the third portion in a direction from the first face toward the second face is 70% or less of the thickness of the first portion in the direction,

the thickness of the third portion in a direction from the first face toward the second face is 70% or less of the thickness of the second portion in the direction.

6. A semiconductor device is characterized by comprising:

a first gate electrode disposed in the first trench;

a second gate electrode disposed in the second trench;

a third gate electrode disposed in the at least one third trench;

the third portion has a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first portion,

the third portion has a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the second portion.

7. The semiconductor device according to claim 6, wherein,

the first conductivity type impurity concentration of the third portion is 80% or less of the first conductivity type impurity concentration of the first portion,

the first conductivity type impurity concentration of the third portion is 80% or less of the first conductivity type impurity concentration of the second portion.

8. A semiconductor device is characterized by comprising:

a fifth semiconductor region of a second conductivity type provided in the semiconductor layer and between the second semiconductor region and the third semiconductor region, and having a second conductivity type impurity concentration higher than that of the second semiconductor region;

a first trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region;

a first gate electrode disposed in the first trench;

a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, between the first gate electrode and the fourth semiconductor region, and between the first gate electrode and the fifth semiconductor region;

A second trench provided on the first surface side of the semiconductor layer and connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region;

a second gate electrode disposed in the second trench;

a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, between the second gate electrode and the fourth semiconductor region, and between the second gate electrode and the fifth semiconductor region;

at least one third trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region;

a third gate electrode disposed in the at least one third trench;

a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, between the third gate electrode and the fourth semiconductor region, and between the third gate electrode and the fifth semiconductor region;

the fifth semiconductor region includes a first portion contiguous with the first trench, a second portion contiguous with the second trench, and a third portion contiguous with the at least one third trench,

the third portion has a second conductivity type impurity concentration higher than that of the first portion, and the third portion has a second conductivity type impurity concentration higher than that of the second portion.

9. A semiconductor device is characterized by comprising:

a first gate electrode disposed in the first trench;

a second gate electrode disposed in the second trench;

a third gate electrode disposed in the at least one third trench;

the semiconductor device includes a first transistor having the first gate electrode, a second transistor having the second gate electrode, and a third transistor having the third gate electrode,

the threshold voltage of the third transistor is lower than the threshold voltage of the first transistor,

the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

10. The semiconductor device according to any one of claims 1 to 9, wherein,

a first turn-on voltage is applied to the first electrode pad,

a second turn-on voltage is applied to the second electrode pad,

A third turn-on voltage is applied to the third electrode pad,

applying a third turn-off voltage to the third electrode pad after applying the first turn-on voltage to the first electrode pad, applying the second turn-on voltage to the second electrode pad, and applying the third turn-on voltage to the third electrode pad,

after the third off-voltage is applied to the third electrode pad, a second off-voltage is applied to the second electrode pad,

after a second off voltage is applied to the second electrode pad, a first off voltage is applied to the first electrode pad.

11. A semiconductor circuit is characterized by comprising:

the semiconductor device according to any one of claims 1 to 9; and

a control circuit that drives the semiconductor device, applies a first on voltage to the first electrode pad, applies a second on voltage to the second electrode pad, applies a third on voltage to the third electrode pad, applies the first on voltage to the first electrode pad, applies the second on voltage to the second electrode pad, applies the third on voltage to the third electrode pad, applies a third off voltage to the third electrode pad, applies the third off voltage to the third electrode pad, applies a second off voltage to the second electrode pad, and applies the first off voltage to the first electrode pad after applying the second off voltage to the second electrode pad.