CN116825779A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN116825779A CN116825779A CN202310968066.9A CN202310968066A CN116825779A CN 116825779 A CN116825779 A CN 116825779A CN 202310968066 A CN202310968066 A CN 202310968066A CN 116825779 A CN116825779 A CN 116825779A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 69
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
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- 239000010936 titanium Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
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- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 3
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
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- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 3
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- 239000011593 sulfur Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 3
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- 239000004408 titanium dioxide Substances 0.000 claims description 3
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Abstract
Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes: a transistor; an interconnect line, at least a portion of which is connected to the transistor; a capacitor comprising a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
In the semiconductor manufacturing process, a technique such as high density Plasma enhanced chemical vapor deposition (High Density Plasma Enhanced Chemical Vapor Deposition, HDPECVD) or Plasma Etching (Plasma Etching) is generally required. In theory, the external electrical property of the plasma is neutral, that is, the positive ions and the negative ions are equal, but because the plasma is unevenly distributed, the positive ions and the negative ions actually entering the semiconductor structure are not equal in a local area, and thus a large amount of free charges are generated. The surface of conductors (e.g., metal interconnect lines) in a semiconductor structure may collect free charges, and the accumulation of these free charges may form leakage currents, which may seriously even lead to device failure, thereby affecting the reliability of the chip and reducing the lifetime of the chip. This condition is commonly referred to as plasma induced damage (Plasma Induced Damage, PID), also known as antenna effect (Process Antenna Effect, PAE).
Accordingly, there is a need for improvements in semiconductor structures and methods of fabricating the same to reduce plasma-induced damage.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.
In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:
in a first aspect, embodiments of the present disclosure provide a semiconductor structure comprising:
a transistor;
an interconnect line, at least a portion of which is connected to the transistor;
a capacitor comprising a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer.
In some embodiments, at least a portion of the interconnect line is electrically connected to a gate, source, or drain of the transistor.
In some embodiments, the material of the first electrode comprises at least one of: monocrystalline silicon, polycrystalline silicon, and amorphous silicon;
the material of the dielectric layer comprises at least one of the following: hafnium oxide HfO 2 Zirconium dioxide ZrO 2 Strontium titanate SrTiO 3 And titanium dioxide TiO 2 。
In some embodiments, the material of the first electrode comprises: gallium arsenide, gaAs;
the material of the dielectric layer comprises: silicon dioxide SiO 2 。
In some embodiments, the material of the first electrode comprises at least one of: gold Au, silver Ag, platinum Pt, molybdenum Mo, copper Cu, aluminum Al, tungsten W, and nickel Ni;
the material of the dielectric layer has MX 2 Wherein M is selected from at least one of the following groups: titanium Ti, vanadium V, tantalum Ta, molybdenum Mo, tungsten W, rhenium Re; x is selected from at least one of the following groups: sulfur S, selenium Se and tellurium Te.
In some embodiments, the semiconductor structure includes a memory chip region and a scribe line region surrounding the memory chip region; the memory chip region is used for forming a memory chip, the dicing channel region is used for forming a test element group, and the transistor is located in the test element group.
In some embodiments, the plasma charges transferred in the interconnect lines include plasma charges generated in a memory chip fabrication process; the memory chip manufacturing process is used for forming the memory chip; the memory chip is connected with the interconnection line.
In some embodiments, the memory chip fabrication process uses a plasma etch process in which plasma charges are generated, the plasma charges being transferred by the memory chip to the interconnect lines.
In some embodiments, the transistor comprises an N-type metal-oxide-semiconductor transistor.
In a second aspect, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method comprising:
forming a transistor;
forming an interconnection line, at least part of which is connected with the transistor;
forming a capacitor, wherein the capacitor comprises a first electrode, a second electrode and a dielectric layer positioned between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer.
Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes: a transistor; an interconnect line, at least a portion of which is connected to the transistor; a capacitor comprising a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer. In the embodiment of the disclosure, the first electrode of the capacitor is connected with the transistor, and at least part of the interconnection line is also connected with the transistor, and the Fermi pinning layer formed at the contact interface between the first electrode of the capacitor and the dielectric layer can be used for adsorbing the plasma charges transmitted in the interconnection line, so that the plasma charges are prevented from flowing to the transistor, the plasma induced damage to the transistor caused by the plasma charges is reduced, and the performance of the transistor is finally improved.
Drawings
FIG. 1 is a schematic diagram of a transistor subjected to plasma induced damage;
FIG. 2 is a schematic diagram of a protection structure of a transistor;
fig. 3 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of the principle of Fermi pinning;
FIG. 5 is a schematic diagram II of the fermi pinning principle;
FIGS. 6A to 6C are schematic cross-sectional views illustrating the formation of the Fermi-pinning layer;
fig. 7 is a flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
Referring to fig. 1, fig. 1 is a schematic diagram of a transistor subjected to plasma-induced damage. As shown in fig. 1, the transistor 101 includes: a source 103 and a drain 104 provided in the substrate; a gate oxide layer 105 and a gate 102 are sequentially disposed over the substrate, with the gate 102 being located between the source 103 and the drain 104.
Illustratively, the transistor may include an N-type Metal-Oxide-Semiconductor Transisitor (NMOS transistor) and the corresponding substrate may include a P-well.
In the semiconductor manufacturing process, plasma is used in various processes such as ion implantation process, CVD process, and plasma etching process. A large amount of free charge generated in these processes may be collected by conductors (e.g., metal interconnect lines) in the semiconductor structure. The metal interconnection line may be connected to the gate of the transistor in the semiconductor structure, and charges in the metal interconnection line may flow to the transistor to form gate leakage current; when the accumulated free charge exceeds a certain amount, such gate leakage current may damage the gate oxide layer, resulting in breakdown of the gate oxide layer and thus failure of the transistor in the semiconductor structure.
It should be noted that the probability of the occurrence of the Antenna effect of the semiconductor structure can be measured by the Antenna Ratio (Antenna Ratio). The antenna ratio refers to the ratio between the area of a conductor (e.g., a metal interconnect line) and the area of a gate oxide layer connected thereto. With the development of semiconductor manufacturing process, the number of metal interconnection lines is increased, and the area of the gate oxide layer is reduced, so that the probability of antenna effect of the semiconductor structure is increased.
Referring to fig. 2, fig. 2 is a schematic diagram of a protection structure of a transistor. As shown in fig. 2, the semiconductor structure includes: a transistor 201 to be protected, the transistor 201 to be protected comprising a gate 202, a source 203, a drain 204 and a base 205; a Pad Diode (Pad Diode) 206 (shown in fig. 2 as a dashed box) connected to the transistor 201 to be protected; a protection Diode (protection Diode) 207 (shown as a solid line box in fig. 2) connected to the transistor 201 to be protected; and a protection capacitor 208, for example, a MOS capacitor, connected to the transistor 201 to be protected. The pad diode 206, the protection diode 207, and the protection capacitor 208 are used to reduce plasma-induced damage to the transistor 201 to be protected.
Note that, in fig. 2, only the relative positional relationship among the pad diode 206, the protection diode 207, the protection capacitor 208, and the transistor 201 to be protected is illustrated, and specific structures of the pad diode 206, the protection diode 207, and the protection capacitor 208 are not illustrated.
Illustratively, to reduce plasma damage caused by plasma charges to the transistor to be protected, i.e., to reduce antenna effects, the following method may be used:
the first method is called a "jumper method", which disconnects the metal interconnect line where antenna effect may occur, connects to other metal interconnect lines through a via hole (for example, connects to an upper metal interconnect line of the current metal interconnect line through an "upward jumper method", or connects to a lower metal interconnect line of the current metal interconnect line through a "downward jumper method"), and finally returns to the current metal interconnect line.
The second method is called "bleeder method", in which a reverse biased diode is connected to a metal interconnect line where an antenna effect may occur near the gate of the transistor to be protected, forming a charge bleeder path.
In a third method, a metal interconnect line where an antenna effect may occur is connected to a capacitor, such as the protection capacitor 208 illustrated in fig. 2, near the gate of the transistor to be protected. However, the capacitance may take up additional space in this approach.
In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.
Referring to fig. 3, fig. 3 is a schematic view of a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 3, an embodiment of the present disclosure provides a semiconductor structure including:
transistor 301 (shown in phantom in fig. 3);
an interconnection line 305, at least part of the interconnection line 305 being connected to the transistor 301;
a capacitor 306, the capacitor 306 comprising a first electrode 307, a second electrode 308, and a dielectric layer 309 between the first electrode 307 and the second electrode 308; the first electrode 307 is connected to the transistor 301, at least part of the interconnect line 305; wherein the contact interface of the first electrode 307 of the capacitor 306 and the dielectric layer 309 forms a fermi-pinning layer.
Here, the transistor refers to a transistor to be protected. The transistor to be protected may be a transistor at any location in the semiconductor structure, in particular a transistor that may be damaged by plasma induction.
Here, the types of transistors may include NMOS transistors or PMOS transistors, and the embodiments of the present disclosure are not particularly limited as to the types of transistors.
Here, the number of transistors may be one or more, and the number of transistors is not particularly limited in the embodiments of the present disclosure. Fig. 3 is merely an example of one transistor, and does not limit the scope of the present disclosure.
For example, a gate oxide layer and a gate electrode may be sequentially formed on a substrate, and a source electrode and a drain electrode may be respectively formed on both sides of the gate oxide layer and the gate electrode in the substrate. The material of the substrate may include, but is not limited to, silicon material, the material of the gate oxide layer may include, but is not limited to, silicon oxide, and the material of the gate electrode may include, but is not limited to, polysilicon or metal.
Illustratively, when the transistor is an NMOS transistor, P-type ions may be doped into the substrate to form a P-type well region, which may include, but are not limited to, boron ions, gallium ions, or indium ions; when the transistor is a PMOS transistor, N-type ions may be doped into the substrate to form an N-type well region, which may include, but are not limited to, phosphorus ions or arsenic ions.
Here, the interconnection line may be a single-layer or multi-layer stacked structure; wherein the interconnection lines of different layers in the multi-layer stack structure can be connected with each other. The number of layers of the interconnect line is not particularly limited in the embodiments of the present disclosure.
Illustratively, an underlying dielectric layer may be formed, in which underlying interconnect lines are formed; forming a top dielectric layer on the bottom dielectric layer, and forming a top interconnection line in the top dielectric layer; wherein, each dielectric layer is correspondingly formed with a layer of interconnecting wire. The bottom dielectric layer (or top dielectric layer) may be formed by a deposition process (e.g., HDPECVD), and the grooves may be formed in the bottom dielectric layer (or top dielectric layer) by an etching process (e.g., a plasma etching process), and a metal material may be deposited in the grooves to form bottom interconnection lines (top interconnection lines).
Here, the interconnection line may include a metal interconnection line. The material of the interconnection line is not particularly limited in the embodiments of the present disclosure.
Here, the contact interface of the first electrode of the capacitor and the dielectric layer may form a fermi-pinning layer. The first electrode of the capacitor is electrically connected with the transistor and at least part of the interconnection lines, wherein the Fermi pinning layer can be used for adsorbing plasma charges transmitted in the interconnection lines, so that the plasma charges are prevented from flowing to the transistor, plasma-induced damage to the transistor caused by the plasma charges is reduced, and the performance of the transistor is finally improved.
Illustratively, the capacitance may comprise a MOS capacitance.
Referring to fig. 4, fig. 4 is a schematic diagram of the principle of fermi pinning. The graph (a) in fig. 4 illustrates the conduction band Ec, the fermi level Ef, the intrinsic fermi level Ei, and the valence band Ev of the surface-state-free polysilicon. Fig. 4 (b) and fig. 4 (c) illustrate that after contact between polysilicon and a high dielectric constant material, electrons are exchanged to achieve thermodynamic equilibrium, forming a fermi pinning layer, pinning the surface state fermi level at an energy level of 1/3 of the forbidden band width Eg. Fig. 4 (d) also illustrates the fermi level of the interconnect line, which is higher than the 1/3 forbidden bandwidth Eg. The graph (e) in fig. 4 illustrates that the interconnection line and the fermi-pinning layer are connected, and the fermi-pinning layer is insensitive to the amount of charge, and can adsorb the charge in the interconnection line, and pull down the fermi level of the interconnection line so that the fermi level of the interconnection line is also located at the level of 1/3 of the forbidden band width Eg, that is, the fermi level of the interconnection line is the same as the fermi level of the fermi-pinning layer.
In some embodiments, at least a portion of the interconnect line is electrically connected to a gate, source, or drain of the transistor.
Here, at least a portion of the interconnect line may be electrically connected to a gate, a source, or a drain of the transistor, such that the fermi-pinning layer may be used to adsorb transferred plasma charges in the interconnect line, thereby preventing the plasma charges from flowing to the transistor, more particularly, the gate, the source, or the drain of the transistor, and thereby reducing plasma-induced damage. Fig. 3 illustrates that the transistor 301 includes a gate 302, a source 303, and a drain 304, at least a portion of the interconnect line 305 being electrically connected to the gate 302 of the transistor 301.
Referring to fig. 5, fig. 5 is a schematic diagram two of the principle of fermi pinning. As shown in fig. 5, at least a part of the interconnection line is electrically connected with the gate electrode of the transistor, and the first electrode of the capacitor is electrically connected with the gate electrode of the transistor and at least a part of the interconnection line at the same time, so that the fermi pinning layer formed at the contact interface between the first electrode of the capacitor and the dielectric layer can be used for adsorbing the plasma charges transferred in the interconnection line, and the fermi level of the first electrode of the capacitor is not changed during the adsorption of the plasma charges in the interconnection line because the fermi pinning layer is insensitive to the charges, so that the fermi level of the interconnection line is identical to the fermi level of the first electrode of the capacitor. And, since the plasma charges transferred in the interconnection line are absorbed by the fermi pinning layer, the plasma charges can be prevented from flowing to the gate of the transistor, and the fermi level of the gate of the transistor can be prevented from being raised. Finally, the Fermi energy levels of the first electrode of the capacitor, the interconnection line and the grid electrode of the transistor are the same, so that thermodynamic balance is realized; wherein, in the above process, the charge exchange process only occurs between the interconnect line and the first electrode of the capacitor. Fig. 5 illustrates that the fermi levels of the gate of the transistor, the first electrode of the capacitor and the interconnect line are the same.
Illustratively, the material of the first electrode of the capacitor may include polysilicon, and the material of the dielectric layer of the capacitor may include a high dielectric constant material, the polysilicon and the high dielectric constant material forming the fermi-pinning layer upon contact. When the fermi levels of the gate of the transistor, the first electrode of the capacitor and the interconnect line reach an equilibrium state, the fermi levels of the gate of the transistor, the first electrode of the capacitor and the interconnect line are the same. Since the fermi-pinning layer is formed, charges transferred in the interconnect line are adsorbed by the fermi-pinning layer and do not flow to the gate of the transistor, and finally the fermi level of the gate of the transistor is not raised, so that the gate and the gate oxide of the transistor can be protected from breakdown.
In some embodiments, a semiconductor structure includes a memory chip region and a scribe line region surrounding the memory chip region; wherein the memory chip area is used for forming a memory chip, the scribe line area is used for forming a test element group (Test Element Group, TEG) in which the transistors are located.
Here, the semiconductor structure may include a memory chip region and a scribe line region surrounding the memory chip region. For example, a plurality of memory chip regions arranged in an array and scribe line regions between any adjacent memory chip regions may be formed on a wafer. Wherein the memory chip area may be used to form a memory chip and the scribe line area may be used to form a set of test elements.
Here, the test element group may include various test elements, and in the manufacturing process of the semiconductor structure, a probe card having a plurality of probes may be used to perform a pin contact with the test elements in the test element group to measure the electrical characteristics of the test elements, and finally confirm whether the manufacturing process of the semiconductor structure is normal or not, and whether the characteristics of the product meet the targets or not. Typically, after testing of the semiconductor structure is completed, the wafer may be diced into a plurality of memory chips by dicing. Specifically, dicing is accomplished by dicing the wafer along scribe line regions with a dicing blade.
In an embodiment of the disclosure, the transistor to be protected may be a test transistor located in the test element group, the interconnection line may be a metal interconnection line for leading out each electrode in the semiconductor structure to the test transistor in the test element group, and the first electrode of the capacitor may be electrically connected to the gate electrode of the transistor and at least a part of the interconnection line at the same time. In this way, the fermi-pinning layer may adsorb plasma charges transferred in the interconnect line, avoiding charge flow to the gate of the transistor, such that the fermi levels of the gate of the transistor, the interconnect line, and the fermi-pinning layer are the same. The Fermi pinning layer is utilized to adsorb plasma charges transmitted in the interconnection line, so that the shunt capacity of the capacitor can be enhanced without increasing the area of the capacitor, and the transistor can be better protected.
In some embodiments, the plasma charges transferred in the interconnect lines include plasma charges generated during the memory chip fabrication process; the manufacturing process of the memory chip is used for forming the memory chip; the memory chip is connected to the interconnect line.
In some embodiments, the memory chip fabrication process uses a plasma etch process in which plasma charges are generated, which are transferred from the memory chip to the interconnect lines.
Here, the plasma charges transferred in the interconnect include plasma charges generated in the memory chip fabrication process and the interconnect fabrication process; the memory chip manufacturing process may be used to form the memory chip, and the interconnection line manufacturing process may be used to form the interconnection line. The memory chip may be electrically connected to the interconnect lines, and plasma generated in the fabrication process of the memory chip may be transferred to the interconnect lines.
It should be noted that the plasma charges transferred in the interconnect may be from any process that may generate plasma charges. Illustratively, the process of generating the plasma charge may include, but is not limited to, an ion implantation process, a chemical vapor deposition process, or a plasma etching process.
In some embodiments, the transistor comprises an NMOS transistor.
Here, the formed fermi-pinning layer may be used to protect the NMOS transistor and the PMOS transistor. After the NMOS transistor is damaged by plasma induction, the threshold voltage of the NMOS transistor is positively shifted and the positive shift amplitude is larger. And after the PMOS transistor is damaged by plasma induction, the threshold voltage of the PMOS transistor cannot be shifted forward. Therefore, the fermi-pinning layer in the semiconductor structure provided by the embodiment of the disclosure has a greater protection effect on the NMOS transistor.
For the NMOS transistor, the threshold voltage of the thick gate NMOS transistor and the thin gate NMOS transistor is shifted forward after being damaged by plasma induction, so that the fermi-pinning layer formed in the capacitor provided by the embodiment of the present disclosure needs to be used to adsorb the plasma charges transferred in the interconnect line, thereby reducing the plasma-induced damage to the NMOS transistor.
In addition, the smaller the size of the transistor, the more severely the transistor is affected by plasma-induced damage. Accordingly, there is a need to adsorb plasma charges transferred in the interconnect lines using the fermi-pinning layer formed in the capacitor provided by embodiments of the present disclosure, thereby reducing plasma-induced damage to small-sized transistors.
In some embodiments, the material of the first electrode comprises at least one of: monocrystalline silicon, polycrystalline silicon, and amorphous silicon;
the material of the dielectric layer comprises at least one of the following: hafnium oxide HfO 2 Zirconium dioxide ZrO 2 Strontium titanate SrTiO 3 And titanium dioxide TiO 2 。
In some embodiments, the material of the first electrode comprises: gallium arsenide, gaAs;
the material of the dielectric layer comprises: silicon dioxide SiO 2 。
In some embodiments, the material of the first electrode comprises at least one of: gold Au, silver Ag, platinum Pt, molybdenum Mo, copper Cu, aluminum Al, tungsten W, and nickel Ni;
the material of the dielectric layer has MX 2 Wherein M is selected from at least one of the following groups: titanium Ti, vanadium V, tantalum Ta, molybdenum Mo, tungsten W, rhenium Re; x is selected from at least one of the following groups: sulfur S, selenium Se and tellurium Te.
Here, the fermi-pinning layer may be formed after the material of the first electrode and the material of the dielectric layer are contacted.
Referring to fig. 6A to 6C, fig. 6A to 6C are schematic cross-sectional structures during formation of the fermi-pinning layer. The process of forming the fermi-pinning layer will be exemplified below with reference to fig. 6A to 6C.
Fig. 6A, 6B, and 6C each illustrate a capacitor 401, a thin gate NMOS transistor 404 located in the peripheral region 402, a thin gate PMOS transistor 405 located in the peripheral region 402, a thick gate NMOS transistor 406 located in the peripheral region 402, a thick gate PMOS transistor 407 located in the peripheral region 402, and an array region 403.
As shown in fig. 6A, the capacitor 401 includes a substrate 408, a gate oxide layer 409, a high dielectric constant layer 410, a lanthanum oxide layer 411, a titanium nitride layer 412, a polysilicon layer 413, and a silicon oxide layer 414, which are stacked in this order. The polysilicon layer 413 may form a first electrode of the capacitor 401, the substrate 408 may form a second electrode of the capacitor 401, the gate oxide layer 409 and the high dielectric constant layer 410 may form a dielectric layer of the capacitor 401 together, and the lanthanum oxide layer 411 and the titanium nitride layer 412 may form a work function adjusting layer together. The stacked structure of thin gate NMOS transistor 404, thin gate PMOS transistor 405, thick gate NMOS transistor 406, and thick gate PMOS transistor 407 is covered with photoresist layer 415.
As also shown in fig. 6A, the array region 403 includes a substrate 408, a silicon oxide layer 416, a silicon nitride layer 417, a silicon oxide layer 418, a high dielectric constant layer 419, a titanium nitride layer 420, a lanthanum oxide layer 421, a titanium nitride layer 422, a polysilicon layer 423, and a silicon oxide layer 424, which are stacked in this order.
As shown in fig. 6A and 6B, the capacitor 401 is turned on, i.e., the silicon oxide layer 414 on top of the capacitor 401 is removed and the work function adjusting layer (i.e., the lanthanum oxide layer 411 and the titanium nitride layer 412) of the capacitor 401 is removed, so that the contact interface of the polysilicon layer 413 and the high dielectric constant layer 410 of the capacitor 401 forms a fermi-pinning layer. Photoresist layer 415 overlying the stacked structure of thin gate NMOS transistor 404, thin gate PMOS transistor 405, thick gate NMOS transistor 406, and thick gate PMOS transistor 407 is removed. The silicon oxide layer 424 on top of the array region 403 is removed and the work function adjusting layer (i.e., the lanthanum oxide layer 421 and the titanium nitride layer 422) of the array region 403 is removed.
As shown in fig. 6B and 6C, the array region 403 is opened, i.e., the polysilicon layer 423, the titanium nitride layer 420, the high dielectric constant layer 419, and the silicon oxide layer 418 of the array region 403 are removed.
As shown above, fig. 6A to 6C illustrate that the process of forming the capacitor in the semiconductor structure provided by the embodiment of the present disclosure may be compatible with the semiconductor manufacturing process, and the fermi-pinning layer is formed in the capacitor provided by the embodiment of the present disclosure, so that the current-dividing capability of the capacitor may be enhanced without increasing the area of the capacitor.
Referring to fig. 7, fig. 7 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 7, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:
step S701: forming a transistor;
step S702: forming an interconnection line, at least part of which is connected with the transistor;
step S703: forming a capacitor, wherein the capacitor comprises a first electrode, a second electrode and a dielectric layer positioned between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; wherein the contact interface of the first electrode of the capacitor and the dielectric layer forms a fermi-pinning layer.
In the embodiment of the present disclosure, in step S701, a transistor is formed.
For example, a gate oxide layer and a gate electrode may be sequentially formed on a substrate, and a source electrode and a drain electrode may be respectively formed on both sides of the gate oxide layer and the gate electrode in the substrate. Wherein the transistors may comprise test transistors in a set of test elements.
In the embodiment of the present disclosure, in step S702, an interconnection line is formed, at least a portion of which is connected to a transistor.
In the embodiment of the present disclosure, in step S703, a capacitor is formed, where the capacitor includes a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; wherein the contact interface of the first electrode of the capacitor and the dielectric layer forms a fermi-pinning layer.
Here, the first electrode of the capacitor may be electrically connected to the transistor and at least a portion of the interconnection line at the same time, and after the fermi pinning layer is formed at the contact interface between the first electrode of the capacitor and the dielectric layer, the fermi pinning layer may adsorb the plasma charges transferred in the interconnection line, so that the fermi energy levels of the transistor (for example, the gate of the transistor), the interconnection line and the fermi pinning layer are the same, so that the plasma charges are prevented from flowing to the transistor, and further, plasma induced damage caused by the plasma charges to the transistor is reduced, and finally, the performance of the transistor is improved.
Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes: a transistor; an interconnect line, at least a portion of which is connected to the transistor; a capacitor comprising a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer. In the embodiment of the disclosure, the first electrode of the capacitor is connected with the transistor, and at least part of the interconnection line is also connected with the transistor, and the Fermi pinning layer formed at the contact interface between the first electrode of the capacitor and the dielectric layer can be used for adsorbing the plasma charges transmitted in the interconnection line, so that the plasma charges are prevented from flowing to the transistor, the plasma induced damage to the transistor caused by the plasma charges is reduced, and the performance of the transistor is finally improved.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.
Claims (10)
1. A semiconductor structure, the semiconductor structure comprising:
a transistor;
an interconnect line, at least a portion of which is connected to the transistor;
a capacitor comprising a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer.
2. The semiconductor structure of claim 1, wherein at least a portion of the interconnect line is electrically connected to a gate, a source, or a drain of the transistor.
3. The semiconductor structure of claim 1, wherein the material of the first electrode comprises at least one of: monocrystalline silicon, polycrystalline silicon, and amorphous silicon;
the material of the dielectric layer comprises at least one of the following: hafnium oxide HfO 2 Zirconium dioxide ZrO 2 Strontium titanate SrTiO 3 And titanium dioxide TiO 2 。
4. The semiconductor structure of claim 1, wherein the material of the first electrode comprises: gallium arsenide, gaAs;
the material of the dielectric layer comprises: silicon dioxide SiO 2 。
5. The semiconductor structure of claim 1, wherein the material of the first electrode comprises at least one of: gold Au, silver Ag, platinum Pt, molybdenum Mo, copper Cu, aluminum Al, tungsten W, and nickel Ni;
the material of the dielectric layer has MX 2 Wherein M is selected from at least one of the following groups: titanium Ti, vanadium V, tantalum Ta, molybdenum Mo, tungsten W, rhenium Re; x is selected from at least one of the following groups: sulfur S, selenium Se and tellurium Te.
6. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a memory chip region and a scribe line region surrounding the memory chip region; the memory chip region is used for forming a memory chip, the dicing channel region is used for forming a test element group, and the transistor is located in the test element group.
7. The semiconductor structure of claim 6, wherein the plasma charges transferred in the interconnect line comprise plasma charges generated during a memory chip fabrication process; the memory chip manufacturing process is used for forming the memory chip; the memory chip is connected with the interconnection line.
8. The semiconductor structure of claim 7, wherein the memory chip fabrication process uses a plasma etch process in which plasma charges are generated, the plasma charges being transferred from the memory chip to the interconnect lines.
9. The semiconductor structure of claim 1, wherein the transistor comprises an N-type metal-oxide-semiconductor transistor.
10. A method of manufacturing a semiconductor structure, the method comprising:
forming a transistor;
forming an interconnection line, at least part of which is connected with the transistor;
forming a capacitor, wherein the capacitor comprises a first electrode, a second electrode and a dielectric layer positioned between the first electrode and the second electrode; the first electrode is connected with the transistor and at least part of the interconnection line; and the contact interface between the first electrode of the capacitor and the dielectric layer forms a Fermi pinning layer.
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