CN116825636A

CN116825636A - Semiconductor structure and forming method thereof

Info

Publication number: CN116825636A
Application number: CN202310583720.4A
Authority: CN
Inventors: 林子敬
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-23
Filing date: 2023-05-23
Publication date: 2023-09-29

Abstract

The present disclosure relates to semiconductor structures and methods of forming the same. A method, comprising: forming a plurality of semiconductor structures over a semiconductor substrate, forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures, forming gate spacers on sidewalls of the dummy gate stack, and etching a first portion of the dummy gate stack to form a through gate trench in the dummy gate stack. The dummy gate stack includes a second portion and a third portion located on opposite sides of the first portion. With the through gate trenches, the plurality of semiconductor structures are etched to form a group of trenches located below and connected to the through gate trenches. The groove set includes two outermost grooves and at least one inner groove located between the two outermost grooves. The two outermost grooves are deeper than the at least one inner groove.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates generally to semiconductor structures and methods of forming the same.

Background

Technological advances in Integrated Circuit (IC) materials and design have resulted in several generations of ICs, where each generation has smaller and more complex circuitry than the previous generation. During the evolution of ICs, functional density (e.g., the number of interconnected devices per chip area) generally increases while geometry decreases. Such a shrinking process generally provides benefits by improving production efficiency and reducing associated costs.

This shrinking also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. For example, gate-All-Around (GAA) transistors have been introduced to replace planar transistors. The structure of Gate All Around (GAA) transistors and methods of fabricating GAA transistors are being developed.

The formation of GAA transistors typically includes forming a long semiconductor stack and a long gate stack, and then forming isolation regions to cut the long semiconductor stack and the long gate stack into shorter portions so that the shorter portions can serve as the channel and gate stack of the resulting GAA transistor.

Disclosure of Invention

According to one aspect of the present disclosure, there is provided a method of forming a semiconductor structure, comprising: forming a plurality of semiconductor structures over a semiconductor substrate; forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; forming gate spacers on sidewalls of the dummy gate stack; etching a first portion of the dummy gate stack to form a through gate trench in the dummy gate stack, wherein the dummy gate stack includes a second portion and a third portion on opposite sides of the first portion; and etching the plurality of semiconductor structures through the through gate trench to form a trench group located under and connected to the through gate trench, wherein the trench group includes two outermost trenches and at least one inner trench located between the two outermost trenches, and wherein the two outermost trenches are deeper than the at least one inner trench.

According to another aspect of the present disclosure, there is provided a semiconductor structure comprising: a semiconductor substrate; a plurality of dielectric strips over a body portion of the semiconductor substrate; a plurality of semiconductor structures protruding above a body portion of the semiconductor substrate, wherein the plurality of semiconductor structures are separated from one another by the plurality of dielectric strips; a gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; and an isolation region having a first longitudinal direction parallel to a second longitudinal direction of the gate stack, wherein the isolation region comprises: penetrating a gate isolation region in the gate stack; and a plurality of isolation regions located below and coupled to the through gate isolation regions, wherein the plurality of isolation regions comprises two outermost isolation regions and at least one isolation region between the two outermost isolation regions, and wherein the two outermost isolation regions are deeper than the at least one isolation region.

According to yet another aspect of the present disclosure, there is provided a semiconductor structure comprising: a bulk semiconductor substrate; a plurality of nanostructures over the bulk semiconductor substrate; a gate stack including an upper portion overlying the plurality of nanostructures and a lower portion extending between the plurality of nanostructures; and an isolation structure including a first edge in contact with a second edge of the gate stack, wherein the isolation structure includes: an upper isolation region; and a plurality of lower isolation regions located below and coupled to the upper isolation region, wherein the plurality of lower isolation regions comprises: a first outermost isolation region; and a plurality of internal isolation regions spaced apart from the plurality of nanostructures by the first outermost isolation region, wherein a height of the first outermost isolation region is greater than a height of the plurality of internal isolation regions.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 to 3, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B fig. 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, and 23C illustrate various views of intermediate stages in forming a Gate All Around (GAA) transistor according to some embodiments.

Fig. 24 illustrates a profile of a plurality of grooves in a groove set, according to some embodiments.

Fig. 25 illustrates an enlarged view of a portion of a structure on one side of a trench, in accordance with some embodiments.

Fig. 26A, 26B, and 26C illustrate perspective and cross-sectional views of GAA transistors according to some embodiments.

Fig. 27 and 28 illustrate top views according to some embodiments.

Figure 29 illustrates a process flow for forming GAA transistors according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature to another element(s) or feature(s) illustrated in the figures. These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A method of forming an isolation region for isolating a transistor is provided. The profile of the isolation structure is also provided. According to some embodiments, a plurality of gate stacks are etched, and then semiconductor regions located under the gate stacks are etched to form a trench set comprising a plurality of trenches. An isolation region group including a plurality of isolation regions is then formed in the trench. The outermost isolation regions in the isolation region group are formed deeper than the inner isolation regions between the outermost isolation regions. Thus, deeper isolation regions are better barriers to leakage current. It should be appreciated that while the concepts of the present application are explained using Gate All Around (GAA) transistors as examples, these embodiments may be applied to forming other transistors, such as fin field effect transistors (finfets). The embodiments discussed herein are intended to provide examples to enable the subject matter of the present disclosure to be made or used, and modifications that remain within the intended scope of the different embodiments will be readily appreciated by those of ordinary skill in the art. In the various views and illustrative embodiments, like reference numerals are used to indicate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

The various crystal phase embodiments of the present disclosure in accordance with fig. 1-3, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B and 23B form an intermediate region of the gate valve according to embodiments of the present disclosure. The corresponding process is also schematically reflected in the process flow shown in fig. 29.

Referring to fig. 1, a cross-sectional view of a wafer 10 is shown. The wafer 10 includes a multi-layer structure that includes a multi-layer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., but other substrates and/or structures may be used, such as, for example, semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc.

According to some embodiments, the multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is shown as process 202 in process flow 200 shown in fig. 29. According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

According to some embodiments, the first layer 22A of the first semiconductor material is formed of or includes: siGe, ge, si, gaAs, inSb, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., siGe) is by epitaxial growth, and the corresponding deposition method may be Vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), chemical Vapor Deposition (CVD), low Pressure CVD (LPCVD), atomic Layer Deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced Pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed at aboutAnd about->A first thickness in the range between. However, any suitable thickness may be used while remaining within the scope of the embodiments.

Once the first layer 22A has been deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, e.g., si, siGe, ge, gaAs, inSb, gasB, inAlAs, inGaAs, gasB, gaAsSB, combinations thereof, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It should be appreciated that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

According to some embodiments, second layer 22B is epitaxially grown on first layer 22A using a deposition technique similar to that used to form first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness as the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A.

Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

According to some embodiments, a liner layer 23 and a hard mask 24 are deposited over the multi-layer stack 22. The liner layer 23 (sometimes referred to as a sacrificial layer) may be formed from a compound comprising silicon and another material(s) selected from carbon, oxide, nitrogen or combinations thereof. The hard mask 24 may be formed of or include silicon nitride.

Referring to fig. 2, the hard mask 24 and the pad 23 are patterned. Next, a portion of the underlying substrate 20 and the multi-layer stack 22 are patterned in an etching process (es) such that trenches 25 are formed. The corresponding process is shown as process 204 in process flow 200 shown in fig. 29. Trench 25 extends into substrate 20. The remainder of the multi-layer stack is hereinafter referred to as multi-layer stack 22'. Portions of the underlying multilayer stack 22', substrate 20 are left behind and are hereinafter referred to as substrate strips 20'. The multilayer stack 22' includes a semiconductor layer 22A and a semiconductor layer 22B. The semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is hereinafter alternatively referred to as a nanostructure. The portions of the multi-layer stack 22 'and underlying substrate strip 20' are collectively referred to as semiconductor strips 27.

In the above embodiments, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithographic processes (including double patterning processes or multiple patterning processes) may be used to pattern the structures. Typically, a double patterning process or a multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns, for example, having a pitch smaller than that obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

Fig. 2, 3, 4A, 4B and 4C illustrate the formation of isolation regions 30, the isolation regions 30 also being referred to as Shallow Trench Isolation (STI) regions throughout the specification. The corresponding process is shown as process 206 in process flow 200 shown in fig. 29. Referring to fig. 2, a dielectric liner 26 (which may be a conformal dielectric layer) is deposited. Dielectric liner 26 may comprise silicon oxide, silicon nitride, or the like, and may be formed using, for example, ALD, high Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, or the like.

Next, referring to fig. 3, a dielectric material 28 is deposited over dielectric liner 26. Dielectric material 28 may comprise silicon oxide or other dielectric materials (including carbon, nitrogen, etc.), and may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, HDPCVD, ALD, CVD, etc.

Subsequent figure numbers in fig. 4A, 4B and 4C through 23A, 23B and 23C may have a corresponding number followed by a letter A, B, or C. The figures, in which the reference numerals include the letter a, show perspective views. The figures, which include the letter B, show cross-sectional views taken from vertical planes X-X (fig. 4A) in corresponding perspective views. The figures, which include the letter C, show cross-sectional views taken from the vertical plane Y-Y (fig. 4A) in corresponding perspective views.

Referring to fig. 4A, 4B, and 4C, a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process) is performed to polish and flush the top surfaces of dielectric material 28 and dielectric liner 26, and the remainder of dielectric material 28 and dielectric liner 26 is STI region 30. The hard mask 24 or the liner layer 23 may be used as a polish stop layer in a planarization process.

Referring to fig. 5A, 5B and 5c, the STI region 30 is recessed such that the top of the semiconductor strip 27 (fig. 5B) protrudes higher than the top surface 30T of the remaining portion of the STI region 30 to form protruding fins 31. The corresponding process is shown as process 208 in process flow 200 shown in fig. 29. Protruding fin 31 includes the top of substrate strip 20 'and multi-layer stack 22'. The recessing of STI regions 30 may be performed by a dry etching process, wherein, for example, NF ₃ And NH ₃ Is used as the etching gas. During the etching process, a plasma may be generated. Argon may also be included. In accordance with an alternative embodiment of the present disclosure, the recessing of STI regions 30 is performed by a wet etching process. For example, the etching chemistry may include HF.

Referring to fig. 6A, 6B and 6C, a cladding (SiGe layer 32 is deposited. The cladding SiGe layer 32 may be formed by a conformal deposition process (e.g., ALD, CVD, etc.). According to an alternative embodiment, the cladding SiGe layer 32 is not formed. An anisotropic etching process may then be performed to remove the horizontal portions of the cladding SiGe layer 32, leaving the vertical portions of the cladding SiGe layer 32.

In fig. 7A, 7B and 7C, a dielectric liner 34 is formed, followed by deposition of a dielectric layer 36. Dielectric liner 34 may be formed of, or include, for example, silicon carbonitride, silicon oxycarbide, silicon nitride, and the like, and may be formed by a conformal deposition process (e.g., ALD, CVD, and the like). Dielectric layer 36 may be formed of or include silicon oxide and may be formed by a deposition process, spin coating, or the like. The corresponding process is shown as process 210 in process flow 200 shown in fig. 29.

Fig. 8A, 8B, and 8C illustrate a deep etch (etch-back) of dielectric layer 36 and dielectric layer 34. The remaining dielectric liner 34 and dielectric layer 36 are in the gap between adjacent multi-layer stacks 22', and are collectively referred to as dielectric regions 37. According to some embodiments, the top surface of the dielectric layer 36 is flush with the top of the multi-layer stack 22 'or below the top of the multi-layer stack 22'. According to some embodiments, the top end of dielectric liner 34 may be higher than the top surface of dielectric layer 36 by controlling the etching process.

Fig. 9A, 9B and 9C illustrate the formation of high-k dielectric regions 38. The corresponding process is shown as process 212 in process flow 200 shown in fig. 29. According to some embodiments, dielectric region 38 is deposited by High Density Plasma Chemical Vapor Deposition (HDPCVD), PECVD, ALD, CVD, or the like. The material of the dielectric region 38 may be selected from hafnium oxide, zirconium oxide, aluminum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like. Then, according to some embodiments, a planarization process is performed to level the top surface of the dielectric region 38 with the hard mask 24.

Next, the hard mask 24 and the liner layer 23 are removed, for example, in a dry etching process and/or a wet etching process. The corresponding process is shown as process 214 in process flow 200 shown in fig. 29. Thus, as shown in fig. 10A, 10B, and 10C, recesses 54 are formed between the high-k dielectric regions 38, which high-k dielectric regions 38 may protrude above the multi-layer stack 22'.

Fig. 11A and 11B illustrate the formation of the dummy gate dielectric layer 44, the dummy gate dielectric layer 44 being formed as a conformal layer. The corresponding process is shown as process 216 in process flow 200 shown in fig. 29. According to some embodiments, the dummy gate dielectric layer 44 is deposited, for example, using a conformal deposition process (e.g., ALD, CVD, etc.). According to some embodiments, the dummy gate dielectric layer 44 may be formed of or include silicon oxide. The dummy gate dielectric layer 44 extends into the recess 54 and over the top surface of the high-k dielectric region 38.

Fig. 12A, 12B and 12C illustrate the deposition of the dummy gate electrode layer 46. According to some embodiments, the dummy gate electrode layer 46 is formed of or includes polysilicon, amorphous silicon, or the like. The corresponding process is shown as process 218 in process flow 200 shown in fig. 29. A hard mask layer 48 is also formed over the dummy gate electrode layer 46. The hard mask layer 48 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or the like, or a plurality of layers thereof.

Next, as shown in fig. 13A, 13B, and 13C, the hard mask layer 48, the dummy gate electrode layer 46, and the dummy gate dielectric layer 44 are patterned in an etching process, thus forming a dummy gate stack 50. The corresponding process is shown as process 220 in process flow 200 shown in fig. 29. The remaining portions of the hard mask layer 48, the dummy gate electrode layer 46, and the dummy gate dielectric layer 44 are referred to as the hard mask 48, the dummy gate electrode 46, and the dummy gate dielectric 44, respectively.

Next, the gate spacer layer 52 is deposited, for example, by a conformal deposition process (e.g., ALD, CVD, etc.). According to some embodiments, the gate spacer layer 52 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon dioxide (SiO) ₂ ) Silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like), and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. After the deposition process, an anisotropic etching process(s) may be performed to etch horizontal portions of the gate spacer layer 52 without removing the gate spacersThe vertical portion of layer 52. The remaining portion of the dielectric layer(s) is referred to as gate spacers 52. The corresponding process is shown as process 221 in process flow 200 shown in fig. 29. In the subsequent figures, the gate stack 50 is shown, while the gate dielectric 44 and the gate electrode 46 may not (or may) be shown separately.

Fig. 14A, 14B, and 14C illustrate the resulting structure after forming the gate spacer 52, with the gate spacer 52 in the plane illustrated in fig. 14A and 14C. Next, portions of the protruding fin 31 not located directly under the dummy gate stack 50 and the gate spacers 52 (fig. 13A, 13B, and 13C) are recessed by an etching process to form recesses 54, these recesses 54 being between unetched portions of the protruding fin 31. The corresponding process is shown as process 222 in process flow 200 shown in fig. 29. For example, C may be used ₂ F ₆ ，CF ₄ ，SO ₂ ，HBr、Cl ₂ And O ₂ HBr, cl ₂ 、O ₂ And CH (CH) ₂ F ₂ A dry etching process is performed to etch the multi-layer semiconductor stack 22 'and underlying substrate strip 20'. The bottom of the recess 54 is at least flush with the bottom of the multi-layer semiconductor stack 22', or may be lower than the bottom of the multi-layer semiconductor stack 22' (as shown in fig. 14C). The etching may be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 54 are vertical and straight.

After forming recess 54, sacrificial semiconductor layer 22A is laterally recessed to form lateral recess 56, as also shown in fig. 14C, lateral recess 56 being recessed from the edges of the corresponding overlying nanostructure 22B and the corresponding underlying nanostructure 22B. The lateral recessing of the sacrificial semiconductor layer 22A may be achieved by a wet etching process that uses an etchant that is more selective to the material of the sacrificial semiconductor layer 22A, e.g., silicon germanium (SiGe), than to the material of the nanostructures 22B and the substrate 20, e.g., silicon (Si). For example, in embodiments where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructures 22B are formed of silicon, a wet etching process may be performed using an etchant such as hydrochloric acid (HCl). According to an alternative embodiment, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process, or a combination of a dry etching process and a wet etching process.

Fig. 15A, 15B, and 15C illustrate the formation of the inner spacer 58. The corresponding process is shown as process 224 in process flow 200 shown in fig. 29. The forming process comprises the following steps: a spacer layer is deposited that extends into the recess 56 and an etching process is performed to remove portions of the inner spacer layer outside the recess 56, leaving the inner spacer layer 58 in the recess 56. The inner spacer 58 may be formed of SiOCN, siON, siOC, siCN or the like or include SiOCN, siON, siOC, siCN or the like. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process in which the etching chemistry may include H ₂ SO ₄ Diluted HF, ammonia solution (NH) ₄ OH, aqueous ammonia), and the like, or combinations thereof.

Referring to fig. 16A, 16B and 16C, epitaxial source/drain regions 60 are formed in recesses 54. The corresponding process is shown as process 226 in process flow 200 shown in fig. 29. The source/drain region(s) may refer to source or drain, individually or collectively, depending on the context. According to some embodiments, the source/drain regions 60 may stress the nanostructures 22B that serve as channels for corresponding GAA transistors, thereby improving performance. When the resulting transistor is an n-type transistor, the epitaxial source/drain regions 60 are formed to be n-type by doping with n-type dopants. For example, the n-type source/drain regions 60 may be formed of or include silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like. When the resulting transistor is a p-type transistor, the epitaxial source/drain regions 60 are formed to be p-type by doping with a p-type dopant. For example, the p-type source/drain regions 60 may be formed of or include silicon germanium boron (SiGeB), silicon boron (sibs), or the like. Fig. 16A and 16B schematically illustrate an exemplary N-type epitaxial source/drain region 60N and P-type epitaxial source/drain region 60P.

Fig. 17A, 17B, and 17C show cross-sectional views of the structure after formation of a Contact Etch Stop Layer (CESL) 62 and an interlayer dielectric (ILD) 64. The corresponding process is shown as process 228 in process flow 200 shown in fig. 29. The CESL 62 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 64 may comprise a dielectric material formed using, for example, FCVD, spin-on, CVD, or any other suitable deposition method. ILD 64 may be formed of an oxygen-containing dielectric material that may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. The formation of CESL 62 and ILD 64 includes depositing conformal CESL 62, depositing ILD 64, and performing a planarization process. According to some embodiments, the hard mask 66 is formed and may be formed of, or include, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like. The forming process may include recessing ILD 64 to form a recess, depositing a corresponding dielectric material into the recess, and performing a planarization process.

Fig. 18A, 18B, and 18C through 22A, 22B, and 22C illustrate forming fin isolation regions 84 in the dummy gate stack 50, and forming underlying isolation regions 86 (fig. 23A, 23B, and 23C) that cut through (cut through) and electrically isolate adjacent protruding fins. Because the forming process involves cutting the polysilicon dummy gate electrode at the edges of the active region, the isolation region is also referred to as cutting the polysilicon on the diffusion side (Cut-Poly on Diffusion Edge, CPODE). Fig. 18A, 18B, and 18C illustrate the deposition of the hard mask 68. The corresponding process is shown as process 230 in process flow 200 shown in fig. 29. It should be appreciated that fig. 18A is rotated by about 90 degrees as compared to fig. 17A. Further, fig. 18B shows a plane with epitaxial source/drain regions 60, as compared to fig. 17B showing STI regions 30. In contrast to fig. 17C, which shows the epitaxial source/drain regions 60, fig. 18C shows a plane with STI regions 30. In fig. 18A, 18B, and 18C, the hard mask 48 is not shown separately, as they may be formed of the same material as the hard mask 68 and are considered to be part of the hard mask 68.

According to some embodiments, the hard mask 68 is formed of, or includes, silicon nitride, silicon oxynitride, or the like. Further, in fig. 18A, 18B, and 18C and subsequent drawings, the drawings including the letter a show perspective views. The figures, which include the letter B, show cross-sectional views taken from the plane X-X (fig. 18A) in corresponding perspective views. The figures, which include the letter C, show cross-sectional views taken from the plane Y-Y in fig. 18A in corresponding perspective views.

Fig. 19A, 19B, and 19C illustrate the formation of the etch mask 70. The corresponding process is shown as process 232 in process flow 200 shown in fig. 29. According to some embodiments, the etch mask 70 is a three-layer etch mask that includes a bottom layer 70B, a middle layer 70M, and a top layer 70T. The bottom layer 70B may be formed of a crosslinked photoresist. The intermediate layer 70M may be formed of an inorganic dielectric material. The top layer 70T is formed of a patterned photoresist having trenches 72 therein.

Fig. 27 shows a top view of the structure shown in fig. 19A, 19B and 19C. The multi-layer stack 22' and the epitaxial source/drain regions 60 are interconnected to form an elongated strip having its longitudinal direction in the X-direction (see also fig. 18A, where the vertical plane X-X is in the X-direction). The dummy gate stack 50 has its longitudinal direction in the Y direction perpendicular to the X direction. It should be appreciated that the formation of the CPODE region may be performed on the dummy gate stack 50 or, alternatively, on the replacement gate stack. Thus, the gate stack shown in fig. 27 is denoted 50/92 to indicate that the gate stack may be either a dummy gate stack 50 or a replacement gate stack 92 when the dicing process is performed (fig. 26B). It should be appreciated that fig. 27 shows a simplified diagram of forming a transistor, wherein the actual layout (e.g., the location of the openings 72) may be different than shown.

According to some embodiments, the etch mask 68 covers the area shown in fig. 19A except that the openings 72 are formed to extend across the plurality of multi-layer stacks 22'. The cross-sectional view shown in fig. 19B may be taken from the plane of fig. 27 containing lines 19B-19B, and the cross-sectional view shown in fig. 19C may be taken from the plane of fig. 27 containing lines 19C-19C.

Next, the top layer 70T (fig. 19A, 19B, and 19C) is used as an etching mask to etch the middle layer 70M and the bottom layer 70B. During the etching process, the top layer 70T (and possibly the middle layer 70M) may be consumed, leaving the bottom layer 70B including the trenches 72 passing from the top layer 70T. The remaining etch mask 70 is then used to etch the hard mask 68 such that the trench 72 is transferred further into the hard mask 68. The corresponding process is shown as process 234 in process flow 200 shown in fig. 29. Then, the remaining etching mask 70 is removed, and the resulting structure is as shown in fig. 20A, 20B, and 20C.

Referring to fig. 21A, 21B and 21C, hard mask 68 is used as an etch mask to etch underlying structures to form trenches 72 and 74. The corresponding process is shown as process 236 in process flow 200 shown in fig. 29. First, the gate stack 50 is etched such that the trenches 72 extend further down into the gate stack 50. The portion of trench 72 in gate stack 50 is also referred to as a through gate trench. The formation process is anisotropic such that the gate stack 50 has vertical sidewalls. When the gate electrode 46 (fig. 20B and 20C) is formed of polysilicon or amorphous silicon, fluorine (F ₂ ) Chlorine (Cl) ₂ ) Hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br) ₂ )、C ₂ F ₆ 、CF ₄ 、SO ₂ Or a combination thereof, to perform the etching of the gate electrode 46.

After etching the gate electrode 46, the dummy gate dielectric 44 (fig. 20B and 20C) and any native oxide formed on the surface of the multi-layer stack 22' are removed by an etching process. The corresponding process is also referred to as a dielectric punch-through process. According to some embodiments, CF may be used ₄ Ar, etc., and the etching may have low selectivity. For example, CF ₄ May range between about 0sccm and about 200sccm, 0sccm meaning that CF is not used ₄ And the corresponding process is a sputtering process. The flow rate of argon may be in a range between about 100sccm and about 1000 sccm.

After the dielectric punch-through process, the high-k dielectric region 38 is exposed. The multi-layer stack 22' is also exposed to the trench 72. Next, the multi-layer stack 22' is etched. The semiconductor strip 20' and underlying body portions of the substrate 20 (which are located below the STI regions 30) are also etched. According to some embodiments, the etching process is performed by selecting process conditions such that there is a high etch selectivity between etching the semiconductor material and etching the dielectric material. Thus, the high-k dielectric region 38, the inner spacer 58 (fig. 21B), the STI region 30, and the like, which are exposed to the etching process, are not etched. Thus forming trenches 74, also referred to as through gate trenches. Fig. 27 also shows the groove 74.

According to some embodiments, HBr, O is used ₂ And Ar to perform etching of the underlying body portion of the substrate 20, the multi-layer stack 22 'and the semiconductor strip 20'. In the etching of the semiconductor strip 20' and the underlying body portion of the substrate 20, in addition to O ₂ In addition to or instead of O ₂ CO may also be added ₂ . Other etching gases (e.g., F ₂ 、Cl ₂ 、HCl、HBr、Br ₂ 、C ₂ F ₆ 、CF ₄ 、SO ₂ 、O ₂ 、CH ₂ F ₂ Etc., or a combination thereof) to perform an etching process. According to some embodiments, the flow rate of HBr may be in the range between about 100sccm and about 1000sccm, CO ₂ And/or O ₂ The flow rate of Ar may be in the range of between about 0sccm and about 100sccm and the flow rate of Ar may be in the range of between about 100sccm and about 1000 sccm. Etching is performed by plasma etching (e.g., using Inductively Coupled Plasma (ICP)). Etching is performed using bias power applied to achieve anisotropic etching.

Fig. 25 shows an enlarged view of the region 75 in fig. 21C. The enlarged view is obtained before etching the semiconductor stripes 20' and the underlying body portion of the substrate 20.

Referring back to fig. 21A, 21B, and 21C, trench 72 is in gate stack 72. Trench 74 is located below trench 72 and is coupled to trench 72 and is separated from each other by high-k dielectric region 38, dielectric region 37, and STI region 30. Trench 74 extends to a level below the bottom surface of STI region 30 such that the isolation region formed therein may block leakage current in the bulk portion of semiconductor substrate 20. The grooves 74 collectively form a groove set 76 that includes two outermost grooves 74-O on the outermost side of the groove set 74, and at least one or more inner grooves 74-I between the outermost grooves 74-O. The grooves 74 in the same groove set 76 may (or may not) have a substantially uniform spacing (e.g., less than about 20% variation).

The inner trench(s) 74-I also include one or two intermediate trenches 74M, and the opposite side of the intermediate trench(s) have the same number of trenches. For example, when the total number of grooves 74 in the same groove group 76 is an odd number, there is one intermediate groove. Otherwise, when the total number of grooves 74 in the same groove group 76 is even, there are two intermediate grooves. Throughout the specification, when referring to the term "intermediate groove", it refers to the middle one or two grooves, depending on whether the total number of grooves is odd or even. The groove set 76 may have any number (total) of grooves greater than 2 or 3. Fig. 21C shows a groove set 76 having three grooves 74, and fig. 24 shows an example groove set 76 having 11 grooves 74. The outermost grooves 74-O, inner grooves 74-I, and intermediate grooves 74M are labeled. In the example shown in FIG. 21C, the single inner groove 74-I located in the middle of the groove set 76 is also the middle groove 74-M.

Referring back to fig. 21C (and also shown in fig. 24), the intermediate trenches 74-M have a depth D1, and the outermost trenches 74-O have a depth D2 that is greater than the depth D1. According to some embodiments, the depth ratio D2/D1 is greater than 1, and may range between about 1 and about 2. The depth ratio D2/D1 may also be in the range between about 1.2 and about 2, or in the range between about 1.5 and about 2. Further, the intermediate grooves 74-M have a width W1, and the outermost grooves 74-O have a width W2 that is greater than the width W1. Width W1 and width W2 may be measured, for example, at the mid-height of dielectric region 37 or STI region 30. According to some embodiments, the width ratio W2/W1 is greater than 1, and may range between about 1 and about 1.5. The width ratio W2/W1 may also be in the range between about 1.1 and about 1.5, or in the range between about 1.2 and about 1.5.

According to some embodiments, the trench depth may be smaller from the outermost trench 74-O to the intermediate trench 74-M. In other words, the outer grooves are deeper than the corresponding inner grooves. According to some embodiments, the bottom of the groove 74 may follow a curve 77, the curve 77 having a highest point in the middle and a lowest point at the opposite end. For example, curve 77 is shown as some examples in fig. 21C and 24. It should be appreciated that there may be variations in depth due to process variations. However, the general trend in depth remains. The width of the grooves may also remain the same, i.e. the outer grooves 74 are wider than the corresponding inner grooves 74.

The above-described profile of trench 74 may be achieved by adjusting process parameters (e.g., the overall height H1 of gate stack 50 and hard mask 68, etching process conditions used to form trench 74, etc.). In order to achieve an outer trench deeper than an inner trench, charge effects may be exploited and maximized by adjusting process parameters and process conditions, which will be discussed in detail in the following paragraphs. In the etching process, plasma is generated. It should be appreciated that the etch rate (reduction in thickness per unit time) is related to the concentration of the plasma (ions of the etching gas), and that the higher the concentration, the higher the etch rate achieved. In etching, the hard mask 68 and the dummy gate electrode 46 have charges, such as electrons, accumulated on the surfaces thereof. On the sidewalls of the hard mask 68 and the dummy gate electrode 46, the accumulated charge attracts the plasma, making the plasma concentration in the outer trenches higher than the plasma concentration in the corresponding inner trenches, the plasma concentration in the outermost trenches 74-O being the highest, and the plasma concentration in the middle trenches 74-M being the lowest. Thus, the charge effect has the effect of increasing the etch rate of the outermost trenches 74-O more than the corresponding inner trenches 74-I.

In addition, the overall height H1 (of the hard mask 68 and the dummy gate 50) affects the charge effect. When the height H1 is higher, the sidewall surfaces of the gate stack 50 and hard mask 68 have a larger area to attract more charge, which in turn attracts more plasma for etching to form the external trench. It has been found that when the height H1 is small (e.g., less than about 50 nm), the outer trench 74 may be shallower than the corresponding inner trench 74 (less than 1 in depth than D2/D1). As the height H1 increases, the outer grooves 74 are less deep (and wider) than the corresponding inner grooves. When the height H1 increases to the threshold value, the outer grooves 74 may have the same depth as the corresponding inner grooves 74, i.e., a depth ratio D2/D1 equal to 1. When the height H1 is further increased to be greater than the threshold value, the outer grooves 74 are deeper than the corresponding inner grooves 74, i.e., the depth ratio D2/D1 is greater than 1, and may be within the above-described range.

Because the depth ratio D2/D1 is affected by a number of factors, the threshold that determines when the depth ratio D2/D1 begins to be greater than the height H1 of 1 is also affected by a number of factors. According to some embodiments, the threshold value of the height H1 may fall within a range between about 130nm and about 160nm, depending on other factors, including a combination of process parameters and process conditions of the etching process.

There are other factors that affect the charge effect. For example, the frequency of an ICP etcher used to generate plasma affects the ability to generate plasma, and higher frequencies result in higher plasma concentrations and higher concentration differences between the outermost trenches and the intermediate trenches. Thus, higher frequencies equal to or higher than 13.56MHz, or equal to or higher than 27MHz may be employed. According to some embodiments, during the etching process, the process chamber may be operated at a pressure in a range between about 3 millitorr (mTorr) and about 150 millitorr and a temperature in a range between about 20 ℃ and about 140 ℃. The RF power generator may be operated to provide a source power in a range between about 100W and about 1500W, and the output of the RF power generator is controlled by a pulse signal having a duty cycle in a range between about 20% and 100%. The RF bias power used to create the anisotropic effect may be in the range between about 10W and about 600W.

Because the etching of the gate stack 50 has little, if any, effect on the depth ratio D2/D1, according to some embodiments, the etching of the gate stack 50 may be performed in a first etcher using a lower frequency (e.g., 13.56MHz or less), while the etching of the multi-layer stack 22', semiconductor strips 20', and bulk semiconductor substrate 20 may be performed in a second etcher using a higher frequency (e.g., 27 MHz). This may provide flexibility in manufacturing processes and may reduce unnecessary damage to the device caused by the high frequency plasma. According to alternative embodiments, the first etcher and the second etcher have the same frequency and may be the same etcher or different etchers.

In the etching process used to form trenches 72 and trenches 74, and in particular in the etching process used to form trenches 74, there are other factors that affect the depth ratio D2/D1. For example, the intermediate trench 74-M has a larger opening than the outermost trench 74-O. This is because the intermediate trench 74-M does not have high sidewalls near the gate stack 50 and the hard mask 68. By comparison, the outermost trench 74-O is blocked from one side by the gate stack 50 and hard mask 68 and has a small opening to the plasma. The difference in opening size results in a tendency opposite to the charge effect. Thus, the difference in opening size has the effect of increasing the etch rate of the inner trench 74-I to be greater than the etch rate of the corresponding outermost trench 74-O.

The final relative etch rate used to form trench 74 is determined by a variety of effects including charge effects and opening size effects. The process parameters and process conditions are adjusted to ensure that the charge effect overcomes the opening size effect. For example, as described above, the frequency of the heights H1 and ICP may be increased to increase the depth ratio D2/D1 to a desired range.

However, it is difficult to provide a universal fixed height H1 and fixed frequency to achieve the desired depth ratio D2/D1. For example, as the etching process proceeds, the height H1 gradually decreases due to the consumption of the hard mask 68. In some experiments, the hard mask 68 may be reduced from 80nm to 35nm. The width of the trenches 74, the spacing of the trenches 74, the structure of the wafer (e.g., whether the high-k dielectric region 38 is formed), etc., all affect the depth ratio D2/D1, and combinations of these factors affect the trench profile. According to some embodiments, experiments may be performed and the structure of the wafer determined. A sample wafer may then be formed, the sample wafer having different heights H1 and/or different frequencies in different combinations. Thus, different sample wafers will have different trench profiles and different D2/D1 ratios, and wafers with desired trench profiles and desired D2/D1 ratios may be selected, and corresponding process parameters (e.g., height H1 and structure) and process conditions (e.g., frequency of etchers) are used for mass production of wafers.

Fig. 22A, 22B, and 22C illustrate a deposition process for filling trenches 74 and 72 with a dielectric layer. According to some embodiments, the deposited dielectric layer includes a dielectric liner 78 and a dielectric layer 80. Dielectric liner 78 may be formed of or include silicon oxide. Dielectric layer 80 may be formed of or include silicon nitride. Other materials (e.g., siC, siON, siCN, siOCN, etc.) may also be used to form the dielectric layer.

In a subsequent process, excess portions of dielectric liner 78 and dielectric layer 80 over gate stack 50 are removed, for example, by a planarization process (e.g., a mechanical polishing process or a CMP process). The dielectric liner 78 and the remainder of the dielectric layer 80 include isolation regions 84 and isolation regions 86, the isolation regions 84 being in the gate stack 50, the isolation regions 86 being located below the isolation regions 84 and being coupled to the isolation regions 84. The isolation regions 86 collectively form an isolation region group 87. The corresponding process is shown as process 238 in process flow 200 shown in fig. 29. The resulting structure is shown in fig. 23A, 23B and 23C. Similar to trench 74, isolation region 86 also includes an outermost isolation region 86-O and an inner isolation region 86-I, wherein inner isolation region 86-I also includes an intermediate isolation region 86-M. Because isolation region 86 fills trench 74, isolation region 86 has the same profile as trench 74. For example, the depth (including depth D1 and depth D2), width (including width W1 and width W2), and the like are the same as the depth and width of the groove 74.

As shown in fig. 23C, forming the outermost isolation regions 86-O deeper than the inner isolation regions 86-I can significantly reduce leakage current from adjacent transistors into the body portion of the semiconductor substrate 20. Furthermore, leakage currents between transistors on opposite sides of the isolation region group can also be significantly reduced.

As shown in fig. 23B, gate stack 50 (fig. 22B) is then replaced with a replacement gate stack 92 that includes gate dielectric 88 and gate electrode 90 (gate stack 50 is a dummy gate stack). The corresponding process is shown as process 240 in process flow 200 shown in fig. 29. The replacement process may include: the dummy gate stack 50 and the sacrificial layer 22A are etched to form a gap, and a replacement gate stack 92 is formed in the gap. Gate dielectric 88 may comprise a high-k dielectric material, such as hafnium oxide, lanthanum oxide, or the like. The gate electrode 90 may include a metal gate electrode. A dielectric layer 94 (which may include an etch stop layer) is formed over gate stack 88 and isolation region 86 and in contact with gate stack 88 and isolation region 86. The nanostructure 22B serves as the channel region of the resulting GAA transistor 100.

Fig. 26A, 26B, and 26C illustrate the resulting GAA transistor 100, with some features of the transistor 100 labeled. Isolation region 86 is not shown and may be on both the left and right sides of transistor 100 as shown in fig. 26C. For example, isolation region 86 may be immediately to the right of rightmost STI region 30 and immediately to the left of leftmost STI region 30, with rightmost STI region 30 and leftmost STI region 30 being partially shown.

Fig. 28 shows a top view of the structure shown in fig. 23A, 23B and 23C, the cross-sectional view shown in fig. 23B being taken from plane 23B-23B in fig. 28, and the cross-sectional view shown in fig. 23C being taken from plane 23C-23C in fig. 28. In fig. 28, an example Gate isolation region 96 (which may be referred to as a Cut-Metal-Gate (CMG) region) is also shown, according to some embodiments. The process of forming the gate isolation region 96 may include: an etching process is performed to form recesses that separate the longer gate stacks 50/92 into shorter portions and fill the corresponding recesses with a dielectric material (e.g., silicon oxide, silicon nitride, or a plurality of layers thereof).

Embodiments of the present disclosure have some advantageous features. By forming the outermost isolation regions of the set of isolation regions to extend deeper into the underlying body portion of the semiconductor substrate than the inner isolation regions, leakage current is better blocked by the deeper outermost isolation regions.

According to some embodiments, a method comprises: forming a plurality of semiconductor structures over a semiconductor substrate; forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; forming gate spacers on sidewalls of the dummy gate stack; etching a first portion of the dummy gate stack to form a through gate trench in the dummy gate stack, wherein the dummy gate stack includes a second portion and a third portion located on opposite sides of the first portion; and etching the plurality of semiconductor structures through the through gate trench to form a trench group located below and connected to the through gate trench, wherein the trench group includes two outermost trenches and at least one inner trench located between the two outermost trenches, and wherein the two outermost trenches are deeper than the at least one inner trench.

In an embodiment, the two outermost trenches and the at least one inner trench are formed by the same etching process. In an embodiment, the method further comprises: a plurality of shallow trench isolation regions are formed extending into the semiconductor substrate, wherein the plurality of semiconductor structures are separated from one another by the plurality of shallow trench isolation regions. In an embodiment, the method further comprises: a plurality of high-k dielectric regions overlying the plurality of shallow trench isolation regions are formed, wherein the plurality of high-k dielectric regions remain after forming the trench set. In an embodiment, etching the plurality of semiconductor structures includes generating a plasma from the etching gas, and wherein the plasma is generated using an RF source having a frequency equal to about 27 MHz.

In an embodiment, the bottoms of the grooves in the groove group follow a curve, the ends of which are lowest, and the heights of the bottoms of the grooves gradually increase from the two outermost grooves to the middle groove in the middle of the two outermost grooves. In an embodiment, the two outermost trenches have a first depth measured from the bottom of the through gate trench and the intermediate trench intermediate the two outermost trenches has a second depth measured from the bottom of the through gate trench, and wherein a depth ratio of the first depth to the second depth is greater than about 1.2. In an embodiment, the depth ratio is in a range between about 1.2 and about 2.

In an embodiment, each semiconductor structure of the plurality of semiconductor structures includes a plurality of sacrificial layers formed of a first material and a plurality of nanostructures formed of a second material different from the first material, and wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately distributed. In an embodiment, the method further comprises: forming additional dummy gate stacks on top surfaces and sidewalls of the plurality of semiconductor structures; and forming a replacement gate stack to replace the additional dummy gate stack and portions of the plurality of sacrificial layers directly beneath the additional dummy gate stack.

According to some embodiments, a structure comprises: a semiconductor substrate; a plurality of dielectric strips over the body portion of the semiconductor substrate; a plurality of semiconductor structures protruding above the body portion of the semiconductor substrate, wherein the plurality of semiconductor structures are separated from each other by a plurality of dielectric strips; a gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; and an isolation region having a first longitudinal direction parallel to a second longitudinal direction of the gate stack, wherein the isolation region comprises: a through gate isolation region in the gate stack; and a plurality of isolation regions located below and coupled to the through gate isolation regions, wherein the plurality of isolation regions includes two outermost isolation regions and at least one isolation region between the two outermost isolation regions, and wherein the two outermost isolation regions are deeper than the at least one isolation region.

In an embodiment, the plurality of dielectric strips includes a plurality of shallow trench isolation regions extending into the semiconductor substrate. In an embodiment, the plurality of dielectric strips further comprises a plurality of high-k dielectric regions overlying the plurality of shallow trench isolation regions. In an embodiment, the bottoms of the plurality of isolation regions conform to a curve, both ends of the curve being lowest, and the heights of the bottoms of the isolation regions gradually increase from the two outermost isolation regions to an intermediate isolation region intermediate the two outermost isolation regions.

In an embodiment, the two outermost isolation regions have a first depth measured from a bottom of the through gate isolation region and the intermediate isolation region intermediate the two outermost isolation regions has a second depth measured from the bottom of the through gate isolation region, and wherein a depth ratio of the first depth to the second depth is greater than about 1.2. In an embodiment, each semiconductor structure of the plurality of semiconductor structures comprises a plurality of nanostructures vertically stacked and separated from each other, and wherein the gate stack extends between the plurality of nanostructures.

According to some embodiments, a structure comprises: a bulk semiconductor substrate; a plurality of nanostructures over a bulk semiconductor substrate; a gate stack including an upper portion overlying the plurality of nanostructures and a lower portion extending between the plurality of nanostructures; and an isolation structure including a first edge in contact with a second edge of the gate stack, wherein the isolation structure includes: an upper isolation region; and a plurality of lower isolation regions located below and coupled to the upper isolation region, wherein the plurality of lower isolation regions comprises: a first outermost isolation region; and a plurality of internal isolation regions spaced apart from the plurality of nanostructures by a first outermost isolation region, wherein a height of the first outermost isolation region is greater than a height of the plurality of internal isolation regions.

In an embodiment, the plurality of lower isolation regions have a uniform pitch. In an embodiment, the lower isolation region further comprises a second outermost isolation region, wherein the plurality of inner isolation regions are between the first and second outermost isolation regions, and wherein both the first and second outermost isolation regions extend deeper into the bulk semiconductor substrate than the plurality of inner isolation regions.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. A method of forming a semiconductor structure, comprising: forming a plurality of semiconductor structures over a semiconductor substrate; forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; forming gate spacers on sidewalls of the dummy gate stack; etching a first portion of the dummy gate stack to form a through gate trench in the dummy gate stack, wherein the dummy gate stack includes a second portion and a third portion on opposite sides of the first portion; and etching the plurality of semiconductor structures through the through gate trench to form a trench group located under and connected to the through gate trench, wherein the trench group includes two outermost trenches and at least one inner trench located between the two outermost trenches, and wherein the two outermost trenches are deeper than the at least one inner trench.

Example 2. The method of example 1, wherein the two outermost trenches and the at least one inner trench are formed by a same etching process.

Example 3. The method of example 1, further comprising: a plurality of shallow trench isolation regions are formed extending into the semiconductor substrate, wherein the plurality of semiconductor structures are separated from one another by the plurality of shallow trench isolation regions.

Example 4. The method of example 3, further comprising: a plurality of high-k dielectric regions overlying the plurality of shallow trench isolation regions are formed, wherein the plurality of high-k dielectric regions remain after forming the set of trenches.

Example 5. The method of example 1, further comprising: a patterned hard mask is formed over the dummy gate stack, wherein the dummy gate stack is etched using the patterned hard mask as an etch mask, and wherein a height measured from a top surface of the patterned hard mask to a bottom surface of the dummy gate stack is greater than about 130nm.

Example 6. The method of example 1, wherein etching the plurality of semiconductor structures comprises generating a plasma from an etching gas, and wherein the plasma is generated using a Radio Frequency (RF) source having a frequency equal to about 27 MHz.

Example 7. The method of example 1, wherein the bottoms of the grooves in the groove set conform to a curve, both ends of the curve being lowest, and the heights of the bottoms of the grooves gradually increase from the two outermost grooves to an intermediate groove intermediate the two outermost grooves.

Example 8 the method of example 1, wherein the two outermost trenches have a first depth measured from a bottom of the through gate trench and an intermediate trench intermediate the two outermost trenches has a second depth measured from the bottom of the through gate trench, and wherein a depth ratio of the first depth to the second depth is greater than about 1.2.

Example 9. The method of example 8, wherein the depth ratio is in a range between about 1.2 and about 2.

Example 10. The method of example 1, wherein each semiconductor structure of the plurality of semiconductor structures includes a plurality of sacrificial layers formed of a first material and a plurality of nanostructures formed of a second material different from the first material, and wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately distributed.

Example 11. The method of example 10, further comprising: forming additional dummy gate stacks on top surfaces and sidewalls of the plurality of semiconductor structures; and forming a replacement gate stack to replace the additional dummy gate stack and portions of the plurality of sacrificial layers directly below the additional dummy gate stack.

Example 12. A semiconductor structure, comprising: a semiconductor substrate; a plurality of dielectric strips over a body portion of the semiconductor substrate; a plurality of semiconductor structures protruding above a body portion of the semiconductor substrate, wherein the plurality of semiconductor structures are separated from one another by the plurality of dielectric strips; a gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; and an isolation region having a first longitudinal direction parallel to a second longitudinal direction of the gate stack, wherein the isolation region comprises: penetrating a gate isolation region in the gate stack; and a plurality of isolation regions located below and coupled to the through gate isolation regions, wherein the plurality of isolation regions comprises two outermost isolation regions and at least one isolation region between the two outermost isolation regions, and wherein the two outermost isolation regions are deeper than the at least one isolation region.

Example 13 the structure of example 12, wherein the plurality of dielectric strips includes a plurality of shallow trench isolation regions extending into the semiconductor substrate.

Example 14 the structure of example 13, wherein the plurality of dielectric strips further comprises a plurality of high-k dielectric regions overlying the plurality of shallow trench isolation regions.

Example 15. The structure of example 12, wherein bottoms of the plurality of isolation regions conform to a curve, both ends of the curve being lowest, and a height of bottoms of the isolation regions gradually increases from the two outermost isolation regions to an intermediate isolation region intermediate the two outermost isolation regions.

Example 16 the structure of example 12, wherein the two outermost isolation regions have a first depth measured from a bottom of the through gate isolation region and an intermediate isolation region intermediate the two outermost isolation regions has a second depth measured from a bottom of the through gate isolation region, and wherein a depth ratio of the first depth to the second depth is greater than 1.2.

Example 17 the structure of example 12, wherein each semiconductor structure of the plurality of semiconductor structures comprises a plurality of nanostructures vertically stacked and separated from one another, and wherein the gate stack extends between the plurality of nanostructures.

Example 18 a semiconductor structure, comprising: a bulk semiconductor substrate; a plurality of nanostructures over the bulk semiconductor substrate; a gate stack including an upper portion overlying the plurality of nanostructures and a lower portion extending between the plurality of nanostructures; and an isolation structure including a first edge in contact with a second edge of the gate stack, wherein the isolation structure includes: an upper isolation region; and a plurality of lower isolation regions located below and coupled to the upper isolation region, wherein the plurality of lower isolation regions comprises: a first outermost isolation region; and a plurality of internal isolation regions spaced apart from the plurality of nanostructures by the first outermost isolation region, wherein a height of the first outermost isolation region is greater than a height of the plurality of internal isolation regions.

Example 19 the structure of example 18, wherein the plurality of lower isolation regions have a uniform spacing.

Example 20 the structure of example 18, wherein the lower isolation region further comprises a second outermost isolation region, wherein the plurality of inner isolation regions are between the first and second outermost isolation regions, and wherein both the first and second outermost isolation regions extend deeper into the bulk semiconductor substrate than the plurality of inner isolation regions.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a plurality of semiconductor structures over a semiconductor substrate;

forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures;

forming gate spacers on sidewalls of the dummy gate stack;

etching a first portion of the dummy gate stack to form a through gate trench in the dummy gate stack, wherein the dummy gate stack includes a second portion and a third portion on opposite sides of the first portion; and

the plurality of semiconductor structures are etched through the through gate trench to form a trench group located below and connected to the through gate trench, wherein the trench group includes two outermost trenches and at least one inner trench located between the two outermost trenches, and wherein the two outermost trenches are deeper than the at least one inner trench.

2. The method of claim 1, wherein the two outermost trenches and the at least one inner trench are formed by a same etching process.

3. The method of claim 1, further comprising: a plurality of shallow trench isolation regions are formed extending into the semiconductor substrate, wherein the plurality of semiconductor structures are separated from one another by the plurality of shallow trench isolation regions.

4. A method according to claim 3, further comprising: a plurality of high-k dielectric regions overlying the plurality of shallow trench isolation regions are formed, wherein the plurality of high-k dielectric regions remain after forming the set of trenches.

5. The method of claim 1, further comprising: a patterned hard mask is formed over the dummy gate stack, wherein the dummy gate stack is etched using the patterned hard mask as an etch mask, and wherein a height measured from a top surface of the patterned hard mask to a bottom surface of the dummy gate stack is greater than 130nm.

6. The method of claim 1, wherein etching the plurality of semiconductor structures comprises generating a plasma from an etching gas, and wherein the plasma is generated using a radio frequency RF source having a frequency equal to 27 MHz.

7. The method of claim 1, wherein the bottoms of the grooves in the groove set conform to a curve, both ends of the curve being lowest, and the bottoms of the grooves gradually increase in height from the two outermost grooves to an intermediate groove intermediate the two outermost grooves.

8. The method of claim 1, wherein the two outermost trenches have a first depth measured from a bottom of the through gate trench and an intermediate trench intermediate the two outermost trenches has a second depth measured from the bottom of the through gate trench, and wherein a depth ratio of the first depth to the second depth is greater than 1.2.

9. A semiconductor structure, comprising:

a semiconductor substrate;

a plurality of dielectric strips over a body portion of the semiconductor substrate;

a plurality of semiconductor structures protruding above a body portion of the semiconductor substrate, wherein the plurality of semiconductor structures are separated from one another by the plurality of dielectric strips;

a gate stack on top surfaces and sidewalls of the plurality of semiconductor structures; and

an isolation region having a first longitudinal direction parallel to a second longitudinal direction of the gate stack, wherein the isolation region comprises:

penetrating a gate isolation region in the gate stack; and

a plurality of isolation regions located below and coupled to the through gate isolation regions, wherein the plurality of isolation regions comprises two outermost isolation regions and at least one isolation region between the two outermost isolation regions, and wherein the two outermost isolation regions are deeper than the at least one isolation region.

10. A semiconductor structure, comprising:

a bulk semiconductor substrate;

a plurality of nanostructures over the bulk semiconductor substrate;

a gate stack including an upper portion overlying the plurality of nanostructures and a lower portion extending between the plurality of nanostructures; and

an isolation structure comprising a first edge in contact with a second edge of the gate stack, wherein the isolation structure comprises:

an upper isolation region; and

a plurality of lower isolation regions located below and coupled to the upper isolation region, wherein the plurality of lower isolation regions comprises:

a first outermost isolation region; and

a plurality of inner isolation regions spaced apart from the plurality of nanostructures by the first outermost isolation region, wherein a height of the first outermost isolation region is greater than a height of the plurality of inner isolation regions.