CN116825163A - Nonvolatile memory unit, control method thereof and nonvolatile memory system - Google Patents

Nonvolatile memory unit, control method thereof and nonvolatile memory system Download PDF

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Publication number
CN116825163A
CN116825163A CN202310783555.7A CN202310783555A CN116825163A CN 116825163 A CN116825163 A CN 116825163A CN 202310783555 A CN202310783555 A CN 202310783555A CN 116825163 A CN116825163 A CN 116825163A
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nonvolatile memory
memory cell
read
buffer layer
threshold
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童浩
温晋宇
王伦
缪向水
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a nonvolatile memory unit and a control method thereof, and a nonvolatile memory system, belonging to the technical field of memory control, wherein the nonvolatile memory unit comprises a first metal electrode layer, a first buffer layer, a threshold switch layer, a second buffer layer and a second metal electrode layer which are sequentially stacked, the first buffer layer comprises a simple substance of a specific element or an alloy composed of a plurality of specific elements, the specific element is any element in III group elements and IV group elements, the second buffer layer comprises one or more dielectric materials, and the threshold switch layer is a chalcogenide semiconductor alloy; nonvolatile memory cells have a lower forward turn-on threshold voltage V after forward electrical operation is applied th1 Has a higher positive turn-on threshold voltage V after applying a negative electrical operation th2 ，V th1 <V th2 . By introducing buffer layers of different materials, the surface states of the upper surface and the lower surface of the threshold switch layer are different, so that the threshold voltage difference under different-direction electric operation is increased, and the reading margin of the large-scale memory array is improved.

Description

Nonvolatile memory unit, control method thereof and nonvolatile memory system
Technical Field
The invention belongs to the technical field of storage control, and particularly relates to a nonvolatile storage unit, a control method thereof and a nonvolatile storage system.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) has been the main memory for computer memory architecture for the last decades because of its advantages in both speed and memory density. However, as technology nodes move into 20nm, DRAMs suffer from reduced capacitance and increased transistor leakage due to scaling, approaching the physical limits of scaling, and the complex processes and high costs required for further scaling of DRAMs also result in the cost benefits of scaling gradually tending to saturate, creating barriers in physical size and cost to create "scaling walls".
For this reason, a new memory that can realize a smaller process size on the basis of matching the DRAM access speed is required. In the current several mainstream new memories based on resistance transition mechanism, the resistive random access Memory (Resistive Random Access Memory, RRAM) and the Phase-Change Memory (PCM) are difficult to match with the DRAM because the Memory cells must undergo structural nonvolatile transition during the erasing and writing processes. While spin-torque transfer-based magnetic Random Access Memory (STT-MRAM) has advantages in terms of read-write speed, but has disadvantages in terms of scalability, storage density and cost, it is considered to be more suitable for application in Static Random-Access Memory (SRAM), and Ferroelectric Random Access Memory (FeRAM) suffers from serious size shrinkage.
The Austrian threshold switch (Ovonic Threshold Switch, OTS for short) has the characteristics of high switching speed, low process cost, easiness in three-dimensional stacking and the like, and is used as a storage unit to be matched with a DRAM application scene in terms of speed and density. Currently, there are corresponding schemes for implementing information storage based on controllable threshold voltage variation of an austenitic threshold switch. However, the existence of the small threshold increment and the large leakage current of the low threshold state in the two threshold voltage states realized based on the prior art scheme make it difficult to be used in a large-scale memory array, so it is necessary to provide an OTS nonvolatile memory cell with a large threshold increment and a low leakage current for realizing a very large-scale OTS-only memory array.
Disclosure of Invention
In view of the above-mentioned drawbacks or improvements of the prior art, the present invention provides a nonvolatile memory cell, a method for operating the same, and a nonvolatile memory system, and is directed to providing an OTS nonvolatile memory cell with a large threshold increment and low leakage current for implementing a very large-scale OTS-only memory array.
In order to achieve the above object, according to one aspect of the present invention, there is provided a nonvolatile memory cell comprising a first metal electrode layer, a first buffer layer, a threshold switch layer, a second buffer layer, and a second metal electrode layer laminated in this order, the first buffer layer containing a simple substance of a specific element or an alloy composed of a plurality of specific elements, the specific element being any one of group iii elements and group iv elements, the second buffer layer containing one or more dielectric materials, the threshold switch layer being a chalcogenide semiconductor alloy;
the nonvolatile memory cell has a lower forward turn-on threshold voltage V after applying a forward electrical operation th1 Has a higher positive turn-on threshold voltage V after applying a negative electrical operation th2 ，V th1 <V th2 。
In one embodiment, in the first buffer layer, the simple substance of the specific element is a simple substance of one element in C, si, ge, B; any two elements in C, si, ge, B are contained in the alloy with the composition of the plurality of specific elements, or any one element in C, si, ge, B and any one element in Al, ga, in, sn are contained in the alloy with the composition of the plurality of specific elements.
In one embodiment, in the second buffer layer, the dielectric material comprises SiO x 、TiO x 、AlO x 、HfO x 、TaO x 、MgO x 、NbO x 、WO x 、SiN x 、Ti x N y O z And Si (Si) x N y O z Wherein x, y, z are any ratio of the components.
In one embodiment, the chalcogenide semiconductor alloy comprises one or more of the Ge, se, te, S, as elements.
In one embodiment, the chalcogenide semiconductor alloy includes a doping element including one or more of C, si, N, sb, B, O, al, ga, in, sn elements, and the doping element has a doping ratio ranging from 0 to 60%.
In one embodiment, the thickness of the first buffer layer is 1-20nm, and the thickness of the second buffer layer is 1-5nm.
According to another aspect of the present invention, there is provided a nonvolatile memory system including a control circuit and a nonvolatile memory cell, the nonvolatile memory cell being the nonvolatile memory cell described above, the control circuit including a write circuit and a read circuit acting on the nonvolatile memory cell, wherein:
the write circuit is used for applying forward electric operation to the designated nonvolatile memory unit to enable the corresponding nonvolatile memory unit to have lower forward conduction threshold voltage V after receiving the first data writing instruction th1 The method comprises the steps of carrying out a first treatment on the surface of the And when receiving the second data writing instruction, applying negative electric operation to the designated nonvolatile memory cell to make the corresponding nonvolatile memory cell have higher positive turn-on threshold voltage V th2 ；V th1 <V th2 ；
The read circuit is used for applying a forward read voltage V to the designated nonvolatile memory cell after receiving the read command read And judging whether the corresponding nonvolatile memory unit is conducted or not, V th1 <V read <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The first data is read as a result of the nonvolatile memory cell being in an on state after the read voltage is applied, and the second data is read as a result of the nonvolatile memory cell being in an off state after the read voltage is applied.
In one embodiment, V th2 -V th1 ≥1V。
In one embodiment, the first data is "0" and the second data is "1".
According to another aspect of the present invention, there is provided a method for operating a nonvolatile memory cell, the nonvolatile memory cell being the nonvolatile memory cell described above, the method comprising:
when receiving the first data writing command, applying a forward electric operation to the designated nonvolatile memory cell to enable the corresponding nonvolatile memory cell to have a lower forward conduction threshold voltage V th1 ；
When receiving the second data writing command, applying negative electric operation to the designated nonvolatile memory cell to make the corresponding nonvolatile memory cell have higher positive turn-on threshold voltage V th2 ；V th1 <V th2 ；
When receiving the read command, applying a forward read voltage V to the designated nonvolatile memory cell read And judging whether the corresponding nonvolatile memory unit is conducted or not, V th1 <V read <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The first data is read as a result of the nonvolatile memory cell being in an on state after the read voltage is applied, and the second data is read as a result of the nonvolatile memory cell being in an off state after the read voltage is applied.
In general, the above technical solutions conceived by the present invention, compared with the prior art, enable the following beneficial effects to be obtained:
the conventional austenitic threshold switch is characterized in that a threshold switch layer is directly arranged between metal layers, different threshold voltages are obtained by applying different electric operations, however, the difference value between the different threshold voltages is too small, which is not beneficial to a large-scale memory array. The invention provides a nonvolatile memory cell based on an austenitic threshold switch, which is characterized in that two buffer layers are introduced between an electrode layer and a threshold switch layer, wherein a first buffer layer contains a simple substance of a specific element or an alloy consisting of a plurality of specific elements, the specific element is any element in a III group element or a IV group element, and a second buffer layer contains one or more dielectric materials. By introducing buffer layers of different materials, on the basis of the threshold voltage difference generated by the electric operation of the chalcogenide semiconductor alloy in different directions, different interface influences are introduced to the contact surfaces of the threshold switch layer and the first buffer layer and the second buffer layer, so that the surface states of the upper surface and the lower surface of the threshold switch layer are different, the migration proportion of atoms in the threshold switch layer to the upper surface and the lower surface under the electric operation in different directions is greatly different due to the interface influences, the threshold voltage difference under the electric operation in different directions is increased, the threshold increment is increased, and the reading margin of the large-scale memory array is improved.
Meanwhile, buffer layers are respectively introduced into the upper surface and the lower surface of the threshold switch layer, the threshold switch layer and the metal electrode layer are separated, damage caused by defects of the contact surface of the threshold switch layer and the electrode is effectively reduced, and a conduction potential barrier is improved due to the introduction of the buffer layers when voltage is applied, so that leakage current of the nonvolatile memory cell is further reduced, and the low-threshold leakage current of the memory cell is ensured to meet the requirement of a large-scale memory array.
Drawings
FIG. 1 is a schematic diagram of a nonvolatile memory cell according to an embodiment;
FIG. 2 is a schematic diagram of a memory array according to an embodiment;
FIG. 3 (a) is an I-V graph of a nonvolatile memory cell of an embodiment after a write logic "0" operation;
FIG. 3 (b) is an I-V graph of a nonvolatile memory cell of an embodiment after a write logic "1" operation;
FIG. 3 (c) is a schematic diagram illustrating the operation of the nonvolatile memory cell from logic "1" to logic "0" according to one embodiment;
FIG. 3 (d) is an integrated view of FIGS. 3 (a) to 3 (c);
FIG. 4 is a schematic diagram showing the I-V curve of a nonvolatile memory cell according to one embodiment performing different data writing;
FIG. 5 is a schematic diagram showing the variation of the I-V curve during the read operation of the nonvolatile memory cell according to one embodiment.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
Fig. 1 is a schematic structural diagram of a nonvolatile memory cell 100 according to an embodiment, which includes a first metal electrode layer 110, a first buffer layer 120, a threshold switch layer 130, a second buffer layer 140, and a second metal electrode layer 150 stacked in sequence. The first buffer layer 120 includes a simple substance of a specific element or an alloy composed of a plurality of specific elements, and the specific element is any one of group iii elements and group iv elements. The second buffer layer 140 is a dielectric material comprising one or more, and the threshold switch layer 130 is a chalcogenide semiconductor alloy. It is understood that the positions of the first buffer layer 120 and the second buffer layer 140 may be interchanged. The threshold switch layer 130 is a chalcogenide semiconductor alloy, and the choice of chalcogenide semiconductor alloy material can be referred to as the material of the threshold switch layer in a conventional austenitic threshold switch.
According to the invention, two buffer layers are introduced between the electrode layer and the threshold switch layer, wherein the first buffer layer is simple substance or alloy containing one or more elements of group III and group IV, and the second buffer layer is dielectric material containing one or more elements of group IV. By introducing buffer layers of different materials, on the basis of the threshold voltage difference generated by the electric operation of the chalcogenide semiconductor alloy in different directions, different interface influences are introduced to the contact surfaces of the threshold switch layer and the first buffer layer and the second buffer layer, so that the surface states of the upper surface and the lower surface of the threshold switch layer are different, the migration proportion of atoms in the threshold switch layer to the upper surface and the lower surface under the electric operation in different directions is greatly different due to the interface influences, the threshold voltage difference under the electric operation in different directions is increased, the threshold increment is increased, and the reading margin of the large-scale memory array is improved. Meanwhile, buffer layers are respectively introduced into the upper surface and the lower surface of the threshold switch layer, the threshold switch layer and the metal electrode layer are separated, damage caused by defects of the contact surface of the threshold switch layer and the electrode is effectively reduced, and in addition, the conduction potential barrier is improved due to the introduction of the buffer layers when voltage is applied, so that the leakage current of the nonvolatile memory cell is further reduced, and the nonvolatile memory cell can be used for realizing a larger-scale memory array.
In an embodiment, the first buffer layer may be an elemental material, and may specifically be an elemental substance of one element in C, si, ge, B; but may also be an alloy material, the alloy comprising any two elements of C, si, ge, B, or the alloy comprising any one element of C, si, ge, B and any one element of Al, ga, in, sn.
In one embodiment, the dielectric material comprises SiO x 、TiO x 、AlO x 、HfO x 、TaO x 、MgO x 、NbO x 、WO x 、SiN x 、Ti x N y O z And Si (Si) x N y O z Wherein x, y, z are any ratio of the components.
In one embodiment, the chalcogenide semiconductor alloy of threshold switch layer 130 comprises one or more of the Ge, se, te, S, as elements, where the composition may be any composition ratio. Further, the chalcogenide semiconductor alloy of the threshold switch layer 130 also has a doping element comprising one or more of C, si, N, sb, B, O, al, ga, in, sn elements, the doping element having a doping ratio in the range of 0 to 60%.
In one embodiment, the first buffer layer has a thickness of 1-20nm and the second buffer layer has a thickness of 1-5nm, the thickness of the first buffer layer being greater than the thickness of the second buffer layer.
Example 2
The invention also relates to a non-volatile memory system comprising a memory array comprising control circuitry and the non-volatile memory cells described above, the control circuitry comprising write circuitry and read circuitry for the non-volatile memory cells, wherein: the write circuit is used for directing the first data after receiving the instruction of writingApplying a forward electrical operation to a given nonvolatile memory cell to cause the corresponding nonvolatile memory cell to have a lower forward turn-on threshold voltage V th1 The method comprises the steps of carrying out a first treatment on the surface of the And when receiving the second data writing instruction, applying negative electric operation to the designated nonvolatile memory cell to make the corresponding nonvolatile memory cell have higher positive turn-on threshold voltage V th2 ；V th1 <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The read circuit is used for applying a forward read voltage V to the designated nonvolatile memory cell after receiving the read command read And judging whether the corresponding nonvolatile memory unit is conducted or not, V th1 <V read <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The first data is read as a result of the nonvolatile memory cell being in an on state after the read voltage is applied, and the second data is read as a result of the nonvolatile memory cell being in an off state after the read voltage is applied.
If the first metal electrode layer is connected with the positive electrode and the second metal electrode layer is connected with the negative electrode, the first metal electrode layer is connected with the negative electrode and the second metal electrode layer is connected with the positive electrode; if the second metal electrode layer is connected with the positive electrode and the first metal electrode layer is connected with the negative electrode, the second metal electrode layer is connected with the negative electrode and the first metal electrode layer is connected with the positive electrode to be negative.
As shown in fig. 2, which is a schematic diagram of a memory array 200, the memory array 200 includes nonvolatile memory cells 210 having different logic states, word lines 215 and bit lines 220 of a particular memory cell can be selected, the word lines 215 and bit lines 220 are spatially perpendicular (including approximately perpendicular), and memory cells in all memory arrays can be distinguished and selected by crossing points of the word lines 215 and bit lines 220. The memory array 200 further includes control circuitry for implementing the operation of the memory cells, including a row decoder 225, a column decoder 230, a read out component 235, a memory controller 240, and an input/output interface 245, when the memory array 200 receives a write instruction, address information corresponding to the write instruction is sent to the row decoder 225 and the column decoder 230 through the memory controller 240, the row decoder 225 activates the corresponding word line 215 according to the received row address, the column decoder 230 activates the corresponding bit line 220 according to the received column address, and the write instruction is applied to the selected memory cell through the activated word line 215 and bit line 220. When the memory array 200 receives a read command, similar to a write command, the memory controller 240 sends address information of the read command to the row decoder 225 and column decoder 230 and activates the corresponding word line 215 and bit line 220, applies the read command to the selected memory cell and monitors the output voltage/current level through the sense element, senses the logic state of the memory cell through the voltage/current amplifier within the sense element, and feeds back to the memory controller 240 for output.
Example 3
The invention also relates to a method for operating a nonvolatile memory cell, the nonvolatile memory cell being the nonvolatile memory cell described above, the method comprising:
when receiving the first data writing command, applying a forward electric operation to the designated nonvolatile memory cell to enable the corresponding nonvolatile memory cell to have a lower forward conduction threshold voltage V th1 ；
When receiving the second data writing command, applying negative electric operation to the designated nonvolatile memory cell to make the corresponding nonvolatile memory cell have higher positive turn-on threshold voltage V th2 ；V th1 <V th2 ；
When receiving the read command, applying a forward read voltage V to the designated nonvolatile memory cell read And judging whether the corresponding nonvolatile memory unit is conducted or not, V th1 <V read <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The first data is read as a result of the nonvolatile memory cell being in an on state after the read voltage is applied, and the second data is read as a result of the nonvolatile memory cell being in an off state after the read voltage is applied.
Wherein different threshold voltages can be corresponding to different stored data, and forward electric operation is applied to make the nonvolatile memory cell have lower forward conduction threshold voltage V th1 Representing writing first data to the nonvolatile memory cell; applying negative electrical operation to cause non-volatile storageThe memory cell has a higher forward conduction threshold voltage V th2 Indicating writing of the second data to the nonvolatile memory cell, the first data and the second data may be set as desired. The first data may be "0", and the second data may be "1"; or the first data may be "1", and the second data may be "0".
Hereinafter, the first data is "1" and the second data is "0" will be described as an example.
To perform the write logic "0" operation, a negative electrical operation is applied to the nonvolatile memory cell to turn on the nonvolatile memory cell, i.e., the write logic "0" operation corresponding to the negative electrical operation is performed on the nonvolatile memory cell, to obtain a positive high threshold state, i.e., to obtain a higher positive turn-on threshold voltage V th2 ＝V “0” . FIG. 3 (a) shows an I-V graph of a nonvolatile memory cell after a write logic "0" operation, with the right side of the abscissa zero line as the positive direction, and after a write logic "0" operation, the nonvolatile memory cell has a forward conduction threshold voltage V “0” When the applied forward voltage reaches the forward conduction threshold voltage V “0” When the nonvolatile memory cell is turned on in the forward direction.
To perform the write logic "1" operation, a forward electrical operation is applied to the nonvolatile memory cell to turn it on, i.e., the corresponding forward electrical operation is a write logic "1" operation of the nonvolatile memory cell, resulting in a forward low threshold state, i.e., a lower forward turn-on threshold voltage V th1 ＝V “1” . FIG. 3 (b) shows an I-V graph of a nonvolatile memory cell after a write logic "1" operation, with the right side of the zero line on the abscissa as the positive direction, and after a write logic "1" operation, the nonvolatile memory cell has a forward conduction threshold voltage V “1” When the applied forward voltage reaches the forward conduction threshold voltage V “1” When the nonvolatile memory cell is turned on in the forward direction.
FIG. 3 (c) is a schematic diagram illustrating an operation procedure of converting the nonvolatile memory cell from logic "1" to logic "0" in an embodiment, and after writing the logic "1", applying negative power until the nonvolatile memory cell is turned on again, so as to implement writing the logic "0".
As can be seen from fig. 3 (d), which is an integrated diagram of fig. 3 (a) to 3 (c), the threshold increment of the nonvolatile memory cell is V “0” And V is equal to “1” Is a difference in (c). The threshold increment in this embodiment is 1V and above, and is large enough to ensure that there is enough differentiation between different threshold states, meeting the requirements for application to large-scale memory arrays.
FIG. 4 is a schematic diagram showing the I-V curve of the nonvolatile memory cell according to one embodiment. The nonvolatile memory cell is currently in a high threshold state ("0" state), and at this time, the forward conduction threshold voltage of the nonvolatile memory cell is V “0” Corresponding to the high threshold state 410, upon receiving a write logic "1" command, a forward electrical operation is applied to the nonvolatile memory cell to turn it on (the applied forward voltage needs to be greater than the current forward on threshold voltage V “0” To be turned on again) the nonvolatile memory cell transitions from the high threshold state 410 to the low threshold state 420, at which time the forward turn-on threshold voltage of the nonvolatile memory cell is defined by V “0” Reduced to V “1” I.e., the write logic "1" operation is completed. Similarly, the nonvolatile memory cell is currently in a low threshold state ("1" state), and the forward conduction threshold voltage of the nonvolatile memory cell is V “1” Corresponding to the low threshold state 420, after receiving a write logic "0" command, a negative electrical operation is applied to the nonvolatile memory cell to turn on (the magnitude of the applied negative voltage is greater than the current positive turn-on threshold voltage V “1” To be turned on again) the nonvolatile memory cell transitions from the low threshold state 420 to the high threshold state 410, at which time the forward turn-on threshold voltage of the nonvolatile memory cell is defined by V “1” Increase to V “0” Namely, the logical 0 writing operation is completed; the voltage range between the high and low threshold states is the read voltage range 430 of the nonvolatile memory cell.
In one embodiment, a write logic "0" operation may be referred to as an erase operation, i.e., the data storage includes a write "1" operation and an erase operation.
As shown in FIG. 5The I-V curve change during a read operation of a nonvolatile memory cell in one embodiment is shown. Due to the read voltage V read Is a forward voltage, and V “1” <V read <V “0” After receiving the read command, when the nonvolatile memory cell is at logic "0", the read voltage is smaller than the current threshold voltage V of the nonvolatile memory cell, corresponding to the high threshold state 510 “0” The read operation applied to the nonvolatile memory cell cannot turn on it to output a small current I off When the read voltage is applied for a plurality of times, the nonvolatile memory cell is not conducted under the read voltage all the time, so that the read command does not destroy the logic state 0 of the nonvolatile memory cell at present, namely, the nonvolatile memory cell is read by the read operation when the logic 0 of the nonvolatile memory cell is read. When the nonvolatile memory cell is at a logic "1", it corresponds to a low threshold state 520. Due to the read voltage V read Is a forward voltage, and V “1” <V read The read operation applied to the nonvolatile memory cell will make it forward conductive to output a large current I out When the read voltage is applied for a plurality of times, the nonvolatile memory unit maintains logic '1' under forward conduction, so that the read command does not destroy the logic '1' of the nonvolatile memory unit, namely the nonvolatile memory unit is read by the read operation when the logic '1' of the nonvolatile memory unit is read.
In summary, by introducing two buffer layers of different materials between the electrode layer and the threshold switch layer, on the basis of the threshold voltage difference generated by the electric operation of the chalcogenide semiconductor alloy in different directions, different interface influences are introduced to the contact surfaces of the threshold switch layer, the upper surface and the lower surface of the threshold switch layer are made to be different, so that the migration proportion of atoms in the threshold switch layer to the upper surface and the lower surface in different directions is greatly different due to the interface influences, the threshold voltage difference in different directions is increased, the threshold increment is increased, and the read margin of the large-scale memory array is improved. Meanwhile, buffer layers are respectively introduced into the upper surface and the lower surface of the threshold switch layer, the threshold switch layer and the metal electrode layer are separated, damage caused by defects of the contact surface of the threshold switch layer and the electrode is effectively reduced, and a conduction potential barrier is improved due to the introduction of the buffer layers when voltage is applied, so that leakage current of the nonvolatile memory cell is further reduced, and the low-threshold leakage current of the memory cell is ensured to meet the requirement of a large-scale memory array.
It will be readily appreciated by those skilled in the art that the foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (10)

1. The nonvolatile memory cell is characterized by comprising a first metal electrode layer, a first buffer layer, a threshold switch layer, a second buffer layer and a second metal electrode layer which are sequentially stacked, wherein the first buffer layer comprises a simple substance of a specific element or an alloy composed of a plurality of specific elements, the specific element is any one element of a III group element and a IV group element, the second buffer layer comprises one or more dielectric materials, and the threshold switch layer is a sulfur-based semiconductor alloy;
the nonvolatile memory cell has a lower forward turn-on threshold voltage V after applying a forward electrical operation th1 Has a higher positive turn-on threshold voltage V after applying a negative electrical operation th2 ，V th1 <V th2 。
2. The nonvolatile memory cell according to claim 1, wherein in the first buffer layer, a simple substance of the specific element is a simple substance of one element in C, si, ge, B; any two elements in C, si, ge, B are contained in the alloy with the composition of the plurality of specific elements, or any one element in C, si, ge, B and any one element in Al, ga, in, sn are contained in the alloy with the composition of the plurality of specific elements.
3. The nonvolatile memory cell of claim 1 or 2 wherein, in said second bufferIn the layer, the dielectric material comprises SiO x 、TiO x 、AlO x 、HfO x 、TaO x 、MgO x 、NbO x 、WO x 、SiN x 、Ti x N y O z And Si (Si) x N y O z Wherein x, y, z are any ratio of the components.
4. The nonvolatile memory cell of claim 1 wherein the chalcogenide semiconductor alloy comprises one or more of the Ge, se, te, S, as elements.
5. The nonvolatile memory cell of claim 4 wherein the chalcogenide semiconductor alloy comprises a doping element comprising one or more of C, si, N, sb, B, O, al, ga, in, sn elements, the doping element having a doping ratio in the range of 0 to 60%.
6. The nonvolatile memory cell of claim 1 wherein the first buffer layer has a thickness of 1-20nm and the second buffer layer has a thickness of 1-5nm.
7. A nonvolatile memory system comprising a control circuit and a nonvolatile memory cell, wherein the nonvolatile memory cell is the nonvolatile memory cell of any one of claims 1 to 6, the control circuit comprising a write circuit and a read circuit for the nonvolatile memory cell, wherein:
the write circuit is used for applying forward electric operation to the designated nonvolatile memory unit to enable the corresponding nonvolatile memory unit to have lower forward conduction threshold voltage V after receiving the first data writing instruction th1 The method comprises the steps of carrying out a first treatment on the surface of the And when receiving the second data writing instruction, applying negative electric operation to the designated nonvolatile memory cell to make the corresponding nonvolatile memory cell have higher positive turn-on threshold voltage V th2 ；V th1 <V th2 ；
The read circuit is used for applying a forward read voltage V to the designated nonvolatile memory cell after receiving the read command read And judging whether the corresponding nonvolatile memory unit is conducted or not, V th1 <V read <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The first data is read as a result of the nonvolatile memory cell being in an on state after the read voltage is applied, and the second data is read as a result of the nonvolatile memory cell being in an off state after the read voltage is applied.
8. The non-volatile storage system of claim 7, wherein V th2 -V th1 ≥1V。
9. The non-volatile storage system of claim 7, wherein the first data is "0" and the second data is "1".
10. A method of operating a nonvolatile memory cell, wherein the nonvolatile memory cell is a nonvolatile memory cell according to any one of claims 1 to 6, the method of operating comprising:
when receiving the first data writing command, applying a forward electric operation to the designated nonvolatile memory cell to enable the corresponding nonvolatile memory cell to have a lower forward conduction threshold voltage V th1 ；
When receiving the second data writing command, applying negative electric operation to the designated nonvolatile memory cell to make the corresponding nonvolatile memory cell have higher positive turn-on threshold voltage V th2 ；V th1 <V th2 ；
When receiving the read command, applying a forward read voltage V to the designated nonvolatile memory cell read And judging whether the corresponding nonvolatile memory unit is conducted or not, V th1 <V read <V th2 The method comprises the steps of carrying out a first treatment on the surface of the The nonvolatile memory cell is turned on after the read voltage is applied as the first data, and turned off after the read voltage is applied as the read junctionThe result is second data.
CN202310783555.7A 2023-06-28 2023-06-28 Nonvolatile memory unit, control method thereof and nonvolatile memory system Pending CN116825163A (en)

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