CN116822451A - Method, equipment and medium for reusing and displaying annotation area of variable chip design code - Google Patents
Method, equipment and medium for reusing and displaying annotation area of variable chip design code Download PDFInfo
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Abstract
The invention relates to a method, equipment and medium for reusing and displaying annotation areas of variable chip design codes, which comprises the following steps of S1, dividing a visual interface into a first display area and a second display area; step S2, obtaining D 0 And M 0 The method comprises the steps of carrying out a first treatment on the surface of the Step S3, if the chip design code is changed, obtaining D 1 And M 1 The method comprises the steps of carrying out a first treatment on the surface of the Step S4, if D 0 And D 1 The number of elements in (a) is not equal, and/or M 0 And M 1 Step S9 is executed if not equal, otherwise, i=1 is set, and step S5 is executed; step S5, if d i 0 And d i 1 If yes, executing the step S7, otherwise, executing the step S6; step S6, determining a subarea to be rewritten, generating annotation rewriting information, and executing step S7; step S7, if i<J, set i=i+1, returnStep S5, if i=j, executing step S8; step S8, rewriting the corresponding subarea to be rewritten, and executing step S10; step S9, based on D 1 Rewriting the second display area; step S10, setting D 0 ＝D 1 ，M 0 ＝M 1 And returning to the step S3. The invention improves the display efficiency of the annotation information display of the variable chip design codes.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method, an apparatus, and a medium for displaying a reuse of an annotation region of a variable chip design code.
Background
In the field of chip design verification, it is often necessary to verify the data values of the same design signal at different points in time. In order to view the corresponding signal value in the design code file, an Annotation (analysis) mode is generally adopted, and in the same display interface, the original design code file is displayed, and specific data values of the signal at the corresponding time point are displayed. In the prior art, the data values of the corresponding signal variables are typically displayed in the design code in a row-by-row fashion, with the signal variable names corresponding to the signal values on the columns. However, when the display length required by the signal value of one signal is longer than the signal variable name, the display interface cannot display the complete signal value data, and the display effect is poor. So that part of the tool will also display annotation information in a multi-line fashion. However, when the number of signal variables in the same row is too large, a large amount of annotation information exists in the display interface, so that enough chip design information cannot be displayed, and the interface utilization rate is low. In addition, there may be variations in the chip design code during the process of displaying the annotation, and when variations occur, the prior art generally needs to rewrite all the annotation information, and the display efficiency of the annotation information is also reduced. Therefore, how to improve the interface utilization rate and the display efficiency of the annotation information display of the variable chip design code becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a method, equipment and medium for reusing and displaying annotation areas of variable chip design codes, which improve the interface utilization rate and display efficiency of the annotation information display of the variable chip design codes.
According to a first aspect of the present invention, there is provided an annotation region reuse display method of a variable chip design code, comprising:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, the second display area is used for displaying annotation information corresponding to the chip design codes, the chip design codes need to display annotation code rows of annotated code rows to be displayed, the second display area comprises subareas with the same number as the annotation code rows to be displayed, and each subarea is used for displaying the annotation information of one corresponding annotation code row to be displayed;
s2, acquiring an annotation code line information set D to be displayed, corresponding to the chip design code initially displayed in the first display area 0 And the total number M of the signal numbers corresponding to all the annotation code lines to be displayed 0 ；
Step S3, if the chip design code in the first display area is changed, acquiring an annotation code line information set D to be displayed corresponding to the chip design code after the first display area is changed 1 And the total number M of the signal numbers corresponding to all the annotation code lines to be displayed 1 ；
Step S4, comparison D 0 And D 1 Comparison of M 0 And M 1 If D 0 And D 1 The number of elements in (a) is not equal, and/or M 0 And M 1 If not, executing step S9, otherwise, setting i=1, and executing step S5;
step S5, comparison D 0 The ith element d of (b) i 0 And D 1 The ith element d of (b) i 1 If d i 0 And d i 1 If the two values are consistent, executing the step S7, otherwise, executing the step S6;
step S6, determining an ith subarea in the second display area as a subarea to be rewritten, based on d i 1 Generating annotation rewriting information, and executing step S7;
step S7, if i<J, i=i+1 is set, and the process returns to step S5, and if i=j, step S8 is executed, J being D 0 Corresponding to the total number of annotation code line information to be displayed;
step S8, if the subarea to be rewritten exists, rewriting the corresponding subarea to be rewritten based on each annotation rewriting information, and then executing step S10;
step S9, based on D 1 Rewriting the second display area;
step S10, setting D 0 ＝D 1 ，M 0 ＝M 1 Step S3 is executed back.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having stored therein computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the annotation region reuse display method, equipment and medium for the variable chip design codes can achieve quite technical progress and practicality, and has wide industrial utilization value, and the method has at least the following beneficial effects:
according to the invention, the visual interface is longitudinally divided into the first display area and the second display area, the chip design code and the annotation information are decoupled, the display of the annotation information is more flexible and compact through the two areas, and the annotation information displayed in the second display area is reused as much as possible in the process of changing the chip design code, so that the interface utilization rate and the display efficiency of the annotation information display of the variable chip design code are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for displaying the reuse of annotation regions of variable chip design codes according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides an annotation region reuse display method of a variable chip design code, which is shown in fig. 1 and comprises the following steps:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, the second display area is used for displaying annotation information corresponding to the chip design codes, the chip design codes need to display annotation code rows of annotated code rows to be displayed, the second display area comprises subareas with the same number as the annotation code rows to be displayed, and each subarea is used for displaying the annotation information of one corresponding annotation code row to be displayed.
The chip design code displayed in the first display area includes a code line that needs to display the annotation, and also includes a code line that does not need to display the annotation. It can be understood that the maximum number of lines that can be displayed in the first display area and the second display area is the same, and if the total number of lines that can be displayed in the first display area by the chip design code is R, the total number of lines that can be displayed in the second display area is also R.
S2, acquiring an annotation code line information set D to be displayed, corresponding to the chip design code initially displayed in the first display area 0 And the total number M of the signal numbers corresponding to all the annotation code lines to be displayed 0 。
It can be understood that, when the chip design code is initially displayed in the first display area, the annotation information corresponding to the initially displayed chip design code is correspondingly displayed in the second display area.
Step S3, if the chip design code in the first display area is changed, acquiring an annotation code line information set D to be displayed corresponding to the chip design code after the first display area is changed 1 And the total number M of the signal numbers corresponding to all the annotation code lines to be displayed 1 。
Step S4, comparison D 0 And D 1 Comparison of M 0 And M 1 If D 0 And D 1 The number of elements in (a) is not equal, and/or M 0 And M 1 If not, step S9 is performed, otherwise, i=1 is set, and step S5 is performed.
If D 0 And D 1 If the number of the elements in the first display area is not equal, the number of lines of the annotation code to be displayed corresponding to the first display area is changed, and the number of sub-areas in the second display area is also changed, so that the second display area needs to be redrawn, and the second display area corresponding to the initially displayed chip design code cannot be reused. In addition, in the process of displaying the annotation information in the second display area, there is a possibility that the number of lines in the second display area is insufficient to display all the annotation information, and when the number of lines is insufficient to display all the annotation information, a part of the annotation information needs to be hidden. Indicating that the total line number of the annotation information has changed, at this time, the method determines how the annotation information is hidden next, so that M 0 And M 1 When not equal, the second display area also needs to be redrawn. When D is 0 And D 1 The number of elements in (a) is equal and M 0 And M 1 When equal, then a further determination is made as to which sub-regions of the second display area can be reused.
Step S5, comparison D 0 The ith element d of (b) i 0 And D 1 The ith element d of (b) i 1 If d i 0 And d i 1 Consistency ofStep S7 is executed, otherwise step S6 is executed.
Wherein d i 0 And d i 1 If they are consistent, then the current d is described i 0 The annotation information of the sub-region in the second display area can be fully reused, i.e. d i 0 The annotation information of the structure of the corresponding sub-region can be reused.
Step S6, determining an ith subarea in the second display area as a subarea to be rewritten, based on d i 1 The annotation overwrite information is generated and step S7 is performed.
And generating corresponding annotation rewriting information for the subarea needing to be rewritten.
Step S7, if i<J, i=i+1 is set, and the process returns to step S5, and if i=j, step S8 is executed, J being D 0 Corresponding to the total number of annotation code line information to be displayed.
And S8, if the subarea to be rewritten exists, rewriting the corresponding subarea to be rewritten based on each annotation rewriting information, and then executing the step S10.
Step S9, based on D 1 The second display area is rewritten.
Step S10, setting D 0 ＝D 1 ，M 0 ＝M 1 Step S3 is executed back.
Through the steps S1-S10, the annotation information displayed in the second display area can be reused as much as possible when the chip design code is changed, so that the interface utilization rate and the display efficiency of the annotation information display of the variable chip design code are improved.
The specific implementation of step S1 to step S10 will be described in detail below by means of two examples.
Embodiment 1,
In a first embodiment, the changing manner of the chip design code in the first display area includes that the chip design code row presented in the first display area is changed, and in this embodiment, the parameter of each chip code row is default to be not adjusted, and the chip design code in the first display area is changed only by folding, folding the chip design code row, or operating the longitudinal scroll bar of the first display area. The chip design codes initially displayed in the first display area have U rows, and the step S2 includes:
step S21, initialize D 0 Is empty, M 0 ＝0,u＝1,j＝0。
Step S22, if the u-th line chip design code B in the first display area u If there is a signal variable, then set j=j+1, then set B u ＝A j Step S23 is performed, otherwise step S24 is performed.
It should be noted that, the chip design code with signal variable is the annotation code line to be displayed.
Step S23, obtaining A j Corresponding physical line number T j 0 And A j Number of corresponding signal variables m j 0 Setting M 0 ＝M 0 +m j 0 Step S24 is performed.
The line content of the chip design code may be divided into visible lines and physical lines, where the physical lines correspond to lines of the real text file and the visible lines correspond to lines visible on the interface. When the folding function exists in the interface, the physical line of the file cannot be obtained through simple line number addition and subtraction. Such as: visible rows 12, 13, 14 may be 12, 13, and 37 for physical rows, i.e., 23 physical rows are hidden from view after visible row 13.
Step S24, if u<U=u+1 is set, and the process returns to step S22, and if u=u, D is generated 0 And M 0 。
The step S2 generates D based on the steps S21 to S24 0 And M 0 Wherein D is 0 ＝{(T 1 0 ,m 1 0 ),(T 2 0 ,m 2 0 ),…,(T j 0 ,m j 0 ),…,(T J 0 ,m J 0 ) (T) therein j 0 ,m j 0 ) J-th annotation code row A to be displayed corresponding to chip design code for initial display j T j 0 Is A j Corresponding physical line number, m j 0 Is A j The corresponding signal variable quantity, J has a value range of 1 to J, J is the total number of annotation code lines to be displayed in the chip design code initially displayed, M 0 For all m j 0 Is a sum of (a) and (b).
The step S3 adopts the same method as the step S21 to the step S24 to generate D 1 And M 1 The total number of codes in the changed chip design code is W, specifically, the step S3 includes:
step S31, initialize D 1 Is empty, M 1 ＝0,w＝1,n＝0。
Step S32, if the w-th row chip design code B in the first display area w If there is a signal variable, then set n=n+1, then set B w ＝A n Step S33 is performed, otherwise step S34 is performed.
It should be noted that, the chip design code with signal variable is the annotation code line to be displayed.
Step S33, obtaining A n Corresponding physical line number T n 1 And A n Number of corresponding signal variables m n 1 Setting M 1 ＝M 1 +m n 1 Step S34 is performed.
Step S34, if w<W is set to w=w+1, the process returns to step S32, and if w=w, D is generated 1 And M 1 。
Wherein D is 1 ＝{(T 1 1 ,m 1 1 ),(T 2 1 ,m 2 1 ),…,(T n 1 ,m n 1 ),…,(T N 1 ,m N 1 ) (T) therein n 1 ,m n 1 ) N-th annotating code row C to be displayed corresponding to changed chip design code n T n 1 Is C n Physical line number, m n 1 Is C n The corresponding signal variable quantity, the value range of N is 1 to N, and N is the annotation generation to be displayed in the changed chip design codeTotal number of code lines M 1 For all m n 1 Is a sum of (a) and (b).
The step S5 includes:
step S51, obtain D 0 The ith element d of (b) i 0 Corresponding T i 0 D (D) 1 The ith element d of (b) i 1 Corresponding T i 1 If T i 0 ＝T i 1 Then determine d i 0 And d i 1 If it is consistent, execute step S7, if T i 0 ≠T i 1 Step S52 is performed.
It should be noted that, since the parameters of each chip code line are not adjusted, when T i 0 ＝T i 1 Then d can be determined i 0 And d i 1 Consistent, when d i 0 And d i 1 And when the sub-areas are consistent, the sub-areas corresponding to the second display area can be completely multiplexed without overwriting.
Step S52, obtain D 0 The ith element d of (b) i 0 Corresponding m i 0 D (D) 1 The ith element d of (b) i 1 Corresponding m i 1 If m i 0 ＝m i 1 Step S6 is performed, otherwise step S9 is performed.
It should be noted that when T i 0 ≠T i 1 And m is i 0 ＝m i 1 When the method is used, although the physical lines corresponding to the subareas before and after the change are different and the corresponding annotation information is different, the structures of the subareas can be multiplexed, and only the annotation information in the subarea structures needs to be replaced, so that the display efficiency is improved. If m is i 0 ≠m i 1 The architecture of the sub-region is not reusable either, and D-based is required 1 The second display area is rewritten.
Embodiment II,
In a second embodiment, the changing manner of the chip design code in the first display area includes that the chip design code line presented in the first display area is changed, and the annotation code line to be displayed corresponds to the addition, deletion or update of the signal variable. The chip design codes initially displayed in the first display area have U rows, and the step S2 includes:
step S201, initializing D 0 Is empty, M 0 ＝0,u＝1,j＝0。
Step S202, if the u-th line of chip design codes B in the first display area u If there is a signal variable, then set j=j+1, then set B u ＝A j Step S203 is executed, otherwise step S204 is executed.
Step S203, obtain A j Corresponding physical line number T j 0 List of signal variables L j 0 And A j Number of corresponding signal variables m j 0 Setting M 0 ＝M 0 +m j 0 Step S204 is performed.
Wherein, the signal variable list L j 0 Includes A j All signal variable identifiers in the list L of signal variables j 0 The number of signal variables in the system is m j 0 。
Step S204, if u<U=u+1 is set, and the process returns to step S202, and if u=u, D is generated 0 And M 0 。
Generating D based on step S201 to step S204 0 And M 0 Wherein D is 0 ＝{(T 1 0 ,L 1 0 ,m 1 0 ),(T 2 0 ,L 2 0 ,m 2 0 ),…,(T j 0 ,L j 0 ,m j 0 ),…,(T J 0 ,L J 0 ,m J 0 ) (T) therein j 0 ,L j 0 ,m j 0 ) J-th annotation code row A to be displayed corresponding to chip design code for initial display j T j 0 Is A j Corresponding physicalLine number, L j 0 Is A j Corresponding signal variable list, m j 0 Is A j The value range of J is 1 to J, J is the total number of annotation code lines to be displayed in the chip design code which is initially displayed, M 0 For all m j 0 Is a sum of (a) and (b).
The step S3 adopts the same method as the step S201 to the step S204 to generate D 1 And M 1 The total number of rows in the changed chip design code is W, specifically,
the step S3 includes:
step S301, initialize D 1 Is empty, M 1 ＝0,w＝1,n＝0。
Step S302, if the w-th row chip design code B in the first display area w If there is a signal variable, then set n=n+1, then set B w ＝A n Step S303 is executed, otherwise step S304 is executed.
Step S303, obtaining A n Corresponding physical line number T n 1 List of signal variables L n 1 And A n Number of corresponding signal variables m n 1 Setting M 1 ＝M 1 +m n 1 Step S304 is performed.
Wherein, the signal variable list L n 1 Includes A n All signal variable identifiers in the list L of signal variables n 1 The number of signal variables in the system is m n 1 。
Step S304, if w<W is set to w=w+1, the process returns to step S302, and if w=w, D is generated 1 And M 1 。
D 1 ＝{(T 1 1 ,L 1 1 ,m 1 1 ),(T 2 1 ,L 2 1 ,m 2 1 ),…,(T n 1 ,L n 1 ,m n 1 ),…,(T N 1 ,L N 1 ,m N 1 ) And } wherein,(T n 1 ,L n 1 ,m n 1 ) Is that
N-th annotation code line C to be displayed corresponding to changed chip design code n T n 1 Is C n Physical line number L of (1) n 1 Is C n Signal variable list, m n 1 Is C n The corresponding signal variable number in the signal variable list is that the value range of N is 1 to N, N is the total number of annotation code lines to be displayed in the changed chip design code, M 1 For all m n 1 Is a sum of (a) and (b).
As an example, the step S5 includes:
step S501, obtain D 0 The ith element d of (b) i 0 Corresponding T i 0 D (D) 1 The ith element d of (b) i 1 Corresponding T i 1 If T i 0 ＝T i 1 Step S502 is executed, if T i 0 ≠T i 1 Step S503 is performed.
It should be noted that, since the corresponding signal variable of the annotation code line to be displayed may involve addition, deletion or update, when T i 0 ＝T i 1 It is further necessary to determine whether the signal list has changed to determine whether d i 0 And d i 1 And consistent.
Step S502, obtain D 0 The ith element d of (b) i 0 Corresponding L j 0 And D 1 The ith element d of (b) i 1 Corresponding L n 1 If L j 0 ＝L n 1 Then determine d i 0 And d i 1 If the two values are consistent, step S7 is executed, if L j 0 ≠L n 1 Step S503 is performed.
Wherein when T i 0 ＝T i 1 And L is j 0 ＝L n 1 Can only determine d i 0 And d i 1 Consistent, when d i 0 And d i 1 And when the sub-areas are consistent, the sub-areas corresponding to the second display area can be completely multiplexed without overwriting.
Step S503, obtaining D 0 The ith element d of (b) i 0 Corresponding m i 0 D (D) 1 The ith element d of (b) i 1 Corresponding m i 1 If m i 0 ＝m i 1 Step S6 is performed, otherwise step S9 is performed.
It should be noted that, although the physical rows and/or the signal lists corresponding to the sub-regions before and after the change, the annotation row numbers corresponding to the sub-regions are the same, and the sub-region structure can be multiplexed, only the annotation information in the sub-region structure needs to be replaced, so that the display efficiency is improved. If m is i 0 ≠m i 1 The architecture of the sub-region is not reusable either, and D-based is required 1 The second display area is rewritten.
Based on D 0 Rendering a second display area or based on D 1 The second display area is rewritten, and a conventional drawing method may be used, or a drawing method of the following example may be used.
The embodiment of the invention further provides a second display area drawing method, which comprises the following steps:
and C1, longitudinally dividing the visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, and the second display area is used for displaying annotation information corresponding to the chip design codes.
Step C2, obtaining the j-th annotation code A to be displayed in the chip design code displayed in the first display area j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) The chip design code is displayed in a first display area, wherein the total display line number of the chip design code displayed in the first display area is R; t (T) i Is A j Corresponding physical line number in chip design code, annotation to be displayedCode behavior requires displaying annotated code lines; x is x j Is A j The number of lines of the annotation to be written, vx, corresponding to the second display area j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j ＝x j ；W j In order to the J-th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is 1 to J, wherein J is the total number of the code lines to be displayed in the currently displayed chip design code, J is less than or equal to R, and 1 is less than or equal to T i ≤R。
As an example, the step C2 includes:
step C21, initializing r=1, j=0, w j =0, step C22 is performed.
Step C22, obtaining the r-th row of design codes B in the chip design codes displayed in the first display area r If B r If there is a signal variable, then set j=j+1, set a j ＝B r Step C23 is performed, otherwise step C25 is performed.
Step C23, obtaining A j Corresponding physical line number T i Number of signals G j Sum signal variable list L j 。
Step SC4, G-based j Acquisition A j The number of lines x of the annotation to be written corresponding to the second display area j ，Wherein m is the number of notes that each line of the second display area can display, ">Representing the rounding up, setting Vx j ＝x j Setting W j ＝W j +x j Based on A j Corresponding T j ,x j ,Vx j ,W j Generation A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Step C25 is performed.
Step C25, if R < R, r=r+1 is set, and step C22 is executed, and if r=r, step C3 is executed.
Step C3, contrast W J And R, if W J And (3) R is not more than, directly executing the step C5, otherwise, executing the step C4.
Step C4, updating at least one Vx j So that all Vx j Is equal to R, and then step C5 is performed.
As an example, the step C4 includes:
step C41, obtaining the number of lines h of the line annotation to be hidden, where h=w J -R, set i=j, perform step C42;
step C42, if Vx i If L is less than or equal to L, executing a step C45, otherwise, executing a step C43, wherein L is the preset minimum annotation display line number corresponding to each annotation code to be displayed;
step C43, if x-L is greater than or equal to h, setting Vx i ＝x i -h, and setting h=0, jumping to step C5, otherwise, executing step C44;
step C44, setting Vx i =l, set h=h- (x) i -L), if h=0, jump to step C5, if h>0, executing step C45;
step C45, if i >1, set i=i-1, and return to step C41.
Step C5, displaying each A in the second display area j Corresponding to Vx j Line annotation information.
As an example, the step C5 includes:
step C51, transversely dividing the second display area into J sub-areas A j And B is connected with j Associated, B j A j-th sub-region of the second display region;
step C52, at B j Middle display A j Corresponding Vx j Line annotation information.
And each subarea of the second display area is provided with a corresponding transverse scroll bar and a corresponding longitudinal scroll bar, annotation information which is transversely displayed in the corresponding subarea is adjusted through operating the transverse scroll bar, and annotation information which is longitudinally displayed in the corresponding subarea is adjusted through operating the longitudinal scroll bar.
If in step C45 i=1 and h >0, then step C5 includes:
step C50, starting with j=1, according to the current Vx i Value the second display area displays A j Corresponding annotation information, when the total number of lines displaying the annotation information reaches R, the rest A is not displayed any more j Is provided.
According to the second display area drawing method, a visual interface is longitudinally divided into a first display area and a second display area, chip design codes and annotation information are decoupled, annotation information corresponding to all to-be-displayed annotation code lines in the first display area is displayed in the second display area as much as possible, when the second annotation display area is insufficient for display, the to-be-displayed annotation code lines in the first display area are covered as much as possible through adjustment of a hiding algorithm, and the to-be-displayed annotation code lines in the first display area are covered maximally. In addition, the display of the annotation information is more flexible and compact through the display of the two areas, and the corresponding annotation information is displayed based on the four-tuple information of each annotation code to be displayed in the chip design code displayed in the first display area by acquiring the four-tuple information of each annotation code to be displayed, so that the interface utilization rate and the display effect of the chip design annotation information display are improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
According to the embodiment of the invention, the visual interface is longitudinally divided into the first display area and the second display area, the chip design code and the annotation information are decoupled, the display of the annotation information is more flexible and compact through the display of the two areas, and the annotation information displayed in the second display area is reused as much as possible in the process of changing the chip design code, so that the interface utilization rate and the display efficiency of the annotation information display of the variable chip design code are improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (9)
1. An annotation region reuse display method of a variable chip design code, comprising the steps of:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, the second display area is used for displaying annotation information corresponding to the chip design codes, the chip design codes need to display annotation code rows of annotated code rows to be displayed, the second display area comprises subareas with the same number as the annotation code rows to be displayed, and each subarea is used for displaying the annotation information of one corresponding annotation code row to be displayed;
s2, obtaining a chip design code initially displayed in the first display areaCorresponding annotation code line information set D to be displayed 0 And the total number M of the signal numbers corresponding to all the annotation code lines to be displayed 0 ；
Step S3, if the chip design code in the first display area is changed, acquiring an annotation code line information set D to be displayed corresponding to the chip design code after the first display area is changed 1 And the total number M of the signal numbers corresponding to all the annotation code lines to be displayed 1 ；
Step S4, comparison D 0 And D 1 Comparison of M 0 And M 1 If D 0 And D 1 The number of elements in (a) is not equal, and/or M 0 And M 1 If not, executing step S9, otherwise, setting i=1, and executing step S5;
step S5, comparison D 0 The ith element d of (b) i 0 And D 1 The ith element d of (b) i 1 If d i 0 And d i 1 If the two values are consistent, executing the step S7, otherwise, executing the step S6;
step S6, determining an ith subarea in the second display area as a subarea to be rewritten, based on d i 1 Generating annotation rewriting information, and executing step S7;
step S7, if i<J, i=i+1 is set, and the process returns to step S5, and if i=j, step S8 is executed, J being D 0 Corresponding to the total number of annotation code line information to be displayed;
step S8, if the subarea to be rewritten exists, rewriting the corresponding subarea to be rewritten based on each annotation rewriting information, and then executing step S10;
step S9, based on D 1 Rewriting the second display area;
step S10, setting D 0 ＝D 1 ，M 0 ＝M 1 Step S3 is executed back.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the changing manner of the chip design code in the first display area includes that the chip design code rows presented in the first display area are changed, the chip design code initially displayed in the first display area has U rows, and the step S2 includes:
step S21, initialize D 0 Is empty, M 0 ＝0,u＝1,j＝0；
Step S22, if the u-th line chip design code B in the first display area u If there is a signal variable, then set j=j+1, then set B u ＝A j Step S23 is executed, otherwise step S24 is executed;
step S23, obtaining A j Corresponding physical line number T j 0 And A j Number of corresponding signal variables m j 0 Setting M 0 ＝M 0 +m j 0 Step S24 is performed;
step S24, if u<U=u+1 is set, and the process returns to step S22, and if u=u, D is generated 0 And M 0 。
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the step S2 generates D based on the steps S21 to S24 0 And M 0 Wherein, the method comprises the steps of, wherein,
D 0 ＝{(T 1 0 ,m 1 0 ),(T 2 0 ,m 2 0 ),…,(T j 0 ,m j 0 ),…,(T J 0 ,m J 0 ) (T) therein j 0 ,m j 0 ) J-th annotation code row A to be displayed corresponding to chip design code for initial display j T j 0 Is A j Corresponding physical line number, m j 0 Is A j The corresponding signal variable quantity, J has a value range of 1 to J, J is the total number of annotation code lines to be displayed in the chip design code initially displayed, M 0 For all m j 0 Is the sum of (3);
the step S3 adopts the same method as the step S21 to the step S24 to generate D 1 And M 1 Wherein, the method comprises the steps of, wherein,
D 1 ＝{(T 1 1 ,m 1 1 ),(T 2 1 ,m 2 1 ),…,(T n 1 ,m n 1 ),…,(T N 1 ,m N 1 ) (T) therein n 1 ,m n 1 ) N-th annotating code row C to be displayed corresponding to changed chip design code n T n 1 Is C n Physical line number, m n 1 Is C n The corresponding signal variable quantity, the value range of N is 1 to N, N is the total number of annotation code lines to be displayed in the changed chip design code, M 1 For all m n 1 Is a sum of (a) and (b).
4. The method of claim 3, wherein the step of,
the step S5 includes:
step S51, obtain D 0 The ith element d of (b) i 0 Corresponding T i 0 D (D) 1 The ith element d of (b) i 1 Corresponding T i 1 If T i 0 ＝T i 1 Then determine d i 0 And d i 1 If it is consistent, execute step S7, if T i 0 ≠T i 1 Step S52 is performed;
step S52, obtain D 0 The ith element d of (b) i 0 Corresponding m i 0 D (D) 1 The ith element d of (b) i 1 Corresponding m i 1 If m i 0 ＝m i 1 Step S6 is performed, otherwise step S9 is performed.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the changing mode of the chip design code in the first display area comprises that the chip design code row presented in the first display area is changed, and the annotation code row to be displayed corresponds to the addition, deletion or update of the signal variable; the chip design codes initially displayed in the first display area have U rows, and the step S2 includes:
step S201, initializing D 0 Is empty, M 0 ＝0,u＝1,j＝0；
Step S202, if the u-th line of chip design codes B in the first display area u If there is a signal variable, then set j=j+1, then set B u ＝A j Step S203 is executed, otherwise, step S204 is executed;
step S203, obtain A j Corresponding physical line number T j 0 List of signal variables L j 0 And A j Number of corresponding signal variables m j 0 Setting M 0 ＝M 0 +m j 0 Step S204 is performed;
step S204, if u<U=u+1 is set, and the process returns to step S202, and if u=u, D is generated 0 And M 0 。
6. The method of claim 5, wherein the step of determining the position of the probe is performed,
the step S2 generates D based on the steps S201 to S204 0 And M 0 Wherein, the method comprises the steps of, wherein,
D 0 ＝{(T 1 0 ,L 1 0 ,m 1 0 ),(T 2 0 ,L 2 0 ,m 2 0 ),…,(T j 0 ,L j 0 ,m j 0 ),…,(T J 0 ,L J 0 ,m J 0 ) (T) therein j 0 ,L j 0 ,m j 0 )
J-th annotation code row A to be displayed corresponding to chip design code for initial display j T j 0 Is A j Corresponding physical line number, L j 0 Is A j A list of corresponding signal variables is provided,m j 0 is A j The value range of J is 1 to J, J is the total number of annotation code lines to be displayed in the chip design code which is initially displayed, M 0 For all m j 0 Is the sum of (3);
the step S3 adopts the same method as the step S201 to the step S204 to generate D 1 And M 1 Wherein, the method comprises the steps of, wherein,
D 1 ＝{(T 1 1 ,L 1 1 ,m 1 1 ),(T 2 1 ,L 2 1 ,m 2 1 ),…,(T n 1 ,L n 1 ,m n 1 ),…,(T N 1 ,L N 1 ,m N 1 ) (T) therein n 1 ,L n 1 ,m n 1 )
N-th annotating code row C to be displayed corresponding to changed chip design code n T n 1 Is C n Physical line number L of (1) n 1 Is C n Signal variable list, m n 1 Is C n The corresponding signal variable number in the signal variable list is that the value range of N is 1 to N, N is the total number of annotation code lines to be displayed in the changed chip design code, M 1 For all m n 1 Is a sum of (a) and (b).
7. The method of claim 6, wherein the step of providing the first layer comprises,
the step S5 includes:
step S501, obtain D 0 The ith element d of (b) i 0 Corresponding T i 0 D (D) 1 The ith element d of (b) i 1 Corresponding T i 1 If T i 0 ＝T i 1 Step S502 is executed, if T i 0 ≠T i 1 Step S503 is executed;
step S502, obtain D 0 I of (a)Element d i 0 Corresponding L j 0 And D 1 The ith element d of (b) i 1 Corresponding L n 1 If L j 0 ＝L n 1 Then determine d i 0 And d i 1 If the two values are consistent, step S7 is executed, if L j 0 ≠L n 1 Step S503 is executed;
step S503, obtaining D 0 The ith element d of (b) i 0 Corresponding m i 0 D (D) 1 The ith element d of (b) i 1 Corresponding m i 1 If m i 0 ＝m i 1 Step S6 is performed, otherwise step S9 is performed.
8. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-7.
9. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-7.
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