CN116822427A - Time sequence analysis method and device, electronic equipment and storage medium - Google Patents
Time sequence analysis method and device, electronic equipment and storage medium Download PDFInfo
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- 238000012300 Sequence Analysis Methods 0.000 title claims abstract description 82
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
Abstract
The invention provides a time sequence analysis method, a time sequence analysis device, electronic equipment and a storage medium, and relates to the technical field of electronic design automation. The method comprises the following steps: dividing the target integrated circuit diagram into a plurality of sub-circuit diagrams, wherein each sub-circuit diagram comprises at least one circuit module; according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, the circuit structures of the plurality of sub-circuit diagrams are adjusted, and a plurality of target sub-circuit diagrams are obtained; transmitting a plurality of target sub-circuit diagrams to a plurality of slave node devices, so that each slave node device performs static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result; and determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results. The time sequence analysis efficiency is improved, the time sequence analysis can be independently carried out on each sub-circuit diagram, the communication and the data transmission in the time sequence analysis process are reduced, and the system performance is improved.
Description
Technical Field
The invention relates to the technical field of electronic design automation, in particular to a time sequence analysis-based method, a time sequence analysis-based device, electronic equipment and a storage medium.
Background
Static timing analysis (static timing analysis, STA) is a method of analyzing the timing behavior of a circuit, which is independent of specific inputs and can analyze all timing paths of the circuit, which is a key step in the chip design process.
In the related art, when a designed chip is large, a plurality of computers are adopted to perform time sequence analysis on a circuit diagram of the chip in parallel, and in the process of time sequence analysis, a large amount of communication and data transmission are needed to be performed among the computers.
However, in the related art, when a plurality of computers perform time sequence analysis in parallel, a large amount of communication and data transmission are required, and system performance is reduced.
Disclosure of Invention
The present invention is directed to a method, an apparatus, an electronic device, and a storage medium for timing analysis, which solve the above-mentioned problems of the related art.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:
In a first aspect, an embodiment of the present invention provides a timing analysis method, which is applied to a master node device, including:
dividing the target integrated circuit diagram into a plurality of sub-circuit diagrams, wherein each sub-circuit diagram comprises at least one circuit module;
adjusting the circuit structures of the plurality of sub-circuit diagrams according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams, wherein the time sequence path relation is used for representing the time sequence signal transmission paths between every two sub-circuit diagrams, and the data path relation is used for representing the data transmission paths between every two sub-circuit diagrams;
transmitting the target sub-circuit diagrams to a plurality of slave node devices so that each slave node device performs static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result;
and determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results.
Optionally, the dividing the target integrated circuit diagram into a plurality of sub-circuit diagrams includes:
dividing the target integrated circuit diagram into a plurality of first sub-circuit diagrams according to circuit modules in the target integrated circuit, wherein at least one circuit module in each first sub-circuit diagram;
And dividing the first sub-circuit diagram again according to the number of sub-circuit modules in each first sub-circuit diagram to obtain a plurality of sub-circuit diagrams, wherein the number of sub-circuit modules included in each sub-circuit diagram is balanced.
Optionally, the re-dividing the first sub-circuit diagram according to the number of sub-circuit modules in the first sub-circuit diagram to obtain the plurality of sub-circuit diagrams includes:
determining second sub-circuit diagrams with the number of sub-circuit modules being greater than or equal to the preset number in the plurality of first sub-circuit diagrams;
dividing the second sub-circuit diagram to obtain a plurality of third sub-circuit diagrams;
the plurality of sub-circuit diagrams includes: the number of the sub-circuit modules included in the other first sub-circuit diagrams is the same as that of the sub-circuit modules included in the third sub-circuit diagrams, and the other first sub-circuit diagrams are circuit diagrams except for the second sub-circuit diagrams in the preset number of first sub-circuit diagrams.
Optionally, the adjusting the circuit structures of the multiple sub-circuit diagrams according to the time sequence path relationship and/or the signal path relationship between every two sub-circuit diagrams in the multiple sub-circuit diagrams to obtain multiple target sub-circuit diagrams includes:
And according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams.
Optionally, the adjusting, according to the timing path relationship between every two circuit diagrams in the plurality of sub-circuit diagrams, a circuit structure of a sub-circuit diagram with a timing path missing in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams includes:
searching a sub-circuit diagram with missing time sequence paths in the plurality of sub-circuit diagrams;
determining a first associated sub-circuit diagram associated with a time sequence path existing in the sub-circuit diagram with the missing time sequence path from the plurality of sub-circuit diagrams according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams;
and adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path according to the related components in the first related sub-circuit diagram.
Optionally, the adjusting the circuit structures of the multiple sub-circuit diagrams according to the time sequence path relationship and/or the data path relationship between every two sub-circuit diagrams in the multiple sub-circuit diagrams to obtain multiple target sub-circuit diagrams includes:
And according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, adjusting the circuit structure of the sub-circuit diagram with the missing data path in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams.
Optionally, the adjusting, according to the data path relationship between every two circuit diagrams in the plurality of sub-circuit diagrams, a circuit structure of a sub-circuit diagram with a missing data path in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams includes:
searching a sub-circuit diagram with missing data paths in the plurality of sub-circuit diagrams;
determining a second associated sub-circuit diagram providing data for the sub-circuit diagram with the missing data path from the plurality of sub-circuit diagrams according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams;
and adjusting the circuit structure of the sub-circuit diagram with the missing data path according to the associated components in the second associated sub-circuit diagram.
In a second aspect, an embodiment of the present invention further provides a timing analysis apparatus, which is applied to a master node device, including:
a dividing module, configured to divide a target integrated circuit diagram into a plurality of sub-circuit diagrams, where each sub-circuit diagram includes at least one circuit module;
The adjustment module is used for adjusting the circuit structures of the plurality of sub-circuit diagrams according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams, wherein the time sequence path relation is used for representing the time sequence signal transmission paths between every two sub-circuit diagrams, and the data path relation is used for representing the data transmission paths between every two sub-circuit diagrams;
the transmitting module is used for transmitting the target sub-circuit diagrams to the slave node equipment so that each slave node equipment can perform static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result;
and the determining module is used for determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results.
Optionally, the dividing module is specifically configured to divide the target integrated circuit diagram into a plurality of first sub-circuit diagrams according to circuit modules in the target integrated circuit, where at least one circuit module in each first sub-circuit diagram; and dividing the first sub-circuit diagram again according to the number of sub-circuit modules in each first sub-circuit diagram to obtain a plurality of sub-circuit diagrams, wherein the number of sub-circuit modules included in each sub-circuit diagram is balanced.
Optionally, the dividing module is specifically configured to determine, from the plurality of first sub-circuit diagrams, second sub-circuit diagrams with the number of sub-circuit modules being greater than or equal to a preset number; dividing the second sub-circuit diagram to obtain a plurality of third sub-circuit diagrams; the plurality of sub-circuit diagrams includes: the number of the sub-circuit modules included in the other first sub-circuit diagrams is the same as that of the sub-circuit modules included in the third sub-circuit diagrams, and the other first sub-circuit diagrams are circuit diagrams except for the second sub-circuit diagrams in the preset number of first sub-circuit diagrams.
Optionally, the adjusting module is specifically configured to adjust a circuit structure of a sub-circuit diagram with a missing timing path in the multiple sub-circuit diagrams according to the timing path relationship between every two circuit diagrams in the multiple sub-circuit diagrams, so as to obtain the multiple target sub-circuit diagrams.
Optionally, the adjusting module is specifically configured to find a sub-circuit diagram with a missing timing path in the plurality of sub-circuit diagrams; determining a first associated sub-circuit diagram associated with a time sequence path existing in the sub-circuit diagram with the missing time sequence path from the plurality of sub-circuit diagrams according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams; and adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path according to the related components in the first related sub-circuit diagram.
Optionally, the adjusting module is specifically configured to adjust a circuit structure of a sub-circuit diagram with missing data paths in the multiple sub-circuit diagrams according to the data path relationship between every two circuit diagrams in the multiple sub-circuit diagrams, so as to obtain the multiple target sub-circuit diagrams.
Optionally, the adjusting module is specifically configured to find a sub-circuit diagram in which a data path is missing in the plurality of sub-circuit diagrams; determining a second associated sub-circuit diagram providing data for the sub-circuit diagram with the missing data path from the plurality of sub-circuit diagrams according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams; and adjusting the circuit structure of the sub-circuit diagram with the missing data path according to the associated components in the second associated sub-circuit diagram.
In a third aspect, an embodiment of the present invention further provides an electronic device, including: a memory storing a computer program executable by the processor, and a processor implementing the timing analysis method according to any one of the first aspects.
In a fourth aspect, embodiments of the present invention further provide a computer readable storage medium having a computer program stored thereon, which when read and executed, implements the timing analysis method of any of the above claims 1-7.
The beneficial effects of the invention are as follows: the embodiment of the invention provides a time sequence analysis method, which comprises the following steps: dividing the target integrated circuit diagram into a plurality of sub-circuit diagrams, wherein each sub-circuit diagram comprises at least one circuit module; according to a time sequence path relation and/or a data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, the circuit structures of the plurality of sub-circuit diagrams are adjusted to obtain a plurality of target sub-circuit diagrams, wherein the time sequence path relation is used for representing a time sequence signal transmission path between every two sub-circuit diagrams, and the data path relation is used for representing a data transmission path between every two sub-circuit diagrams; transmitting a plurality of target sub-circuit diagrams to a plurality of slave node devices, so that each slave node device performs static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result; and determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results. The plurality of slave node devices can perform parallel analysis on a plurality of target sub-circuit diagrams, so that the efficiency of time sequence analysis on the target integrated circuit diagrams is improved, and the circuit structures of the plurality of sub-circuit diagrams are adjusted based on the time sequence path relation and/or the data path relation between every two sub-circuit diagrams, so that the circuit structures contained in each sub-circuit diagram are more complete, static time sequence analysis can be independently performed on each sub-circuit diagram, communication and data transmission in the time sequence analysis process are greatly reduced, and the system performance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a timing analysis system according to an embodiment of the present invention;
FIG. 2 is a flow chart of a timing analysis method according to an embodiment of the present invention;
FIG. 3 is a flow chart of a timing analysis method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a plurality of first sub-circuit diagrams according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a plurality of sub-circuit diagrams according to an embodiment of the present invention;
FIG. 6 is a flow chart of a timing analysis method according to an embodiment of the present invention;
FIG. 7 is a flow chart of a timing analysis method according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a plurality of sub-circuit diagrams according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a target sub-circuit diagram according to an embodiment of the present application;
FIG. 10 is a flow chart of a timing analysis method according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a target sub-circuit diagram according to an embodiment of the present application
Fig. 12 is a schematic structural diagram of a timing analysis device according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship conventionally put in use of the product of the application, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
In the related art, when a designed chip is large, a plurality of computers are adopted to perform time sequence analysis on a circuit diagram of the chip in parallel, and in the process of time sequence analysis, a large amount of communication and data transmission are needed to be performed among the computers. However, in the related art, when a plurality of computers perform time sequence analysis in parallel, a large amount of communication and data transmission are required, and system performance is reduced.
Aiming at the technical problems in the related art, the embodiment of the application provides a time sequence analysis method, which can carry out static time sequence analysis on a received target sub-circuit diagram by a slave node device, can carry out parallel analysis on a plurality of target sub-circuit diagrams by a plurality of slave node devices, improves the time sequence analysis efficiency on a target integrated circuit diagram, and adjusts the circuit structure of the plurality of sub-circuit diagrams based on the path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, so that the circuit structure contained in each sub-circuit diagram is more complete, and can independently carry out static time sequence analysis on each sub-circuit diagram, thereby greatly reducing communication and data transmission in the time sequence analysis process and improving the system performance.
The following explains a timing analysis system on which the timing analysis method provided by the embodiment of the present application is based.
Fig. 1 is a schematic structural diagram of a timing analysis system according to an embodiment of the present application, as shown in fig. 1, the timing analysis system includes a master node device 10, a plurality of slave node devices 11, and a distributed file system 12, where the master node device 10 is communicatively connected to each slave node device 11, and the distributed file system 12 may include a plurality of folders, and each master node device 10 may correspond to one folder.
In some implementations, the target integrated circuit diagram is divided into a plurality of sub-circuit diagrams; according to the path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, the circuit structures of the plurality of sub-circuit diagrams are adjusted to obtain a plurality of target sub-circuit diagrams; transmitting a plurality of target sub-circuit diagrams to a plurality of slave node equipment 11, and performing static time sequence analysis on the received target sub-circuit diagrams by the slave node equipment 11 to obtain a sub-static time sequence analysis result; the master node device 10 receives a plurality of sub-static timing analysis results transmitted from the plurality of slave node devices 11; and determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results.
In the embodiment of the present application, the master node device 10 is responsible for scheduling static timing analysis tasks and storing metadata, i.e., a target integrated circuit diagram. The slave node device 11 is responsible for static timing analysis for the target sub-circuit diagram. The master node device 10 and the slave node device 11 may communicate with each other, and the slave node device 11 does not communicate with each other.
In some embodiments, the master node device 10 may store the plurality of target sub-circuit diagrams in a plurality of folders of the distributed file system 12, i.e., a distributed DB (database); the slave node device 11 may read the target sub-circuit diagram from the corresponding folder, the slave node device 11 may store the sub-static timing analysis result in the distributed file system 12, and the master node device 10 may obtain the sub-static timing analysis result from the distributed file system 12.
According to the embodiment of the application, various input files and calculation data can be efficiently stored, and the calculation resources can be automatically scheduled.
The time sequence analysis method provided by the embodiment of the application is applied to the master node device 10, and the master node device 10 can be an electronic device, and can be a terminal device or a server, and the terminal device can be any one of the following: desktop computers, notebook computers, tablet computers, smart phones, and the like.
The following explains a timing analysis method provided by the embodiment of the present application.
Fig. 2 is a flow chart of a timing analysis method according to an embodiment of the present application, as shown in fig. 2, the method may include:
s101, dividing a target integrated circuit diagram into a plurality of sub-circuit diagrams.
Wherein each sub-circuit diagram comprises at least one circuit module.
In the embodiment of the application, the target integrated circuit diagram is divided into a plurality of sub-circuit diagrams, wherein the number of circuit modules included in each sub-circuit diagram can be balanced, and the circuit modules can comprise a plurality of connected components.
It should be noted that the target integrated circuit diagram may be an integrated circuit diagram of a target chip, and the target integrated circuit diagram may be an integrated circuit diagram designed by using EDA (Electronic design automation ) software, or may be an integrated circuit diagram designed by using other software, which is not limited in particular by the embodiment of the present application.
S102, adjusting the circuit structures of the plurality of sub-circuit diagrams according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams.
Wherein, the path relation may include: timing paths and/or data paths that are required for static timing analysis.
In some embodiments, according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, the circuit structure of the sub-circuit diagram with the time sequence path missing and/or the data path missing in the plurality of sub-circuit diagrams is adjusted, so that a plurality of target sub-circuit diagrams are obtained. The sub-circuit diagram with the timing path loss and/or the data path loss refers to the sub-circuit diagram with the timing path loss and/or the data path loss in static timing analysis.
It should be noted that, according to the time sequence path relationship and/or the data path relationship between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, the circuit structures of the plurality of sub-circuit diagrams are adjusted; comprising the following steps: the circuit structures of the plurality of sub-circuit diagrams are adjusted according to the time sequence path relation, or the circuit structures of the plurality of sub-circuit diagrams are adjusted according to the data path relation, or the circuit structures of the plurality of sub-circuit diagrams are adjusted according to the time sequence path relation and the data path relation, which is not particularly limited in the embodiment of the application.
In addition, part of the circuit structures in part of the target sub-circuit diagrams among the plurality of target sub-circuit diagrams are identical, that is, identical parts exist.
In the embodiment of the application, the circuit structures of the plurality of sub-circuit diagrams are adjusted according to the time sequence path relation and/or the data path relation, and each obtained target sub-circuit diagram is more complete, namely each target sub-circuit diagram comprises a complete time sequence path and a data path, and the slave node can independently perform static time sequence analysis according to the received circuit structures in the target sub-circuit diagram, so that frequent communication and data interaction when performing the static time sequence analysis on each target sub-circuit diagram are reduced.
S103, the target sub-circuit diagrams are sent to the slave node equipment, so that each slave node equipment performs static time sequence analysis on the received target sub-circuit diagrams, and a sub-static time sequence analysis result is obtained.
The slave node devices can perform static time sequence analysis on the target sub-circuit diagrams in parallel.
In some embodiments, the master node device sends multiple target sub-circuit diagrams to multiple slave node devices respectively, and each slave node device may receive one target sub-circuit diagram and perform static timing analysis on the received one target sub-circuit diagram to obtain a sub-static timing analysis result. Of course, the master node device may also allocate at least one target sub-circuit diagram to each slave node device, which is not particularly limited by the embodiment of the present application.
It should be noted that, the slave node device may use an STA (static timing analysis ) tool to perform static timing analysis on the target sub-circuit diagram to obtain a sub-static timing analysis result.
In the embodiment of the application, the master node device and the slave node device can be computer devices.
S104, determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results.
Wherein, the static time sequence analysis on the target sub-circuit diagram may include: delay computation, timing checking, constraint checking, signal integrity analysis, and the like. Correspondingly, the sub-static time sequence analysis result comprises: delay computation results, timing check results, constraint check results, signal integrity analysis results, and the like.
In some embodiments, the master node device receives a plurality of sub-static time sequence analysis results sent by a plurality of slave node devices, and performs merging processing on the plurality of sub-static time sequence analysis results to obtain a static time sequence analysis result of the target integrated circuit diagram.
In summary, an embodiment of the present application provides a timing analysis method, including: dividing the target integrated circuit diagram into a plurality of sub-circuit diagrams, wherein each sub-circuit diagram comprises at least one circuit module; according to a time sequence path relation and/or a data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams, the circuit structures of the plurality of sub-circuit diagrams are adjusted to obtain a plurality of target sub-circuit diagrams, wherein the time sequence path relation is used for representing a time sequence signal transmission path between every two sub-circuit diagrams, and the data path relation is used for representing a data transmission path between every two sub-circuit diagrams; transmitting a plurality of target sub-circuit diagrams to a plurality of slave node devices, so that each slave node device performs static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result; and determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results. The plurality of slave node devices can perform parallel analysis on a plurality of target sub-circuit diagrams, so that the efficiency of time sequence analysis on the target integrated circuit diagrams is improved, and the circuit structures of the plurality of sub-circuit diagrams are adjusted based on the time sequence path relation and/or the data path relation between every two sub-circuit diagrams, so that the circuit structures contained in each sub-circuit diagram are more complete, static time sequence analysis can be independently performed on each sub-circuit diagram, communication and data transmission in the time sequence analysis process are greatly reduced, and the system performance is improved.
Optionally, fig. 3 is a flow chart of a timing analysis method according to an embodiment of the present application, as shown in fig. 3, a process of dividing a target integrated circuit diagram into a plurality of sub-circuit diagrams in S101 may include:
s201, dividing the target integrated circuit diagram into a plurality of first sub-circuit diagrams according to the circuit modules in the target integrated circuit.
Wherein at least one circuit module in each first sub-circuit diagram.
In the embodiment of the present application, the circuit modules included in each of the first circuit diagrams may be the same, but the number of sub-circuit modules included in the circuit modules in some of the first circuit diagrams is large, and the first circuit diagrams need to be divided again, that is, the following process of S202 needs to be performed.
Fig. 4 is a schematic structural diagram of a plurality of first sub-circuit diagrams according to an embodiment of the present application, as shown in fig. 4, the process of S201 is performed, and the target integrated circuit is divided into three first sub-circuit diagrams, i.e. A, B and C, where the size of C in fig. 4 is larger than the size of A, B, and the number of sub-circuit modules included in C is large.
S202, dividing the first sub-circuit diagrams again according to the number of sub-circuit modules in each first sub-circuit diagram to obtain a plurality of sub-circuit diagrams.
Wherein the number of sub-circuit modules included in each sub-circuit diagram is balanced.
In addition, the target integrated circuit may be referred to as design, and the plurality of sub-circuits may be referred to as sg (sub graph).
In some embodiments, according to the number of sub-circuit modules in each first sub-circuit diagram, determining a first sub-circuit diagram needing to be divided again, namely a second sub-circuit diagram, from a plurality of first sub-circuit diagrams, and dividing the second sub-circuit diagram to obtain a plurality of sub-circuit diagrams.
Fig. 5 is a schematic structural diagram of a plurality of sub-circuit diagrams provided in an embodiment of the present invention, where, as shown in fig. 5, the sub-circuit modules in C in fig. 4 include two sub-circuit modules, a and B each include one sub-circuit diagram module, and C is taken as a second sub-circuit diagram, and C in fig. 4 is divided again to obtain D and E, where the plurality of sub-circuit diagrams include: A. b, D, E.
Optionally, fig. 6 is a flow chart of a timing analysis method provided in an embodiment of the present invention, as shown in fig. 6, the first sub-circuit diagram is divided again according to the number of sub-circuit modules in the first sub-circuit diagram, so as to obtain a plurality of sub-circuit diagrams, including:
s301, determining second sub-circuit diagrams with the number of sub-circuit modules being greater than or equal to the preset number in the plurality of first sub-circuit diagrams.
In some embodiments, the number of sub-circuit modules in each first sub-circuit diagram is determined, and whether the number of sub-circuit modules in each first sub-circuit diagram is greater than a preset number is determined, and if yes, the first sub-circuit diagram is determined to be a second sub-circuit diagram.
It should be noted that the preset number may be set according to actual requirements, for example, the preset number may be 2, as shown in fig. 4, where the sub-circuit modules in C include two sub-circuit modules, and C is the second sub-circuit diagram.
In addition, since the number of sub-circuit blocks included in the second sub-circuit diagram is large, the second sub-circuit diagram may be regarded as a larger sub-circuit diagram among the plurality of first sub-circuit diagrams, and the second sub-circuit diagram needs to be divided again in order to make the plurality of sub-circuit diagrams more uniform.
S302, dividing the second sub-circuit diagram to obtain a plurality of third sub-circuit diagrams.
Wherein the plurality of sub-circuit diagrams includes: the first sub-circuit diagrams are the same as the third sub-circuit diagrams in number, and the first sub-circuit diagrams are circuit diagrams except the second sub-circuit diagrams in the preset number.
In some embodiments, the second sub-circuit diagram may be divided according to the number of sub-circuit modules in the other first sub-circuit diagram, so that the number of sub-circuit modules included in the third sub-circuit diagram is the same as the number of sub-circuit modules included in the other first sub-circuit diagram.
As shown in fig. 4, C is a second sub-circuit diagram, and D and E are obtained by dividing C, where D and E are a plurality of third sub-circuit diagrams, and the other first sub-circuit diagrams include: a and B, as shown in fig. 5, the plurality of sub-circuit diagrams includes: other first sub-circuit diagram A, B and a plurality of third sub-circuit diagrams D, E.
In the embodiment of the present application, the number of the sub-circuit modules included in each of the plurality of sub-circuit diagrams is the same, and the above-mentioned processes S301 to S302 implement dynamic adjustment of the number of the plurality of sub-circuit diagrams, so that the size of each sub-circuit diagram is more balanced.
Optionally, in the step S102, the process of adjusting the circuit structures of the multiple sub-circuit diagrams according to the time sequence path relationship and/or the signal path relationship between every two sub-circuit diagrams in the multiple sub-circuit diagrams to obtain multiple target sub-circuit diagrams may include:
and according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams.
The sub-circuit diagram with missing timing paths refers to the incomplete timing paths when the sub-circuit diagram performs timing analysis.
It should be noted that, the multiple sub-circuit diagrams are obtained based on the equalization division of the circuit module and the sub-circuit module, some sub-circuit diagrams with missing time sequence paths exist in the multiple sub-circuit diagrams, different sub-circuit diagrams run on different slave node devices, if the time sequence paths of the sub-circuit diagrams have missing time sequence paths, the sub-circuit diagrams with missing time sequence paths need to be frequently interacted with the associated sub-circuit diagrams to normally perform static time sequence analysis.
In the embodiment of the application, the circuit structure of each target sub-circuit diagram is adjusted according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, so that the time sequence path of each obtained target sub-circuit diagram is more complete, the data interaction between the slave node equipment and other slave node equipment when static time sequence analysis is carried out based on the target sub-circuit diagram is reduced, and the system performance is improved.
Optionally, fig. 7 is a flow chart of a timing analysis method provided in an embodiment of the present application, as shown in fig. 7, a process for adjusting a circuit structure of a sub-circuit diagram having a timing path missing in a plurality of sub-circuit diagrams according to a timing path relationship between every two circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams may include:
S401, searching a sub-circuit diagram with missing time sequence paths in the plurality of sub-circuit diagrams.
And taking the sub-circuit diagram with incomplete time sequence paths in the plurality of sub-circuit diagrams as the sub-circuit diagram with missing time sequence paths.
S402, determining a first associated sub-circuit diagram associated with a time sequence path in the sub-circuit diagram with the missing time sequence path from the plurality of sub-circuit diagrams according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams.
The first related sub-circuit diagram comprises a timing path missing from the sub-circuit diagram with the missing timing path. Specifically, the circuit module in the first associated sub-circuit diagram includes a timing path missing from the sub-circuit diagram in which the timing path is missing.
It should be noted that, the first related sub-circuit diagram and the circuit modules in the sub-circuit diagram may form a path, and the first related sub-circuit diagram may be a sub-circuit diagram adjacent to the sub-circuit diagram with the missing timing path, or may be a sub-circuit diagram at an upper layer of the sub-circuit diagram with the missing timing path, which is not particularly limited in the embodiment of the present application.
S403, according to the related components in the first related sub-circuit diagram, the circuit structure of the sub-circuit diagram with the missing timing path is adjusted.
In some embodiments, the related components and the connection relation between the related components in the first related sub-circuit diagram are duplicated, and the circuit structure of the sub-circuit diagram with the missing time sequence path is complemented according to duplicated content, so that the time sequence path of the obtained target sub-circuit diagram is more complete.
In the embodiment of the application, under the condition of ensuring the division balance of a plurality of target sub-circuit diagrams, the integrity of the time sequence paths of the target sub-circuit diagrams is also considered, so that a plurality of slave node devices can perform efficient static time sequence analysis according to the plurality of target sub-circuit diagrams, and communication and interaction in the static time sequence analysis process are reduced.
It is worth noting that there is an overlap between the target sub-circuit diagrams, which is reasonable.
Fig. 8 is a schematic structural diagram of a plurality of sub-circuit diagrams according to an embodiment of the present application, where, as shown in fig. 8, the plurality of sub-circuit diagrams include: the sub-circuit diagram a and the sub-circuit diagram B include the component 20 and the component 21, the sub-circuit diagram B includes the component 22, the component 23, and the component 24, and the sub-circuit diagram 25, which is not divided into the sub-circuit diagrams, in the target integrated circuit is also included in fig. 8. The sub-circuit diagram B in fig. 8 is a sub-circuit diagram in which the timing path is missing, the sub-circuit diagram a belongs to the first associated sub-circuit diagram of the sub-circuit diagram B, and the component 25 also belongs to the first associated sub-circuit diagram of the sub-circuit diagram B.
Fig. 9 is a schematic structural diagram of a target sub-circuit diagram according to an embodiment of the present invention, and according to the first related sub-circuit diagram in fig. 8, the sub-circuit diagram B in fig. 8 is adjusted to obtain fig. 9, and as shown in fig. 9, the connection relationships among the components 20, 21, 25 and the components are copied to the sub-circuit diagram B to obtain the target sub-circuit diagram B.
Optionally, in the step S102, the process of adjusting the circuit structures of the multiple sub-circuit diagrams according to the time sequence path relationship and/or the data path relationship between every two sub-circuit diagrams in the multiple sub-circuit diagrams to obtain multiple target sub-circuit diagrams may include:
and according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, adjusting the circuit structure of the sub-circuit diagram with the missing data path in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams.
The sub-circuit diagram with the missing data path refers to incomplete data when the sub-circuit diagram is subjected to time sequence analysis.
It should be noted that, the multiple sub-circuit diagrams are obtained based on the circuit modules and the balanced division of the sub-circuit modules, some sub-circuit diagrams with missing data paths exist in the multiple sub-circuit diagrams, different sub-circuit diagrams run on different slave node devices, if the data paths of the sub-circuit diagrams have missing data paths, the sub-circuit diagrams with missing data paths need to interact with the associated sub-circuit diagrams frequently, so that static time sequence analysis can be normally performed.
In the embodiment of the application, the circuit structure of the sub-circuit diagram with missing data paths in the plurality of sub-circuit diagrams is adjusted according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, so that the data path of each obtained target sub-circuit diagram is more complete, the data interaction between the slave node equipment and other slave node equipment when the static time sequence analysis is carried out based on the target sub-circuit diagram is reduced, and the system performance is improved.
Optionally, fig. 10 is a flow chart of a timing analysis method provided in an embodiment of the present application, as shown in fig. 10, a process for adjusting a circuit structure of a sub-circuit diagram with missing data paths in a plurality of sub-circuit diagrams according to a data path relationship between every two circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams may include:
s501, searching a sub-circuit diagram with missing data paths in a plurality of sub-circuit diagrams.
And taking the sub-circuit diagram with incomplete data paths during time sequence analysis in the plurality of sub-circuit diagrams as a sub-circuit diagram with missing data paths.
S502, determining a second associated sub-circuit diagram for providing data in the sub-circuit diagrams with missing data paths from the plurality of sub-circuit diagrams according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams.
In the embodiment of the present application, the second related sub-circuit diagram includes a data path missing from the sub-circuit diagram in which the data path is missing, and the data path is also formed by connecting components. The second associated sub-circuit diagram may also include components in the target integrated circuit that are not partitioned into the sub-circuit diagram, which is not particularly limited by the embodiments of the present application.
S503, according to the related components in the second related sub-circuit diagram, the circuit structure of the sub-circuit diagram with the missing data path is adjusted.
In some embodiments, the related components and the connection relation between the related components in the second related sub-circuit diagram are duplicated, and the circuit structure of the sub-circuit diagram with the missing data path is complemented according to the duplicated content, so that the data path of the obtained target sub-circuit diagram is more complete.
It should be noted that, under the condition of ensuring the division balance of the multiple target sub-circuit diagrams, the integrity of the data paths of the target sub-circuit diagrams is also considered, so that the multiple slave node devices can perform efficient static time sequence analysis according to the multiple target sub-circuit diagrams, and meanwhile, communication and interaction in the static time sequence analysis process are reduced.
Fig. 11 is a schematic structural diagram of a target sub-circuit diagram according to an embodiment of the present invention, where, as shown in fig. 11, the target sub-circuit diagram includes: sub-circuit diagram X, and the data path of the added N lines. The sub-circuit diagram X is a sub-circuit diagram in which a data path is missing, and the data path corresponding to the N line is the data path added after adjustment.
In summary, the embodiment of the present invention provides a timing analysis method, where multiple slave node devices may perform parallel analysis on multiple target sub-circuit diagrams, so that efficiency of performing timing analysis on the target integrated circuit diagrams is improved, and based on a path relationship between every two sub-circuit diagrams, circuit structures of the multiple sub-circuit diagrams are adjusted, so that circuit structures included in each sub-circuit diagram are more complete, static timing analysis can be independently performed on each sub-circuit diagram, and data do not need to be acquired from other target sub-circuit diagrams. The computing power of the modern computer cluster is fully utilized, the decoupling of STA service logic and computer resources is realized, and the computing capacity, expansibility and reliability of the system are greatly improved.
Compared with the STA tool of a common single-machine system, the application fully utilizes the computing power of the computer cluster, realizes the parallelization of the STA and can realize the acceleration of 6 to 20 times at the highest speed. And adjusting the number of the sub-graphs after segmentation according to the use condition of the computing resources of the system and the setting of the user, so that the overall efficiency of the system is highest. When the system is divided, the sizes of all sub-graphs are guaranteed to be similar as much as possible, so that the overall load of the system is more balanced.
In addition, a distributed DB is designed on the basis of a distributed file system, EDA research personnel can obtain corresponding data only through file names, and all storage details are transparent to the EDA research personnel. This allows EDA developers to focus more on business logic without having to expend time in the storage and management of data, greatly improving the efficiency of the development. A set of distributed computing framework suitable for EDA is also designed, so that computing resources can be automatically scheduled, and the operation efficiency is improved.
The following describes a timing analysis device, an electronic device, a storage medium, etc. for executing the timing analysis method provided by the present application, and specific implementation processes and technical effects thereof refer to relevant contents of the foregoing timing analysis method, which are not described in detail below.
Fig. 12 is a schematic structural diagram of a timing analysis device according to an embodiment of the present invention, as shown in fig. 12, the device may include:
a dividing module 1201, configured to divide the target integrated circuit diagram into a plurality of sub-circuit diagrams, where each sub-circuit diagram includes at least one circuit module;
an adjustment module 1202, configured to adjust a circuit structure of each two sub-circuit diagrams according to a timing sequence path relationship and/or a data path relationship between the two sub-circuit diagrams in the plurality of sub-circuit diagrams, so as to obtain a plurality of target sub-circuit diagrams, where the timing sequence path relationship is used to characterize a timing sequence signal transmission path between the two sub-circuit diagrams, and the data path relationship is used to characterize a data transmission path between the two sub-circuit diagrams;
a sending module 1203, configured to send the multiple target sub-circuit diagrams to multiple slave node devices, so that each slave node device performs static timing analysis on the received target sub-circuit diagram to obtain a sub-static timing analysis result;
and the determining module 1204 is configured to determine a static timing analysis result of the target integrated circuit diagram according to a plurality of the sub-static timing analysis results.
Optionally, the dividing module 1201 is specifically configured to divide the target integrated circuit diagram into a plurality of first sub-circuit diagrams according to the circuit modules in the target integrated circuit, where at least one circuit module in each of the first sub-circuit diagrams; and dividing the first sub-circuit diagram again according to the number of sub-circuit modules in each first sub-circuit diagram to obtain a plurality of sub-circuit diagrams, wherein the number of sub-circuit modules included in each sub-circuit diagram is balanced.
Optionally, the dividing module 1201 is specifically configured to determine, from a plurality of the first sub-circuit diagrams, a number of sub-circuit modules that is greater than or equal to a preset number of second sub-circuit diagrams; dividing the second sub-circuit diagram to obtain a plurality of third sub-circuit diagrams; the plurality of sub-circuit diagrams includes: the number of the sub-circuit modules included in the other first sub-circuit diagrams is the same as that of the sub-circuit modules included in the third sub-circuit diagrams, and the other first sub-circuit diagrams are circuit diagrams except for the second sub-circuit diagrams in the preset number of first sub-circuit diagrams.
Optionally, the adjusting module 1202 is specifically configured to adjust a circuit structure of a sub-circuit diagram with a missing timing path in the multiple sub-circuit diagrams according to the timing path relationship between every two circuit diagrams in the multiple sub-circuit diagrams, so as to obtain the multiple target sub-circuit diagrams.
Optionally, the adjusting module 1202 is specifically configured to find a sub-circuit diagram with a missing timing path in the plurality of sub-circuit diagrams; determining a first associated sub-circuit diagram associated with a time sequence path existing in the sub-circuit diagram with the missing time sequence path from the plurality of sub-circuit diagrams according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams; and adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path according to the related components in the first related sub-circuit diagram.
Optionally, the adjusting module 1202 is specifically configured to adjust a circuit structure of a sub-circuit diagram with missing data paths in the plurality of sub-circuit diagrams according to the data path relationship between every two circuit diagrams in the plurality of sub-circuit diagrams, so as to obtain the plurality of target sub-circuit diagrams.
Optionally, the adjusting module 1202 is specifically configured to find a sub-circuit diagram in which a data path is missing in the plurality of sub-circuit diagrams; determining a second associated sub-circuit diagram providing data for the sub-circuit diagram with the missing data path from the plurality of sub-circuit diagrams according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams; and adjusting the circuit structure of the sub-circuit diagram with the missing data path according to the associated components in the second associated sub-circuit diagram.
The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital singnal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, as shown in fig. 13, where the electronic device may include: processor 1301, memory 1302.
The memory 1302 is used for storing a program, and the processor 1301 calls the program stored in the memory 1302 to execute the above method embodiment. The specific implementation manner and the technical effect are similar, and are not repeated here.
Optionally, the present invention also provides a program product, such as a computer readable storage medium, comprising a program for performing the above-described method embodiments when being executed by a processor.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the invention. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of timing analysis, applied to a master node device, comprising:
dividing the target integrated circuit diagram into a plurality of sub-circuit diagrams, wherein each sub-circuit diagram comprises at least one circuit module;
adjusting the circuit structures of the plurality of sub-circuit diagrams according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams, wherein the time sequence path relation is used for representing the time sequence signal transmission paths between every two sub-circuit diagrams, and the data path relation is used for representing the data transmission paths between every two sub-circuit diagrams;
transmitting the target sub-circuit diagrams to a plurality of slave node devices so that each slave node device performs static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result;
and determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results.
2. The method of claim 1, wherein the dividing the target integrated circuit pattern into a plurality of sub-circuit patterns comprises:
Dividing the target integrated circuit diagram into a plurality of first sub-circuit diagrams according to circuit modules in the target integrated circuit, wherein at least one circuit module in each first sub-circuit diagram;
and dividing the first sub-circuit diagram again according to the number of sub-circuit modules in each first sub-circuit diagram to obtain a plurality of sub-circuit diagrams, wherein the number of sub-circuit modules included in each sub-circuit diagram is balanced.
3. The method of claim 2, wherein the re-dividing the first sub-circuit diagram according to the number of sub-circuit modules in the first sub-circuit diagram to obtain the plurality of sub-circuit diagrams includes:
determining second sub-circuit diagrams with the number of sub-circuit modules being greater than or equal to the preset number in the plurality of first sub-circuit diagrams;
dividing the second sub-circuit diagram to obtain a plurality of third sub-circuit diagrams;
the plurality of sub-circuit diagrams includes: the number of the sub-circuit modules included in the other first sub-circuit diagrams is the same as that of the sub-circuit modules included in the third sub-circuit diagrams, and the other first sub-circuit diagrams are circuit diagrams except for the second sub-circuit diagrams in the preset number of first sub-circuit diagrams.
4. The method according to claim 1, wherein the adjusting the circuit structure of the plurality of sub-circuit diagrams according to the timing path relationship and/or the signal path relationship between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams includes:
and according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams.
5. The method of claim 4, wherein adjusting the circuit structure of the sub-circuit diagram having the missing timing path among the plurality of sub-circuit diagrams according to the timing path relationship between each two of the plurality of sub-circuit diagrams, to obtain the plurality of target sub-circuit diagrams, comprises:
searching a sub-circuit diagram with missing time sequence paths in the plurality of sub-circuit diagrams;
determining a first associated sub-circuit diagram associated with a time sequence path existing in the sub-circuit diagram with the missing time sequence path from the plurality of sub-circuit diagrams according to the time sequence path relation between every two circuit diagrams in the plurality of sub-circuit diagrams;
And adjusting the circuit structure of the sub-circuit diagram with the missing time sequence path according to the related components in the first related sub-circuit diagram.
6. The method according to claim 1 or 4, wherein the adjusting the circuit structure of the plurality of sub-circuit diagrams according to the time sequence path relationship and/or the data path relationship between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams includes:
and according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams, adjusting the circuit structure of the sub-circuit diagram with the missing data path in the plurality of sub-circuit diagrams to obtain the plurality of target sub-circuit diagrams.
7. The method of claim 6, wherein adjusting the circuit structure of the sub-circuit diagram with missing data paths in the plurality of sub-circuit diagrams according to the data path relationship between each two of the plurality of sub-circuit diagrams, to obtain the plurality of target sub-circuit diagrams, comprises:
searching a sub-circuit diagram with missing data paths in the plurality of sub-circuit diagrams;
determining a second associated sub-circuit diagram providing data for the sub-circuit diagram with the missing data path from the plurality of sub-circuit diagrams according to the data path relation between every two circuit diagrams in the plurality of sub-circuit diagrams;
And adjusting the circuit structure of the sub-circuit diagram with the missing data path according to the associated components in the second associated sub-circuit diagram.
8. A timing analysis apparatus, applied to a master node device, comprising:
a dividing module, configured to divide a target integrated circuit diagram into a plurality of sub-circuit diagrams, where each sub-circuit diagram includes at least one circuit module;
the adjustment module is used for adjusting the circuit structures of the plurality of sub-circuit diagrams according to the time sequence path relation and/or the data path relation between every two sub-circuit diagrams in the plurality of sub-circuit diagrams to obtain a plurality of target sub-circuit diagrams, wherein the time sequence path relation is used for representing the time sequence signal transmission paths between every two sub-circuit diagrams, and the data path relation is used for representing the data transmission paths between every two sub-circuit diagrams;
the transmitting module is used for transmitting the target sub-circuit diagrams to the slave node equipment so that each slave node equipment can perform static time sequence analysis on the received target sub-circuit diagrams to obtain a sub-static time sequence analysis result;
and the determining module is used for determining the static time sequence analysis result of the target integrated circuit diagram according to the plurality of sub-static time sequence analysis results.
9. An electronic device, comprising: a memory and a processor, the memory storing a computer program executable by the processor, the processor implementing the timing analysis method of any of the preceding claims 1-7 when the computer program is executed.
10. A computer readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when read and executed, implements the timing analysis method according to any of the preceding claims 1-7.
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