CN116820392A - Data processing system, data processing method and electronic equipment - Google Patents

Abstract

The disclosure provides a data processing system, a data processing method and electronic equipment, and relates to the technical field of computers. The data processing system includes: a memory configured to store operation data including first operation data and second operation data; an identification generation unit configured to generate an identification corresponding to the operation data, the identification being used to characterize the operation data as zero or non-zero; and the multiplication processing unit comprises a multiplier, and is configured to receive the identification corresponding to the first operation data and the identification corresponding to the second operation data and control the multiplier to stop working and output a zero value when at least one of the first operation data and the second operation data is zero value. The method and the device can reduce the operation amount of the multiplier and improve the overall operation efficiency of the system.

Description

Data processing system, data processing method and electronic equipment

Technical Field

The present disclosure relates to the field of computer technology, and in particular, to a data processing system, a data processing method, and an electronic device.

Background

The advent of Deep Learning (DL) has greatly driven the development of the artificial intelligence field. The deep learning mode is utilized to realize functions such as image recognition, voice recognition, object classification and the like, and can be widely applied to various fields such as man-machine interaction, safety monitoring, intelligent driving, medical intellectualization and the like.

However, deep learning generally has problems of large operation amount and high power consumption.

Disclosure of Invention

The disclosure provides a data processing system, a data processing method and electronic equipment, and further solves the problem of large operand in a deep learning process at least to a certain extent.

According to a first aspect of the present disclosure there is provided a data processing system comprising: a memory configured to store operation data including first operation data and second operation data; an identification generation unit configured to generate an identification corresponding to the operation data, the identification being used to characterize the operation data as zero or non-zero; and the multiplication processing unit comprises a multiplier, and is configured to receive the identification corresponding to the first operation data and the identification corresponding to the second operation data and control the multiplier to stop working and output a zero value when at least one of the first operation data and the second operation data is zero value.

According to a second aspect of the present disclosure, there is provided a data processing method comprising: storing, by a memory, operation data including first operation data and second operation data; generating an identifier corresponding to the operation data through an identifier generating unit, wherein the identifier is used for representing the operation data as zero value or non-zero value; and receiving the identifiers corresponding to the first operation data and the identifiers corresponding to the second operation data through the multiplication processing unit, and controlling a multiplier contained in the multiplication processing unit to stop working and output a zero value under the condition that at least one of the first operation data and the second operation data is zero value.

According to a third aspect of the present disclosure, there is provided an electronic device comprising the data processing system described above.

In the technical schemes provided by some embodiments of the present disclosure, by configuring the identifier of whether the operation data to be multiplied is a zero value, and controlling the multiplier to stop working and output the zero value when at least one operation data is a zero value, the situation that the zero value still participates in the multiplication operation of the multiplier can be avoided, the operation amount is reduced, the overall operation speed of the system is improved, and the power consumption of the operation of the device is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:

FIG. 1 illustrates a schematic diagram of a convolution operation implemented with a processing engine according to an embodiment of the present disclosure;

FIG. 2 schematically illustrates a block diagram of a data processing system of an embodiment of the present disclosure;

FIG. 3 schematically illustrates a block diagram of a multiplication processing unit of an embodiment of the present disclosure;

FIG. 4 schematically illustrates a block diagram of a first data output unit of an embodiment of the present disclosure;

FIG. 5 shows a schematic diagram of a multiplication processing unit of an embodiment of the present disclosure;

FIG. 6 schematically illustrates a block diagram of a data processing system according to another embodiment of the present disclosure;

FIG. 7 schematically illustrates a block diagram of a data conversion unit of an embodiment of the present disclosure;

FIG. 8 is a schematic diagram illustrating the addition of zero value decision logic in a data transmission link according to an embodiment of the present disclosure;

FIG. 9 schematically illustrates a flow chart of a data processing method of an exemplary embodiment of the present disclosure;

fig. 10 schematically illustrates a block diagram of an electronic device according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

The flow diagrams depicted in the figures are exemplary only and not necessarily all steps are included. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations. In addition, all of the following terms "first," "second," are used for distinguishing purposes only and should not be taken as a limitation of the present disclosure.

It should be noted that, the data processing scheme of the embodiment of the present disclosure may be implemented by an electronic device, and specifically, the data processing system of the embodiment of the present disclosure may be configured in an electronic device, and each step of the data processing method of the embodiment of the present disclosure may be executed by the electronic device. The electronic device may be a server in addition to a terminal device such as a smart phone, a tablet computer, a personal computer, etc., which is not limited in this disclosure.

FIG. 1 shows a schematic diagram of a convolution operation implemented with a processing engine according to an embodiment of the present disclosure.

The processing engine may be a computing engine in a Neural Network Processor (NPU) included in the electronic device, including, but not limited to, a vector processing engine and a tensor processing engine. Wherein the vector processing engine may be used to process operations of the one-dimensional array. The tensor processing engine can be used for operation between oriented multidimensional arrays, and in an artificial intelligence (Artificial Intelligence, AI) accelerator, parallel operation of large-scale convolution is responsible, so that the operation performance can be remarkably improved.

The processing engine calculates convolution operation in the artificial intelligent network, wherein the convolution operation comprises multiplication of the characteristic image and weight data of the corresponding position, and accumulation of all multiplication results on one channel.

Referring to fig. 1, first, a processing engine may read out feature images and weight data from a memory and store them in a register file inside the processing engine. Then, the multiply-accumulate array reads data from the register file, generates a data processing result through the operation processing of multiplication and addition, and writes the data processing result back into the memory.

In the actual calculation process, since the pre-algorithm network performs operations such as pruning compression on the weight data, a certain proportion of zero values exist for the weight data. In addition, there is also typically a proportion of zero values in the feature image.

For a multiplier, if only one of the two operands is a zero value, then the result of the calculation is also a zero value. However, zero values in some current technologies still participate in the operation process of the multiplier, which causes redundant operation and affects the system processing efficiency.

In order to solve the problem that zero value participates in multiplication operation to cause great calculation amount of a computer system, the embodiment of the disclosure provides a new data processing scheme.

FIG. 2 schematically illustrates a block diagram of a data processing system of an embodiment of the present disclosure.

Referring to fig. 2, the data processing system 2 of the embodiment of the present disclosure may include a memory 21, an identification generating unit 22, and a multiplication processing unit 23.

The memory 21 may be configured to store operation data, which may include first operation data and second operation data. Wherein the first operation data is feature image data and the second operation data is corresponding weight data. Alternatively, the first operation data is weight data, and the second operation data is feature image data.

It should be noted that the feature image data may be feature image data extracted for an object recognition scene in an image, for example, feature extraction is performed on an environmental image collected by the camera module to obtain feature image data. In addition, the feature image data may be feature image data obtained by extracting features from audio data, and the source of the feature image data is not limited in the present disclosure. That is, the present disclosure does not limit the application scenario of the artificial intelligence algorithm to be aimed at.

The identification generation unit 22 may be configured to generate an identification corresponding to the operation data, the identification being used to characterize the operation data as zero or non-zero.

Specifically, first, the identification generating unit 22 may read out the operation data, i.e., the first operation data or the second operation data, from the memory 21. Next, the flag generation unit 22 may perform a line or operation on the operation data, that is, perform or operation on the operation data by bit. Then, the identifier generating unit 22 may perform a reversal process on the result of the line or operation to obtain an identifier corresponding to the operation data.

If at least one bit in the operation data is 1, then the result after the row or operation is 1 and the result after the inversion is 0, i.e., the flag 0 characterizes the operation data as a non-zero value. If all bits in the operation data are 0, then the result after the row or operation is 0 and the result after the inversion is 1, i.e., the flag 1 characterizes the operation data as a zero value.

The multiplication processing unit 23 includes at least a multiplier, and the multiplication processing unit 23 may be configured to receive the identification corresponding to the first operation data and the identification corresponding to the second operation data and to control the multiplier to stop operating and output a zero value in case at least one of the first operation data and the second operation data is zero value.

The multiplication processing unit 23 may be further configured to control the multiplier to multiply the first operation data with the second operation data, and output a result of the multiplication, in a case where both the first operation data and the second operation data are non-zero values.

Fig. 3 schematically shows a block diagram of a multiplication processing unit of an embodiment of the present disclosure.

Referring to fig. 3, the multiplication processing unit 23 of the embodiment of the present disclosure may include a multiplier 30, an identification analysis unit 31, a first data selector 32, a first data output unit 33, and a second data output unit 34.

The identifier analysis unit 31 is configured to receive the identifier corresponding to the first operation data and the identifier corresponding to the second operation data, and generate and output an analysis result of whether at least one of the first operation data and the second operation data is zero according to the identifier corresponding to the first operation data and the identifier corresponding to the second operation data.

In particular, the identity analysis unit 31 may be configured as an or logic circuit comprising two inputs and one output. The two input ends respectively receive the identification corresponding to the first operation data and the identification corresponding to the second operation data, and the output end outputs an analysis result of whether at least one of the first operation data and the second operation data is zero.

For example, if the analysis result of the identification analysis unit 31 is 1, it indicates that at least one of the identification corresponding to the first operation data and the identification corresponding to the second operation data is 1, that is, at least one of the first operation data and the second operation data is zero. The analysis result of the identification analysis unit 31 is 0, which indicates that the identification corresponding to the first operation data and the identification of the second operation data are both 0, that is, the first operation data and the second operation data are both non-zero values.

The first data selector 32 includes a first input terminal, a second input terminal, and a selection control terminal. The first input is connected to the output of multiplier 30 and the second input receives a zero value and the selection control receives the analysis result of identification analysis unit 31. The first data selector 32 is configured to select one output from the output value of the multiplier and the zero value based on the analysis result.

Specifically, if the analysis result of the identification analysis unit 31 is 1, it indicates that at least one of the first operation data and the second operation data is zero value, in which case the first data selector 32 may select zero value output. If the analysis result of the identification analysis unit 31 is 0, it indicates that both the first operation data and the second operation data are non-zero values, in which case the first data selector 32 may select the output value of the multiplier for output.

The first data output unit 33 may be configured to receive the first operation data, the analysis result of the identification analysis unit 31, and the clock signal, and determine whether to output the first operation data to the multiplier according to the analysis result and the clock signal.

The second data output unit 34 may be configured to receive the second operation data, the analysis result of the identification analysis unit 31, and the clock signal, and determine whether to output the second operation data to the multiplier according to the analysis result and the clock signal.

The circuit configuration of the first data output unit 33 and the second data output unit 34 may be the same. The first data output unit 33 will be described below as an example.

Referring to fig. 4, the first data output unit 33 may include a clock control module 41 and a register 42.

The clock control module 41 may be configured to receive an analysis result identifying the analysis unit 31 and a clock signal, and control the clock signal using the analysis result to output a register control signal. The register 42 may be configured to receive the first operation data and determine whether to output the first operation data to the multiplier 30 in response to a register control signal.

Specifically, if the analysis result of the identification analysis unit 31 is 1, it indicates that at least one of the first operation data and the second operation data is zero, in which case the clock control module 41 may control the clock signal to maintain the current state, such as a state of maintaining a low level, thereby ensuring that the multiplier does not flip. If the analysis result of the identification analysis unit 31 is 0, it indicates that the first operation data and the second operation data are both non-zero values, in which case the clock control module 41 does not affect the clock signal, the multiplier may acquire the current first operation data, and similarly, the multiplier may acquire the current second operation data, whereby the multiplier may perform the multiplication operation of the first operation data and the second operation data.

Similarly, the second data output unit 34 may also include a clock control module and a register, which will not be described again.

Fig. 5 shows a schematic diagram of a multiplication processing unit of an embodiment of the present disclosure.

Referring to fig. 5, the identifier corresponding to the first operation data and the identifier corresponding to the second operation data may be subjected to an or logic operation to obtain a control signal, that is, an analysis result of the identifier analysis unit 31. In one aspect, based on the control signal, clock gating of the clock signal may be controlled to determine whether to input the first operational data and the second operational data to the multiplier for multiplication. On the other hand, based on the control signal, the output of the first data selector may also be selected.

Based on the data processing system, under the condition that at least one operation data is zero, the multiplier is controlled to stop working and output the zero value, so that the situation that the zero value still participates in multiplication operation of the multiplier can be avoided, the operation amount is reduced, the overall operation speed of the system is improved, and the power consumption of equipment operation is reduced.

Further, the multiplication processing unit 23 may be included in a processing engine, and the operation data includes data written back to the memory by the processing engine. For example, in a scenario in which feature extraction operations are performed on feature images a plurality of times, the operation data a is data obtained after the processing engine performs the feature extraction operations, and the operation data a may be written back to the memory. The next time operation using the operation data a is required, the operation data a may be read out from the memory and the operation processing of the operation data a may be continued by the processing engine.

In view of the fact that the data with smaller values generally do not have a great influence on the final operation result, and in addition, the limitation of calculation force and power consumption, another embodiment of the present disclosure may convert the data with smaller values into 0, and further may reduce the system operation amount by combining the processing mode that the control multiplier of the data processing system does not multiply the zero value.

FIG. 6 schematically illustrates a block diagram of a data processing system according to another embodiment of the present disclosure. In contrast to the data processing system 2 exemplarily shown in fig. 2, the data processing system 6 may comprise a data conversion unit 61 in addition to the memory 21, the identification generation unit 22 and the multiplication processing unit 23.

The data conversion unit 61 may be configured to receive raw data written back by the processing engine and compare the raw data with a data threshold. If the original data is smaller than or equal to the data threshold value, the zero value can be used as operation data to be written back to the memory; if the raw data is greater than the data threshold, the raw data may be written back to memory as operational data. The specific value of the data threshold is not limited in the present disclosure, and for example, the data threshold may be set to 10 ^-5 。

Referring to fig. 7, the data conversion unit 61 may include a comparator 71 and a second data selector 72.

The comparator 71 may be configured to compare the raw data with a data threshold and output a comparison result.

The second data selector 72 includes a first input terminal that receives the original data, a second input terminal that receives a zero value, and a selection controller that receives the comparison result output by the comparator 71. The second data selector 72 may be configured to select one write back to the memory from the original data and the zero value based on the comparison result.

Specifically, in the case where the raw data is greater than the data threshold, the second data selector 72 outputs the raw data; in the case where the original data is equal to or less than the data threshold, the second data selector 72 outputs a zero value.

Fig. 8 schematically shows a block diagram of a data conversion unit of an embodiment of the present disclosure.

Firstly, outputting original data obtained by operation of a tensor processing engine, wherein on one hand, the original data is input into a comparator, and the comparator compares the original data with a data threshold value; on the other hand, the raw data is one input of the data selector (i.e., the second data selector described above).

If the original data is less than or equal to the data threshold, the data selector outputs a zero value, and writes the zero value as operation data into the SRAM (Static Random Access Memory ); if the original data is greater than the data threshold, the data selector outputs the original data as operation data to be written into the SRAM.

Next, when the tensor processing engine needs to perform an operation using the operation data, the operation data may be read out from the SRAM. In one aspect, the operational data may be obtained by a tensor processing engine; alternatively, the operational data may undergo a logical processing of a line or inverse to obtain an indication of whether the value is zero, which may be obtained by the tensor processing engine.

The tensor processing engine may then perform tensor processing operations on the operation data, including the processing of the multiplication processing unit described above. It should be understood that the tensor processing engine processes the next raw data, which may undergo the processing shown in fig. 8. After a plurality of processing procedures, the final operation result of the tensor processing engine can be determined and output.

Further, the embodiment of the disclosure also provides a flow chart of the data processing method.

Fig. 9 schematically shows a flow chart of a data processing method of an exemplary embodiment of the present disclosure. Referring to fig. 9, a data processing method of an exemplary embodiment of the present disclosure may include the steps of:

s92, storing operation data through a memory, wherein the operation data comprises first operation data and second operation data;

s94, generating an identifier corresponding to the operation data through an identifier generating unit, wherein the identifier is used for representing the operation data as zero value or non-zero value;

s96, receiving the identification corresponding to the first operation data and the identification corresponding to the second operation data through the multiplication processing unit, and controlling the multiplier contained in the multiplication processing unit to stop working and output a zero value under the condition that at least one of the first operation data and the second operation data is zero value.

According to an exemplary embodiment of the present disclosure, in the case where the first operation data and the second operation data are both non-zero values, the multiplier is controlled by the multiplication processing unit to multiply the first operation data with the second operation data, and a result of the multiplication is output.

According to an exemplary embodiment of the present disclosure, the multiplication processing unit includes an identification analysis unit and a first data selector including a first input terminal connected to an output terminal of the multiplier, a second input terminal receiving a zero value, and a selection control terminal receiving an analysis result. The identification analysis unit receives the identification corresponding to the first operation data and the identification corresponding to the second operation data, and outputs an analysis result of whether at least one of the first operation data and the second operation data is zero according to the identification corresponding to the first operation data and the identification corresponding to the second operation data. One output is selected from the output value of the multiplier and the zero value based on the analysis result by the first data selector.

According to an exemplary embodiment of the present disclosure, the multiplication processing unit further includes a first data output unit and a second data output unit. The first operation data, the analysis result and the clock signal are received through the first data output unit, and whether the first operation data is output to the multiplier is determined according to the analysis result and the clock signal. And receiving the second operation data, the analysis result and the clock signal through the second data output unit, and determining whether to output the second operation data to the multiplier according to the analysis result and the clock signal.

According to an exemplary embodiment of the present disclosure, the first data output unit includes a clock control module and a register. The clock control module receives the analysis result and the clock signal, and controls the clock signal by using the analysis result so as to output a register control signal. The first operation data is received through the register and it is determined whether to output the first operation data to the multiplier in response to the register control signal.

According to an exemplary embodiment of the present disclosure, operation data is read out from a memory by an identification generating unit, a line or operation is performed on the operation data, and a negation process is performed on the result of the line or operation to obtain an identification corresponding to the operation data.

According to an exemplary embodiment of the present disclosure, the multiplication processing unit is included in the processing engine, and the operation data includes data written back to the memory by the processing engine.

According to an exemplary embodiment of the present disclosure, raw data written back by a processing engine is received through a data conversion unit, the raw data is compared with a data threshold, a zero value is written back to a memory as operation data if the raw data is less than or equal to the data threshold, and the raw data is written back to the memory as operation data if the raw data is greater than the data threshold.

According to an exemplary embodiment of the present disclosure, the data conversion unit includes a comparator and a second data selector including a first input terminal receiving raw data, a second input terminal receiving a zero value, and a selection control terminal receiving a comparison result. And comparing the original data with a data threshold value through a comparator, and outputting a comparison result. And selecting one write-back from the original data and the zero value to the memory based on the comparison result through the second data selector.

Various aspects of the data processing method of the exemplary embodiments of the present disclosure have been described in the above description of the data processing system, and are not described in detail herein.

It should be noted that although the steps of the methods in the present disclosure are depicted in the accompanying drawings in a particular order, this does not require or imply that the steps must be performed in that particular order, or that all illustrated steps be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

Fig. 10 shows a schematic diagram of an electronic device suitable for use in implementing exemplary embodiments of the present disclosure. It should be noted that the electronic device shown in fig. 10 is only an example, and should not impose any limitation on the functions and the application scope of the embodiments of the present disclosure.

An electronic device may include a data processing system as described in any of the embodiments above.

Specifically, as shown in fig. 10, the electronic device 100 may include: processor 1010, internal memory 1021, external memory interface 1022, universal serial bus (Universal Serial Bus, USB) interface 1030, charge management module 1040, power management module 1041, battery 1042, antenna 1, antenna 2, mobile communication module 1050, wireless communication module 1060, audio module 1070, sensor module 1080, display 1090, camera module 1091, indicator 1092, motor 1093, keys 1094, and subscriber identity module (Subscriber Identification Module, SIM) card interface 1095, among others. The sensor module 1080 may include, among other things, depth sensors, pressure sensors, gyroscopic sensors, barometric sensors, magnetic sensors, acceleration sensors, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, piezoelectric sensors, touch sensors, ambient light sensors, bone conduction sensors, and the like.

It is to be understood that the structure illustrated in the embodiments of the present disclosure does not constitute a specific limitation on the electronic device 100. In other embodiments of the present disclosure, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 1010 may include one or more processing units, such as: the processor 1010 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), an image signal processor (Image Signal Processor, ISP), a controller, a video codec, a digital signal processor (Digital Signal Processor, DSP), a baseband processor, and/or a neural network processor, among others. Wherein the different processing units may be separate devices or may be integrated in one or more processors. In addition, a memory may be provided in the processor 1010 for storing instructions and data.

The internal memory 1021 may be used to store computer executable program code including instructions. The internal memory 1021 may include a storage program area and a storage data area. The external memory interface 1022 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 100.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

Furthermore, the above-described figures are only schematic illustrations of processes included in the method according to the exemplary embodiments of the present disclosure, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (11)

1. A data processing system, comprising:

a memory configured to store operation data including first operation data and second operation data;

an identification generation unit configured to generate an identification corresponding to the operation data, the identification being used to characterize the operation data as zero or non-zero;

and the multiplication processing unit comprises a multiplier, and is configured to receive the identification corresponding to the first operation data and the identification corresponding to the second operation data and control the multiplier to stop working and output zero value when at least one of the first operation data and the second operation data is zero value.

2. The data processing system according to claim 1, wherein the multiplication processing unit is further configured to control the multiplier to multiply the first operation data with the second operation data, and output a result of the multiplication, in a case where the first operation data and the second operation data are both non-zero values.

3. The data processing system of claim 2, wherein the multiplication processing unit further comprises:

the identification analysis unit is configured to receive the identification corresponding to the first operation data and the identification corresponding to the second operation data, and output an analysis result of whether at least one of the first operation data and the second operation data is zero according to the identification corresponding to the first operation data and the identification corresponding to the second operation data;

the first data selector comprises a first input end, a second input end and a selection control end, wherein the first input end is connected with the output end of the multiplier, the second input end receives a zero value, the selection control end receives the analysis result, and the first data selector is configured to select one from the output value and the zero value of the multiplier to output based on the analysis result.

4. A data processing system according to claim 3, wherein the multiplication processing unit further comprises:

a first data output unit configured to receive the first operation data, the analysis result, and a clock signal, and determine whether to output the first operation data to the multiplier according to the analysis result and the clock signal;

and a second data output unit configured to receive the second operation data, the analysis result, and the clock signal, and determine whether to output the second operation data to the multiplier according to the analysis result and the clock signal.

5. The data processing system of claim 4, wherein the first data output unit comprises:

a clock control module configured to receive the analysis result and the clock signal, and control the clock signal by using the analysis result to output a register control signal;

and a register configured to receive the first operation data and determine whether to output the first operation data to the multiplier in response to the register control signal.

6. The data processing system according to claim 1, wherein the identification generating unit is configured to read out the operation data from the memory, perform a line or operation on the operation data, and perform a reversal process on a result of the line or operation to obtain the identification corresponding to the operation data.

7. The data processing system of any of claims 1 to 6, wherein the multiplication processing unit is included in a processing engine, and the operation data includes data written back to the memory by the processing engine.

8. The data processing system of claim 7, wherein the data processing system further comprises:

and the data conversion unit is configured to receive the original data written back by the processing engine, compare the original data with a data threshold value, write back the zero value as the operation data to the memory if the original data is smaller than or equal to the data threshold value, and write back the original data as the operation data to the memory if the original data is larger than the data threshold value.

9. The data processing system of claim 8, wherein the data conversion unit comprises:

a comparator configured to compare the raw data with the data threshold and output a comparison result;

a second data selector comprising a first input receiving the raw data, a second input receiving a zero value, and a selection control receiving the comparison result, the second data selector being configured to select one of the raw data and the zero value to write back to the memory based on the comparison result.

10. A method of data processing, comprising:

storing, by a memory, operation data, the operation data including first operation data and second operation data;

generating an identifier corresponding to the operation data through an identifier generating unit, wherein the identifier is used for representing that the operation data is zero or non-zero;

receiving, by a multiplication processing unit, the first operation data and the identifier corresponding to the first operation data, and the second operation data and the identifier corresponding to the second operation data, and controlling a multiplier included in the multiplication processing unit to stop working and output a zero value when at least one of the first operation data and the second operation data is zero.

11. An electronic device comprising the data processing system of any of claims 1 to 9.