CN116804956A - Method for verifying PCIe port - Google Patents
Method for verifying PCIe port Download PDFInfo
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- CN116804956A CN116804956A CN202310650469.9A CN202310650469A CN116804956A CN 116804956 A CN116804956 A CN 116804956A CN 202310650469 A CN202310650469 A CN 202310650469A CN 116804956 A CN116804956 A CN 116804956A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000012795 verification Methods 0.000 claims abstract description 92
- 230000009977 dual effect Effects 0.000 claims description 12
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Abstract
The invention relates to the field of storage, in particular to a method for verifying PCIe ports, which can flexibly configure the connection mode of PCIe and Host VIP by configuring compiling parameters and simulation parameters, can flexibly select a single-port verification platform or a double-port verification platform for verification, can flexibly select different PCIe devices for verification of different functions in a double-port mode, overcomes the limitation of only verifying a single port, effectively reduces resource consumption and improves verification efficiency.
Description
Technical Field
The invention relates to the field of storage, in particular to a verification method of a solid state disk, and specifically relates to a method for verifying a PCIe port.
Background
With the advancement of technology, SSD (Solid State Drive, solid state disk) based PCIe interfaces have been commonly used for enterprise-level applications. The single-port SSD has only one path, when a fault occurs, the problem that an upper layer application cannot access is caused, while the dual-port technology allows data to be independently transmitted from two ports, fault tolerance can be provided for any one data path, namely, when one path fails and cannot access, the other path can still be normally accessed.
At present, the server has higher and higher requirements on SSD performance, and has the advantages of adapting to different application scenes, improving the performance and the reliability of SSD and simultaneously supporting SSD with single port and double port. The existing verification platform can only verify the single-port PCIe, and can not verify the single-port PCIe on the same verification platform, and can also verify the double-port PCIe.
Disclosure of Invention
Aiming at the verification scheme of single-port PCIe at present, the invention provides a method for verifying PCIe ports flexibly applied to single-port and double-port PCIe, which is used for realizing that the same verification platform can verify single-port PCIe and also can verify double-port PCIe, thereby solving the problem that the same verification platform can only verify single-port PCIe.
In order to solve the technical problems, the invention adopts the following technical scheme: a method of validating a PCIe port, comprising the steps of:
s01), assigning a variable DUAL_PORT_EN in a makefile to determine a verification mode of a verification platform, wherein the verification mode comprises single-PORT mode verification and double-PORT mode verification;
s02), according to the verification mode configured in the step S01), assigning a value to a variable TEST_DEVICE in a makefile, if the verification mode is a single-port verification mode, configuring the TEST_DEVICE to be a fixed value, verifying the function of a single PCIe controller, and if the verification mode is a double-port verification mode, configuring the TEST_DEVICE to be the fixed value or a random value, and randomly selecting to perform function verification on the single PCIe controller or two PCIe controllers;
s03), verifying the number of channels configured by the platform and connected with the Host VIP according to the configured DUAL_PORT_EN variable, selecting a corresponding connection mode, and simultaneously connecting the verification platform with the PCIe design to be tested;
s04), the verification platform is pre-configured with two connection schemes with PCIe Host VIP, and when single-port PCIe is verified, PCIe is configured to be connected with one Host VIP; when the dual-port PCIe is verified, the PCIe is configured to be connected with the two Host VIPs;
s05), the verification platform determines a current verification mode by analyzing the test_device variable value, and when the current verification mode is a single-port mode, the test_device is configured to be a fixed value; when the DUAL_PORT_EN is in a DUAL PORT mode, the TEST_DEVICE is configured to be a constant value or a random value;
s06), after analyzing the test_device variable value, the verification platform carries out link initialization configuration on the PCIe controller appointed by the variable value, and meanwhile, the related function of the PCIe controller appointed by the variable value is verified; if the PCIe controller specified by the TEST_DEVICE variable value is a single PCIe controller, carrying out link initialization configuration and function verification on the single PCIe controller, and if the PCIe controller specified by the TEST_DEVICE variable value is a dual PCIe controller, carrying out link initialization configuration and function verification on the dual PCIe controller.
Further, during single-port mode verification, 4 channels between the Host VIP and the chip verification platform are all used for transmission of a single PCIe controller, during double-port mode verification, 4 channels between the Host VIP and the chip verification platform are equally divided into two groups, every 2 channels are 1 group, and 2 groups of data channels are independently transmitted.
Further, in step S03), when the verification mode determined by the dual_port_en variable is a single-PORT verification mode, configuring the number of Host VIP channels to be 4, where the PCIe controller to be tested is connected to one Host VIP, and the 4 channels between the Host VIP and the chip verification platform are all used for transmission by a single PCIe controller; when the verification mode determined by the DUAL_PORT_EN variable is a DUAL-PORT verification mode, configuring the number of Host VIP channels to be 2, connecting the PCIe controller to be tested with two Host VIPs, dividing 4 channels between the Host VIPs and the chip verification platform into two groups, wherein each 2 channels are 1 group, and the 2 groups of data channels are respectively connected with the two Host VIPs and are used for transmitting data between the two Host VIPs and the PCIe controller to be tested.
Further, when the verification mode determined by the DUAL_PORT_EN variable is a single-PORT verification mode, the TEST_DEVICE is configured to be a constant value TEST_DEVICE0, that is, to verify the function of PCIe controller0, and when the verification mode determined by the DUAL_PORT_EN variable is a DUAL-PORT verification mode, the TEST_DEVICE is configured to be TEST_DEVICE0, TEST_DEVICE1, TEST_ALL, TEST_RAND, wherein the TEST_RAND has a value range { TEST_DEVICE0, TEST_DEVICE1, TEST_ALL }, and function verification is randomly selected to be performed on PCIe controller0 or PCIe controller1 or both controllers.
The invention has the beneficial effects that: compared with the traditional single-port verification platform, the method has the advantages that the connection mode of PCIe and Host VIP can be flexibly configured through configuration of compiling parameters and simulation parameters, meanwhile, the single-port verification platform or the double-port verification platform can be flexibly selected for verification, and meanwhile, different PCIe devices can be flexibly selected for verification of different functions in a double-port mode, so that the limitation that only one port can be verified is overcome, resource consumption is effectively reduced, and verification efficiency is improved.
Drawings
FIG. 1 is a flow chart of the method of example 1;
FIG. 2 is a schematic diagram of channel allocation and connection between PCIe to be tested and Host VIP during single port verification;
fig. 3 is a schematic diagram of channel allocation and connection between PCIe to be tested and Host VIP during dual port verification.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
Example 1
The embodiment discloses a method for verifying a PCIe port, as shown in fig. 1, the implementation steps of the method are as follows:
s01), assigning a variable dual_port_en in makefile to determine whether the authentication platform is single-PORT mode authentication or DUAL-PORT mode authentication. As shown in fig. 2, in the single port mode, 4 lanes are used for transmission by a single PCIe controller, such as PCIe controller0 (controller 0), and in the dual port mode, all data lanes are equally divided into two groups, as shown in fig. 3, 4 lanes are divided into two groups, each 2 lanes is 1 group, and 2 groups of data lanes are independently transmitted.
S02), according to the verification mode configured by the makefile, assigning a variable TEST_DEVICE in the makefile, and if the variable TEST_DEVICE is in a single-port verification mode, configuring the TEST_DEVICE as a fixed value TEST_DEVICE0, namely verifying the function of a single PCIe controller such as PCIe controller0 by default; in the case of dual port authentication mode, test_device may be configured to be a constant value or a random value, i.e., to randomly choose to perform functional authentication on PCIe controller0 or PCIe controller1 or both controllers.
S03), verifying the number of channels configured by the platform and connected with the Host VIP according to the configured DUAL_PORT_EN variable, selecting a corresponding connection mode, and simultaneously connecting the verification platform with the PCIe design to be tested. As shown in fig. 2 and 3, when the single port mode is selected, the number of Host VIP channels is required to be configured to be 4; when the dual port mode is selected, two Host VIP channels are required to be configured, the number of which is 2.
S04), the verification platform configures two connection schemes with PCIe Host VIP in advance, namely, when single-port PCIe is verified, PCIe is configured to be connected with one Host VIP, as shown in figure 2; when dual port PCIe is verified, PCIe is configured to connect to two Host VIPs, as shown in fig. 3.
S05), the verification platform determines a current verification mode by analyzing the test_device variable value, and when the DUAL_PORT_EN is in a single-PORT mode, the test_device is configured to be a fixed value of test_device0; when the DUAL_PORT_EN is in DUAL PORT mode, TEST_DEVICE may be configured as TEST_DEVICE0, TEST_DEVICE1, TEST_ALL, TEST_RAND. The value range of TEST_RAND is { TEST_DEVICE0, TEST_DEVICE1, TEST_ALL }.
S06), after analyzing the TEST_DEVICE variable value, the verification platform performs link initialization configuration on the PCIe controller0 if the TEST_DEVICE variable value is the TEST_DEVICE0, and only verifies related functions of the PCIe controller 0; if the value is the fixed value TEST_DEVICE1, carrying out link initialization configuration and related function verification on the PCIe controller 1; if the value is the fixed value TEST_ALL, the PCIe controller0 and the controller1 need to perform link initialization configuration, and meanwhile, related function verification can be performed. If the verification platform analyzes that the test_device variable value is not the fixed value described above, the input test_device variable value is considered to be wrong, the wrong information is printed and the user exits.
The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art in light of the present invention.
Claims (4)
1. A method of validating a PCIe port, comprising: the method comprises the following steps:
s01), assigning a variable DUAL_PORT_EN in a makefile to determine a verification mode of a verification platform, wherein the verification mode comprises single-PORT mode verification and double-PORT mode verification;
s02), according to the verification mode configured in the step S01), assigning a value to a variable TEST_DEVICE in a makefile, if the verification mode is a single-port verification mode, configuring the TEST_DEVICE to be a fixed value, verifying the function of a single PCIe controller, and if the verification mode is a double-port verification mode, configuring the TEST_DEVICE to be the fixed value or a random value, and randomly selecting to perform function verification on the single PCIe controller or two PCIe controllers;
s03), verifying the number of channels configured by the platform and connected with the Host VIP according to the configured DUAL_PORT_EN variable, selecting a corresponding connection mode, and simultaneously connecting the verification platform with the PCIe design to be tested;
s04), the verification platform is pre-configured with two connection schemes with PCIe Host VIP, and when single-port PCIe is verified, PCIe is configured to be connected with one Host VIP; when the dual-port PCIe is verified, the PCIe is configured to be connected with the two Host VIPs;
s05), the verification platform determines a current verification mode by analyzing the test_device variable value, and when the current verification mode is a single-port mode, the test_device is configured to be a fixed value; when the DUAL_PORT_EN is in a DUAL PORT mode, the TEST_DEVICE is configured to be a constant value or a random value;
s06), after analyzing the test_device variable value, the verification platform carries out link initialization configuration on the PCIe controller appointed by the variable value, and meanwhile, the related function of the PCIe controller appointed by the variable value is verified; if the PCIe controller specified by the TEST_DEVICE variable value is a single PCIe controller, carrying out link initialization configuration and function verification on the single PCIe controller, and if the PCIe controller specified by the TEST_DEVICE variable value is a dual PCIe controller, carrying out link initialization configuration and function verification on the dual PCIe controller.
2. The method of validating a PCIe port of claim 1, wherein: and in the single-port mode verification, 4 channels between the Host VIP and the chip verification platform are all used for transmission of a single PCIe controller, and in the double-port mode verification, the 4 channels between the Host VIP and the chip verification platform are equally divided into two groups, each 2 channels are 1 group, and the 2 groups of data channels are independently transmitted.
3. The method of validating a PCIe port of claim 2, wherein: in step S03), when the verification mode determined by the dual_port_en variable is a single-PORT verification mode, configuring the number of Host VIP channels to be 4, wherein the PCIe controller to be tested is connected with one Host VIP, and the 4 channels between the Host VIP and the chip verification platform are all used for transmission of a single PCIe controller; when the verification mode determined by the DUAL_PORT_EN variable is a DUAL-PORT verification mode, configuring the number of Host VIP channels to be 2, connecting the PCIe controller to be tested with two Host VIPs, dividing 4 channels between the Host VIPs and the chip verification platform into two groups, wherein each 2 channels are 1 group, and the 2 groups of data channels are respectively connected with the two Host VIPs and are used for transmitting data between the two Host VIPs and the PCIe controller to be tested.
4. The method of validating a PCIe port of claim 1, wherein: when the authentication mode determined by the DUAL_PORT_EN variable is a single-PORT authentication mode, the TEST_DEVICE is configured to be a constant value TEST_DEVICE0, that is, the function of PCIe controller0 is authenticated, and when the authentication mode determined by the DUAL_PORT_EN variable is a DUAL-PORT authentication mode, the TEST_DEVICE is configured to be TEST_DEVICE0, TEST_DEVICE1, TEST_ALL and TEST_RAND, wherein the TEST_RAND value range is { TEST_DEVICE0, TEST_DEVICE1, TEST_ALL }, and function authentication is randomly selected for PCIe controller0 or PCIe controller1 or both controllers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310650469.9A CN116804956A (en) | 2023-06-02 | 2023-06-02 | Method for verifying PCIe port |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310650469.9A CN116804956A (en) | 2023-06-02 | 2023-06-02 | Method for verifying PCIe port |
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| CN116804956A true CN116804956A (en) | 2023-09-26 |
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