CN116803228A - Single transistor (1T) One Time Programmable (OTP) antifuse bit-cell with reduced threshold voltage - Google Patents

Abstract

A one-time programmable (OTP) antifuse bit-cell for a single transistor (1T) is provided. The 1T OTP antifuse bit-cell includes a gate, a diffusion region having at least two sub-regions, and a gate oxide region between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

Description

Single transistor (1T) One Time Programmable (OTP) antifuse bit-cell with reduced threshold voltage

Priority

The present application claims priority from U.S. non-provisional application No. 17/544583 entitled "One-Transist (1T) One-Time Programmable (OTP) Anti-Fuse Bitcell With Reduced Threshold Voltage" (attorney docket number SYNP 3718-2) filed on month 07 of 2021, which claims priority from U.S. C. 25 (e) to U.S. provisional application No. 63/125907 entitled "One Time Programmable Anti-Fuse Bitcell with Narrow Width to Reduce Voltage Threshold" (attorney docket number SYNP 3718-2) filed on month 15 of 2020. The entire contents of the provisional and non-provisional applications are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates generally to an electronic circuit device. In particular, the present disclosure relates to a one-time programmable (OTP) antifuse bit-cell with a reduced Voltage Threshold (VT) for a single transistor (1T).

Background

One Time Programmable (OTP) bit cells can be implemented using a single transistor. These OTP bit cells are referred to as single transistor (1T) OTP bit cells. Further, the 1T OTP bit cell may be of a fuse type or an antifuse type. The fuse type 1T OTP bit cell (i.e., 1TOTP fuse bit cell) starts with a low resistance read/write (conductive) path and is designed to permanently break the low resistance read/write (conductive) path when the current exceeds a limit. As a result, the low resistance read/write path is broken, leaving an open circuit. The antifuse-type 1T OTP bit cell (i.e., a 1T OTP antifuse bit cell) begins with a high-resistance read/write path that transitions to a low-resistance read/write path when current exceeds a limit. The 1T OTP antifuse bit-cell is programmed by applying a current exceeding the limit to create a low-resistance conductive read/write path.

As described above, a 1T OTP bit cell (fuse or antifuse) uses only a single transistor with a single gate. A single gate supports two gate oxide thicknesses, including a thick input/output (IO) gate oxide portion and a thin core gate oxide portion. The thin core gate oxide portion is used to program the 1T OTP bit cell by applying the required current.

Disclosure of Invention

In one embodiment, the present disclosure provides a one-transistor (1T) one-time programmable (OTP) antifuse bit cell. The 1T OPT antifuse bit-cell may include: a gate; a diffusion region comprising at least two sub-regions, the at least two sub-regions being isolated from each other at one or more locations; and a gate oxide region between the gate and the diffusion region, the gate oxide region comprising a first gate oxide region and a second gate oxide region, wherein the first gate oxide region has a thinner thickness than the second gate oxide region.

In another embodiment, each of the at least two sub-regions may be shorted to a thin gate oxide region.

In further embodiments, the 1T OTP antifuse bit-cell may be programmed by applying a voltage sufficient to cause cracking in the thin gate oxide region.

In one embodiment, each of the at least two sub-regions may be shorted to contact a bit line.

In another embodiment, the width of a first sub-region of the at least two sub-regions may be narrower than the width of a second sub-region of the at least two sub-regions.

In further embodiments, at least two sub-regions of the diffusion region may include a third sub-region, and a width of the third sub-region may be sufficiently narrow to affect a threshold voltage of the 1T OTP antifuse bit cell during a read operation.

In one embodiment, at least two sub-regions of the diffusion region may include a third sub-region, and the width of the third sub-region may be narrower than the width of the second sub-region.

In another embodiment, the width of the first sub-region may be the same as the width of the third sub-region, and the width of each of the first and third sub-regions may be less than the width of the second sub-region.

In further embodiments, the 1T OTP antifuse bit-cell may be programmed by applying a voltage sufficient to cause cracking in the thin gate oxide region such that each of the at least two sub-regions is shorted to the thin gate oxide region.

In one embodiment, each of the at least two sub-regions may be shorted to contact a bit line.

In another embodiment, at least two sub-regions may be formed in the diffusion region by forming one or more grooves in the diffusion region along a portion of the length of the diffusion region such that a first groove is positioned between and extends between the lengths of at least two sub-regions.

In further embodiments, the at least two sub-regions may include three sub-regions, the one or more grooves may include a first groove and a second groove, and a width of at least one of the first groove and the second groove may be wider than a width of at least one of the three sub-regions.

In one embodiment, the at least two sub-regions may include three sub-regions, the one or more grooves may include a first groove and a second groove, and a length of at least one of the first groove and the second groove may be the same as a length of at least one of the three sub-regions.

In another embodiment, the total combined width of the at least two sub-regions may be sufficient to provide sufficient current during the rupture of the thin gate oxide region to form a permanent low resistance filament therein.

In further embodiments, the first and second sub-regions of the at least two sub-regions may be formed in the diffusion region by forming a groove in the diffusion region along a portion of the length of the diffusion region such that the groove is positioned and extends between the length of the first sub-region and the length of the second sub-region.

In one embodiment, the width of the slot may be wider than the width of the first sub-region.

In another embodiment, the length of the slot may be the same as the length of at least one of the first sub-region and the second sub-region.

In further embodiments, a bipolar complementary metal oxide semiconductor double diffused metal oxide semiconductor (BCD) chip is provided. The BCD chip may include a row of single transistor (1T) one-time programmable (OTP) antifuse bit cells, each pair of 1T OTP antifuse bit cells of the row sharing a common bit line, and each 1T OTP antifuse bit cell of the row includes: a gate; a diffusion region comprising at least two sub-regions, the at least two sub-regions being isolated from each other at one or more locations; and a gate oxide region between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

In another embodiment, for each respective 1T OTP antifuse bit-cell of a row of BCD chips, a width of a first sub-region of the at least two sub-regions may be narrower than a width of a second sub-region of the at least two sub-regions.

In one embodiment, a method of fabricating a one-time programmable (OTP) antifuse bit-cell for a single transistor (1T) is provided. The method may include: forming a diffusion region comprising at least two sub-regions, the at least two sub-regions being isolated from each other at one or more locations; forming a gate oxide region over the diffusion region, the gate oxide region comprising a thin gate oxide region and a thick gate oxide region; and forming a gate over the gate oxide region.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the disclosure. The drawings are intended to provide a knowledge and understanding of embodiments of the present disclosure and are not intended to limit the scope of the present disclosure to these particular embodiments. Moreover, the drawings are not necessarily drawn to scale.

Fig. 1 illustrates a cross-sectional view of a one-time programmable (OTP) antifuse bit-cell having a thick gate oxide portion and a thin gate oxide portion.

FIG. 2 illustrates a top view of a 1T OTP antifuse bit-cell having a single-finger diffusion region.

Fig. 3 illustrates a top view of a 1TOTP antifuse bit-cell having a multi-fingered diffusion area, according to an embodiment of the present disclosure.

Fig. 4 illustrates a top view of a 1T OTP antifuse bit-cell having a multi-fingered diffusion area including example current flow, according to an embodiment of the present disclosure.

FIG. 5A illustrates a cross-sectional view along line B-B of FIG. 2 to illustrate the single-finger diffusion region of a 1T OTP antifuse bit-cell.

Fig. 5B illustrates a cross-sectional view along line D-D of fig. 3 to illustrate a three-finger diffusion region of a 1T OTP antifuse bit cell, according to an embodiment of the disclosure.

FIG. 6 illustrates two adjacent 1T OTP antifuse bit-cells each having a single-finger diffusion region.

Fig. 7 illustrates two adjacent 1T OPT antifuse bit-cells each having a three-finger diffusion region, according to an embodiment of the present disclosure.

Fig. 8 illustrates a flowchart including various operations performed to fabricate a 1T OTP antifuse bit cell according to an embodiment of the disclosure.

Fig. 9 depicts a flowchart of various processes used during design and manufacture of an integrated circuit, according to some embodiments of the present disclosure.

FIG. 10 depicts an abstract view of one example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure relate to a single transistor (1T) one-time programmable (OTP) antifuse bit-cell having a multi-fingered diffusion region to reduce a voltage threshold, where multi-fingered refers to splitting the diffusion region into multiple diffusion regions or sub-regions that are separated and/or insulated from each other at one or more points.

The 1T OTP antifuse bit cell (or memory) has an advantage over a two transistor (2T) OTP antifuse bit cell such that the 1T OTP bit cell requires only one gate and only one signal from row logic, as opposed to the 2T OTP bit cell, which requires two gates and two signals from row logic. Thus, the bit cell itself, as well as the peripheral logic, can be smaller.

However, a 1T OTP antifuse bit-cell requires a thick gate input/output (IO) oxide region under the gate and a thin gate core region. The thick gate oxide region of the 1T OPT antifuse bit-cell sets the threshold Voltage (VT) of the bit-cell. The thin gate oxide portion of the bitcell limits the maximum voltage that can be applied across the bitcell gate during a read operation to avoid any damage during reading. The high VT from the thick gate oxide portion can be combined to limit the minimum voltage at which a bit cell can be read.

There is an increasing demand for 1T OTP bit cells in bipolar complementary metal oxide semiconductor (BCD) processes. A common use of BCD processes is in techniques for controlling displays, power management and microelectromechanical system (MEMS) controllers, which are designed to have a very large operating voltage range. This makes the use of 1T OTP bit cells difficult due to the high VT and the maximum voltage with which the 1TOTP bit cells can be read. For example, a Liquid Crystal Display (LCD) driver chip has pairs of devices (i.e., 3 pairs of devices, 6 devices in total in the LCD driver chip) operating at 1 volt (1V), 8 volts (8V), and 30 volts (30V). The above-described LCD driver chip is only one example, and other 28mm display drivers may operate at 1.2 volts, 8 volts, and 32 volts. Other common uses of BCD processes are microelectromechanical system (MEMS) controllers and power management.

Returning to the LCD display driver example, the display driver is used to control flat panel displays in smart phones, computer monitors, and televisions. Flat panel displays are typically made using thin film transistors. These thin film transistors are fabricated on glass substrates and typically operate at voltages of about 30V. BCD processes optimized for display drivers typically have a double Diffused Metal Oxide Semiconductor (DMOS) device (e.g., 30V device) for driving the display, a standard Complementary Metal Oxide Semiconductor (CMOS) logic device (e.g., 1V device) for logic computation, a bridge device (e.g., 8V device) that is used to step the output of the logic device voltage to a voltage that can switch the DMOS device, and a non-volatile memory. The bridge devices are typically CMOS devices with thicker gate oxides. The bridge device is also used for chip-to-chip IO. The non-volatile memory may include the 1T OTP antifuse bit-cell described above. The nonvolatile memory is used to store configuration settings, analog adjustment values, and correction settings. The configuration settings may be used to define which display the LCD driver chip is driving. This allows one display driver chip to be used for many different display screens. The configuration settings may include analog adjustment settings that may be used to compensate for manufacturing variations in the display. For example, if one color of the display is somewhat weak, the display driver may be compensated by making that color brighter. This is also called gamma correction. The configuration settings may also include correction settings that may be used to compensate for bad pixels in the display. If there is a defective pixel that cannot be turned on, it can be masked by making the adjacent pixel brighter.

As described above, one example of a display driver BCD process may have a 1VCMOS core logic device, an 8V CMOS bridge device, a 30V DMOS device, and a 1T OTP antifuse bit cell serving as a non-volatile memory. A 1T OTP antifuse bit cell may be problematic when there is a difference between a low voltage device (e.g., a 1V core logic device) and a bridge device (e.g., an 8V device). In this example, if the display driver chip is used in a mobile battery powered product, it is generally desirable for the memory to operate at low voltages. Thus, it is expected that the 1V power supply may drop to 0.9V. A 1T OTP bit cell typically uses a thin (low voltage) gate oxide for the fuse portion (i.e., read/write) of the bit cell and a thick gate oxide for the bridge device or other select device. The VT of the bitcell is set by the thick gate oxide portion. 8V CMOS devices typically have VT of about 1V, which means that 1V is required from gate to well to generate significant drain to source current, and 1V logic devices typically have read reliability issues with gate oxide stress greater than 1V, which means that the gate may be damaged when operated over long periods of time beyond its device rating. Gate damage may cause an unprogrammed antifuse to become programmed. This results in a very small operating window because 1V is required for 1V of the 1T OTP bit cell for read operations and some designs require operation at low voltages to achieve low power. The small operating window may be addressed with either a usual circuit solution (i.e. using a circuit arrangement connected to the device driver chip) or a device solution (i.e. modifying the 1T OPT bit cell of the device driver chip). This common circuit solution involves increasing the gate voltage by boosting the VDD power supply or involves turning down the higher power supply to ensure that the gate voltage is not too low to perform a read operation nor too high to cause damage to the gate or other parts of the chip. The usual circuit scheme increases the area and has a relatively high power consumption.

The present disclosure describes improving low voltage reading by implementing a multi-finger diffusion region as opposed to a single-finger diffusion region to reduce the VT required for a read operation of a 1T OTP antifuse bit cell. Technical advantages of the 1T OTP antifuse bit-cell of the present disclosure include reduced VT in order to read the bit-cell at relatively low voltages.

FIG. 1 illustrates a cross-sectional view of a 1TOTP antifuse bit-cell having a thick gate oxide portion and a thin gate oxide portion.

Specifically, fig. 1 illustrates a 1TOTP bit cell 100 including a gate oxide region having two thicknesses. The 1T OTP bit cell 100 includes a polysilicon gate 101. The gate oxide region is under the polysilicon gate 101. The gate oxide region may be a dielectric layer separating the polysilicon gate 101 from the source/drain terminal(s) (e.g., bit line BL 108 in this case). BL 108 is an electrical connection that can connect drain 112 (e.g., an N+ drain) of 1T OTP bit cell 100 to peripheral logic (e.g., column logic for reading from and writing to 1T OTP bit cell 100). The gate oxide region under the polysilicon gate 101 includes a thick IO gate oxide (region) 102 and a thin core gate oxide (region) 104. The thick IO gate oxide 102 serves as a select device and the thin core gate oxide 104 allows the region 106 to be programmed (i.e., an antifuse that can be programmed and then read). In particular, the thin core gate oxide 104 is used to program (e.g., break down) the programming region 106 of the polysilicon gate 101. As illustrated, the 1T OTP bit cell 100 includes a Bit Line (BL) 108, a Word Line (WL) 114, an n+ doped drain region 112, a Lightly Doped Drain (LDD) 116, a P-doped channel 118, shallow Trench Isolation (STI) 120, and a diffusion region 110. Diffusion region 110 may include, but is not limited to, P-doped channel 118.

As described above, the Voltage Threshold (VT) of the bitcell is set by the thick IO gate oxide. Devices are typically designed to operate at a target voltage (e.g., +/-10%). Thus, 1V devices are expected to operate from 0.9V to 1.1V. 8V CMOS devices typically have a VT of about 1V, and 1V logic devices typically have reliability issues with long term operation of greater than 1.1V. For example, if a read operation is always performed at a voltage greater than 1.1V, the lifetime of the bit cell may decrease. An example bitcell may have a lifetime of 10 years. However, if the read operation is always higher than 1.1V, the lifetime of the bit cell may be reduced to less than 10 years due to current leakage caused by damage caused by the continuous read operation higher than 1.1V. This results in a very small operating window of the target voltage for the read operation, equal to or higher than 1V VT, but not greater than 1.1V where damage may begin to occur. For example, it may be difficult to read a 1T OTP bit cell 100 having a VT of approximately 1V, where 1V is required on the gate for reading. Some low power products operate at reduced voltages. If a 1V/8V 1t OTP bit cell is read below 1V, there may not be enough current to correctly sense the programmed (ruptured) bit cell.

The cross-sectional view of the 1T OTP in fig. 1 does not illustrate the single-finger diffusion area configuration or the multi-finger diffusion area configuration described above. However, fig. 2 illustrates a single-finger diffusion region configuration, and fig. 3 illustrates a multi-finger diffusion region configuration.

FIG. 2 illustrates a top view of a 1T OTP antifuse bit-cell having a single-finger diffusion region.

Specifically, fig. 2 illustrates a 1T OTP antifuse bit-cell 200, the bit-cell 200 including a single-finger diffusion region 202, a polysilicon gate 204 over the diffusion region 202, and a bit-line 206 connected to the diffusion region 202. Bit line 206 may also be connected to column logic. The single-finger diffusion region 202 comprises a semiconductor wafer substrate and a shallow trench isolation dielectric separates the single-finger diffusion region 202 from other bit cells on the 3-side.

Fig. 2 also illustrates a region 208 (under the polysilicon gate 204) including the thick IO gate oxide 102 of fig. 1, a region 210 (under the polysilicon gate 204) including the thin core gate oxide 104 of fig. 1, and a transition region 212 in which the polysilicon gate 204 transitions from a higher position for accommodating the thick IO gate oxide 102 to a lower position for accommodating the thin core gate oxide 104, as illustrated in fig. 1. Note that fig. 1 may be a section taken from line A-A of fig. 2. The location of regions 208, 210, and 212 will be more clear when considering region 208 comprising thick IO gate oxide 102, region 210 comprising thin core gate oxide 104, and transition region 212 comprising the portion of thick IO gate oxide 102 that transitions to thin core gate oxide 104 with respect to fig. 1.

As an example, the single finger 1T OTP bit cell of fig. 2 may be implemented in a 28nm1.2V/8V/32V display driver process. As described above, a 1T OTP bit cell may have a thick IO gate oxide (e.g., 8V) in region 208 to act as a select device and a thin core gate oxide (e.g., 1.2V) in region 210 for programming. The size of the 1T OTP bit cell 200 is greater than that required to match the 1T OTP bit cell to the row and column logic pitch. An OTP antifuse bit-cell that programs the bit by cracking the gate oxide requires sufficient current to pass through the filament formed during the cracking to form a permanent low resistance filament. This requirement of high current during rupture can make the bit cell or peripheral circuitry large enough to provide the required current. The width (W) of the bit cell may need to be greater than the minimum width allowed, or the interconnect may need to be greater than the minimum width allowed to reduce interconnect resistance to avoid current/voltage drop, or the width of the BL or WL driver may need to be greater than the minimum required to drive the current. The minimum width allowed may be set based on a Design Rule Manual (DRM) and may be determined based on, for example, the results that a manufacturing facility may manufacture.

To program a 1T OTP bit cell, sufficient voltage/current may be applied to the polysilicon gate 204 to cause a break in the thin core gate oxide 102 to create a filament that provides a low resistance path through the thin core gate oxide 102 included in region 210. The filaments may be formed exactly at the transition from the thin core gate oxide 102 to the thick IO gate oxide 104 (e.g., at the transition region 212), or the filaments may be formed in the thin core gate oxide 102 itself as opposed to being formed in the transition region 212.

Fig. 2 also illustrates the width W of the single-finger diffusion region 202 covered by the polysilicon gate 204. Due to the voltage/current requirements for programming a 1T OTP bit cell, the width W is much larger than the minimum allowed in the process. This is needed to allow enough current to flow from the gate oxide rupture location through the channel of the transistor to the bit line 206 to form a permanent low resistance filament.

Fig. 3 illustrates a top view of a 1TOTP bitcell with multi-fingered diffusion area according to one embodiment of the present disclosure.

Specifically, fig. 3 illustrates a 1T OTP antifuse bit-cell 300, the bit-cell 300 being similar to fig. 2 with respect to the polysilicon gate 204, bit-line 206, and regions 208, 210, and 212. Note that fig. 1 may also be a section taken along line C-C of fig. 3.

The 1T OTP antifuse bit-cell 300 differs from the 1T OTP antifuse bit-cell of fig. 2 in that the 1T OTP bit-cell 300 includes a three-finger diffusion region 302, the three-finger diffusion region 302 including (i) a first finger 304 (a bottommost horizontal region in the three-finger diffusion region 302), (ii) a second finger 306 (a middle horizontal region in the three-finger diffusion region 302), and (iii) a third finger 308 (an uppermost horizontal region in the three-finger diffusion region 302). The first, second, and third fingers 304, 306, 308 may be formed by creating a slot 303 in the diffusion region 302. The trench 303 may be formed by cutting Shallow Trench Isolation (STI) into the diffusion (wafer surface) region 202. In this bit cell, since the space between the plurality of bit cells is larger than necessary (as described above), three fingers 304, 306, and 308 can be formed so that one finger can be changed to three fingers. The first finger 304, the second finger 306, and the third finger 308 may also be referred to as sub-regions of the diffusion region 202. Diffusion region 202 is larger than is actually needed for 1T OTP bit cell 300 to allow room in the peripheral circuitry to make the device large enough to provide the necessary current during programming to form a low resistance filament during rupture. In addition, the 1TOTP bit cell 300 of FIG. 3 may be the same size as the 1T OTP bit cell 200 of FIG. 2 because the polysilicon gate 204 of the 1T OTP bit cell 200 of FIG. 2 has additional space to properly pitch match peripheral circuitry and also allows for larger peripheral devices.

The three finger diffusion region 302 structure results in the formation of three gate regions: a first gate region (where the polysilicon gate 204 extends over the first finger 304 in the X-direction and the Y-direction), a second gate region (where the polysilicon gate 204 extends over the second finger 306 in the X-direction and the Y-direction), and a third gate region (where the polysilicon gate 204 extends over the third finger 308 in the X-direction and the Y-direction). These three gate regions will become more apparent when looking at fig. 5B.

Further, as shown in fig. 3, the width W1 of the first finger 304 covered by the polysilicon gate 204 is less than the width W of the single-finger diffusion region 202 of fig. 2, the width W2 of the second finger 306 covered by the polysilicon gate 204 is less than the width W of the single-finger diffusion region 202 of fig. 2, and the width W3 of the third finger 308 covered by the polysilicon gate 204 is less than the width W of the single-finger diffusion region 202 of fig. 2. The narrower widths W1, W2, and W3 (as compared to the width W of the single-finger diffusion region 202) allow the (read) VT of the 1T OTP bit cell 300 to be less than the VT of the 1T OTP bit cell 200 of fig. 2. As shown in fig. 3, the width W1 of the first finger 304 and the width W3 of the third finger 308 are narrower than the width W2 of the second finger 306, and the width W2 of the second finger 306 is wide enough to allow sufficient current flow during rupture to properly form a low resistance filament (e.g., rupture or breakdown a thin gate oxide high voltage to form a low resistance filament). Further, the widths W1, W2, and W3 of the first, second, and third fingers 304, 306, and 308 may be the same. The lengths of the first, second and third fingers 304, 306 and 308 and the length of the slot 303 extend in the X direction, and the widths of the first, second and third fingers 304, 306 and 308 and the width of the slot 303 extend in the Y direction, as shown in fig. 3. The length of the slot 303 may be equal to, less than, or greater than the defined lengths of the first, second, and third fingers 304, 306, 308. Further, the width of each of the grooves 303 may be the same, or they may be different from each other. Further, the width of the slot 303 may be equal to, less than, or greater than any of the widths of the first finger 304, the second finger 306, and/or the third finger 308. The width W1 of the first finger 304 may be equal to, less than, or greater than the width W3 of the third finger 308. The first finger 304 and the third finger 308 are narrow enough to allow lower voltage reading and the second finger 306 is wide enough to provide a width W2 sufficient to allow the current required during programming to form a low resistance filament through the thin gate oxide during rupture.

The layout in fig. 3 may have some corner rounding such that the ends of the slots 303 become rounded and shortened during manufacture. The slots 303 may be extended to compensate for corner rounding.

The multi-fingered diffusion area 302 may also include two or four fingers. Additional fingers are also possible depending on the amount of available space without departing from the scope of the present disclosure. Similar to the above description, the voltage threshold required to read data from a 1T OTP antifuse bit-cell having two, three, or four fingers, etc., is lower than the voltage threshold required to read data from a single-finger 1T OTP antifuse bit-cell (including a diffusion region having only a single finger).

Fig. 4 illustrates a top view of a 1T OTP bit cell with a three finger diffusion area including an example current flow according to an embodiment of the disclosure. Fig. 4 includes an arrow 402 to illustrate the path of current flow to be in the case of a right-hand lower corner filament of the 1T OTP bit cell 400.

In particular, fig. 4 illustrates the same 1T OTP bit cell 400 as the 1T OTP bit cell 300 of fig. 3 except that one possible breaking point 401 and current path (arrow) 402 are illustrated. During programming of the 1T OTP bit cell 400, a voltage (e.g., a programming voltage) large enough to rupture the thin core gate oxide 104 (see fig. 1) in region 212 is applied to the thin gate core oxide 104. The programming voltage is much higher than the VT of thick gate devices. Fig. 4 illustrates the break point as being proximate to the first finger 304. The first finger 304, the second finger 306, and the third finger 308 are shorted to the thin gate oxide 104 due to the fracture at the fracture point 401. The location of the break point 401 may be anywhere in the regions 210 and 212. In order for the 1T OTP bit cell 400 to utilize all of the fingers 304, 306, and 308, when forming small filaments in random locations in the thin gate oxide 104, all of the fingers 304, 306, and 308 must be shorted on the side of the multi-finger diffusion region 302 where the BL 206 is located, and also in the thin gate core oxide 104. On the side where BL 206 is located, the short circuit may be with metal (e.g., a metal contact). In the thin gate core oxide 104, the shorts may be in a diffusion under the polysilicon gate 204, or in a diffusion extending from under the polysilicon gate 204, and the shorts may be in the source/drain regions.

When broken at the break point 401, current will travel along the current path 402, along each of the first finger 304, the second finger 306, and the third finger 308 to reach the metal contact with the BL 206. This provides three paths along the first finger 304, the second finger 306, and the third finger 308 between the break point 401 and the metal contact. The use of first finger 304, second finger 306, and third finger 308 ensures that the entire width (e.g., widths W1, W2, and W3) of 1T OTP bit cell 400 is used as a current path for programming and reading. The layout may take into account any process variations when designing the 1T OTP bit cell 400.

Since some of the individual widths W1, W2, and W3 (see fig. 3) are narrower than the width W (see fig. 2), less gate voltage is required to perform a read operation after the 1T OTP bit cell 400 is programmed. With the polysilicon gate 204 at a very high voltage, the 1T OTP bit cell 400 will use all three fingers 304, 306, and 308 to conduct current during programming. During low voltage reading, current will likely only flow through the narrow fingers 304 and 308 with the smallest width.

FIG. 5A illustrates a cross-sectional view along line B-B of FIG. 2 to illustrate the single-finger diffusion region of a 1T OTP antifuse bit-cell. Specifically, as shown in fig. 5A, there is a single finger diffusion region 502 under the polysilicon gate 500 and between the two STI regions 503.

Fig. 5B illustrates a cross-sectional view along line D-D of fig. 3 to illustrate a three-finger diffusion region of a 1T OTP antifuse bit cell, according to an embodiment of the disclosure. Specifically, as shown in fig. 5B, there are three diffusion regions that may correspond to the first, second, and third fingers 304, 306, 308 discussed with reference to fig. 3 and 4. The three diffusion regions (i.e., first finger 304, second finger 306, and third finger 308) are formed by forming trenches 303 (see fig. 3) with a silicon wafer surface isolated by STI oxide (STI region 503) between the trenches 303.

The process of forming STI typically forms small recesses in the STI oxide adjacent to the diffusion regions. The recess allows the conductive gate material of the gate 500 to descend around the edges of the small recess. This results in the gate 500 being on both sides of the diffusion region on the extreme edges of the small recess 504. This increases the electric field from the gate 500 to the nearest corner of the diffusion region. This increased electric field may occur even if the small recess 504 is not present, as there will still be an electric field fringing field that extends from the polysilicon gate 204 over the STI to the sidewalls of the diffusion region 308. This increased electric field reduces the VT of the three-finger 1T OTP bit cell compared to a single-finger 1T OTP bit cell.

Fig. 6 illustrates two adjacent 1T OTP antifuse bit-cells 600 each having a single finger diffusion region. Specifically, two adjacent 1T OTP antifuse bit-cells may include the 1T OTP antifuse bit-cell 200 structure illustrated in fig. 2. Two adjacent 1T OTP bit cells 600 share the same BL 206.

Fig. 7 illustrates two adjacent 1T OPT antifuse bit-cells 700 each having a three-finger diffusion region, according to an embodiment of the present disclosure. Specifically, two adjacent 1T OTP antifuse bit-cells may include the 1T OTP antifuse bit-cell 300 structure illustrated in fig. 3. Two adjacent 1T OTP bit cells 700 share the same BL 206.

Fig. 8 illustrates a flowchart 800, the flowchart 800 including various operations performed to fabricate a 1T OTP antifuse bit cell according to an embodiment of the disclosure.

Specifically, flowchart 800 includes an operation 802 of forming a diffusion region comprising at least two sub-regions that are isolated from one another at one or more locations.

The flowchart 800 also includes an operation 804 of forming a gate oxide region over the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

In addition, flowchart 800 includes an operation 806 of forming a gate over the gate oxide region.

FIG. 9 illustrates an example set of processes 900 used during design, verification, and manufacture of an article of manufacture, such as an integrated circuit (or OTP bit cell as described above), to convert and verify design data and instructions representing an integrated circuit. Each of these processes may be structured and enabled as multiple modules or operations. The term 'EDA' means the term 'electronic design Automation'. These processes begin with creating a product idea 910 using information provided by a designer, which is converted to produce an article using a set of EDA processes 912. Upon completion of the design, a design is streamed (tape-out) 934, which is the time that a picture (e.g., a geometric pattern) of the integrated circuit is sent to a manufacturing facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After the die is flowed, the semiconductor die are fabricated 936 and a packaging and assembly process 938 is performed to produce a finished integrated circuit 940.

The specification of a circuit or electronic structure may range from a low-level transistor material layout to a high-level description language. Using hardware description languages ('HDL') such as VHDL, verilog, systemVerilog, systemC, myHDL or OpenVera, high-level representations can be used to design circuits and systems. The HDL description may be converted into a register transfer level ('RTL') description, a gate level description, a layout level description, or a mask level description of the logic level. Each lower level of representation (i.e., a more detailed description) adds more useful details to the design description, e.g., for modules comprising the description. The lower level of representation (which is a more detailed description) may be computer generated, derived from a design library, or created by another design automation process. One example of a specification language for specifying a lower representation language level for a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each presentation level is enabled for use by the corresponding tool of the layer (e.g., formal verification tool). The design process may use the sequence depicted in fig. 9. The described process is enabled by EDA products (or tools).

During system design 914, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or code lines), cost reduction, etc. At this stage, the design may be divided into different types of modules or components.

During logic design and functional verification 916, modules or components in the circuit are specified in one or more description languages and the functional accuracy of the specification is checked. For example, components of a circuit may be verified to generate an output that matches the specification requirements of the designed circuit or system. Functional verification may use simulators and other programs such as test bench generators, static HDL testers, and formal verifiers. In some embodiments, special systems of components called 'emulators' or 'prototype systems' are used to speed up functional verification.

During synthesis and design for test 918, HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure in which edges of the graph structure represent components of a circuit, and in which nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are manufactured, layered products that can be used by EDA products to verify: whether an integrated circuit is being manufactured is performed according to a specified design. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify whether the integrated circuit meets the requirements of the specification.

During netlist verification 920, the netlist is checked for compliance with timing constraints and for correspondence with HDL code. During design planning 922, an overall plan view of the integrated circuit is constructed and analyzed for timing and top-level routing.

During the placement or physical implementation 924, physical placement (placement of circuit components such as transistors or capacitors) and routing (connection of circuit components through multiple conductors) are performed and selection of cells from a library to enable a particular logic function may be performed. As used herein, the term 'cell' may designate a collection of transistors, other components, and interconnects that provide a boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit 'block' may refer to more than two cells. Both units and circuit blocks may be referred to as modules or components and may be enabled as both physical structures and simulations. Parameters such as size are specified for the selected cell (based on 'standard cell') and made accessible in the database for use by the EDA product.

During analysis and extraction 926, the circuit functions are verified at a layout level that allows for improvements to the layout design. During physical verification 928, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, lithography constraints) are correct and that circuit functions match HDL design specifications. During parsing enhancement 930, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

During the streaming, data is created for (after applying lithography enhancement, if appropriate) producing a lithography mask. During mask data preparation 932, the 'flow sheet' data is used to create a photolithographic mask that is used to produce a finished integrated circuit.

The storage subsystem of a computer system, such as computer system 900 of fig. 9, may be used to store programs or data structures used by some or all of the EDA products described herein, and by products for developing units of libraries and products for physical and logical designs using the libraries.

Fig. 10 illustrates an example machine of a computer system 1000 in which a set of instructions, such as the manufacture of an OTP bit cell, for causing the machine to perform any one or more of the methods discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, and as a server or client computer in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet computer, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a network appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read Only Memory (ROM), flash memory, dynamic Random Access Memory (DRAM) such as Synchronous DRAM (SDRAM)), a static memory 1006 (e.g., flash memory, static Random Access Memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030.

The processing device 1002 represents one or more processors, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1002 may also be one or more special-purpose processing devices, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. The processing device 1002 may be configured to execute instructions 1026 to perform the operations and steps described herein.

Computer system 1000 may further include a network interface device 1008 to communicate over a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

The data storage device 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. During execution of instructions 1026 by computer system 1000, instructions 1026 may also reside, completely or at least partially, within main memory 1004 and/or within processing device 1002, main memory 1004 and processing device 1002 also constituting machine-readable storage media.

In some implementations, instructions 1026 include instructions for implementing functions corresponding to the present disclosure. While the machine-readable storage medium 1024 is illustrated in an example embodiment as a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) to store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and processing device 1002 to perform any one or more of the methodologies of the present disclosure. Accordingly, the term "machine-readable storage medium" shall be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the present description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the desired purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and the like.

In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular, more than one element may be depicted in the drawings and like elements are labeled with like reference numerals. Accordingly, the disclosure and figures are to be regarded as illustrative rather than restrictive.

Claims (20)

1. A single transistor (1T) One Time Programmable (OTP) antifuse bit-cell, comprising:

a gate;

a diffusion region comprising at least two sub-regions, the at least two sub-regions being isolated from each other at one or more locations; and

a gate oxide region between the gate and the diffusion region, the gate oxide region comprising a first gate oxide region and a second gate oxide region, wherein the first gate oxide region has a thinner thickness than the second gate oxide region.

2. The 1T OTP of claim 1 wherein each of the at least two sub-regions is shorted to the thin gate oxide region.

3. The 1T OTP antifuse bit-cell of claim 1, wherein the 1TOTP antifuse bit-cell is programmed by applying a voltage sufficient to cause cracking in the thin gate oxide region.

4. The 1T OTP antifuse bit-cell of claim 3, wherein each of the at least two sub-regions is shorted to contact a bit line.

5. The 1T OTP antifuse bit-cell of claim 1, wherein a first of the at least two subregions has a width that is narrower than a width of a second of the at least two subregions.

6. The 1T OTP antifuse bit cell of claim 5, wherein the at least two sub-regions of the diffusion region include a third sub-region, and wherein a width of the third sub-region is sufficiently narrow to affect a threshold voltage of the 1T OTP antifuse bit cell during a read operation.

7. The 1T OTP antifuse bit-cell of claim 5, wherein the at least two subregions of the diffusion region include a third subregion, and wherein the third subregion has a width that is narrower than the width of the second subregion.

8. The 1T OTP antifuse bit-cell of claim 7, wherein the width of the first subregion is the same as the width of the third subregion, and the width of each of the first and third subregions is less than the width of the second subregion.

9. The 1T OTP antifuse bit-cell of claim 7, wherein the 1T OTP antifuse bit-cell is programmed by applying a voltage sufficient to cause cracking in the thin gate oxide region such that each of the at least two sub-regions is shorted to the thin gate oxide region.

10. The 1T OTP antifuse bit-cell of claim 9, wherein each of the at least two sub-regions is shorted to contact a bit line.

11. The 1T OTP antifuse bit cell of claim 1, wherein the at least two sub-regions are formed in the diffusion region by forming one or more slots in the diffusion region along a portion of a length of the diffusion region such that a first slot is positioned between and extends between lengths of the at least two sub-regions.

12. The 1T OTP antifuse bit cell of claim 11, wherein the at least two sub-regions comprise three sub-regions, the one or more slots comprise a first slot and a second slot, and at least one of the first slot and the second slot has a width that is wider than a width of at least one of the three sub-regions.

13. The 1T OTP antifuse bit cell of claim 11, wherein the at least two subregions comprise three subregions, the one or more slots comprise a first slot and a second slot, and at least one of the first slot and the second slot has a length that is the same as a length of at least one of the three subregions.

14. The 1T OTP antifuse bit cell of claim 1, wherein a total combined width of the at least two sub-regions is sufficient to provide sufficient current during rupture of the thin gate oxide region to form a permanent low-resistance filament therein.

15. The 1T OTP antifuse bit-cell of claim 1, wherein a first and second of the at least two subregions are formed in the diffusion region by: a groove is formed in the diffusion region along a portion of a length of the diffusion region such that the groove is positioned between and extends between a length of the first sub-region and a length of the second sub-region.

16. The 1T OTP antifuse bit cell of claim 15, wherein a width of the slot is wider than a width of the first subregion.

17. The 1T OTP antifuse bit-cell of claim 15, wherein a length of the slot is the same as a length of at least one of the first and second subregions.

18. A bipolar complementary metal oxide semiconductor double diffused metal oxide semiconductor (BCD) chip comprising:

a row of single transistor (1T) One Time Programmable (OTP) antifuse bit cells, each pair of 1T OTP antifuse bit cells of the row sharing a common bit line, and each 1TOTP antifuse bit cell of the row comprising:

a gate;

a diffusion region comprising at least two sub-regions, the at least two sub-regions being isolated from each other at one or more locations; and

a gate oxide region between the gate and the diffusion region, the gate oxide region comprising a thin gate oxide region and a thick gate oxide region.

19. The BCD chip of claim 18 wherein, for each respective 1T OTP antifuse bit cell of the row, a width of a first of the at least two subregions is narrower than a width of a second of the at least two subregions.

20. A method of fabricating a one-time programmable (OTP) antifuse bit-cell of a single transistor (1T), the method comprising:

Forming a diffusion region comprising at least two sub-regions, the at least two sub-regions being isolated from each other at one or more locations;

forming a gate oxide region over the diffusion region, the gate oxide region comprising a thin gate oxide region and a thick gate oxide region; and

a gate is formed over the gate oxide region.