CN1168005C

CN1168005C - Treating method and system for local defect internal memory

Info

Publication number: CN1168005C
Application number: CNB011104082A
Authority: CN
Inventors: 林锡聪
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2001-04-02
Filing date: 2001-04-02
Publication date: 2004-09-22
Anticipated expiration: 2021-04-02
Also published as: CN1378139A

Abstract

The present invention relates to a method for processing a locally defective memory. The method is characterized in that original program codes are scanned, and a first breaking point and a second breaking point are determined in front of and behind a defective address to which a defective storage unit corresponds; block program codes which are set between the first breaking point and the second breaking point are moved between a first address and a second address, and the first address and the second address do not correspond to the defective address; the block program codes after the move and the execution sequence of the part which is not moved in the original program codes are connected, and the reference addresses between the block program codes after the move and the part which is not moved in the original program codes or the reference addresses of the block program codes are adjusted; in this way, modified programs can be loaded into the memory. The present invention can keep away from the defective storage unit and does not influence the executive function of the original program codes.

Description

The disposal route of local defect internal memory and system

Technical field

The invention relates to a kind of disposal route and system of local defect internal memory, be particularly related to a kind of disposal route and system, can be at also not loading internal memory or the program code that has been present in the internal memory is adjusted, and in the internal memory that makes this program code still can be loaded on to have the local defect storage unit and carried out.

Background technology

If internal memory IC internal memory was when any defected memory cell (defective memorycell), generally was such internal memory IC can not to be sold on the market in the past.In order to reduce because of situation single or that the minority defective is discarded entire I C, have many technology can allow the internal memory IC of local defect at present, in operation as fully normal internal memory IC.

For example, promptly disclose among the United States Patent (USP) NO.4939694 a kind of can selftest (self-testing) and the memory system of self-repair (self-repairing).This memory system can carry out selftest at the use scene, so that orient defected memory cell wherein.In case find any defected memory cell, this memory system just can use a kind of device that is called bug patch code engine (error correction code engine), repairs for these defected memory cells.If the bug patch code engine can't be loaded, just then memory system can replace to fall these defected memory cells.

Then be to utilize replacement internal memory (substitutionmemory) to handle the semiconductor memory that contains defected memory cell in addition in U.S. Patent No. 5644541.When the error bit of semiconductor memory in several known location, then utilize a reflection logic (mapping logic) to need access to arrive the access request of these error bits all, be directed to and replace good storage unit in the internal memory, replace defected memory cell originally whereby.

Then be to disclose a kind of use error detection/correcting code (error detecting and correcting code, fault-tolerant (fault-tolerating) memory system EDAC) in the U.S. Patent No. 5278847.The fiduciary level of storage data can be utilized for each data character and add the EDAC coding and increase guard position (spare-bit) and reach.

But then be to utilize laser repairing technique and journey fuse repairing technique to handle defected memory cell in the U.S. Patent No. 5579266, can utilize redundancy memory to come the substitutional defect internal memory.

Wherein similarly be disclosed coding and guard position technology in disclosed error-detecting and repairing technique among the United States Patent (USP) NO.4939694, the U.S. Patent No. 5278847, disclosed access guiding technique also or in the U.S. Patent No. 5644541, not only can increase the degree of difficulty on the hardware design, the burden that when executable machine code is carried out at every turn, also can cause program to carry out simultaneously.In addition, as U.S. Patent No. 5579266 disclosed redundancy memory technology, on the hardware design or also all very complicated on actual program of repairing.

On the other hand, general executable machine program code is the source code (source code) by computer program, utilizes editing machine (compiler) and connector (linker) to produce.The machine program code then can directly load in the internal memory and carry out.The 1st figure represents the system layout of general single-chip computing machine (single chip computer) or system-on-a-chip (system-on-a-chip).As shown in the figure, this system comprises CPU (central processing unit, or claim microprocessor) 1, RAM (random access memory, random access memory) 3 ROM (read-only memory,, ROM (read-only memory)) 5, I/O interface 7 and external storage device 9, for example Winchester disk drive, floppy drive or CD-ROM or the like.Under normal operation, CPU1 can pass through data/address bus 10, will prepare the machine program code of carrying out by I/O interface 7 or external storage device 9, is loaded among the RAM3.Comprise three parts in the general machine program code, be respectively instruction (instruction), data (data) and storehouse (stack).CPU1 can begin to carry out this machine program code from the program entry point (entry point) of operation part.

The 2nd figure represents the process flow diagram of general machine program code when carrying out (execution).At first, obtain program entry point (S1).The address (address) of then obtaining next instruction (S2), and according to this address, read in the next instruction operational code (opcode) (S3).Then operational code is deciphered (S4), and judged whether needs operand (operand) according to instruction type.If this instruction needs operand, read operands (S5) from subsequent address more then.Last according to the instruction action of operational code representative and the data content or the reference address of operand representative, carry out this instruction (S6).If this instruction is for program command for stopping (S7), machine program code complete (S8) then, otherwise get back to the address that step S2 obtains next instruction.Mandatory declaration be, each instruction might not comprise identical hyte length, this is relevant with the cpu type that is adopted.The instruction set that general CPU is adopted can be divided into variable length codeword instruction set and fixed-length code word instruction collection.

In above-mentioned execution flow process, mainly be at the operation part in the machine program code.If identical executive routine is applied to data division or storehouse part, its decode results is entanglement fully then.When certain data byte is decoded into certain wrong operational code by CPU1 after, then can allow several data of back be mistaken as operand according to the operational code of mistake.General CPU1 be can't be by standard acquisition and decoding action recognize what person and be operation part, what person is data division or storehouse part.In addition, the operation part of program code and data/storehouse part also cannot be at random in addition disjunction, the disjunction of operation part must decide according to the form of each instruction, that is each instructs the hyte length of (comprising operand and operational code).And data/storehouse part generally can't disjunction, and this is therefore to comprise the data association that only could judge when carrying out in data/storehouse part, for example the array in the data structure.

Summary of the invention

In view of this, fundamental purpose of the present invention, be to provide a kind of disposal route and system of local defect internal memory, can not change hardware configuration and not increase under the prerequisite of software execution burden, respectively can program code do not load or the already present situation of program code in, the storing mode of update routine code in this local defect internal memory is to avoid using defected memory cell.

Purpose of the present invention can reach by following measure:

A kind of program code is loaded internal memory for the method for carrying out, be applicable to the internal memory that comprises a plurality of storage unit and to be loaded in an original program code of above-mentioned internal memory, it comprises the following steps:

Determine whether above-mentioned internal memory comprises defected memory cell;

When above-mentioned internal memory does not comprise defected memory cell, then load above-mentioned original program code to above-mentioned internal memory;

When above-mentioned internal memory comprises at least one defected memory cell, then carry out the following step:

Scan above-mentioned original program code, above-mentioned defected memory cell corresponding to before and after the defective addresses of above-mentioned original program code, determine first fen breakpoint and second fen breakpoint;

Move the section program code between above-mentioned first minute breakpoint and the above-mentioned second minute breakpoint, between first address and second address, the neither above-mentioned defective addresses in the address between above-mentioned first address and above-mentioned second address corresponding to above-mentioned internal memory;

When above-mentioned section program code comprises at least one executable instruction, provide a link order, in order to connect in above-mentioned section program code after moving and the above-mentioned original program code the not execution sequence of movable part; And

Load in the above-mentioned original program code not movable part, above-mentioned link order and move after above-mentioned section program code to above-mentioned internal memory.

A kind of internal memory disposal system, in order to handle an internal memory that comprises a plurality of storage unit, it comprises:

One microprocessor, be coupled to above-mentioned internal memory, in order to load an original program code, when the storage unit that is loaded when above-mentioned original program code is all the zero defect storage unit, then load above-mentioned original program code in above-mentioned internal memory, when the storage unit that is loaded when above-mentioned original program code comprises at least one defected memory cell, then scan above-mentioned original program code, above-mentioned defected memory cell corresponding to before and after the defective addresses of above-mentioned original program code, determine first fen breakpoint and second fen breakpoint, and move between section program code to the first address and second address between above-mentioned first minute breakpoint and the above-mentioned second minute breakpoint, and when above-mentioned section program code comprises at least one executable instruction, one link order is provided, in order to connect in above-mentioned section program code and the above-mentioned original program code the not execution sequence of movable part, and load in the above-mentioned original program code not movable part, above-mentioned link order and move after above-mentioned section program code to above-mentioned internal memory, the pairing memory address of program code between wherein above-mentioned first address and above-mentioned second address does not comprise above-mentioned defective addresses.

A kind of local weakness internal memory processing method of preventing and treating is applicable to an internal memory of loading with an original program code, and it comprises the following steps:

Check above-mentioned internal memory, in order to find out the defected memory cell of function reduction in the above-mentioned internal memory;

In above-mentioned internal memory, comprise the storage unit of at least one function reduction, then carry out the following step:

Scan above-mentioned original program code, before and after the defective addresses of above-mentioned defected memory cell, determine first fen breakpoint and second fen breakpoint corresponding to above-mentioned original program code;

Move the section program code between above-mentioned first minute breakpoint and the above-mentioned second minute breakpoint, extremely between first storage unit and second storage unit in the above-mentioned internal memory, do not comprise above-mentioned defected memory cell between above-mentioned first storage unit and above-mentioned second storage unit; And

When above-mentioned section program code comprises at least one executable instruction, connect in above-mentioned section program code after moving and the above-mentioned original program code the not execution sequence of movable part.

A kind of internal memory disposal system comprises a plurality of storage unit and has stored the internal memory of an original program code in order to handle one, and it comprises:

One microprocessor, be coupled to above-mentioned internal memory, the storage unit whether the function reduction is arranged in order to the storage unit of checking above-mentioned internal memory, when the storage unit of above-mentioned reduction exists and stored above-mentioned original program code, then scan above-mentioned original program code, before and after the reduction address of storage unit corresponding to above-mentioned original program code of above-mentioned reduction, determine first fen breakpoint and second fen breakpoint, and move between first storage unit and second storage unit of section program code to the above-mentioned internal memory between above-mentioned first minute breakpoint and the above-mentioned second minute breakpoint, and when above-mentioned section program code comprises at least one executable instruction, the execution sequence of movable part not in above-mentioned section program code after connect moving and the above-mentioned original program code does not comprise above-mentioned defected memory cell between wherein above-mentioned first storage unit and above-mentioned second storage unit.

A kind of internal memory processing method is applicable to the internal memory that comprises a plurality of storage unit and to be loaded in an original program code of above-mentioned internal memory, and it comprises the following steps:

When above-mentioned internal memory does not comprise defected memory cell or above-mentioned original program code and is not loaded in above-mentioned internal memory the pairing defective addresses of defected memory cell, then load above-mentioned original program code to above-mentioned internal memory;

When above-mentioned original program code is loaded in the above-mentioned internal memory the pairing defective addresses of at least one defected memory cell, then carry out the following step:

Load above-mentioned original program code to above-mentioned internal memory;

Load the section program code between above-mentioned first minute breakpoint and the above-mentioned second minute breakpoint, between first storage unit and second storage unit, do not comprise above-mentioned defected memory cell between above-mentioned first storage unit and above-mentioned second storage unit; And

When above-mentioned section program code comprises at least one executable instruction, connect the execution sequence of other parts in above-mentioned section program code between above-mentioned first storage unit and second storage unit and the above-mentioned original program code.

One microprocessor, be coupled to above-mentioned internal memory, in order to load an original program code, when the storage unit that is loaded when above-mentioned original program code comprises at least one defected memory cell, then this system can scan above-mentioned original program code, and above-mentioned defected memory cell corresponding to before and after the defective addresses of above-mentioned original program code, determine first fen breakpoint and second fen breakpoint, and load above-mentioned original program code to the above-mentioned internal memory and load between section program code to the first storage unit and second storage unit between above-mentioned first minute breakpoint and the above-mentioned second minute breakpoint, and when above-mentioned section program code comprises at least one executable instruction, connection between above-mentioned first storage unit and second storage unit above-mentioned section program code and above-mentioned original program code in the execution sequence of other parts, do not comprise above-mentioned defected memory cell between wherein above-mentioned first storage unit and above-mentioned second storage unit.

A kind of program code scans disposal route, in order to determine the divided breakpoint of an original program code, said procedure code scans disposal route comprises the following steps:

One first tables of data and one second tables of data are provided, and above-mentioned first tables of data is in order to write down the relevant address to be scanned of conditional branch instructions in the above-mentioned original program code, the address realm that above-mentioned second tables of data has read in order to record;

Read above-mentioned original program code in regular turn;

When the instruction of being read is a conditional branch instructions, writes down the relevant address to be scanned of above-mentioned conditional branch instructions in above-mentioned first tables of data, and continue scanning according to next address or branch's destination address of above-mentioned conditional branch instructions;

With reading of instruction, upgrade the address realm of above-mentioned second tables of data, and when finishing when reading at least one complete instruction, output can divide breakpoint; And

When the instruction of being read is an END instruction or its address in the address realm of above-mentioned second tables of data time, then continue to read, and should from above-mentioned first tables of data, remove address to be scanned according to an address to be scanned of above-mentioned first tables of data.

The present invention has following advantage compared to existing technology:

According to above-mentioned purpose, the present invention proposes a kind of disposal route of local defect internal memory, can be useful between the original program code of the internal memory that comprises a plurality of storage unit and this internal memory to be loaded.Suppose in this internal memory, to have at least one defected memory cell.At first, scan this original program code, and in the original program code, before and after the pairing defective addresses, determine first fen breakpoint and second fen breakpoint at defected memory cell.Then move section program code between first fen breakpoint and the second fen breakpoint between first address and second address, wherein do not comprise above-mentioned defective addresses between first address and second address.When comprising at least one executable instruction in the section program code that is moved (that is comprising operation part), then need to connect in section program code after moving and the original program code the not execution sequence of movable part.And do not exist the reference address or the inside of section program code itself to have reference address between the movable part in section program code after moving and the original program code, then adjust according to circumstances.At last, just can with in the original program code not movable part, link order and move after the section program code be loaded in the internal memory in regular turn.Because utilize program code that aforesaid way loads for executable state and can not be stored among the known defected memory cell, even therefore have defected memory cell in the internal memory, this internal memory still can normally use.In addition, do not relate to the modification or the change of hardware circuit in the above-mentioned processing procedure, so implementation cost is quite low.

In addition, if original program code to be loaded process modularization processing itself, just then when carrying out program code scans, could directly determine needed minute breakpoint.If but the original program code not in advance in addition modularization handle, then read the original program code in regular turn, form according to each instruction in the original program code again, export a plurality of breakpoints that divide, just can determine needed first minute breakpoint and second fen breakpoint according to defective addresses and the link order that is inserted into length at last.Determine to scan complete original program code, the present invention then provides following method.At first, provide first tables of data and second tables of data, wherein first tables of data is used for writing down branch's destination address of conditional branch instructions in the original program code, and second tables of data then is used for writing down the address realm that has read.When the instruction of being read is a conditional branch instructions, just in first tables of data, note branch's destination address of conditional branch instructions; When finishing the reading an of instruction, then upgrade the address realm of second tables of data.When the instruction of being read is that an END instruction or its address are in the address realm of second tables of data time, then, just can continue to read according to branch's destination address of first tables of data as long as branch's destination address of first tables of data does not belong in the address realm of second tables of data.By above-mentioned processing branch and round-robin mode, just can guarantee to scan all instructions.

In addition, connect in section program code after moving and the original program code not movable part, can insert two unconditional branches and instruct and finish.The instruction of first unconditional branch is inserted on the address of first fen breakpoint, and its destination address is first address of section program code after moving; Second address that the instruction of second unconditional branch is inserted in the section program code after moving, its destination address then is second fen breakpoint.

Above-mentioned processing mode can also change in practicality slightly.Edge this, the present invention has proposed a kind of local defect internal memory disposal route in addition, its program has different on a small quantity with aforesaid way.At first, scan the original program code and before and after the defective addresses of defected memory cell correspondence, determine first fen breakpoint and second fen breakpoint.Then, be loaded in the internal memory the original program code is whole earlier, and in addition between first storage unit that does not comprise defected memory cell and second storage unit, load the section program code between first fen breakpoint and second fen breakpoint once more.Then then identical: the execution sequence of other parts, correction reference address to each other in section program code that connection reloads and the original program code with aforementioned manner.By this mode, except the purpose that can reach last mode,, can also accelerate the speed of subsequent processing steps because program code is loaded into earlier in the internal memory, for example revise the processing of reference address.

In addition, the present invention provides a kind of disposal route of local defect internal memory in addition, goes for the original program code and has been present in situation in the internal memory.At first, check internal memory and find out at least one defected memory cell of function reduction in the internal memory.Then scan the original program code, so that before and after the pairing defective addresses of defected memory cell, determine first fen breakpoint and second fen breakpoint.Then with the section program code between first fen breakpoint and the second fen breakpoint, move to internal memory and do not comprise between first storage unit and second storage unit of above-mentioned defected memory cell.Then then identical: as to connect in section program code and the original program code after moving not execution sequence, the correction reference address to each other of movable part with aforementioned manner.Because the internal memory during this mode goes for using is therefore more convenient on using.

Comprehensive the above, the disposal route of local defect internal memory of the present invention and system have following advantage:

1. solve the mode of local defect storage unit among the present invention, do not need to change the design on the hardware (memory configurations) or increase hardware circuit, but avoid using defected memory cell by the mode of update routine code; And the burden that program code is increased when carrying out is also not serious, only needs to add two unconditional branch orders (being JMP) under the best circumstances and gets final product.Therefore on implementation complexity and cost, the present invention has splendid industrial utilization really.

2. the present invention not only goes for the situation of known defect internal memory, also goes for internal memory just in use, as described in the 3rd embodiment.Hardware modifications mode of the prior art all must be extracted internal memory out independent correct usually when carrying out, therefore the present invention then can use upward more convenient for the internal memory adjustment program code wherein in using.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:

Description of drawings

The 1st figure represents the system layout of general single-chip computing machine (single chip computer) or system-on-a-chip (system-on-a-chip).

The 2nd figure represents the process flow diagram of general machine program code when carrying out (execution).

The 3rd figure represents the arrangement plan of the local defect internal memory disposal system of first embodiment of the invention.

The 4th figure represents the process flow diagram of the local defect internal memory disposal route of first embodiment of the invention.

The 5th figure is illustrated in the process flow diagram of program code scans method among the present invention.

The 6th figure represents that program code scans method according to the present invention handles the synoptic diagram of a program code example.

The 7th figure is illustrated among the present invention to connect and moves the not synoptic diagram of movable part of back section program code and original program code.

The 8th figure is illustrated in the synoptic diagram of revising reference address among the present invention.

The 9th figure represents the process flow diagram of the local defect internal memory disposal route of second embodiment of the invention.

The 10th figure represents the arrangement plan of the local defect internal memory disposal system of third embodiment of the invention.

The 11st figure represents the process flow diagram of the local defect internal memory disposal route of third embodiment of the invention.

Symbol description 1 ~ CPU; 3 ~ RAM (internal memory); 5 ~ ROM; 7 ~ I/O interface; 9 ~ external storage device; 10 ~ data/address bus; 20 ~ original program code; 30 ~ the first tables of data; 40 ~ the second tables of data; C1-C7 ~ instruction segment part; D1-D3 ~ data/storehouse part; 21 ~ defective addresses; 51,52 ~ link order; Program code behind the 50 ~ mobile section program code; 60 ~ finish the program code of reference address correction; R1-R3, R1 '-R3 ' ~ reference address.

Embodiment

Local defect internal memory disposal route of the present invention and system mainly are to revise to be loaded or already present original program code, still can normal operation with the internal memory IC that avoids taking place the storage unit of defective, allow whereby having the local defect storage unit.Revising the processing mode of original program code, mainly is that the divided breakpoint (break point) and the mode of mobile section program code by identification machine program code reached.That is, pick out the divided breakpoint in the original program code earlier, again according to the program point that storage unit corresponded to of actual generation defective, determine transportable section program code; With this section program code move to can the internal storage location of operate as normal after, utilize link order again, keep section program code after moving and the execution sequence between the original program code, just can avoid using defected memory cell.Because the present invention does not need change or redesign hardware circuit, and the added burden yet very limited (only increasing link order) that is increased on software is carried out, and therefore can reach purpose of the present invention.Below cooperation is graphic, describes the technology contents of various embodiments of the present invention in detail.

First embodiment:

The 3rd figure represents the arrangement plan of the local defect internal memory disposal system of first embodiment.In the 3rd figure, internal memory 3 comprises at least one defected memory cell, and in the following description, except particularly pointing out, is pre-conditioned with single defected memory cell or one group of adjacent defected memory cell all.CPU1 then is that preparation is loaded into internal memory 3 by data/address bus 10 with original program code 20, and just comprises above-mentioned defected memory cell in original program code 20 storage unit that preparation loads originally.Therefore, performed loader (loader) in CPU1 must be carried out some pre-process actions, and the original program code 20 after can guaranteeing to load can not take defected memory cell, and original program code 20 still can be carried out normally itself simultaneously.In the present embodiment, CPU1 and internal memory 3 can coexist as in the same integrated circuit, the for example application of system-on-a-chip (system on a chip), in addition, it can also be integrated circuit independently individually, this moment, CPU1 was connected by specific I C pin with internal memory 3, was used for carrying out follow-up described defect inspection, processing or the like step.

The 4th figure represents the process flow diagram of the local defect internal memory disposal route of first embodiment, and the various steps of CPU1 necessary execution of institute before loading original program code 20 wherein are described in detail in detail.At first, CPU1 must determine the position (S10) of defected memory cell in internal memory 3.That is, need carry out defect test for internal memory 3, so that check out wherein whether include defected memory cell and its provider location.Whether a kind of storage unit of checking is the example of defective, is with data " 1 " and " 0 " write each storage unit, whether correct, if the data of writing and sense data misfit, promptly represent this storage unit defectiveness if reading its data again.The actual device of carrying out test can be CPU1 itself, can also be carried out by the tester or the computing machine of outside.

According to the loading message of resulting defected memory cell physical address and original program code 20 (for example loading the starting point address) after tested, just can determine this defected memory cell pairing defective addresses (S11) in original program code 20, that is this defected memory cell is in the absolute reference address of original program code 20 representatives.Because defected memory cell can't normal running, so the performed loader of CPU1 must allow the predetermined originally program code part that is stored in this defected memory cell, and change is loaded into other storage unit, to avoid the loss of data.Yet, according to aforementioned description for general machine program code as can be known, the disjunction arbitrarily of machine program code, some bytes may only be the parts of certain instruction, cannot be moved separately, to avoid the entanglement of instruction and data.Therefore, CPU1 must find out suitable branch breakpoint in original program code 20, could correctly move the byte that takies defected memory cell originally.

Then, scan (S12), so that find out all the divided breakpoints in the original program code 20 for original program code 20.In general machine program code, be between the individual instructions in the operation part and can divide breakpoint, even this be because individual instructions by disjunction, CPU1 still can go out correct command message by correct decoding when carrying out; Relatively, data division and storehouse part then can not disjunction, and this is because may have the correlativity that just may check out, for example array data between data and the storehouse when carrying out.On the other hand, CPU1 can't directly tell operation part and the other parts in the machine program code.Therefore, CPU1 must scan the operation part in the original program code 20 is whole, just can determine all divided breakpoints.

The 5th figure represents the scan method process flow diagram of original program code 20 in the present embodiment.So-called herein " scanning ", be to comprise acquisition operational code, decoding, these actions of acquisition operand, but do not need to carry out.In order to scan the whole operation part of original program code 20, must handle two kinds of common special kenels in the general machine program code especially, i.e. branch (branch) and circulation (loop).

Branch's kenel can produce two kinds of different instruction execution sequences in original program code 20, generally be to be caused by conditional branch instructions (conditional branch instruction), for example JNE, JE, JG or the like.In scanning process, in order to determine to handle all instructions, therefore two kinds of instruction execution sequences all need to be scanned.In the present embodiment, can set up first tables of data 30 (shown in the 5th figure) in the scanning process, when running into any conditional branch instructions, the next address of this branch instruction or branch's destination address (branch-toaddress) of this branch instruction can be stored in first tables of data 30.Whereby, after main instruction execution sequence is finished scanning, just can carry out the scanning of other execution sequence according to first tables of data 30.Need to prove in addition, general branch instruction also comprises a kind of unconditional branch instruction (unconditionalbranch instruction), JMP for example, but because this instruction can't cause two different instruction execution sequences, so the scanning in the present embodiment can be complied with its destination address (branch-to address) continuation scanning.On the other hand, cyclic pattern then can cause scanning to stop.And in the present embodiment, then be in scanning process, to set up second tables of data 40, be used for writing down the address realm that had been scanned, and instruction of every scanning promptly can be upgraded second tables of data 40.When multiple scanning is inner to circulation, just can judge scanned this part according to second tables of data 40, therefore can prevent to continue to scan follow-up instruction.

Below describe the action of each step among the 5th figure in detail.At first obtain program entry point (S110).Then obtain and specify the address (S111) of next instruction, and, read the operational code in the next instruction and decipher (S112) according to this address.If this instruction needs operand, read operands (S113) from subsequent address more then.This moment, the taker of reading was a complete instruction, and therefore can be recorded as one can divide breakpoint.Judge then whether this instruction is conditional branch instructions (S114), if, then can: (i) the branch's destination address with this conditional branch instructions joins in first tables of data 30 (S115), and continues scanning according to the next address of this conditional branch instructions; Or (ii) the next address of this conditional branch instructions is joined in first tables of data, and continue scanning according to branch's destination address of this conditional branch instructions.Then determine the next address (S116) of scanning, judge whether the instruction of this address is that link order (for example RET) or EOP (end of program) instruct (for example END) (S117).If the instruction of next address is not the instruction of link order or EOP (end of program), then judge that according to second tables of data 40 whether this address is scan address scope (S121).If the also non-scan address of this next address scope is then revised second tables of data 40 to upgrade (S122) after the scope of scan address, continue to handle next instruction.If the link order really of the instruction of next address or EOP (end of program) instruction in step S117, next address is scanned address realm also or in step S121, then judges whether still have address to be scanned (S118) in first tables of data 30.If still have, then from first tables of data 30, obtain an address to be scanned and it is removed (S119) from first tables of data 30, revise the scope of scan address (S122) in second tables of data 40 again, continue to handle the subsequent instructions of this address to be scanned.If when not had address to be scanned in first tables of data 30, then expression has scanned and has finished whole instruction (S120).Obtained all divided breakpoints this moment, and can judge operation part and data/storehouse part in the original program code 20.In the 5th figure, frame of broken lines P1 represents to handle the correlation step of branch's kenel, and frame of broken lines P2 then represents the correlation step of cycle of treatment kenel.

Processing action in the above-mentioned scanning process, can be briefly described as follows: when (1) is a conditional branch instructions (for example JNE, JE, JG or the like) when the instruction of being read, the branch order address or the next address of conditional branch instructions is recorded in first tables of data 30; (2) read when instruction when finishing, address realm and the output of just upgrading second tables of data 40 can divide breakpoint; (3) if the instruction of being read is that an END instruction or link order or its address are in the address realm of second tables of data 40, as long as certain address to be scanned of first tables of data 30 does not belong to the address realm of second tables of data 40, just continue to read from this address to be scanned of first tables of data 30.

According to the described scanning sequence of the 5th figure, below the action of its scanning is described with an example.The 6th figure represents to handle according to the 5th figure scan method the synoptic diagram of a program code example.Wherein, program entry point is Q1.When being scanned up to Q2 from Q1, read a conditional branch instructions JNE, in first tables of data 30, write down the destination address Q6 of branch of this conditional branch instructions JNE this moment.When continuing to be scanned up to Q3, then read a non-conditional branch instructions JMP.Do not need to store the destination address Q10 of its branch for non-conditional branch instructions JMP, but directly proceed scanning to its branch's destination address.Then scan Q11, then read two conditional branch instructions JG and JE in regular turn from Q10.Same, behind the destination address Q4 of branch and Q8 of these two instructions of 30 records of first tables of data, proceed scanning.When scanning Q12, read EOP (end of program) instruction END, therefore finish the scanning of mother block.At this moment, the zone of having scanned comprises C1, C2, C6, C7, then writes down the address to be scanned of Q6, Q4 and Q8 in first tables of data 30.Then, proceed scanning from first address Q6 to be scanned, till Q7 reads link order RET.Then proceed scanning from second address Q4 to be scanned again, up to scanning Q5, though do not read any END instruction or link order, its next address Q6 belongs to scanning area, therefore still finishes scanning.Then proceed scanning from the 3rd address Q8 to be scanned again, up to scanning Q9.Same, though do not read any END instruction or link order, its next address Q10 belongs to scanning area, therefore still finishes scanning.So far, do not had other address to be scanned in first tables of data 30, therefore whole scanning work is finished.In scanning process, can judge all divided breakpoints (be the front and back of each complete instruction be all to divide breakpoint), and judge C1-C7 and belong to operation part, D1-D3 then belongs to non-operation parts such as data or storehouse, and, can be regarded as non-instruction sections such as data or storehouse when scanning a continuous program code segments of finishing but being scanned not yet.

Get back to the 4th figure,, just can before and after the pairing defective addresses of defected memory cell, determine first fen breakpoint and second fen breakpoint (S13) respectively according to the resulting breakpoint that divides when the scanning motion of finishing original program code 20.Between each complete instruction or before, be all and divide breakpoint.Operation part (also may comprise data/storehouse part) between first fen breakpoint and the second fen breakpoint is called the section program code, and the section program code need be moved on other the address, to avoid defective addresses.In the present embodiment, the deciding means of first fen breakpoint and second fen breakpoint, be select with near defective addresses but and still exist the branch breakpoint of several bytes to be as the criterion between the defective addresses, that is still have several good storage unit between the first/the second fen breakpoint and the defective addresses, can be in order to store link order (this point describes in detail after a while).In the following description, be that example describes all with this kind situation.But above-mentioned branch Cut Selection mode is not in order to limit the present invention.For instance, the first/the second fen breakpoint also can according to and defective addresses between several can divide the mode of breakpoint to select at least at interval.In addition, if follow-up move mode is to adopt the mode of all program codes after the defective addresses toward bottom offset certain-length byte, this moment first fen breakpoint can according to before the defective addresses and and defective addresses between still exist the mode of several bytes to select, breakpoint then was located at the last of program code in second minute, promptly after last byte of this program code, and near the program code at the defective addresses and rear is made as the section program code that need move, and this section program code is moved to after this defective addresses, still can reach purpose of the present invention.

Determine then then this section program code to be moved between first address and second address (S14) after the section program code between first fen breakpoint and the second fen breakpoint.Must be noted that defective addresses should just not include defected memory cell in the storage unit of section program code after loading between first address and second address.After finishing the re-addressing of section program code, if the section program code that is moved comprises operation part, then must insert link order, allow the original program code still keep its program execution sequence.In the present embodiment, mainly be to insert two unconditional branch instructions (JMP) to reach purpose of connecting.First unconditional branch instruction is to be inserted on the address of first fen breakpoint, and its branch's destination address is the section program code that points to after moving; Second unconditional branch instruction is to be inserted in the back of moving back section program code, its branch's destination address then is the address of pointing to second fen breakpoint, if but the address of second fen breakpoint is provided in a side of the last of program code, then do not need this second unconditional branch instruction.Therefore, when program code is carried out instruction (it is the beginning part of section program code) on the breakpoint address in first fen, then can be by first unconditional branch instruction, the section program code that jump to after moving continues to carry out; After finishing the instruction of moving back section program code, then instruct and jump back to the instruction on the breakpoint address in second fen by second unconditional branch.In addition,, then do not need to add link order, only need to revise relative reference address and get final product if the section program code is simple data/storehouse part.

The 7th figure represents in the present embodiment to connect and moves the not synoptic diagram of movable part of back section program code and original program code.As shown in the figure, original program code 20 has comprised each program code A-G, and defective addresses 21 then is positioned at program code E, then determines first fen breakpoint and second fen breakpoint respectively in the front and back of program code E.When mobile code E to the new address realm, the program code E ' after promptly occurring moving.Symbol 51 and 52 represent respectively to insert first/second unconditional branch instruction.After program code D is complete, promptly jump to program code E ' by first unconditional branch instruction; After program code E ' is complete, then again by second unconditional branch instruction rebound program code F.Therefore, the program execution sequence of original program code can be kept, and only needs two unconditional branches instructions of many execution to get final product.

After the connecting moves of completing steps S15, the preposition action that CPU1 loads is roughly finished, and common reference address (reference address) also is untreated in the only remaining general machine program code.If the reference address in original program code 20 with move after the section program code relevant, then must check and revise.Therefore, CPU1 must revise relevant reference address (S16).The 8th figure is illustrated in the synoptic diagram of revising reference address in the present embodiment.As shown in the figure, have in the original program code 20 three kinds can be relevant with reference to the address with the program code E that comprises defective addresses 21, be denoted as R1, R2, R3 respectively.The reference address of instructing among the R1 representation program code E is pointed to the situation of address among the program code E; The situation of address among the reference address sensing program code E that R2 represents to instruct in other program code (for example program code B); The reference address of instructing among the R3 representation program code E is pointed to the situation of other program code (as program code B).These reference addresss must be revised its reference address (as R1 ', R2 ', R3 '), so that produce the actual machine program code 60 that can be loaded into internal memory 3 for behind the program code E ' after program code E moves.

Revise reference address, CPU1 can scan once more for whole original program code 20, so that find out and the relevant reference address of section program code that comprises defective addresses.In addition, general reference address can be subdivided into two kinds of addressing modes (addressing mode) again, is respectively relative address addressing mode (relative addressing mode) and specific address addressing mode (absolute addressing mode).If with above-mentioned three kinds consider in the lump with reference to the address situation, then have six types.In the reference address of R1, have only the reference address of specific address addressing mode just to need to revise.In the reference address of R3, have only the reference address of relative address addressing mode just to need to revise.Then reaching specific address in the reference address of R2 relatively all needs to revise.When revising the reference address of above-mentioned specific address addressing mode (all being to point to section program code E), the relative shift that then adds in this reference address between program code E and the mobile back program code E ' gets final product.If will revise the reference address of above-mentioned relative address addressing mode, can also utilize the relative shift between program code E and the mobile back program code E ' to reach.But the relative address addressing mode generally has its restriction in the use, that is relative address can limit within the specific limits usually, therefore in that handle can be comparatively complicated on the relative address addressing mode.For example, a considerable amount of storage available are all reserved in the front and back in defective addresses 21 in the present embodiment, then can utilize the instruction of this part insertion connection and reach identical effect indirectly; In addition, also can select the past rear (being the direction of higher address) of all program codes several bytes of displacement with defective addresses 21 back, so that avoid defected memory cell, so also can avoid moving the puzzlement that consequently surpasses relative address addressing mode scope far away because of a section program code; Another kind of settling mode then is a coded format of adjusting editing machine, for example adopt specific address as far as possible and avoid using relative address to encode, or will change specific address addressing sign indicating number into because of the addressing sign indicating number that a section program code moved relative address far away and affected.

When finishing above-mentioned pre-process, the loader of CPU1 just can be with original program code, link order and the section program code after moving be loaded in the internal memory 3, finish all steps (S17).Be moved owing to can take the section program code of defected memory cell originally, so program code can be carried out and operate normally.

In addition, though above-mentioned explanation is to be example with single defected memory cell, for haveing the knack of this skill person, can extend the situation that is applied to a plurality of defected memory cells, its base conditioning pattern is still identical.In addition, though be that scan mode with byte decides to divide breakpoint in the present embodiment, for haveing the knack of this skill person, also can with the original program code in addition modularization (modularized) can divide breakpoint to make things convenient for decision.Do not need to carry out this moment as the scanning motion described in the present embodiment, just can utilize better simply scanning sequence to determine first fen breakpoint and second fen breakpoint before and after the defective addresses.

The disposal route of above disclosed local defect internal memory and system, though be to be example, but its best exemplary applications should be on system-on-a-chip (system-on-a-chip) or single-chip computing machine (single chip computer) with general computer system.In this type systematic, memory modules generally is built-in (embedded), can't replace arbitrarily.Finding just can to utilize disclosed method in the present embodiment under the defective situation of partial memory cell, entire chip normal executive routine code still after processing.In addition, disclosed local defect internal memory can also be useful in the application of burning program in the present embodiment, for example flash memory (flash memory) or electronics can be smeared on the burning program of formula PROM (electricallyerasable programmable read-only memory), even the LSU local store unit defectiveness still can use.The most important thing is that present embodiment can't increase the cost and the complexity of hardware design on the implementation, and the burden when carrying out for software is also come gently than prior art.Hence one can see that, and the present invention has high industrial utilization.

Second embodiment:

Though disclosed the processing mode of certain program among first embodiment, can solve the problem of local defect internal memory, still have subprogram to change therebetween.For example, present embodiment then is to change the scan process mode of its original program code and load the order of internal memory and produce for first embodiment.

The 9th figure represents the process flow diagram of the local defect internal memory disposal route of second embodiment.Shown in the 9th figure, CPU1 determines the provider location (S20) of defected memory cell and determines defected memory cell pairing defective addresses (S21) in original program code 20 on the one hand, also scans (S22) for original program code 20 on the other hand.Can determine the defective addresses of defected memory cell by step S20 and step S21, then can determine divided breakpoint in the original program code 20 by step S22.This synchronous processing goes for having among the CPU or the system of multiple CPU of multitask function.Then, just can further determine first fen breakpoint and second fen breakpoint (S23), just need the section program code scope that moves according to defective addresses and the address that can divide breakpoint.

Sequence of steps then is then different with first embodiment.Earlier whole original program code 20 is loaded into (S24) in the internal memory 3, the section program code that comprise defective addresses this moment also can be loaded in the defected memory cell adjacent memory unit, but owing to wherein comprise defected memory cell, so the section program code of this part can't actually use.Then, load once more this section program code in the internal memory 3 first storage unit and second storage unit between (S25), between first storage unit and second storage unit, then do not comprise defected memory cell.Then then identical with first embodiment, insert link order so that the other parts (S26) in jointing program code and the original program code 20, and revise reference address (S27) wherein.The same with first embodiment, this moment, the program code in internal memory 3 can normally be carried out, and the actual program code of carrying out can not be stored in the defected memory cell.

In a second embodiment, be the section program code after loading earlier original program code 20 respectively and moving, the processing that connects again and revise reference address.The processing mode of this sample can also obtain preferable treatment effeciency except can reaching the identical effect of first embodiment.The source of general original program code mostly is outside storing media, for example Winchester disk drive, floppy drive or the like.Carry out connecting moves and revise reference address etc. when handling, on processing speed than internal memory 3 slowly, particularly when revising reference address, must scan for whole original program code 3 once more.And in the present embodiment, all pending program codes all have been loaded in internal memory 3, therefore can finish above-mentioned treatment step quickly.In addition, the original program code also can be stored in the known flawless internal memory, as ROM, RAM or PROM, can accelerate the speed of said procedure code scans, but this mode needs this original program code temporarily or is for a long time deposited in other good internal memory, or determines not contain the part of defected memory cell in the internal memory.

The 3rd embodiment:

First and second embodiment are applicable to that the original program code does not also load the situation in the internal memory, and CPU this moment (microprocessor) can promptly impose pre-process before the original program code does not also load internal memory, avoid defected memory cell so that adjust program code.And present embodiment situation to be processed then is successfully to have loaded in the internal memory when the original program code, but the partial memory cell but phenomenon of Presentation Function reduction over time.Though the storage unit of these functions reduction can normally read at present, after certain hour, will become from its logical value of reading more and more is difficult to recognize.Must be adjusted this moment for the original program code content in the internal memory, to avoid the defected memory cell of these function reductions.

The 10th figure represents the arrangement plan of the local defect internal memory disposal system of the 3rd embodiment.Shown in the 10th figure, original program code 20 has loaded in the internal memory 3 at this moment.And in the system operation process, then can pass through CPU1 itself or other outside processor or tester, periodically test for each storage unit in the internal memory 3.If when the data that certain storage unit is read in test more and more have been difficult to recognize, then promptly to set this storage unit be defected memory cell to CPU1, and carry out the following disclosed disposal route of this enforcement, so that stop using the defected memory cell of function reduction.

The 11st figure represents the process flow diagram of the local defect internal memory disposal route of the 3rd embodiment.Shown in the 11st figure, original program code 20 is (S30) in the internal memory 3 Already in.At this moment, CPU1 can scan (S31) for original program code 20 on the one hand, obtains all the divided breakpoints in the original program code 20; Also carry out periodically testing and determining the wherein defected memory cell (S32) of function reduction on the other hand for internal memory 3.Because original program code 20 has loaded on internal memory 3, therefore can judge corresponding defective addresses soon according to defected memory cell.Then can divide the address of breakpoint, just can further determine first fen breakpoint and second fen breakpoint (S33), just need the section program code scope that moves according to defective addresses and all.

Earlier in internal memory 3, find out one section normally functioning memory block (promptly between first storage unit and second storage unit), so that hold the section program code that needs move.Then this section program code is copied between first storage unit and second storage unit (S34).Then then identical with first embodiment, insert link order so that the other parts (S35) in jointing program code and the original program code 20, and revise reference address (S36) wherein.This moment, the program code in internal memory 3 can normally be carried out, and the actual program code of carrying out can not be stored in the defected memory cell of function reduction.

In addition, as containing a plurality of and non-conterminous defected memory cell in the above-mentioned internal memory, also can use the present invention and produce array and the corresponding breakpoint group of dividing of these defected memory cells, and can divide several code segments between the breakpoint group to move to several different new addresses these, and do the corrigendum of relevant reference address, to produce the program code of more correcting one's mistakes that when carrying out, can avoid these defected memory cells.

Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a spot of change and retouching, so protection scope of the present invention is when looking claim and being as the criterion in conjunction with instructions and accompanying drawing.

Claims

1. one kind loads internal memory for the method for carrying out with program code, is applicable to the internal memory that comprises a plurality of storage unit and to be loaded in an original program code of above-mentioned internal memory, and it is characterized in that: it comprises the following steps:

2. as claimed in claim 1 program code is loaded internal memory for the method for carrying out, it is characterized in that: also comprise a step:

Revise in above-mentioned section program code and the above-mentioned original program code the not reference address between the movable part.

3. as claimed in claim 2 program code is loaded internal memory for the method for carrying out, it is characterized in that: above-mentioned correction step is in order to revising above-mentioned section program code after moving for the relative addressing schema reference address of movable part not in the above-mentioned original program code, and revises in the above-mentioned original program code not movable part for the relative addressing schema reference address and the absolute addressing schema reference address of the above-mentioned section program code after moving.

4. as claimed in claim 2 program code is loaded internal memory for the method for carrying out, it is characterized in that: also comprise a step:

Revise the absolute addressing schema reference address in the above-mentioned section program code after moving.

5. as claimed in claim 1 program code is loaded internal memory for the method for carrying out, it is characterized in that: wherein scan in the step of above-mentioned original program code and also comprise the following steps:

Read above-mentioned original program code in regular turn;

Form according to each instruction in the above-mentioned original program code, export a plurality of breakpoints that divide; And

According to the above-mentioned link order of above-mentioned defective addresses and insertion, determine above-mentioned first minute breakpoint and above-mentioned second minute breakpoint.

6. as claimed in claim 5 program code is loaded internal memory for the method for carrying out, it is characterized in that: read in regular turn in the step of above-mentioned original program code and also comprise the following steps:

One first tables of data and one second tables of data are provided, and above-mentioned first tables of data is in order to write down branch's destination address of conditional branch instructions in the above-mentioned original program code, the address realm that above-mentioned second tables of data has read in order to record;

When the instruction of being read was a conditional branch instructions, the branch's destination address that writes down above-mentioned conditional branch instructions was in above-mentioned first tables of data;

Read when instruction when finishing, upgrade the address realm of above-mentioned second tables of data; And

When the instruction of being read is that an END instruction or its address are in the address realm of above-mentioned second tables of data time, and when branch's destination address of above-mentioned first tables of data did not belong to the address realm of above-mentioned second tables of data, then the branch's destination address according to above-mentioned first tables of data continued to read.

7. as claimed in claim 1 program code is loaded internal memory for the method for carrying out, it is characterized in that: in the above-mentioned Connection Step, be to insert first unconditional branch to instruct on the address of above-mentioned first minute breakpoint, the destination address of above-mentioned first unconditional branch instruction is first address after above-mentioned section program code moves, and insert second unconditional branch and instruct second address after above-mentioned section program code moves, the destination address of above-mentioned second unconditional branch instruction is above-mentioned second minute breakpoint.

8. as claimed in claim 1 program code is loaded internal memory for the method for carrying out, it is characterized in that: breakpoint was after last byte of above-mentioned original program code in above-mentioned second minute.

9. internal memory disposal system, in order to handle an internal memory that comprises a plurality of storage unit, it is characterized in that: it comprises:

10. internal memory disposal system as claimed in claim 9 is characterized in that: breakpoint was after last byte of above-mentioned original program code in above-mentioned second minute.

11. internal memory disposal system as claimed in claim 9, it is characterized in that: the reference address between the movable part not in the above-mentioned section program code after above-mentioned microprocessor is also revised and moved and the above-mentioned original program code, and the interior reference address of the above-mentioned section program code after moving.

12. internal memory disposal system as claimed in claim 9, it is characterized in that: in the connecting moves of above-mentioned microprocessor, be to insert first unconditional branch to instruct on the address of above-mentioned first minute breakpoint, the destination address of above-mentioned first unconditional branch instruction is first address after above-mentioned section program code moves, and insert second unconditional branch and instruct second address after above-mentioned section program code moves, the destination address of above-mentioned second unconditional branch instruction is above-mentioned second minute breakpoint.

13. internal memory disposal system as claimed in claim 9 is characterized in that: above-mentioned internal memory and above-mentioned microprocessor are to place in the same chip.

14. internal memory disposal system as claimed in claim 9 is characterized in that: above-mentioned internal memory is to place in the independently different chips with above-mentioned microprocessor.

15. prevent and treat the local weakness internal memory processing method for one kind, be applicable to an internal memory of loading with an original program code, it is characterized in that: it comprises the following steps:

16. the local weakness internal memory processing method of preventing and treating as claimed in claim 15 is characterized in that: breakpoint was after last byte of above-mentioned original program code in above-mentioned second minute.

17. the local weakness internal memory processing method of preventing and treating as claimed in claim 15 is characterized in that: also comprise a step:

The reference address between the movable part not in above-mentioned section program code after revise moving and the above-mentioned original program code.

18. the local weakness internal memory processing method of preventing and treating as claimed in claim 17, it is characterized in that: above-mentioned correction step is in order to revising above-mentioned section program code after moving for the relative addressing schema reference address of movable part not in the above-mentioned original program code, and revises in the above-mentioned original program code not movable part for the relative addressing schema reference address and the absolute addressing schema reference address of the above-mentioned section program code after moving.

19. the local weakness internal memory processing method of preventing and treating as claimed in claim 18 is characterized in that: also comprise a step:

20. the local weakness internal memory processing method of preventing and treating as claimed in claim 15 is characterized in that: scan in the step of above-mentioned original program code and also comprise the following steps:

Read above-mentioned original program code in regular turn;

21. the local weakness internal memory processing method of preventing and treating as claimed in claim 20 is characterized in that: read in regular turn in the step of above-mentioned original program code and also comprise the following steps:

22. the local weakness internal memory processing method of preventing and treating as claimed in claim 15, it is characterized in that: in the above-mentioned Connection Step, be to insert first unconditional branch to instruct on the address of above-mentioned first minute breakpoint, the destination address of above-mentioned first unconditional branch instruction is first storage unit after above-mentioned section program code moves, and insert second unconditional branch and instruct after second storage unit after above-mentioned section program code moves, the destination address of above-mentioned second unconditional branch instruction is above-mentioned second minute breakpoint.

23. an internal memory disposal system comprises a plurality of storage unit and stored the internal memory of an original program code in order to handle one, it is characterized in that: it comprises:

24. internal memory disposal system as claimed in claim 23 is characterized in that: breakpoint was after last byte of above-mentioned original program code in above-mentioned second minute.

25. internal memory disposal system as claimed in claim 23 is characterized in that: above-mentioned microprocessor is directly to be coupled to above-mentioned internal memory.

26. internal memory disposal system as claimed in claim 23, it is characterized in that: the reference address between the movable part not in the above-mentioned section program code after above-mentioned microprocessor is also revised and moved and the above-mentioned original program code, and the interior reference address of the above-mentioned section program code after moving.

27. internal memory disposal system as claimed in claim 23, it is characterized in that: in the connecting moves of above-mentioned microprocessor, be to insert first unconditional branch to instruct on the address of above-mentioned first minute breakpoint, the destination address of above-mentioned first unconditional branch instruction is first storage unit after above-mentioned section program code moves, and insert second unconditional branch and instruct second storage unit after above-mentioned section program code moves, the destination address of above-mentioned second unconditional branch instruction is above-mentioned second minute breakpoint.

28. internal memory disposal system as claimed in claim 23 is characterized in that: above-mentioned internal memory and above-mentioned microprocessor are that to place be to place in the same chip.

29. internal memory disposal system as claimed in claim 23 is characterized in that: above-mentioned internal memory and above-mentioned microprocessor are that to place be to place in the independently different chips.

30. an internal memory processing method is applicable to the internal memory that comprises a plurality of storage unit and to be loaded in an original program code of above-mentioned internal memory, it is characterized in that: it comprises the following steps:

Load above-mentioned original program code to above-mentioned internal memory;

31. internal memory processing method as claimed in claim 30 is characterized in that: also comprise a step:

Correction between above-mentioned first storage unit and second storage unit above-mentioned section program code and above-mentioned original program code in reference address between the other parts.

32. internal memory processing method as claimed in claim 31, it is characterized in that: above-mentioned correction step is in order to revising above-mentioned section program code between above-mentioned first storage unit and second storage unit for the relative addressing schema reference address of other parts in the above-mentioned original program code, and revises in the above-mentioned original program code other parts for the relative addressing schema reference address and the absolute addressing schema reference address of the above-mentioned section program code between above-mentioned first storage unit and second storage unit.

33. internal memory processing method as claimed in claim 32 is characterized in that: also comprise a step:

Absolute addressing schema reference address in the above-mentioned section program code of correction between above-mentioned first storage unit and second storage unit.

34. internal memory processing method as claimed in claim 30 is characterized in that: scan in the step of above-mentioned original program code and also comprise the following steps:

Read above-mentioned original program code in regular turn;

35. internal memory processing method as claimed in claim 34 is characterized in that: read in regular turn in the step of above-mentioned original program code and also comprise the following steps:

36. internal memory processing method as claimed in claim 30, it is characterized in that: in the above-mentioned Connection Step, be to insert first unconditional branch to instruct on the address of above-mentioned first minute breakpoint, the destination address of above-mentioned first unconditional branch instruction is first storage unit of above-mentioned section program code, and insert second unconditional branch and instruct in second storage unit of above-mentioned section program code, the destination address of above-mentioned second unconditional branch instruction is above-mentioned second minute breakpoint.

37. an internal memory disposal system, in order to handle an internal memory that comprises a plurality of storage unit, it is characterized in that: it comprises:

38. internal memory disposal system as claimed in claim 37 is characterized in that: breakpoint was after last byte of above-mentioned original program code in above-mentioned second minute.

39. internal memory disposal system as claimed in claim 37, it is characterized in that: above-mentioned microprocessor is also revised the reference address between the other parts in above-mentioned section program code between above-mentioned first storage unit and second storage unit and the above-mentioned original program code, and the reference address in the above-mentioned section program code between above-mentioned first storage unit and second storage unit.

40. internal memory disposal system as claimed in claim 37, it is characterized in that: in the above-mentioned connecting moves of above-mentioned microprocessor, be to insert first unconditional branch to instruct on the address of above-mentioned first minute breakpoint, the destination address of above-mentioned first unconditional branch instruction is first storage unit of above-mentioned section program code, and insert second unconditional branch and instruct in second storage unit of above-mentioned section program code, the destination address of above-mentioned second unconditional branch instruction is above-mentioned second minute breakpoint.

41. internal memory disposal system as claimed in claim 37 is characterized in that: above-mentioned internal memory and above-mentioned microprocessor are that to place be to place in the same chip.

42. internal memory disposal system as claimed in claim 37 is characterized in that: above-mentioned internal memory and above-mentioned microprocessor are that to place be to place in the independently different chips.

43. a program code scans disposal route in order to determine the divided breakpoint of an original program code, is characterized in that: said procedure code scans disposal route comprises the following steps:

Read above-mentioned original program code in regular turn;

44. program code scans disposal route as claimed in claim 43 is characterized in that: said procedure code scans disposal route is when an original program code loads an internal memory, determines movably section program code.

45. program code scans disposal route as claimed in claim 44 is characterized in that: above-mentioned internal memory comprises at least one defected memory cell.

46. program code scans disposal route as claimed in claim 43 is characterized in that: the address to be scanned that above-mentioned conditional branch instructions is relevant is branch's destination address of above-mentioned conditional branch instructions.

47. program code scans disposal route as claimed in claim 43 is characterized in that: the address to be scanned that above-mentioned conditional branch instructions is relevant is the next address of above-mentioned conditional branch instructions.

48. program code scans disposal route as claimed in claim 43 is characterized in that: also comprise a step:

When the instruction of being read was unconditional branch instruction, then the branch's destination address by above-mentioned unconditional branch instruction continued scanning.

49. program code scans disposal route as claimed in claim 43, it is characterized in that: when above-mentioned instruction of reading is that an END instruction or its address are in the address realm of above-mentioned second tables of data, and during no address to be scanned, then finish scanning in above-mentioned first tables of data.

50. program code scans disposal route as claimed in claim 43 is characterized in that: when the end of scan, a continuous program code address that is scanned not yet is judged to be a data program code segments.

51. program code scans disposal route as claimed in claim 43 is characterized in that: when the end of scan, a continuous program code address that is scanned not yet is judged to be data or storehouse code segment.

52. program code scans disposal route as claimed in claim 43 is characterized in that: when the end of scan, a continuous program code address that is scanned not yet is judged to be a non-instruction section.