CN116800293A - Base band chip and radio frequency chip synchronization method, base band chip and radio frequency chip - Google Patents
Base band chip and radio frequency chip synchronization method, base band chip and radio frequency chip Download PDFInfo
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Abstract
The application relates to a baseband chip and radio frequency chip synchronization method, a baseband chip and a radio frequency chip, and belongs to the technical field of wireless communication. The method comprises the following steps: the baseband chip respectively sends a data receiving and transmitting mode switching signal, a first clock signal, a first enabling signal and a second enabling signal to a corresponding PAD, and then sends the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal to the baseband chip and the radio frequency chip at the same time through the PAD; the radio frequency chip sends the second clock signal to the corresponding PAD, and then sends the second clock signal to the baseband chip and the radio frequency chip at the same time through the PAD. The method provided by the application enables the baseband chip and the radio frequency chip to simultaneously respond to the clock signal and the control signal by changing the wiring path design of the interface signals of the baseband chip and the radio frequency chip, and performs data transmission through the bidirectional data interface, thereby realizing the synchronization of the baseband chip and the radio frequency chip.
Description
Technical Field
The application relates to the technical field of wireless communication, in particular to a baseband chip and radio frequency chip synchronization method, a baseband chip and a radio frequency chip.
Background
In wireless communication, the most important core is a baseband chip and a radio frequency chip, wherein the radio frequency chip is responsible for radio frequency transceiving, frequency synthesis and power amplification, and the baseband chip is responsible for signal processing and protocol processing. When signals are sent, the baseband chip processes information first, the processed signals are transmitted to the radio frequency chip, and the radio frequency chip transmits the processed signals; when receiving signals, the radio frequency chip receives external signals and transmits the signals to the baseband chip, and the baseband chip processes the signals, so that a large amount of data interaction exists between the baseband chip and the radio frequency chip.
The HRF baseband chip and the radio frequency chip are used as two chips needing data interaction, and the connection can be realized by a sealing (SIP, system in package) or board-level (PCB, printed circuit board) mode, but delay problems exist in any connection mode. On one hand, the delay problem can lead to the problem of static time sequence analysis of the chip, increase the difficulty of back-end design, and on the other hand, the receiving-transmitting switching is slower, so that the efficiency of data transmission is reduced, and even data loss can be caused when the data transmission speed is faster.
In summary, there is delay in data transmission between the existing baseband chip and the radio frequency chip, so that the static timing problem of the chip and the switching speed of data receiving and transmitting are reduced, and even data is lost.
Disclosure of Invention
Therefore, the application aims to solve the technical problems that the static time sequence problem of the chip and the data receiving and transmitting switching speed are reduced and even the data is lost due to the fact that time delay exists when data interaction is carried out between the baseband chip and the radio frequency chip in the prior art.
In order to solve the above technical problems, the present application provides a baseband chip, including:
the data receiving and transmitting mode switching end is connected to the first PAD, and transmits a data receiving and transmitting mode switching signal to the first PAD, and the first PAD simultaneously transmits the data receiving and transmitting mode switching signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip, so that the baseband chip and the radio frequency chip simultaneously respond to the data receiving and transmitting mode switching signal;
the first clock end is connected to the second PAD, when the data receiving and transmitting mode switching signal is at a high level, a first clock signal is sent to the second PAD, and the second PAD simultaneously sends the first clock signal to the first clock end of the baseband chip and the first clock end of the radio frequency chip so that the baseband chip and the radio frequency chip simultaneously respond to the first clock signal;
the first enabling end is connected to a third PAD, a first enabling signal is sent to the third PAD, and the third PAD simultaneously sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip so that the baseband chip and the radio frequency chip simultaneously respond to the first enabling signal;
the second enabling end is connected to a fourth PAD, a second enabling signal is sent to the fourth PAD, and the fourth PAD simultaneously sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip so that the baseband chip and the radio frequency chip simultaneously respond to the second enabling signal;
the bidirectional data interface is used for sending data to the radio frequency chip when the data receiving and transmitting mode switching signal is at a high level; and when the data receiving and transmitting mode switching signal is at a low level, receiving the data sent by the radio frequency chip.
In one embodiment of the present application, further comprising:
and the second clock end is connected to a fifth PAD, and when the data receiving and transmitting mode switching signal is at a low level, the second clock signal sent by the PAD corresponding to the second clock end of the radio frequency chip is received through the fifth PAD, so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time.
The application also provides a radio frequency chip, comprising:
the data receiving and transmitting mode switching end is connected to the sixth PAD, and receives a data receiving and transmitting mode switching signal sent by the first PAD corresponding to the data receiving and transmitting mode switching end of the baseband chip through the sixth PAD, so that the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal at the same time;
the first clock end is connected to a seventh PAD, and when the data receiving and transmitting mode switching signal is at a high level, a first clock signal sent by a second PAD corresponding to the first clock end of the baseband chip is received through the seventh PAD, so that the baseband chip and the radio frequency chip respond to the first clock signal at the same time;
the first enabling end is connected to an eighth PAD, and receives a first enabling signal sent by a third PAD corresponding to the first enabling end of the baseband chip through the eighth PAD, so that the baseband chip and the radio frequency chip respond to the first enabling signal at the same time;
the second enabling end is connected to a ninth PAD, and a second enabling signal sent by a fourth PAD corresponding to the second enabling end of the baseband chip is received through the ninth PAD, so that the baseband chip and the radio frequency chip respond to the second enabling signal at the same time;
the bidirectional data interface is used for receiving data sent by the baseband chip when the data receiving and transmitting mode switching signal is at a high level; and when the data receiving and transmitting mode switching signal is in a low level, transmitting data to the baseband chip.
In one embodiment of the present application, further comprising:
and the second clock end is connected to a tenth PAD, when the data receiving and transmitting mode switching signal is at a low level, a second clock signal is sent to the tenth PAD, and the tenth PAD simultaneously sends the second clock signal to the second clock end of the radio frequency chip and the second clock end of the baseband chip so that the baseband chip and the radio frequency chip simultaneously respond to the second clock signal.
The application also provides a baseband chip and radio frequency chip synchronization method, which comprises the following steps:
the data receiving and transmitting mode switching end of the baseband chip sends a data receiving and transmitting mode switching signal to a first PAD, and the first PAD simultaneously sends the data receiving and transmitting mode switching signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip;
if the data receiving and transmitting mode switching signal is in a high level, a first clock end of the baseband chip sends a first clock signal to a second PAD, and the second PAD simultaneously sends the first clock signal to the first clock end of the baseband chip and the first clock end of the radio frequency chip;
the first enabling end of the baseband chip sends a first enabling signal to a third PAD, and the third PAD sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip at the same time;
the second enabling end of the baseband chip sends a second enabling signal to a fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time;
the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal at the same time, and data are sent to a bidirectional data interface of the radio frequency chip through the bidirectional data interface of the baseband chip.
In one embodiment of the present application, if the data transceiver mode switching signal is at a low level, the second clock terminal of the radio frequency chip sends a second clock signal to a tenth PAD, and the tenth PAD sends the second clock signal to the second clock terminal of the baseband chip and the second clock terminal of the radio frequency chip at the same time;
the first enabling end of the baseband chip sends a first enabling signal to a third PAD, and the third PAD sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip at the same time;
the second enabling end of the baseband chip sends a second enabling signal to a fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time;
the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the second clock signal, the first enabling signal and the second enabling signal at the same time, and data are sent to the bidirectional data interface of the baseband chip through the bidirectional data interface of the radio frequency chip.
In one embodiment of the present application, when the first enable signal is at a high level, the baseband chip and the radio frequency chip enter an operating state at the same time based on the first enable signal.
In one embodiment of the present application, when the second enable signal is at a low level, the baseband chip and the radio frequency chip perform automatic gain control on received data based on the second enable signal, and when the automatic gain control is locked, the second enable signal becomes at a high level.
In one embodiment of the present application, the bidirectional data interfaces of the baseband chip and the radio frequency chip each include 12 parallel data lines.
The method for synchronizing the baseband chip and the radio frequency chip comprises the following steps: the data receiving and transmitting mode switching end of the baseband chip sends a data receiving and transmitting mode switching signal to a first PAD, and the first PAD simultaneously sends the data receiving and transmitting mode switching signal to the baseband chip and the radio frequency chip so that the baseband chip and the radio frequency chip synchronously adjust a data sending or receiving mode; when the data receiving and transmitting mode switching signal is at a high level, a first clock end of the baseband chip sends a first clock signal to a second PAD, and the second PAD simultaneously sends the first clock signal to the baseband chip and the radio frequency chip, so that the baseband chip and the radio frequency chip simultaneously respond to the first clock signal; when the data receiving and transmitting mode switching signal is at a low level, a second clock end of the radio frequency chip sends a second clock signal to a corresponding PAD, and the PAD sends the second clock signal to the baseband chip and the radio frequency chip at the same time, so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time; the first enabling end and the second enabling end of the baseband chip respectively send a first enabling signal and a second enabling signal to a third PAD and a fourth PAD, and the third PAD and the fourth PAD simultaneously send the first enabling signal and the second enabling signal to the baseband chip and the radio frequency chip; the wiring path design based on the first clock signal, the second clock signal and the control signal is such that the baseband chip and the radio frequency chip remain synchronized.
According to the application, the wiring paths of the clock signal and the control signal are designed on the baseband chip and the radio frequency chip, so that the time difference between the clock signal and the control signal reaching the baseband chip and the radio frequency chip is reduced, the synchronization of the baseband chip and the radio frequency chip is realized, the static time sequence problem of the chip is simplified, the switching speed of the data receiving and transmitting modes of the baseband chip and the radio frequency chip is improved, and the problem of data loss is avoided.
Drawings
In order that the application may be more readily understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, in which,
FIG. 1 is a schematic diagram of a signal routing path of a baseband chip interface provided by the present application;
FIG. 2 is a schematic diagram of a signal routing path of an RF chip interface provided by the present application;
FIG. 3 is a schematic diagram of a baseband chip and RF chip connection provided by the present application;
FIG. 4 is a flowchart of a method for synchronizing a baseband chip and a radio frequency chip provided by the application;
description of the drawings: 1. a first PAD; 2. a second PAD; 3. a third PAD; 4. a fourth PAD; 5. a fifth PAD; 6. a sixth PAD; 7. a seventh PAD; 8. an eighth PAD; 9. a ninth PAD; 10. tenth PAD.
Detailed Description
The present application will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the application and practice it.
Example 1
Referring to fig. 1, a baseband chip provided by the present application includes:
the data receiving and transmitting mode switching end is connected to the first PAD, and transmits a data receiving and transmitting mode switching signal to the first PAD, and the first PAD simultaneously transmits the data receiving and transmitting mode switching signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip, so that the baseband chip and the radio frequency chip simultaneously respond to the data receiving and transmitting mode switching signal.
The first clock end is connected to the second PAD, when the data receiving and transmitting mode switching signal is at a high level, the first clock signal is sent to the second PAD, and the second PAD simultaneously sends the first clock signal to the first clock end of the baseband chip and the first clock end of the radio frequency chip, so that the baseband chip and the radio frequency chip simultaneously respond to the first clock signal.
The first enabling end is connected to the third PAD, a first enabling signal is sent to the third PAD, and the third PAD simultaneously sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip, so that the baseband chip and the radio frequency chip simultaneously respond to the first enabling signal.
The second enabling end is connected to the fourth PAD, a second enabling signal is sent to the fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time, so that the baseband chip and the radio frequency chip respond to the second enabling signal at the same time.
The bidirectional data interface is used for transmitting data to the radio frequency chip when the data receiving and transmitting mode switching signal is at a high level; when the data receiving and transmitting mode switching signal is at a low level, data sent by the radio frequency chip is received.
Specifically, the bidirectional data interface in this embodiment includes 12 parallel data lines, and each data line corresponds to a different PAD, through which data is sent or received.
In some embodiments of the application, the baseband chip further comprises:
the second clock end is connected to the fifth PAD, and when the data receiving and transmitting mode switching signal is at a low level, the second clock signal sent by the PAD corresponding to the second clock end of the radio frequency chip is received through the fifth PAD, so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time.
As shown in fig. 1, an exemplary baseband chip schematic diagram provided by the present application is shown, wherein BBP is a baseband, trx_m is a DATA transceiver mode switching end of the baseband chip, BBCLK is a first clock end of the baseband chip, ENABLE is a first ENABLE end of the baseband chip, agc_enb is a second ENABLE end of the baseband chip, DATA is a bidirectional DATA interface of the baseband chip, and RFCLK is a second clock end of the baseband chip.
Specifically, when the data receiving and transmitting mode switching end of the baseband chip sends a data receiving and transmitting mode switching signal, the baseband chip does not immediately respond to the signal, but sends the data receiving and transmitting mode switching signal to the first PAD, and then sends the signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip through the first PAD, and the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal sent by the first PAD at the same time.
When the data receiving and transmitting mode switching signal is at a high level, the baseband chip and the radio frequency chip are used as a whole to transmit data to an external data transmitting mode, the baseband chip transmits the data to the radio frequency chip, and the radio frequency chip receives the data transmitted by the baseband chip and transmits the data to the outside.
At this time, the first clock signal sent by the BBCLK is used as a sending clock for sending data to the baseband chip, the baseband chip does not respond to the first clock signal immediately, but sends the first clock signal to the second PAD, and then sends the first clock signal to the baseband chip and the radio frequency chip through the second PAD, so that the baseband chip and the radio frequency chip respond to the first clock signal sent by the second PAD at the same time.
ENABLE is effective as the first enabling end of baseband chip, and the baseband chip does not respond to the first enabling signal immediately, but sends the first enabling signal to the third PAD, and sends the first enabling signal to the baseband chip and the radio frequency chip through the third PAD, so that the baseband chip and the radio frequency chip respond to the first enabling signal simultaneously and enter a working state.
The agc_enb is effective at a low level as a second enable terminal of the baseband chip, the baseband chip does not immediately respond to the second enable signal, but transmits the second enable signal to a fourth PAD, and simultaneously transmits the second enable signal to the baseband chip and the radio frequency chip through the fourth PAD, so that the baseband chip and the radio frequency chip perform Automatic Gain Control (AGC) on received data based on the second enable signal, and the second enable signal becomes a high level after the AGC is locked.
At this time, the baseband chip and the radio frequency chip respond to the data transceiving mode switching signal, the first clock signal, the first enabling signal and the second enabling signal at the same time, and data is sent to the radio frequency chip through a bidirectional data interface of the baseband chip.
When the data receiving and transmitting mode switching signal is at a low level, the baseband chip and the radio frequency chip are taken as a whole to externally receive data, the radio frequency chip receives externally transmitted data and transmits the data to the baseband chip, and the baseband chip receives the data transmitted by the radio frequency chip.
At this time, the RFCLK is used as a sampling clock for receiving data from the baseband chip, and the second clock signal sent by the PAD corresponding to the second clock end of the radio frequency chip is received through the fifth PAD, so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time.
The application designs the wiring paths of the interface signals of the data receiving and transmitting mode switching end, the first clock end, the first enabling end and the second enabling end of the baseband chip, so that the baseband chip does not respond immediately after transmitting the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal, but firstly transmits the signals to the corresponding PAD, receives and responds to the signals returned by the PAD, and reduces the time difference of the signals reaching the internal logic of the baseband chip and the internal logic of the radio frequency chip, thereby realizing the synchronization of the baseband chip and the radio frequency chip.
Example 2
Referring to fig. 2, a radio frequency chip provided by the present application includes:
the data receiving and transmitting mode switching end is connected to the sixth PAD, and receives the data receiving and transmitting mode switching signal sent by the first PAD corresponding to the data receiving and transmitting mode switching end of the baseband chip through the sixth PAD, so that the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal at the same time.
The first clock end is connected to the seventh PAD, and when the data receiving and transmitting mode switching signal is at a high level, the first clock signal sent by the second PAD corresponding to the first clock end of the baseband chip is received through the seventh PAD, so that the baseband chip and the radio frequency chip respond to the first clock signal simultaneously.
The first enabling end is connected to the eighth PAD, and receives a first enabling signal sent by a third PAD corresponding to the first enabling end of the baseband chip through the eighth PAD, so that the baseband chip and the radio frequency chip respond to the first enabling signal at the same time.
The second enabling end is connected to the ninth PAD, and receives a second enabling signal sent by a fourth PAD corresponding to the second enabling end of the baseband chip through the ninth PAD, so that the baseband chip and the radio frequency chip respond to the second enabling signal at the same time.
The bidirectional data interface is used for receiving data sent by the baseband chip when the data receiving and transmitting mode switching signal is at a high level; when the data transmission/reception mode switching signal is at a low level, data is transmitted to the baseband chip.
Specifically, the bidirectional data interface in this embodiment includes 12 parallel data lines, and each data line corresponds to a different PAD, through which data is received or transmitted.
In other embodiments of the present application, the radio frequency chip further comprises:
and the tenth PAD transmits the second clock signal to the second clock end of the radio frequency chip and the second clock end of the baseband chip at the same time so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time.
As shown in fig. 2, an exemplary radio frequency chip schematic diagram provided by the present application is shown, wherein DFE is a digital front end, AFE is an analog front end, trx_m-2 is a DATA transceiver mode switching end of the radio frequency chip, BBCLK-2 is a first clock end of the radio frequency chip, ENABLE-2 is a first ENABLE end of the radio frequency chip, agc_enb-2 is a second ENABLE end of the radio frequency chip, DATA-2 is a bidirectional DATA interface of the radio frequency chip, and RFCLK-2 is a second clock end of the radio frequency chip.
The radio frequency chip and the baseband chip simultaneously respond to a data receiving and transmitting mode switching signal sent by the baseband chip through the first PAD, and when the signal is in a high level, the radio frequency chip is in a data sending mode outwards, and data sent by the baseband chip is needed to be received internally.
At this time, BBCLK-2 is used as a sampling clock for receiving data by the radio frequency chip, and the seventh PAD is used to receive the first clock signal sent by the second PAD corresponding to the first clock end of the baseband chip, so that the baseband chip and the radio frequency chip respond to the first clock signal at the same time.
Enabling-2 receives a first enabling signal sent by a third PAD corresponding to a first enabling end of the baseband chip through an eighth PAD, so that the baseband chip and the radio frequency chip respond to the first enabling signal at the same time.
The AGC_ENB-2 receives a second enabling signal sent by a fourth PAD corresponding to a second enabling end of the baseband chip through a ninth PAD, so that the baseband chip and the radio frequency chip respond to the second enabling signal at the same time.
When the data receiving and transmitting mode switching signal sent by the baseband chip is at a low level, the radio frequency chip is in a data receiving mode, and the received data needs to be sent to the baseband chip.
At this time, the second clock signal transmitted by RFCLK-2 is used as a transmission clock for transmitting data by the radio frequency chip, the radio frequency chip does not immediately respond to the second clock signal, but transmits the second clock signal to the tenth PAD, and then transmits the second clock signal to the baseband chip and the radio frequency chip through the tenth PAD, so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time.
The baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the second clock signal, the first enabling signal and the second enabling signal at the same time, and data are sent to the bidirectional data interface of the baseband chip through the bidirectional data interface of the radio frequency chip.
According to the application, the wiring path design of the interface signal is carried out on the second clock end of the radio frequency chip, so that the radio frequency chip does not respond immediately after sending the second clock signal, but sends the second clock signal to the corresponding PAD first, receives and responds to the second clock signal returned by the PAD, and the time difference of the second clock signal reaching the internal logic of the baseband chip and the internal logic of the radio frequency chip is reduced, thereby realizing the synchronization of the baseband chip and the radio frequency chip.
Example 3
Based on the baseband chip provided in the above embodiment 1 and the radio frequency chip provided in the embodiment 2, the present application connects the baseband chip and the radio frequency chip, and provides a synchronization method based on the connected baseband chip and radio frequency chip, as shown in fig. 3, which is a schematic diagram of connection between the baseband chip and the radio frequency chip provided in the embodiment of the present application:
the first to fifth PADs are arranged on the baseband chip, and the sixth to tenth PADs are arranged on the radio frequency chip.
Specifically, a first PAD corresponding to a data receiving and transmitting mode switching end of a baseband chip is connected with a sixth PAD corresponding to a data receiving and transmitting mode switching end of a radio frequency chip; connecting a second PAD corresponding to the first clock end of the baseband chip with a seventh PAD corresponding to the first clock end of the radio frequency chip; connecting a third PAD corresponding to the first enabling end of the baseband chip with an eighth PAD corresponding to the first enabling end of the radio frequency chip; connecting a fourth PAD corresponding to a second enabling end of the baseband chip with a ninth PAD corresponding to a second enabling end of the radio frequency chip; connecting a fifth PAD corresponding to the second clock end of the baseband chip with a tenth PAD corresponding to the second clock end of the radio frequency chip; twelve PADs corresponding to the bidirectional data interfaces of the baseband chip are respectively connected with twelve PADs corresponding to the bidirectional data interfaces of the radio frequency chip.
Based on the above connection manner, this embodiment provides a method for synchronizing a baseband chip and a radio frequency chip, as shown in fig. 4, which includes:
s10: the data receiving and transmitting mode switching end of the baseband chip sends a data receiving and transmitting mode switching signal to a first PAD, and the first PAD simultaneously sends the data receiving and transmitting mode switching signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip.
S20: if the data receiving and transmitting mode switching signal is in a high level, the first clock end of the baseband chip sends a first clock signal to the second PAD, and the second PAD simultaneously sends the first clock signal to the first clock end of the baseband chip and the first clock end of the radio frequency chip.
S30: the first enabling end of the baseband chip sends a first enabling signal to a third PAD, and the third PAD sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip at the same time.
S40: the second enabling end of the baseband chip sends a second enabling signal to a fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time.
S50: the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal simultaneously, and data are sent to the bidirectional data interface of the radio frequency chip through the bidirectional data interface of the baseband chip.
According to the base band chip and radio frequency chip synchronization method provided by the application, the wiring path design of the interface signals is carried out by changing the data receiving and transmitting mode switching end, the first clock end, the first enabling end and the second enabling end of the base band chip, so that the base band chip and the radio frequency chip can simultaneously respond to the data receiving and transmitting mode switching signals, data loss is avoided, and when the base band chip transmits data to the radio frequency chip, the base band chip and the radio frequency chip can simultaneously respond to the first clock signal, the first enabling signal and the second enabling signal, and the time difference that the clock signal and the control signal reach the internal logic of the base band chip and the internal logic of the radio frequency chip is reduced, so that the synchronization of the base band chip and the radio frequency chip is realized.
Specifically, in other embodiments, the method further comprises:
s60: if the data receiving and transmitting mode switching signal is at a low level, the second clock end of the radio frequency chip sends a second clock signal to a tenth PAD, and the tenth PAD sends the second clock signal to the second clock end of the baseband chip and the second clock end of the radio frequency chip at the same time.
S70: the first enabling end of the baseband chip sends a first enabling signal to a third PAD, and the third PAD sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip at the same time.
S80: the second enabling end of the baseband chip sends a second enabling signal to a fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time.
S90: the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the second clock signal, the first enabling signal and the second enabling signal at the same time, and data are sent to the bidirectional data interface of the baseband chip through the bidirectional data interface of the radio frequency chip.
Based on the design of the wiring path of the interface signal of the baseband chip, the application also designs the wiring path of the interface signal of the second clock end of the radio frequency chip, and when the radio frequency chip sends data to the baseband chip, the baseband chip and the radio frequency chip can simultaneously respond to the second clock signal, the first enabling signal and the second enabling signal, so that the synchronization of the baseband chip and the radio frequency chip is realized.
Specifically, when the first enabling signal is at a high level, the baseband chip and the radio frequency chip respond to the first enabling signal simultaneously and enter a working state; when the second enable signal is at a low level, the baseband chip and the radio frequency chip perform Automatic Gain Control (AGC) on the received data based on the second enable signal, and when the AGC is locked, the second enable signal becomes at a high level.
Specifically, the bidirectional data interfaces of the baseband chip and the radio frequency chip comprise 12 parallel data lines, each data line corresponds to different PADs, namely, the 12 parallel data lines of the baseband chip correspond to 12 PADs on the baseband chip, the 12 parallel data lines of the radio frequency chip correspond to 12 PADs on the radio frequency chip, and the PADs corresponding to the bidirectional data interfaces of the baseband chip are respectively connected with the PADs corresponding to the bidirectional data interfaces of the radio frequency chip so as to facilitate data transmission of the baseband chip and the radio frequency chip.
In the traditional connection method of the baseband chip and the radio frequency chip, the delay time from the baseband chip to the radio frequency chip of the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal is as follows:
，
wherein,,for line delay of the logic inside the baseband chip to reach PAD,delay for output of baseband chip PAD, < ->Delay for inputting of radio frequency chip PAD, +.>The line delay for the rf chip PAD to reach the internal logic.
The delay of the second clock signal sent by the radio frequency chip to reach the baseband chip is as follows:
，
wherein,,for line delay of the logic inside the rf chip to the PAD,delay for output of radio frequency chip PAD, < +.>Delay for input of baseband chip PAD, +.>The line delay for the baseband chip PAD to reach the internal logic.
Therefore, the delay path between the baseband chip and the radio frequency chip is longer, so that the baseband chip and the radio frequency chip cannot keep synchronous, and especially when the baseband chip sends a data receiving and transmitting mode switching signal, the delay between the baseband chip and the radio frequency chip can cause the data receiving and transmitting mode of the radio frequency chip to be switched slowly, for example, when the baseband chip is switched to a sending mode, the radio frequency chip should be synchronously switched to the sending mode, and the delay between the baseband chip and the radio frequency chip can cause the baseband chip and the radio frequency chip to be simultaneously in different modes, so that data is lost.
When the delay between the baseband chip and the radio frequency chip mainly comprises an on-chip delay and an on-chip epitaxy, specifically, for a data receiving and transmitting mode switching signal, the delay from a first PAD to the baseband chip is the on-chip delay, the delay from the first PAD to a sixth PAD is the on-chip delay, and the delay from the sixth PAD to the radio frequency chip is the on-chip delay; for the first clock signal, the delay of the first clock signal from the second PAD to the baseband chip is an on-chip delay, the delay of the first clock signal from the second PAD to the seventh PAD is an on-chip delay, and the delay of the first clock signal from the seventh PAD to the radio frequency chip is an on-chip delay; for the first enabling signal, the delay of the first enabling signal transmitted from the third PAD to the baseband chip is an on-chip delay, the delay of the first enabling signal transmitted from the third PAD to the eighth PAD is an on-chip delay, and the delay of the first enabling signal transmitted from the eighth PAD to the radio frequency chip is an on-chip delay; for the second enabling signal, the delay from the fourth PAD to the baseband chip is an on-chip delay, the delay from the fourth PAD to the ninth PAD is an on-chip delay, and the delay from the ninth PAD to the radio frequency chip is an on-chip delay; for the second clock signal, the delay of the second clock signal from the tenth PAD to the radio frequency chip is an on-chip delay, the delay of the second clock signal from the tenth PAD to the fifth PAD is an on-chip delay, and the delay of the second clock signal from the fifth PAD to the baseband chip is an on-chip delay.
The application uses clock tree synthesis and back-end layout wiring method to control in-chip delay, and controls off-chip delay by wire sealing mode, so that the time for transmitting signals to baseband chip and radio frequency chip is equal.
Specifically, in the embodiment of the present application, the wiring paths of interface signals of a baseband chip and a radio frequency chip are designed, as shown in fig. 3, the delay of sending a data transceiving mode switching signal, a first clock signal, a first enabling signal and a second enabling signal from a first PAD, a second PAD, a third PAD and a fourth PAD of the baseband chip to the radio frequency chip is respectively:
，
wherein,,the input delay of the radio frequency chip PAD, namely when the chip is epitaxial,the line delay for the radio frequency chip PAD to reach the internal logic, namely the on-chip delay;
the delay of the second clock signal sent from the tenth PAD of the radio frequency chip to the baseband chip is as follows:
，
wherein,,the input delay for the baseband chip PAD, i.e. when the chip is epitaxial,the line delay for the baseband chip PAD to reach the internal logic, i.e. the on-chip delay.
The application designs the wiring paths of the interface signals of the baseband chip and the radio frequency chip, so that the on-chip delay of the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal respectively returns to the baseband chip from the first PAD, the second PAD, the third PAD and the fourth PAD as far as possible to be equal toSo that the on-chip delay of the second clock signal from the tenth PAD back to the radio frequency chip is as equal as possible to +.>The method comprises the steps of carrying out a first treatment on the surface of the Namely, the time for returning the data receiving and transmitting mode switching signal from the first PAD to the baseband chip is equal to the time for reaching the radio frequency chip from the first PAD, the time for returning the first clock signal from the second PAD to the baseband chip is equal to the time for reaching the radio frequency chip from the second PAD, the time for returning the first enabling signal from the third PAD to the baseband chip is equal to the time for reaching the radio frequency chip from the third PAD, the time for returning the second enabling signal from the fourth PAD to the baseband chip is equal to the time for reaching the radio frequency chip from the fourth PAD, and the time for returning the tenth PAD to the radio frequency chip is equal to the time for reaching the baseband chip from the tenth PAD.
The application is further explained by taking the baseband chip to receive data and the radio frequency chip to send data as an example:
step 1: when the baseband chip receives data, a low-level data receiving and transmitting mode signal is sent to the first PAD, at the moment, the baseband chip does not immediately respond to the data receiving and transmitting mode signal, and the first PAD simultaneously sends the data receiving and transmitting mode switching signal to the baseband chip and the radio frequency chip;
step 2: the baseband chip sends a first clock signal to the second PAD, and the baseband chip does not immediately respond to the first clock signal at the moment, and the second PAD simultaneously sends the first clock signal to the baseband chip and the radio frequency chip;
step 3: the baseband chip sends a high-level first enabling signal to a third PAD, at the moment, the baseband chip does not immediately respond to the first enabling signal, the third PAD simultaneously sends the first enabling signal to the baseband chip and the radio frequency chip, and because the delay from the third PAD to the baseband chip is equal to the delay from the third PAD to the radio frequency chip, the baseband chip and the radio frequency chip simultaneously receive and respond to the first enabling signal and enter a working state at the same time;
step 4: the baseband chip sends a low-level second enabling signal to a fourth PAD, at the moment, the baseband chip does not immediately respond to the second enabling signal, the fourth PAD simultaneously sends the second enabling signal to the baseband chip and the radio frequency chip, and because the delay from the fourth PAD to the baseband chip is equal to the delay from the fourth PAD to the radio frequency chip, the baseband chip and the radio frequency chip simultaneously receive and respond to the second enabling signal and perform automatic gain control;
step 5: based on the signals, the radio frequency chip sends data to the bidirectional data interface of the baseband chip through the bidirectional data interface of the radio frequency chip.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present application will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (9)
1. A baseband chip, comprising:
the data receiving and transmitting mode switching end is connected to the first PAD, and transmits a data receiving and transmitting mode switching signal to the first PAD, and the first PAD simultaneously transmits the data receiving and transmitting mode switching signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip, so that the baseband chip and the radio frequency chip simultaneously respond to the data receiving and transmitting mode switching signal;
the first clock end is connected to the second PAD, when the data receiving and transmitting mode switching signal is at a high level, a first clock signal is sent to the second PAD, and the second PAD simultaneously sends the first clock signal to the first clock end of the baseband chip and the first clock end of the radio frequency chip so that the baseband chip and the radio frequency chip simultaneously respond to the first clock signal;
the first enabling end is connected to a third PAD, a first enabling signal is sent to the third PAD, and the third PAD simultaneously sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip so that the baseband chip and the radio frequency chip simultaneously respond to the first enabling signal;
the second enabling end is connected to a fourth PAD, a second enabling signal is sent to the fourth PAD, and the fourth PAD simultaneously sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip so that the baseband chip and the radio frequency chip simultaneously respond to the second enabling signal;
the bidirectional data interface is used for sending data to the radio frequency chip when the data receiving and transmitting mode switching signal is at a high level; and when the data receiving and transmitting mode switching signal is at a low level, receiving the data sent by the radio frequency chip.
2. The baseband chip of claim 1, further comprising:
and the second clock end is connected to a fifth PAD, and when the data receiving and transmitting mode switching signal is at a low level, the second clock signal sent by the PAD corresponding to the second clock end of the radio frequency chip is received through the fifth PAD, so that the baseband chip and the radio frequency chip respond to the second clock signal at the same time.
3. A radio frequency chip, comprising:
the data receiving and transmitting mode switching end is connected to the sixth PAD, and receives a data receiving and transmitting mode switching signal sent by the first PAD corresponding to the data receiving and transmitting mode switching end of the baseband chip through the sixth PAD, so that the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal at the same time;
the first clock end is connected to a seventh PAD, and when the data receiving and transmitting mode switching signal is at a high level, a first clock signal sent by a second PAD corresponding to the first clock end of the baseband chip is received through the seventh PAD, so that the baseband chip and the radio frequency chip respond to the first clock signal at the same time;
the first enabling end is connected to an eighth PAD, and receives a first enabling signal sent by a third PAD corresponding to the first enabling end of the baseband chip through the eighth PAD, so that the baseband chip and the radio frequency chip respond to the first enabling signal at the same time;
the second enabling end is connected to a ninth PAD, and a second enabling signal sent by a fourth PAD corresponding to the second enabling end of the baseband chip is received through the ninth PAD, so that the baseband chip and the radio frequency chip respond to the second enabling signal at the same time;
the bidirectional data interface is used for receiving data sent by the baseband chip when the data receiving and transmitting mode switching signal is at a high level; and when the data receiving and transmitting mode switching signal is in a low level, transmitting data to the baseband chip.
4. The radio frequency chip of claim 3, further comprising:
and the second clock end is connected to a tenth PAD, when the data receiving and transmitting mode switching signal is at a low level, a second clock signal is sent to the tenth PAD, and the tenth PAD simultaneously sends the second clock signal to the second clock end of the radio frequency chip and the second clock end of the baseband chip so that the baseband chip and the radio frequency chip simultaneously respond to the second clock signal.
5. A method for synchronizing a baseband chip and a radio frequency chip, comprising:
the data receiving and transmitting mode switching end of the baseband chip sends a data receiving and transmitting mode switching signal to a first PAD, and the first PAD simultaneously sends the data receiving and transmitting mode switching signal to the data receiving and transmitting mode switching end of the baseband chip and the data receiving and transmitting mode switching end of the radio frequency chip;
if the data receiving and transmitting mode switching signal is in a high level, a first clock end of the baseband chip sends a first clock signal to a second PAD, and the second PAD simultaneously sends the first clock signal to the first clock end of the baseband chip and the first clock end of the radio frequency chip;
the first enabling end of the baseband chip sends a first enabling signal to a third PAD, and the third PAD sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip at the same time;
the second enabling end of the baseband chip sends a second enabling signal to a fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time;
the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the first clock signal, the first enabling signal and the second enabling signal at the same time, and data are sent to a bidirectional data interface of the radio frequency chip through the bidirectional data interface of the baseband chip.
6. The method according to claim 5, wherein if the data transmit/receive mode switching signal is at a low level, the second clock terminal of the radio frequency chip transmits a second clock signal to a tenth PAD, and the tenth PAD transmits the second clock signal to the second clock terminal of the baseband chip and the second clock terminal of the radio frequency chip at the same time;
the first enabling end of the baseband chip sends a first enabling signal to a third PAD, and the third PAD sends the first enabling signal to the first enabling end of the baseband chip and the first enabling end of the radio frequency chip at the same time;
the second enabling end of the baseband chip sends a second enabling signal to a fourth PAD, and the fourth PAD sends the second enabling signal to the second enabling end of the baseband chip and the second enabling end of the radio frequency chip at the same time;
the baseband chip and the radio frequency chip respond to the data receiving and transmitting mode switching signal, the second clock signal, the first enabling signal and the second enabling signal at the same time, and data are sent to the bidirectional data interface of the baseband chip through the bidirectional data interface of the radio frequency chip.
7. The method according to claim 6, wherein when the first enable signal is at a high level, the baseband chip and the radio frequency chip enter an operation state at the same time based on the first enable signal.
8. The method according to claim 6, wherein when the second enable signal is at a low level, the baseband chip and the radio frequency chip perform automatic gain control on received data based on the second enable signal, and when the automatic gain control is locked, the second enable signal becomes at a high level.
9. The method of synchronizing a baseband chip and a radio frequency chip according to claim 6, wherein the bidirectional data interfaces of the baseband chip and the radio frequency chip each comprise 12 parallel data lines.
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| CN201114507Y (en) * | 2007-09-20 | 2008-09-10 | 厦门华侨电子股份有限公司 | A wireless digital high-definition interface device without compression |
| CN101527959A (en) * | 2008-03-03 | 2009-09-09 | 中兴通讯股份有限公司 | Clock synchronization system |
| CN102209402A (en) * | 2010-03-31 | 2011-10-05 | 重庆重邮信科通信技术有限公司 | Interface of radio frequency chip and base band chip of multi-mode terminal |
| CN105510937A (en) * | 2015-11-27 | 2016-04-20 | 武汉梦芯科技有限公司 | Multi-mode multi-frequency baseband chip pin control circuit and control method |
| CN212305330U (en) * | 2020-06-03 | 2021-01-05 | 泰斗微电子科技有限公司 | Signal processing device and communication terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201114507Y (en) * | 2007-09-20 | 2008-09-10 | 厦门华侨电子股份有限公司 | A wireless digital high-definition interface device without compression |
| CN101527959A (en) * | 2008-03-03 | 2009-09-09 | 中兴通讯股份有限公司 | Clock synchronization system |
| CN102209402A (en) * | 2010-03-31 | 2011-10-05 | 重庆重邮信科通信技术有限公司 | Interface of radio frequency chip and base band chip of multi-mode terminal |
| CN105510937A (en) * | 2015-11-27 | 2016-04-20 | 武汉梦芯科技有限公司 | Multi-mode multi-frequency baseband chip pin control circuit and control method |
| CN212305330U (en) * | 2020-06-03 | 2021-01-05 | 泰斗微电子科技有限公司 | Signal processing device and communication terminal |
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