CN116800055A - Converter circuit and corresponding method of testing a converter circuit - Google Patents
Converter circuit and corresponding method of testing a converter circuit Download PDFInfo
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- CN116800055A CN116800055A CN202310270633.3A CN202310270633A CN116800055A CN 116800055 A CN116800055 A CN 116800055A CN 202310270633 A CN202310270633 A CN 202310270633A CN 116800055 A CN116800055 A CN 116800055A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Abstract
The present disclosure relates to a converter circuit and a corresponding method of testing a converter circuit. The switching DC-DC converter circuit includes a switching stage having an input node receiving an input voltage and an output node generating an output voltage. The converter comprises feedback loop circuit means coupled to the output nodes of the switching stages for generating control signals of the converter circuit at the respective output nodes dependent on the difference between the output voltage and the reference voltage. The converter comprises a test loop circuit arrangement arranged between an output node of the feedback loop circuit arrangement and an output node of the switching stage. When enabled, the test loop provides current to the output node of the switching stage or sinks current from the output node of the switching stage depending on the value of the control signal of the converter circuit. The feedback loop circuit arrangement is calibrated during a test phase of the switching DC-DC converter circuit.
Description
Cross Reference to Related Applications
The present application claims priority from italian patent application No.102022000005477 filed on 3/21 of 2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.
Technical Field
The present disclosure relates to DC-DC converter circuits and methods of testing DC-DC converter circuits (e.g., integrated circuit testing, IC testing) to fine tune and/or calibrate them. For example, one or more embodiments may be applied in a Power Management Integrated Circuit (PMIC) for an Active Matrix Organic Light Emitting Diode (AMOLED) display driver.
Background
DC-DC converters are used in a variety of applications to generate appropriate supply voltages for use by complex systems to operate and provide desired performance. In many of these applications, it is desirable for the DC-DC converter to provide an accurate output voltage to meet the specifications of the application. Thus, the expected operating point (e.g., the expected output voltage) of the DC-DC converter will be considered during the converter design phase, especially with respect to typical statistics and/or systematic errors of the integrated electronic circuit. Dedicated trimming circuits may be implemented in the DC-DC converter to be able to compensate for such errors during the IC testing phase performed during the IC manufacturing process (e.g. before dicing and packaging, or even on the final sample that has been diced and packaged).
Thus, trimming circuits implemented into the integrated circuit are set during the IC test phase to meet the expected performance of the chip. However, in many automatic test setups (e.g., automatic Test Equipment (ATE)), testing a DC-DC converter operating in a closed loop may not be possible or convenient, for example, due to non-optimal connections of the ATE, which may create instability problems (e.g., due to board parasitics and other non-idealities), and/or due to ATE measurements which may suffer from noise, and/or due to excessive time for performing accurate ATE measurements on the switching DC-DC converter.
Known methods conventionally used to measure the accuracy of the DC-DC converter during the test phase and thus to fine tune the converter itself rely on implementing a closed loop architecture on an automatic test board and operating the converter in a normal regulation mode during testing (i.e. as it would be operating in the end application). This approach increases the complexity and cost of the test board to be used and may still fail in operating the DC-DC converter under stable conditions. Furthermore, even if a stable operation of the converter is to be achieved, the output voltage of the converter may exhibit ripple that is to be filtered in order to measure an accurate value of the regulated output voltage. Ripple filtering can typically be achieved by applying long time averaging, which results in lengthy test times, which will increase test costs, especially in the case of DC-DC converters with multiple outputs to be tested.
Another known method may be used to measure the accuracy of the DC-DC converter and thus adjust the converter itself, but this is limited to the case where the converter may operate in pulse skipping conditions. The method relies on operating the converter under open loop conditions (e.g., without an inductor) during testing, forcing the output voltage to a value close to the desired regulation value, and analyzing the behavior of the converter switching node (e.g., sensing the voltage at the switching node). If the output voltage is forced to a value below the desired set point (expected value), the switching node exhibits switching activity because the DC-DC converter attempts to increase the output voltage but fails due to the absence of an external inductor. If the output voltage is forced to a value higher than the desired set point, the switching node does not exhibit switching activity because the DC-DC converter enters a pulse skipping mode of operation. Thus, by imposing a ramp voltage signal at the output node of the converter, the voltage value at which the converter stops switching can be detected, which can be estimated as an accurate converter output value. However, this test method is not applicable to all DC-DC converters (e.g., a DC-DC converter operating in a forced Continuous Conduction Mode (CCM) would not have this behavior). In addition, the test method involves applying a slow ramp to improve the accuracy of the measurement and thus also results in lengthy test times, which becomes an increased test cost, especially in the case of a DC-DC converter with multiple outputs to be tested.
Accordingly, there is a need in the art to provide improved DC-DC converters and related testing methods that make the testing phase easier, faster and/or more convenient.
There is also a need in the art for a DC-DC converter and related testing methods that help provide such improvements.
Disclosure of Invention
One or more embodiments relate to a DC-DC converter circuit.
One or more embodiments relate to a corresponding method of testing a DC-DC converter circuit.
In one or more embodiments, a switching DC-DC converter circuit includes a switching stage having an input node configured to receive an input voltage and an output node configured to generate an output voltage. The converter comprises feedback loop circuit means coupled to the output nodes of the switching stages and configured to generate control signals of the converter circuit at the respective output nodes as a function of the difference between the output voltage and the reference voltage. The converter comprises a test loop circuit arrangement arranged between an output node of the feedback loop circuit arrangement and an output node of the switching stage. The test loop circuit arrangement is configured to provide current to or sink current from the output node of the switching stage when enabled, depending on the value of the control signal of the converter circuit. The feedback loop circuit arrangement is calibratable (e.g., trimmable) during a test phase of the switching DC-DC converter circuit.
Accordingly, one or more embodiments facilitate testing and calibrating DC-DC converter circuits.
In one or more embodiments, the test loop circuit arrangement includes one or more enable switches configured to selectively couple the test loop circuit arrangement to an output node of the feedback loop circuit arrangement and/or an output node of the switching stage. The test loop circuit device is enabled by turning on the one or more enable switches and disabled by turning off the one or more enable switches.
In one or more embodiments, the test loop circuit arrangement is permanently coupled between the output node of the feedback loop circuit arrangement and the output node of the switching stage. The test loop circuit means is enabled and disabled in accordance with the test mode signal.
In one or more embodiments, the test loop circuit arrangement includes a first transistor having a control terminal coupled to an output node of the feedback loop circuit arrangement to receive the control signal such that a current flowing through the first transistor is dependent on the control signal. The test loop circuit arrangement comprises a current-to-voltage conversion circuit configured to generate a transistor control voltage for controlling the output transistor, the transistor control voltage being dependent on a current flowing through the first transistor. The test loop circuit arrangement includes an output transistor coupled to an output node of the switching stage. The output transistor is configured to receive the transistor control voltage at a respective control terminal and to supply current to or sink current from an output node of the switching stage depending on a value of the transistor control voltage.
In one or more embodiments, the first transistor comprises a p-channel MOS transistor having a source terminal coupled to the first supply voltage rail and a gate terminal coupled to the output node of the feedback loop circuit means to receive the control signal. The current-to-voltage conversion circuit includes a current mirror circuit having a mirror input node coupled to a drain terminal of the first transistor and a mirror output node coupled to a first terminal of a resistor having a second terminal coupled to a second supply voltage rail. The output transistor comprises a p-channel MOS transistor having a source terminal coupled to the second supply voltage rail, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to an output node of the switching stage. The output transistor is configured to provide current to an output node of the switching stage.
In one or more embodiments, the first supply voltage rail is an internal supply voltage rail of the converter circuit, and the second supply voltage rail is configured to receive an input voltage of the converter circuit.
In one or more embodiments, the first transistor comprises an n-channel MOS transistor having a source terminal coupled to ground and a gate terminal coupled to the output node of the feedback loop circuit device to receive the control signal. The current-to-voltage conversion circuit includes a resistor having a first terminal coupled to the drain terminal of the first transistor and a second terminal coupled to the supply voltage rail. The output transistor includes an n-channel MOS transistor having a source terminal coupled to ground, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to an output node of the switching stage. The output transistor is configured to sink current from an output node of the switching stage.
In one or more embodiments, the feedback loop circuit arrangement includes: a feedback voltage divider circuit coupled to an output node of the switching stage and configured to generate a feedback voltage dependent on a voltage division (partitioning) of the output voltage; and an error amplifier configured to amplify a difference between the feedback voltage and the reference voltage to generate a control signal. The offset voltage of the error amplifier and/or the reference voltage of the error amplifier is calibratable (e.g., trimmable) during the test phase of the switching DC-DC converter circuit.
In one or more embodiments, the feedback voltage divider circuit includes: a digital-to-analog converter circuit configured to convert the digital signal into an analog voltage signal; a buffer circuit configured to receive the analog voltage signal output from the digital-to-analog converter circuit and generate a buffered analog voltage signal; and a voltage step circuit disposed between the output node of the buffer circuit and the output node of the switching stage and configured to generate a feedback voltage at an intermediate node thereof. The offset voltage of the snubber circuit is calibratable (e.g., trimmable) during the test phase of the switching DC-DC converter circuit.
In one or more embodiments, the feedback voltage divider circuit includes a voltage ladder circuit disposed between an output node of the switching stage and a ground node and configured to generate a feedback voltage at an intermediate node thereof.
In one or more embodiments, the switching DC-DC converter circuit further comprises a voltage ramp generating circuit arrangement configured to generate a ramp signal, and a comparator circuit configured to compare the ramp signal with the control signal to generate a pulse width modulated signal for controlling switching activity of the switching stage. Optionally, the voltage ramp generating circuit device includes: a ramp generator circuit configured to generate a basic ramp signal; a current sensing circuit configured to sense a current flowing through one or more switches of the switching stage and to generate a signal indicative of the sensed current; and an adder circuit configured to add the base ramp signal and a signal indicative of the sensed current to generate a ramp signal.
In one or more embodiments, a method of testing a switching DC-DC converter circuit according to one or more embodiments includes the steps of:
-setting the switching DC-DC converter circuit into a test operation mode by preventing switching activity of the switching stage and enabling the test loop circuit arrangement;
-providing current to or sinking current from an output node of the switching stage via the test loop circuit arrangement in accordance with a value of a control signal of the converter circuit;
-sink current from the output node of the switching stage or provide current to the output node of the switching stage via an external current generator means;
-sensing a value of an output voltage generated at an output node of the conversion stage; and
-calibrating one or more electronic components of the feedback loop circuit arrangement until a desired value of an output voltage is generated at an output node of the switching stage.
In one or more embodiments, the method includes calibrating an offset voltage of the error amplifier and/or calibrating a reference voltage of the error amplifier until a desired value of the output voltage is produced at an output node of the switching stage.
In one or more embodiments, the method includes calibrating an offset voltage of the error amplifier and/or calibrating an offset voltage of the buffer circuit until a desired value of the output voltage is generated at an output node of the switching stage.
Drawings
One or more embodiments will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a circuit block diagram example of a conventional DC-DC buck-boost converter apparatus;
FIG. 2 is an exemplary circuit block diagram of a DC-DC buck-boost converter apparatus including an auxiliary loop for testing in accordance with one or more embodiments of the present disclosure;
FIG. 3 is a circuit block diagram of exemplary implementation details of a DC-DC buck-boost converter apparatus including an auxiliary loop for testing in accordance with one or more embodiments of the present disclosure; and
fig. 4 is a circuit block diagram of exemplary implementation details of a DC-DC boost converter apparatus including an auxiliary loop for testing in accordance with one or more embodiments of the present disclosure.
Detailed Description
In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.
Reference in the framework of this specification to "one embodiment" or "an embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present specification do not necessarily refer to the same embodiment. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Headings/references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.
In the drawings attached hereto, identical parts or elements are indicated with identical reference numerals/numerals unless the context indicates otherwise, and the corresponding description will not be repeated for the sake of brevity.
By way of introduction to the detailed description of the exemplary embodiments, referring first to fig. 1, fig. 1 is an exemplary circuit block diagram of a DC-DC converter device 1, in particular a buck-boost DC-DC converter comprising a current-controlled feedback loop. The DC-DC converter 1 as illustrated in fig. 1 comprises a switching stage HB (e.g. a half-bridge circuit) having a circuit configured to receive an input voltage V IN And is configured to generate an output voltage V OUT Is provided. For example, the switching stage HB may include a first high-side switch HS1 coupled between the input node and the switching node LX, and a first low-side switch LS1 coupled between the switching node LX and the output node. The switching stage HB may further comprise a second high-side switch HS2 coupled between the input node and the switching node LX, and a second low-side switch LS2 coupled between the switching node LX and the output node, for example in case the DC-DC converter 1 involves dynamic control of the switching stage HB to accommodate different operating conditions. As shown in fig. 1, the switches HS1, HS2, LS1 and LS2 may comprise (power) transistors, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), for example n-channel MOS transistors. For example, when the DC-DC converter chip 1 is mounted on a Printed Circuit Board (PCB) in an end application, an inductor L (e.g., an external inductor) may be coupled between the switching node LX and the ground node GND.
As illustrated in fig. 1, the DC-DC converter 1 may further include a ramp generator circuit 12, a current sensing circuit 14 coupled to one or more high-side switches of the switching stage HB (e.g., configured to sense current flowing through the high-side switches HS1 and/or HS 2), and a logic circuit configured to add output signals from the ramp generator circuit 12 and the current sensing circuit 14 to generate a ramp signal V SUM Is provided for the adder node 15.
As shown in fig. 1, the DC-DC converter 1 may further comprise a feedback voltage divider circuit 16 and an error amplifier 18, the feedback voltage divider circuit 16 being coupled to the output node of the switching stage HB and configured to generate an indication output voltage V OUT (e.g. with output voltage V) OUT Proportional) feedback voltage V FB Error amplifier 18 has a circuit configured to receive a reference voltage V REF A first input configured to receive a feedback voltage V from circuit 16 FB To generate a control voltage V of the DC-DC converter 1 C Is provided for the second input of (a).
As shown in fig. 1, the DC-DC converter 1 may further include a comparator circuit 20 (e.g., a voltage comparator) configured to compare the ramp signal V SUM And control signal V C A comparison is made to generate a pulse width modulated signal P for controlling the switching activity of the switching stage HB. The DC-DC converter 1 may further include: a digital circuit 22 configured to receive the PWM signal P from the comparator 20 and generate a high-side activation signal and a low-side activation signal for the switching stage HB; and a driver circuit 10 coupled to the digital circuit 22 and the switching stage HB and configured to generate drive signals VHS1, VHS2, VLS1, VLS2 for driving commutation of the switches HS1, HS2, LS1, LS2 in accordance with the received high-side and low-side activation signals.
Fig. 1 is thus an example of a peak current feedback loop of a DC-DC converter 1, which DC-DC converter 1 is adapted to be tested according to one or more of the known methods discussed previously.
To alleviate or overcome one or more of the disadvantages of the known test architectures previously discussed, one or more converter embodiments may rely on providing an auxiliary loop (loop) (e.g., a linear loop) in the converter architecture for testing purposes. Such an auxiliary loop may help to measure the accuracy of the DC-DC converter and/or apply a trimming process in a simpler, easier and/or faster way during the testing phase. In particular, providing an auxiliary circuit may allow to perform a test procedure that is not dependent on the results of difficult and/or unreliable measurements made under switching conditions.
For example, fig. 2 is an exemplary circuit block diagram of a DC-DC converter device 2, in particular a buck-boost DC-DC converter, comprising a main feedback loop as discussed with reference to fig. 1 and an auxiliary loop 24 for trimming during a test phase of the converter integrated circuit. For example, the auxiliary loop 24 may be provided between the output of the error amplifier 18 and the output node of the switching stage HB. During normal operation of the DC-DC converter 2 (e.g. when the converter 2 is implemented in an end application), the auxiliary loop 24 remains inactive (e.g. disconnected) so that it does not affect the normal operation of the converter 2 and does not increase power consumption. For example, auxiliary loop 24 may be disconnected from the output of error amplifier 18 and/or from the output node of switching stage HB via one or more electronic switches (not visible in fig. 2,3, and 4, but whose design and implementation may be provided by those skilled in the art); additionally or alternatively, the auxiliary loop 24 may remain connected to the error amplifier 18 and/or the switching stage HB, but may be deactivated or turned off. Instead, during the test phase, the auxiliary loop 24 is connected as shown in fig. 2, and the auxiliary loop 24 is enabled to properly address the linear loop test method during which the switching activity of the main feedback loop of the DC-DC converter 2 is kept suspended (e.g., suspended, blocked, disabled, blocked). For example, the converter 2 may be kept on hold by disabling the converter clock to stop switching activity, and/or by disabling one or more control circuits of the DC-DC converter, such as a comparator (e.g., comparator 20) or a digital core (e.g., digital circuit 22).
As an example, fig. 2 also shows a possible implementation of the feedback voltage divider circuit 16. As illustrated in fig. 2, circuit 16 may include a digital-to-analog converter circuit 161 (e.g., a 7-bit DAC converter) configured to receive a reference voltage V REF_DAC And a digital signal SET (e.g., 7-bit signal), and is equal to V REF_DAC Generates an analog voltage V corresponding to the value of the digital signal SET (e.g., proportional to the signal SET) over the full range of outputs of (a) DAC . The circuit 16 may further include a buffer circuit 162 coupled to the output of the DAC circuit 161 and configured to receive the analog signal V therefrom DAC To generate a buffered analog voltage V TOP . Electric powerThe voltage step has a voltage step configured to receive an analog voltage V TOP And is configured to receive the converter output voltage V OUT To generate a feedback voltage V at the intermediate node of the ladder FB Is provided. For example, the voltage step may be a resistive step comprising a first resistor coupled between the output of the buffer 162 and the feedback input of the error amplifier 18, and a second resistor coupled between the feedback input of the error amplifier 18 and the output of the switching stage HB of the converter 2.
As an example, fig. 2 also shows a pulse skipping circuit that can be implemented in the DC-DC converter 2. For example, the pulse skipping circuit may include a skipping comparator 26 (e.g., a comparator with hysteresis) configured to control the voltage V C With reference voltage V REF_SKIP A comparison is made to generate a skip signal S which is fed to the digital circuit 22.
Fig. 3 is an exemplary circuit block diagram of certain components of buck-boost DC-DC converter 2 shown in fig. 2 during a testing phase. Specifically, fig. 2 is an example of a possible implementation of the auxiliary loop circuit arrangement 24. The auxiliary loop circuit arrangement 24 may include a circuit arranged to provide (e.g., internally) a supply voltage V DD A first current line between (e.g., internal) supply voltage rail and ground GND. The first current line may include a p-channel MOS transistor Q1 and an n-channel MOS transistor Q2 coupled in series. Transistor Q1 has a voltage supply rail V coupled thereto DD Coupled (e.g., via a closed switch not visible in the figures attached hereto) to the output of error amplifier 18 to receive control voltage V C And a drain terminal coupled to the drain terminal of transistor Q2. Transistor Q2 has a source terminal coupled to ground GND and a gate terminal coupled to its drain terminal (i.e., it is diode connected). The auxiliary loop circuit device 24 may include a circuit device arranged to provide a supply voltage V INA A second current line between the supply voltage rail of (c) and ground GND. In one or more embodiments, the supply voltage V INA Can be connected with the input voltage V of the converter IN The same applies. Alternatively, the supply voltage V INA Can be connected with the internal power supply voltage V of the converter DD Identical to. The second current flow line may include a resistor R1 and an n-channel MOS transistor Q3 coupled in series. Resistor R1 has a voltage supply rail V coupled to INA And a second terminal coupled to the drain terminal of transistor Q3. Transistor Q3 has a source terminal coupled to ground GND and a gate terminal coupled to the gate terminal of transistor Q2 such that transistors Q2 and Q3 implement a current mirror in which the current flowing through transistor Q2 is mirrored through transistor Q3. The auxiliary loop circuit device 24 may include a p-channel MOS transistor Q4 disposed on a supply voltage rail V INA And generating a voltage V OUT Between the output nodes of the switching stage HB. In particular, transistor Q4 may have a voltage supply rail V coupled thereto INA A drain terminal coupled to the output node of the switching stage HB, and a gate terminal coupled to the node intermediate resistor R1 and the transistor Q3.
As shown in fig. 3, during a test phase of the converter 2, an external current source 30 (or equivalent external voltage source with serially coupled resistors) is connected to the output node of the DC-DC converter 2 to sink the current I therefrom, for example using external hardware available in an automatic test equipment LOAD . External capacitor C OUT Or between the output node of the converter 2 and ground GND. Thus, during testing, current I is drawn from the output node of converter 2 LOAD 。
It should also be noted that in one or more embodiments as shown in FIG. 3, the reference input of error amplifier 18 may be coupled to ground GND (e.g., reference voltage V REF May be a ground voltage, for example 0V).
Essentially, during the testing phase of the converter 2, the auxiliary loop circuit device 24 is connected between the output node of the error amplifier 18 and the output node of the switching stage HB (e.g., via one or more electronic switches not visible in the accompanying drawings herein), and is capable of operating as discussed below. In the test mode is enabled (e.g., as a function of the value of the test mode signal) and the external current I LOAD Forced by the ATE, a loop is provided that includes a circuit with corresponding reference voltage generation circuitry (i.e., DAC161 and buffer 162)A feedback voltage divider circuit 16, an error amplifier 18 and an auxiliary loop 24. The auxiliary loop 24 receives the control voltage V generated by the error amplifier 18 C As its input signal. The conductivity of the transistor Q1 (e.g., its on-off state) is thus dependent on the control voltage V C To modulate. Further, the current flowing through transistors Q1 and Q2 depends on voltage V C To modulate. Since the current is mirrored and forced to flow through transistor Q3 and resistor R1, the gate voltage of transistor Q4 is also dependent on voltage V C To modulate. Further, the current flowing through the transistor Q4 and injected into the output node of the switching stage HB is also dependent on the voltage V C Modulated. Thus, the loop will output the voltage V OUT Regulated to a selected value and in a steady state, an external current I LOAD Will flow through transistor Q4. Under this regulation condition, the circuit blocks involved in the loop (i.e., the feedback voltage divider circuit 16 and the error amplifier 18) are the same blocks that also operate during normal operation of the DC-DC converter 2. Thus, the contribution to the inaccuracy of the converter 2 caused by the circuits 16 and 18 is taken into account in the test phase, while the additional inaccuracy generated by the auxiliary loop 24 can be ignored, since the circuit block 24 is arranged downstream of the error amplifier 18, the error amplifier 18 typically introducing a high gain (for example 60dB to greater than 100 dB), so that the loop 24 contributes to the output voltage V OUT The contribution of the value of (c) is substantially negligible. During testing, the external capacitor C may be selected (e.g., adjusted) OUT Is connected with the external current I LOAD To ensure the stability of the circuit.
In one or more embodiments, the trimming process performed during testing of the DC-DC converter 2 may include enabling the auxiliary loop 24 as previously discussed (e.g., connecting the loop circuit arrangement 24 to the error amplifier 18 by closing the corresponding switches not visible in fig. 2,3, and 4, while the transistor Q4 may be permanently connected to the output node of the switching stage HB), then setting (e.g., adjusting) the available trim points in the main control loop of the converter 2 to output the voltage V OUT Is adjusted to a desired value. For example, error amplifier 18 may be fine tuned by calibrating its offset in an appropriate manner, and/or bufferedThe circuit 162 may be fine tuned by calibrating its offset in an appropriate manner. Thus, the trimming process disclosed herein considers all circuit blocks (16 and 18) that affect the accuracy of the converter 2 during normal operation (i.e., under application conditions), and thus the trimmed output value V OUT As close as possible to the output value that occurs in normal operation of the converter 2. In addition, in case any shift is required, the output voltage V can also be adjusted with slightly different target values OUT So as to arrange the normal operation of the converter 2 including the optional shift.
Fig. 4 is an exemplary circuit block diagram of certain components of boost DC-DC converter 4. In particular, fig. 4 is an example of a possible implementation of the auxiliary loop circuit arrangement 24', which auxiliary loop circuit arrangement 24' may be arranged between the output node of the error amplifier 18 and the output node of the switching stage HB of the boost DC-DC converter. For simplicity, certain components of boost converter 4 (e.g., the specific arrangement of the high-side switches, low-side switches, and external inductors in the switching stage) are not shown in fig. 4. The auxiliary loop circuit arrangement 24' may include a circuit arranged to provide (e.g., internally) a supply voltage V DD A (e.g., internal) supply voltage rail and ground GND. The current flow line may include a resistor R2 and an n-channel MOS transistor Q5 coupled in series. Resistor R2 has a voltage supply rail V coupled to DD And a second terminal coupled to the drain terminal of transistor Q5. Transistor Q5 has a source terminal coupled to ground GND and an output coupled to error amplifier 18 (e.g., via a closed switch not visible in the figures appended hereto) to receive control voltage V C Is provided. The auxiliary loop circuit arrangement 24' may include a circuit arrangement arranged to generate a voltage V OUT An n-channel MOS transistor Q6 between the output node of the switching stage HB and ground GND. In particular, transistor Q6 may have a source terminal coupled to ground GND, a drain terminal coupled to the output node of switching stage HB, and a gate terminal coupled to node intermediate resistor R2 and transistor Q5.
As shown in fig. 4, during the test phase of the converter 4, an external current source 40 (or a power supply with series couplingAn equivalent external voltage source of the resistor) is connected to the output node of the DC-DC converter 4 to supply it with a current I, for example using external hardware available in automatic test equipment LOAD . External capacitor C OUT Or between the output node of the converter 4 and ground GND. Thus, during testing, current I LOAD Is provided to the output node of the converter 4.
Basically, the test operation of the DC-DC boost converter 4 illustrated in fig. 4 is based on the same method discussed with reference to the DC-DC buck-boost converter 2 of fig. 3. Also in this example, during the testing phase of the converter device 4, the auxiliary loop circuit arrangement 24' is connected between the output node of the error amplifier 18 and the output node of the switching stage HB (e.g. via one or more electronic switches not visible in the figures attached hereto), and is able to operate as described below. In the test mode is enabled (e.g., as a function of the value of the test mode signal) and the external current I LOAD In the case of being forced by ATE, a loop is provided that includes a feedback voltage divider circuit 16, an error amplifier 18, and an auxiliary loop 24'. The auxiliary loop 24' receives the control voltage V generated by the error amplifier 18 C As its input signal. The conductivity of the transistor Q5 (e.g., its on-off state) is thus modulated to a control voltage V C Is a function of (2). Further, the current flowing through the transistor Q5 and the resistor R2 is modulated to a voltage V C Is a function of (2). The gate voltage of transistor Q6 is thus also modulated to voltage V C Is a function of (2). Conversely, the current flowing through transistor Q6 and being drawn from the output node of switching stage HB is also taken as voltage V C Is modulated. Thus, the loop will output the voltage V OUT Regulated to a selected value and in a steady state, an external current I LOAD Will flow through transistor Q6. Under this regulation condition, the circuit blocks involved in the loop (i.e., the feedback voltage divider circuit 16 and the error amplifier 18) are the same blocks that also operate during normal operation of the DC-DC converter 4. Thus, the additional inaccuracy generated by the auxiliary circuit 24 'can be ignored in the test phase, taking into account the contribution of the circuits 16 and 18 to the inaccuracy of the converter 4, since the circuit block 24' is arranged in errorDownstream of the difference amplifier 18. During testing, the external capacitor C may be selected (e.g., adjusted) OUT Is connected with the external current I LOAD To ensure the stability of the circuit.
In one or more embodiments, the trimming process performed during testing of the DC-DC converter 4 may include enabling the auxiliary loop 24 'as previously discussed (e.g., connecting the loop circuit arrangement 24' to the error amplifier 18 by closing a corresponding switch not visible in the figures attached hereto, while the transistor Q6 may be permanently connected to the output node of the switching stage HB), and then setting (e.g., adjusting) the available trim points in the main control loop of the converter 4 to set the output voltage V OUT Is adjusted to a desired value. For example, error amplifier 18 may be trimmed by calibrating the offset of error amplifier 18 in an appropriate manner, and/or reference voltage V may be trimmed REF Is a value of (2). The trimming process disclosed herein takes into account the circuit blocks (16 and 18) that affect the accuracy of the converter 4 during normal operation (i.e., under application conditions), and thus the trimmed output value V OUT As close as possible to the output value that occurs in normal operation of the converter 4. In addition, in the case of a desired shift, the output voltage V may be adjusted with a slightly different target value OUT To arrange normal operation including optional shifting.
Thus, one or more embodiments as illustrated herein may provide one or more of the following advantages:
for testing purposes, reusing the same circuits already available in the DC-DC converter loop and used in the normal operation of the DC-DC converter, which helps to monitor the converter voltage regulation and detect possible block mismatch of the converter under operating conditions, so that virtually all sources of inaccuracy are taken into account during these trimming processes;
-providing an auxiliary test loop implemented downstream (e.g. after) the error amplifier of the feedback loop of the converter, such that the inaccuracy of the auxiliary loop is negligible with respect to the inaccuracy of the feedback loop itself;
small silicon area increase;
no additional power consumption during normal operation of the DC-DC converter (e.g. when deployed in an end application), since the auxiliary loop may even be permanently disconnected (e.g. disconnected and not used) from the main feedback loop of the converter once the trimming phase is completed;
no switching system is required in an automatic test environment, resulting in a reduction of the cost and complexity of the test equipment;
faster, more reliable and/or more accurate test procedures, resulting in reduced costs and complexity of the test phase compared to previously known solutions;
-applicability to all control schemes of the DC-DC converter, irrespective of their operation in Continuous Conduction Mode (CCM), discontinuous Conduction Mode (DCM) or pulse skip mode of operation; and
suitable for all DC-DC converter architectures (e.g., buck-boost, buck, flyback, cuk, SEPIC, and others).
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection.
Claims (19)
1. A switching DC-DC converter circuit comprising:
a switching stage including an input node configured to receive an input voltage and an output node configured to generate an output voltage;
feedback loop circuit means coupled to the output node of the switching stage and configured to generate a control signal of the switching DC-DC converter circuit at a loop output node in dependence on a difference between the output voltage and a reference voltage; and
a test loop circuit arrangement arranged between the loop output node of the feedback loop circuit arrangement and the output node of the switching stage, wherein the test loop circuit arrangement is configured to apply a current at the output node in accordance with a value of the control signal of the switching DC-DC converter circuit when enabled;
wherein the feedback loop circuit arrangement is calibrated during a test phase of the switching DC-DC converter circuit.
2. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit arrangement is configured to: when enabled, the current is applied at the output node by providing the current to the output node of the switching stage according to the value of the control signal of the switching DC-DC converter circuit.
3. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit arrangement is configured to: when enabled, the current is applied at the output node of the switching stage by sinking the current from the output node according to the value of the control signal of the switching DC-DC converter circuit.
4. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit means comprises one or more enable switches configured to selectively couple the test loop circuit means to one or more of the loop output node of the feedback loop circuit means and the output node of the switching stage, and wherein the test loop circuit means is enabled by rendering the one or more enable switches conductive and disabled by rendering the one or more enable switches non-conductive.
5. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit means is coupled between the loop output node of the feedback loop circuit means and the output node of the switching stage, and wherein the test loop circuit means is enabled and disabled according to a test mode signal.
6. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit means comprises:
a first transistor having a control terminal coupled to the loop output node of the feedback loop circuit means to receive the control signal, wherein a current flowing through the first transistor is dependent on the control signal;
a current-voltage conversion circuit configured to generate a transistor control voltage for controlling an output transistor according to the current flowing through the first transistor; and
an output transistor coupled to the output node of the switching stage, the output transistor configured to receive the transistor control voltage at a respective control terminal and configured to provide current to or sink current from the output node of the switching stage in accordance with a value of the transistor control voltage.
7. The switching DC-DC converter circuit of claim 6, wherein:
the first transistor having a source terminal coupled to a first supply voltage rail and a gate terminal coupled to the loop output node of the feedback loop circuit device to receive the control signal;
the current-to-voltage conversion circuit includes a current mirror circuit having a mirrored input node coupled to a drain terminal of the first transistor and a mirrored output node coupled to a first terminal of a resistor having a second terminal coupled to a second supply voltage rail; and
the output transistor has a source terminal coupled to the second supply voltage rail, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to the output node of the switching stage, the output transistor configured to provide current to the output node of the switching stage.
8. The switching DC-DC converter circuit of claim 7, wherein the first supply voltage rail is an internal supply voltage rail of the switching DC-DC converter circuit and the second supply voltage rail is configured to receive the input voltage of the switching DC-DC converter circuit.
9. The switching DC-DC converter circuit of claim 6, wherein:
the first transistor has a source terminal coupled to ground and a gate terminal coupled to the loop output node of the feedback loop circuit device to receive the control signal;
the current-to-voltage conversion circuit includes a resistor having a first terminal coupled to a drain terminal of the first transistor and a second terminal coupled to a supply voltage rail; and
the output transistor has a source terminal coupled to ground, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to the output node of the switching stage, the output transistor configured to sink current from the output node of the switching stage.
10. The switching DC-DC converter circuit of claim 1, wherein the feedback loop circuit means comprises:
a feedback voltage divider circuit coupled to the output node of the switching stage and configured to generate a feedback voltage divided according to a voltage of the output voltage; and
an error amplifier configured to amplify a difference between the feedback voltage and the reference voltage to generate the control signal,
wherein one or more of an offset voltage of the error amplifier and the reference voltage of the error amplifier are calibrated during a test phase of the switching DC-DC converter circuit.
11. The switching DC-DC converter circuit of claim 10, wherein the feedback voltage divider circuit comprises:
a digital-to-analog converter circuit configured to convert the digital signal into an analog voltage signal;
a buffer circuit configured to receive the analog voltage signal from the digital-to-analog converter circuit and to generate a buffered analog voltage signal; and
a voltage step circuit arranged between an output node of the snubber circuit and the output node of the switching stage and configured to generate the feedback voltage at an intermediate node of the voltage step circuit,
wherein an offset voltage of the snubber circuit is calibrated during a test phase of the switching DC-DC converter circuit.
12. The switching DC-DC converter circuit of claim 10, wherein the feedback voltage divider circuit comprises a voltage ladder circuit disposed between the output node of the switching stage and a ground node and configured to generate the feedback voltage at an intermediate node of the voltage ladder circuit.
13. The switching DC-DC converter circuit of claim 1, further comprising:
a voltage ramp generating circuit means configured to generate a ramp signal; and
a comparator circuit configured to compare the ramp signal with the control signal to generate a pulse width modulated signal for controlling switching activity of the switching stage;
wherein the voltage ramp generating circuit arrangement comprises:
a ramp generator circuit configured to generate a basic ramp signal;
a current sensing circuit configured to sense a current flowing through one or more switches of the switching stage and to generate a signal indicative of the sensed current; and
an adder circuit configured to add the basic ramp signal and the signal indicative of the sensed current to generate the ramp signal.
14. A method of testing a switching DC-DC converter circuit, comprising:
setting the switching DC-DC converter circuit to a test mode of operation by preventing switching activity of the switching stage and enabling the test loop circuit arrangement;
applying a current according to the value of a control signal of the switching DC-DC converter circuit to an output node of the switching stage via the test loop circuit arrangement;
wherein applying the current to the output node of the switching stage is performed via an external current generator circuit;
sensing a value of an output voltage generated at the output node of the switching stage; and
one or more electronic components of the feedback loop circuit arrangement are calibrated until a desired value of the output voltage is generated at the output node of the switching stage.
15. The method of claim 14, wherein applying the current comprises providing a current to the output node of the switching stage; and wherein the external current generator circuit is a current source circuit.
16. The method of claim 14, wherein applying current comprises sinking current from the output node of the switching stage; and wherein the external current generator circuit is a current sink circuit.
17. The method of claim 14, further comprising calibrating an offset voltage of an error amplifier until a desired value of the output voltage is produced at the output node of the switching stage.
18. The method of claim 14, further comprising calibrating a reference voltage of an error amplifier until a desired value of the output voltage is produced at the output node of the switching stage.
19. The method of claim 14, further comprising calibrating an offset voltage of a buffer circuit until a desired value of the output voltage is produced at the output node of the switching stage.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT102022000005477 | 2022-03-21 | ||
| US18/121,767 | 2023-03-15 | ||
| US18/121,767 US20230299670A1 (en) | 2022-03-21 | 2023-03-15 | Dc-dc converter circuit and corresponding method of testing a dc-dc converter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116800055A true CN116800055A (en) | 2023-09-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310270633.3A Pending CN116800055A (en) | 2022-03-21 | 2023-03-20 | Converter circuit and corresponding method of testing a converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116800055A (en) |
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2023
- 2023-03-20 CN CN202310270633.3A patent/CN116800055A/en active Pending
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