CN116798871A

CN116798871A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN116798871A
Application number: CN202310064877.6A
Authority: CN
Inventors: 杨柏峰; 杨世海; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-17
Filing date: 2023-02-06
Publication date: 2023-09-22

Abstract

The application discloses a semiconductor device and a method of manufacturing the same. A method comprising forming a thin film omega transistor comprising: a gate fin is formed over the dielectric layer, a gate dielectric is formed on sidewalls and a top surface of the gate fin, and an oxide semiconductor layer is deposited over the gate dielectric. The gate fin, gate dielectric, and oxide semiconductor layer collectively form a fin structure. A source region is formed to contact the first sidewall and the first top surface of the first portion of the oxide semiconductor layer. A drain region is formed to contact the second sidewall and the second top surface of the second portion of the oxide semiconductor layer.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to semiconductor devices and methods of manufacturing the same.

Background

As the demand for more functionality and higher speeds in integrated circuits increases, the size of integrated circuit devices decreases. This makes it desirable to have new devices and greater flexibility in the design and fabrication of integrated circuits.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided a method for forming a semiconductor structure, comprising: forming a first thin film omega transistor comprising: forming a gate fin over the first dielectric layer; forming a first gate dielectric on sidewalls and a top surface of the gate fin; depositing a first oxide semiconductor layer over the first gate dielectric, wherein the gate fin, the first gate dielectric, and the first oxide semiconductor layer together form a fin structure; forming a source region in contact with a first sidewall and a first top surface of a first portion of the first oxide semiconductor layer; and forming a drain region in contact with the second sidewall and the second top surface of the second portion of the first oxide semiconductor layer.

According to a second aspect of the present disclosure, there is provided a semiconductor structure comprising: a first dielectric layer; and a thin film omega transistor comprising: a gate fin over the first dielectric layer; a gate dielectric on sidewalls and a top surface of the gate fin; an oxide semiconductor layer over the gate dielectric; a source region contacting the first sidewall and the first top surface of the first portion of the oxide semiconductor layer; and a drain region contacting the second sidewall and the second top surface of the second portion of the oxide semiconductor layer; an etch stop layer over and contacting the oxide semiconductor layer; and a second dielectric layer over the etch stop layer, wherein the source region and the drain region are in the etch stop layer and the second dielectric layer.

According to a third aspect of the present disclosure, there is provided a semiconductor structure comprising: a first dielectric layer; a thin film omega transistor comprising: a conductive fin protruding above a top surface of the first dielectric layer; a gate dielectric on the conductive fin; an oxide semiconductor layer on the gate dielectric, wherein the oxide semiconductor layer has a substantially omega-shaped cross-sectional shape; a source region contacting a first portion of the oxide semiconductor layer; and a drain region contacting a second portion of the oxide semiconductor layer; and a dielectric layer over and contacting a third portion of the oxide semiconductor layer, wherein the third portion is between and interconnects the first and second portions.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawing figures. It is noted that the various features are not drawn to scale according to standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a perspective view of a thin film omega transistor according to some embodiments.

Fig. 2 and 3 illustrate perspective and cross-sectional views, respectively, of a complementary transistor including a thin film omega transistor and a fin field effect transistor (FinFET) having parallel current flow directions, in accordance with some embodiments.

Fig. 4 and 5 illustrate perspective and cross-sectional views, respectively, of a complementary transistor including a thin film omega transistor and a FinFET having a perpendicular current flow direction, in accordance with some embodiments.

Fig. 6A, 6B, 7A, 7B, 8A, 8B, 9A, and 9B illustrate cross-sectional views of intermediate stages of forming a thin film omega transistor without a work function layer according to some embodiments.

Fig. 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, and 15B illustrate cross-sectional views of intermediate stages in forming a thin film omega transistor including a work function layer according to some embodiments.

Fig. 16 and 17 illustrate cross-sectional and top views, respectively, of a thin film omega transistor according to some embodiments.

Fig. 18A and 18B illustrate cross-sectional views of thin film omega transistors including high carrier concentration oxide semiconductor layers in the source and drain regions according to some embodiments.

Fig. 19 illustrates a cross-sectional view of some adjacent thin film omega transistors having connected or separated channel layers, according to some embodiments.

Fig. 20A and 20B illustrate top views of FinFET and thin film omega transistors, respectively, according to some embodiments.

Fig. 21 illustrates a circuit diagram of a complementary transistor including a thin film omega transistor and a FinFET, in accordance with some embodiments.

Fig. 22 illustrates a process flow for forming a thin film omega transistor in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "lower," "overlying," "upper," etc.) may be used herein to facilitate a description of the relationship of one element or feature to another element(s) or feature(s) shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A thin film omega transistor and a complementary transistor including a thin film omega transistor and a fin field effect transistor (FinFET) are provided. Methods of forming the same are provided. According to some embodiments of the present disclosure, a thin film omega transistor includes a fin gate, a gate dielectric on a top surface and sidewalls of the fin gate, an oxide semiconductor layer over the gate dielectric to function as a channel, and source and drain regions over and in contact with the oxide semiconductor layer. Thin film omega transistors have high currents for the fin structures employed. In addition, thin film omega transistors may form complementary devices with finfets. The embodiments discussed herein are provided to provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the scope of the various embodiments contemplated. Like reference numerals are used to denote like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1 illustrates a perspective view of a thin film omega transistor 20 in accordance with some embodiments. The thin film omega transistor 20 may be formed over a dielectric layer 22. Features underlying dielectric layer 22 are not shown. According to some embodiments, features underlying dielectric layer 22 may include etch stop layers, interlayer dielectrics, contact etch stop layers, semiconductor substrates, and the like. Dielectric layer 22 may be a silicon oxide layer, a low-k dielectric layer, a high-k dielectric layer, or the like. For example, dielectric layer 22 may include an inter-metal dielectric (IMD) in which metal lines and metal vias are formed.

A gate fin 24 is formed on the dielectric layer 22. According to some embodiments, the gate fin 24 is formed of a conductive material, which may be discussed in detail in subsequent paragraphs. Fig. 1 shows two gate fins 24 that may be electrically connected to each other, as shown in fig. 20B. It will be appreciated that the thin film omega transistor 20 may also be a single gate fin transistor, or may include more than two gate fins.

A gate dielectric 26 is formed on the sidewalls and top surface of the gate fin 24. The gate dielectric 26 is formed of a dielectric material such that the gate fin 24 is electrically insulated from a subsequently formed oxide semiconductor layer 28. According to some embodiments, gate dielectric 26 includes silicon oxide, silicon nitride, silicon oxynitride, such as hafnium oxide, aluminum oxide, hafnium zirconium oxide (HfZrO ₂ ) Such as high-k dielectric materials, combinations thereof, multilayers thereof, and the like. According to some embodiments, gate dielectric 26 is formed by deposition and thus includes a horizontal portion that extends over the top surface of dielectric layer 22. According to an alternative embodiment, the gate dielectric 26 is formed by an oxidation process, wherein a surface layer of each gate fin 24 is oxidized to form the gate dielectric 26. The corresponding gate dielectric 26 does not include a horizontal portion extending over the top surface of the dielectric layer 22.

An oxide semiconductor layer 28 is formed on the gate dielectric 26. The oxide semiconductor layer 28 includes an oxide and includes two sidewall portions on the sidewall portions of the gate dielectric 26 and a top portion over the top surface portion of the gate dielectric 26. Accordingly, the oxide semiconductor layer 28 has an omega (Ω) shape, and the resulting transistor is referred to as a thin film omega transistor. The gate fin 24, gate dielectric 26, and oxide semiconductor layer 28 collectively form a fin structure that protrudes above the dielectric layer 22.

According to some embodiments, the oxide semiconductor layer 28 is used to form an n-type transistor that is turned on when a positive bias voltage is applied across the gate fin 24 (relative to the voltage on the corresponding source region). The corresponding oxide semiconductor layer 28 may include indium (In). Since indium has a 5s electron orbit, the resulting oxide is conductive. By mixing indium with other elements such as gallium (Ga), zinc (Zn), tungsten (W), and the like, the conductivity of the resultant oxide can be adjusted to have semiconductor characteristics. According to some embodiments, when the resulting transistor is an n-type transistor, the oxide semiconductor layer 28 may be formed of or include: indium Tin Oxide (ITO), indium oxide (InO), indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), indium tungsten oxide (IWO), and the like, or combinations thereof.

According to an alternative embodiment, the oxide semiconductor layer 28 is used to form a p-type transistor that is turned on when a negative bias voltage is applied to the gate (relative to the voltage on the corresponding source region). The corresponding oxide semiconductor layer 28 may also include, for example, niO, cuO, cr ₂ O ₃ 、Co ₃ O ₄ 、Mn ₃ O ₄ And the like. According to some embodiments, example N-type and P-type transistors are shown as transistors 20N and 20P (fig. 21), respectively, which may form part of an inverter.

The thin film omega transistor 20 also includes source/drain regions 60. Throughout the specification, the source/drain region(s) may refer to a source or a drain, individually or collectively, depending on the context. The source/drain regions 60 may be in physical contact with the oxide semiconductor layer 28 without a silicide layer in between. According to some embodiments, the source/drain regions 60 are formed of or include: ti, tiN, W, al, mo, ni, etc., or alloys thereof.

Fig. 2 shows a perspective view of a transistor including a thin film omega transistor 20 and a FinFET 120. According to some embodiments, either one of the thin film omega transistor 20 and the FinFET 120 may be an n-type transistor, while the other may be a p-type transistor. Thus, the thin film omega transistor 20 and the FinFET 120 may together form a complementary transistor. According to alternative embodiments, both the thin film omega transistor 20 and the FinFET 120 are p-type transistors or n-type transistors.

According to some embodiments, finFET 120 is formed based on semiconductor substrate 34. Shallow Trench Isolation (STI) regions 36 may be formed over a body portion of semiconductor substrate 34 with semiconductor strips 38 between STI regions 36. A top portion of semiconductor strap 38 may protrude above a top surface of STI region 36 to form a protruding semiconductor fin 40. A gate stack 46 including a gate dielectric 42 and a gate electrode 44 is formed on the protruding semiconductor fin 40. Portions of the protruding semiconductor fin 40 on opposite sides of the gate stack 46 may be replaced with n-type semiconductor material to form source/drain regions of an n-type transistor, or with p-type semiconductor material to form source/drain regions of a p-type transistor. According to some embodiments, the FinFET 120 is formed using a front-end-of-line process. The formation of FinFET 120 may involve high temperatures that may be greater than about 700 deg.c.

A thin film omega transistor 20 is formed over FinFET 120. According to some embodiments, the thin film omega transistor 20 overlaps at least a portion or all of the FinFET 120. When the thin film omega transistor 20 and the FinFET 120 are electrically interconnected, this may reduce the routing distance between them.

Fig. 3 illustrates a cross-sectional schematic diagram of a thin film omega transistor 20 and FinFET 120 in accordance with some embodiments. The cross-sectional view of the thin film omega transistor 20 is taken from the plane (plane 1-plane 1) in fig. 2. Thus, the source/drain regions 48 and the gate stack 46 of the FinFET 120 are in the illustrated plane. The gate fin 24, gate dielectric 26, oxide semiconductor 28, and source/drain regions 60 of the thin film omega transistor 20 are also in the plane shown.

According to some embodiments, the operation of the thin film omega transistor 20 is similar to the operation of the FinFET 120. For example, when a positive voltage VGS is applied between the gate fin 24 and the source region 60 of the n-type thin film omega transistor 20, the conductive channel in the oxide semiconductor layer 28 is turned on to electrically connect the source region 60 to the corresponding drain region 60. Thus, a current I1 flows between the drain region 60 and the source region 60. In contrast, when a voltage VGS lower than the threshold voltage of the n-type thin film omega transistor 20 is applied between the gate fin 24 and the source region 60, the channel in the oxide semiconductor layer 28 is turned off to electrically disconnect the source region 60 from the corresponding drain region 60. In contrast, for the p-type thin film omega transistor 20, the negative voltage VGS turns on the channel, while a small negative, zero or positive voltage VGS turns off the channel.

Fig. 4 illustrates a perspective view of a transistor including a thin film omega transistor 20 and a FinFET 120 in accordance with some embodiments. These embodiments are similar to the embodiments shown in fig. 2 and 3, except that: in fig. 2 and 3, the current flow directions of the thin film omega transistor 20 and the FinFET 120 are parallel to each other, and the current flow directions of the thin film omega transistor 20 and the FinFET 120 in fig. 4 are perpendicular to each other. For example, in fig. 2, the current flow directions of the currents I1 and I2 of both the thin film omega transistor 20 and the FinFET 120 are along the X direction, respectively; in fig. 4, the current I1 of the thin film omega transistor 20 flows in the Y direction and the current I2 of the FinFET 120 flows in the X direction. By arranging the current flow directions of the thin film omega transistor 20 and the FinFET 120 to be perpendicular or parallel to each other, the metal wiring of the metal line and the contact plug can be optimized.

Fig. 5 illustrates a cross-sectional view of some thin film omega transistors 20 and finfets 120 according to some embodiments. The cross-sectional view of the thin film omega transistor 20 is taken from the plane (plane 2-plane 2) in fig. 4. Thus, in fig. 5, the source/drain regions 48 and the gate stack 46 of the FinFET 120 are in the illustrated plane. The gate fin 24, gate dielectric 26, oxide semiconductor 28, and source/drain regions 60 of the thin film transistor 20 are in the plane shown.

Fig. 6A, 6B, 7A, 7B, 8A, 8B, 9A, and 9B illustrate cross-sectional views of intermediate stages of forming a thin film omega transistor 20 according to some embodiments. The thin film omega transistor 20 according to these embodiments does not include a work function layer therein. The corresponding process is also schematically reflected in the process flow 200 shown in fig. 22. Fig. 6A, 7A, 8A and 9A show a section A-A in fig. 1, and fig. 6B, 7B, 8B and 9B show a section B-B in fig. 1. The formation of the thin film omega transistor 20 may be performed at a temperature below about 400 deg.c to maintain the characteristics of the oxide semiconductor layer 28. This temperature range is compatible with the back-end-of-line process. Thus, the thin film omega transistor 20 may be formed in a back-end-of-line configuration rather than in a front-end-of-line configuration.

It should be appreciated that the process shown in fig. 6A, 6B, 7A, 7B, 8A, 8B, 9A, and 9B begins after the process of forming FinFET 120 and after forming dielectric layer 22. According to some embodiments, the formation of FinFET 120 may include forming STI regions 36 (fig. 2 and 4) extending into semiconductor substrate 34. Referring to fig. 2 and 4, semiconductor strips 38 are between adjacent STI regions 36. STI region 36 is then recessed. The top portion of semiconductor strap 38 thus protrudes higher than the top surface of recessed STI region 36 to form protruding semiconductor fin 40. A dummy gate stack is then formed over a portion of the protruding semiconductor fin 40, followed by recessing portions of the semiconductor stripe 38 and forming source/drain regions starting from the corresponding recesses. A Contact Etch Stop Layer (CESL) 82 (fig. 19) and an interlayer dielectric (ILD) 84 are then formed. The dummy gate stack may then be replaced with a replacement gate stack 46, which replacement gate stack 46 may include a high-k gate dielectric and a metal gate stack.

After forming FinFET 120, some overlying features, such as gate contact plugs, source/drain contact plugs, ILD(s), etch stop layer(s), may then be formed over FinFET 120. According to some embodiments, the vertical space between the thin film omega transistor 20 and the FinFET 120 may be filled with ILD(s), etch stop layer(s), and may or may not include an IMD that may be a low-k dielectric layer.

The process then moves to the process shown in fig. 6A and 6B, with fig. 6A and 6B showing vertical cross-sections of the first plane A-A and the second plane B-B in fig. 1, respectively. The first vertical plane A-A is perpendicular to the longitudinal direction of the gate fin 24. The second plane B-B is parallel to the longitudinal direction of the gate fin 24.

Referring to fig. 6A, a gate fin 24 is formed. The corresponding process is shown as process 202 in process flow 200 shown in fig. 22. The forming process may include depositing a blanket conductive layer and then patterning the blanket conductive layer by etching. According to some embodiments, gate fin 24 is formed of a conductive material, which may be formed of or include: aluminum, aluminum copper, tungsten, cobalt, nickel, etc., or alloys thereof. The blanket conductive layer may be deposited by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or the like.

In the above embodiments, the gate fin 24 may be patterned by any suitable method. For example, one or more photolithographic processes (including double patterning or multiple patterning processes) may be used to pattern the gate fins 24. In general, a double patterning process or a multiple patterning process combines a photolithography process and a self-aligned process, allowing patterns to be created with smaller pitches than would otherwise be possible using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used to pattern the fins.

The width W1 of the gate fin 24 is selected to be neither too large nor too small. If the gate fin 24 is too wide, the chip area utilization is low and the gate control of the fin is poor. Conversely, if the gate fin 24 is too narrow, the gate fin 24 may collapse due to the significant height of the gate fin 24. According to some embodiments, the width W1 of the gate fin 24 is in a range between about 5nm to about 30 nm. The total number of gate fins 24 in a thin film omega transistor may be in the range between 2 and 10 (while a single fin is also possible). It will be appreciated that mobility may be poor if a single gate fin 24 is employed. If one transistor employs too many gate fins 24, the chip area occupied by the corresponding device is too large. The height H1 of the gate fin 24 may be in a range between about 20nm to about 100 nm. The spacing S1 of the gate fins 24 may be in a range between about 20nm to about 120 nm.

Fig. 7A and 7B illustrate the formation of gate dielectric 26. The corresponding process is shown as process 206 in process flow 200 shown in fig. 22. According to some embodiments, gate dielectric 26 comprises silicon oxide, silicon nitride, silicon oxynitride, or the like. Gate dielectric 26 may also be formed from or include the following: such as hafnium oxide, aluminum oxide, hafnium zirconium oxide (HfZrO ₂ ) Such as high-k dielectric materials, combinations thereof, multilayers thereof, and the like. According to some embodiments, gate dielectric 26 is formed by deposition and thus includes a horizontal portion directly on the top surface of dielectric layer 22. According to an alternative embodiment, the gate electricity is formed by oxidizing and/or nitriding sidewall surface portions and top surface portions of the gate fin 24Dielectric 26 to form metal oxides and/or nitrides. Thus, the gate dielectric 26 includes an oxide and/or nitride of the metal used in the gate fin 24. Further, when formed by oxidation and/or nitridation, the corresponding gate dielectric 26 is not included over the top surface of the dielectric layer 22 and contacts a horizontal portion of the top surface of the dielectric layer 22. According to some embodiments, the thickness T1 of the gate dielectric 26 is in a range between about 1nm to about 10 nm.

Fig. 7A and 7B also illustrate deposition of an oxide semiconductor layer 28 according to some embodiments. The corresponding process is shown as process 208 in process flow 200 shown in fig. 22. The material of the oxide semiconductor layer 28 is discussed in the previous paragraphs, and thus will not be described here again. For example, when the resulting transistor is an n-type transistor, the oxide semiconductor layer 28 may include ITO, inO, IGZO, IZO, IWO or the like or a combination thereof. When the resulting transistor is a p-type transistor, the oxide semiconductor layer 28 may include NiO, cuO, cr ₂ O ₃ 、Co ₃ O ₄ 、Mn ₃ O ₄ Etc.

The oxide semiconductor layer 28 can be formed by ALD, PVD, CVD or the like. For example, when ALD is used to form IGZO, the precursors may include: (3-dimethylaminopropyl) -dimethylindium (DADI) as an indium precursor, diethylzinc (DEZ) as a zinc precursor, and trimethylgallium (TMGa) as a gallium precursor. O (O) ₂ The plasma may be used to introduce oxygen. The wafer temperature during deposition of oxide semiconductor layer 28 may be in a range between about 180 ℃ to about 250 ℃.

The thickness T2 of the oxide semiconductor layer 28 is selected to be within a certain range, and the oxide semiconductor layer 28 cannot be too thick nor too thin. When the oxide semiconductor layer 28 is too thick, the carrier concentration in the oxide semiconductor layer 28 is too high, which may result in the threshold voltage of the corresponding transistor being too low (e.g., having a zero threshold voltage or even a negative threshold voltage), which means that the transistor may be always on. When the oxide semiconductor layer 28 is too thin, the carrier concentration is too high, and the threshold voltage is too high. According to some embodiments, the thickness T2 of the oxide semiconductor layer 28 is in a range between about 2nm to about 15 nm.

According to some embodiments, the oxide semiconductor layer 28 includes a homogeneous oxide semiconductor material, which may be selected from the foregoing materials. According to alternative embodiments, the oxide semiconductor layer 28 may be a composite layer including two or more sub-layers formed of materials different from each other. For example, the oxide semiconductor layer 28 may include a lower sub-layer 28A and an upper sub-layer 28B over the lower sub-layer 28A. The upper sub-layer 28B may have a higher conductivity value than the lower sub-layer 28A. The interface between sub-layers 28A and 28B is shown as a dashed line to indicate that oxide semiconductor layer 28 may be formed of a homogenous material or may include sub-layers. Both the lower sub-layer 28A and the upper sub-layer 28B may be oxide semiconductor layers formed using a material selected from the above-described candidate material group. For example, both the lower sub-layer 28A and the upper sub-layer 28B may be indium-containing semiconductor layers, with the upper sub-layer 28B having a higher atomic percent of indium than the lower sub-layer 28A.

According to some embodiments, the upper sub-layer 28B comprises a high concentration of oxide semiconductor material, the upper sub-layer 28B having a higher carrier concentration than the lower sub-layer 28A. Thus, the upper sub-layer 28B may have a higher conductivity value than the lower sub-layer 28A. With the upper sub-layer 28B having a higher carrier concentration, the contact resistance between the source/drain region 60 and the oxide semiconductor layer 28 can be reduced. The type (p-type or n-type) of the lower sub-layer 28A is the same as the type of the upper sub-layer 28B. For example, when the upper sub-layer 28B is used to form an n-type transistor and may include ITO, inO, IGZO, IZO, IWO, etc., or a combination thereof, the lower sub-layer 28A may also be selected from any of ITO, inO, IGZO, IZO, IWO, etc. When upper sub-layer 28B is used to form a p-type transistor and may include NiO, cuO, cr ₂ O ₃ 、Co ₃ O ₄ 、Mn ₃ O ₄ Etc., or combinations thereof, the lower sub-layer 28A may also be selected from NiO, cuO, cr ₂ O ₃ 、Co ₃ O ₄ 、Mn ₃ O ₄ And the like.

The lower sub-layer 28A and the upper sub-layer 28B may include the same elements with different element percentages. For example, both the lower sub-layer 28A and the upper sub-layer 28B may be one of ITO, inO, IGZO, IZO, IWO, wherein the indium atomic percent IC28B in the upper sub-layer 28B is higher than the indium atomic percent IC28A in the lower sub-layer 28A. For example, the ratio of IC28A/IC28B may be greater than about 1.2, and may range between about 1.2 and 2.0. The forming process may include depositing a lower sub-layer 28A and increasing the flow rate of the indium-containing gas to deposit an upper sub-layer 28B. Alternatively, elements (e.g., tin, gallium, zirconium, nickel, cu, cr, co, and/or Mn) included in one of the lower sub-layer 28A and the upper sub-layer 28B may not be in the other of the lower sub-layer 28A and the upper sub-layer 28B.

Fig. 8A and 8B illustrate the formation of an etch stop layer 54 and a dielectric layer 56 according to some embodiments. The corresponding process is shown as process 210 in process flow 200 shown in fig. 22. The etching stop layer 54 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. Dielectric layer 56 may comprise a dielectric material formed using, for example, CVD, ALD, PECVD, FCVD, spin-on, or any other suitable deposition method. Dielectric layer 56 may be formed of or include the following: silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Dielectric layer 56 may also be formed of or include a low-k dielectric material, such as a carbon-containing dielectric material, having a dielectric constant (k value) of less than about 3.5, and possibly less than about 3.0. The low-k dielectric material may be porous.

Next, source/drain openings 58 are formed by etching through dielectric layer 56 and etch stop layer 54, wherein etch stop layer 54 serves to stop etching of dielectric layer 56. The corresponding process is shown as process 212 in process flow 200 shown in fig. 22. Thus, the oxide semiconductor layer 28 is formed.

Fig. 9A and 9B illustrate the formation of source/drain regions 60. The corresponding process is shown as process 214 in process flow 200 shown in fig. 22. The formation process may include depositing a conductive material (e.g., a metal material) into the source/drain openings 58, and then performing a planarization process to remove the excess conductive material. The deposition process may include ALD, CVD, PVD, etc. The material of the source/drain regions 60 may include a metallic material, such as Ti, tiN, W, al, mo, ni, or the like, or an alloy thereof. Thus forming a thin film omega transistor 20.

According to some embodiments, the source/drain regions 60 are formed of a homogenous material, which may be a metallic material. According to an alternative embodiment, the source/drain regions 60 are multi-layer regions comprising a plurality of sub-layers. For example, fig. 9A and 9B illustrate that source/drain regions 60 may include a sub-layer 60A and a sub-layer 60B on sub-layer 60A. The materials of sub-layers 60A and 60B are discussed in detail with reference to fig. 18A and 18B. The interface between sub-layers 60A and 60B is shown as a dashed line to indicate that source/drain regions 60 may be formed of a homogenous material or may include sub-layers.

In the operation of the thin film omega transistor 20, when an appropriate bias voltage VGS (higher than a threshold voltage) is applied, a channel 28C (fig. 9B) is formed in the oxide semiconductor layer 28 and between the source/drain regions 60. Accordingly, the thin film omega transistor 20 is on and a current I1/I2 flows through the channel, where the current I1 represents the current when the thin film omega transistor 20 is an n-type transistor and the current I2 represents the current when the thin film omega transistor 20 is a p-type transistor. In other cases, no channel is formed, and the thin film omega transistor 20 is turned off.

Fig. 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, and 15B illustrate cross-sectional views of intermediate stages of forming a thin film omega transistor 20 including a work function layer according to some embodiments. Unless otherwise indicated, the materials and formation of the components in these embodiments are substantially the same as the same components in the previous embodiments denoted by the same reference numerals. Accordingly, details regarding the formation processes and materials of components in these embodiments may be found in the discussion of the foregoing embodiments. These processes are also shown in the process flow shown in fig. 22, except for the addition of processes 204 and 205.

Fig. 10A and 10B illustrate the formation of gate fin 24. Referring to fig. 11A and 11B, a work function layer 25 is deposited. The corresponding process is shown as process 204 in process flow 200 shown in fig. 22. The work function layer determines a work function of the corresponding gate electrode and includes at least one layer or a plurality of layers formed of different materials. The material of the work function layer 25 is selected according to whether the corresponding thin film omega transistor is an n-type FinFET or a p-type FinFET. For example, when the resulting thin film omega transistor 20 (fig. 15A and 15B) is a p-type transistor, the work function layer 25 may be or may include TiN, W, mo, and the like. When the resulting thin film omega transistor (fig. 15A and 15B) is a p-type transistor, the work function layer 25 may be or may include an aluminum-containing metal layer (e.g., tiAl, tiAlC, tiAlN, W, mo, etc.). The work function layer 25 may be formed by a conformal deposition process such as ALD, CVD, or the like.

Referring to fig. 12A and 12B, an etch mask 66 is formed and patterned. The etch mask 66 covers the portion of the work function layer 25 directly over the gate fin 24 and exposes at least some portions of the work function layer 25 away from the gate fin 24. The etch mask 66 may comprise photoresist and may be a single layer etch mask, a double layer etch mask, a triple layer etch mask, or the like. Next, the work function layer 25 is patterned, and an exposed portion of the work function layer 25 is removed by etching, as shown in fig. 13A and 13B. The corresponding process is shown as process 205 in process flow 200 shown in fig. 22. The etch mask 66 is then removed.

Referring to fig. 14A and 14B, a gate dielectric 26 is formed. An oxide semiconductor layer 28 is then formed on the gate dielectric 26. Next, as also shown in fig. 14A and 14B, an etch stop layer 54 and a dielectric layer 56 are formed, and then source/drain openings 58 are formed. Fig. 15A and 15B illustrate the formation of source/drain regions 60. Thus forming a thin film omega transistor 20. The interface between sub-layers 60A and 60B is shown as a dashed line to indicate that source/drain regions 60 may be formed of a homogenous material or may include sub-layers. The interface between the lower sub-layer 28A and the upper sub-layer 28B of the oxide semiconductor layer 28 is also shown as a dashed line to indicate that the oxide semiconductor layer 28 may or may not include sub-layers.

Fig. 16 shows a cross-sectional view of the thin film omega transistor 20 as shown in fig. 9A and 9B or fig. 15A and 15B. The width W1, height H1, spacing S1, and thicknesses T1 and T2 discussed with reference to the previous figures are reproduced. The pitch P1 of the thin film omega transistor 20 and the adjacent nearest thin film omega transistor 20 (not shown) may be in the range between about 60nm to about 150nm, assuming that the thin film omega transistor 20 has two gate fins 24. The pitch P1 may be a pitch of the source/drain regions 60 of the adjacent thin film omega transistors 20. The spacing S2 between the illustrated source/drain regions 60 and adjacent source/drain regions 60 (not shown) nearest thereto may be in the range of between about 10nm to about 30 nm.

Fig. 17 illustrates a top view of the thin film omega transistor 20 as shown in fig. 9A and 9B or fig. 15A and 15B, according to some embodiments. The width W2 of the source/drain regions 60 may be in a range between about 40nm to about 60 nm. The spacing S3 between adjacent source/drain regions 60 may be in the range between about 15nm to about 45 nm. The gate fin 24 may extend (in the longitudinal direction) beyond the edge of the source/drain region 60 by a distance D1, which distance D1 may be in the range between about 15nm and about 40 nm. The source/drain region spacing P2 from the source/drain region of an adjacent thin film omega transistor 20 (not shown) may range between about 70nm and about 120 nm.

Fig. 18A and 18B illustrate some embodiments when the source/drain regions 60 include sublayers 60A and 60B formed of different materials. According to some embodiments, sub-layer 60A includes a high carrier concentration oxide semiconductor material having a higher carrier concentration than oxide semiconductor layer 28. By forming the sub-layer 60A from an oxide semiconductor material having a higher carrier concentration, contact resistance between the source/drain region 60 and the oxide semiconductor layer 28 can be reduced. The conductivity type (p-type or n-type) of the sub-layer 60A is the same as that of the oxide semiconductor layer 28. For example, when the oxide semiconductor layer 28 is used to form an n-type transistor and may include ITO, inO, IGZO, IZO, IWO or the like, or a combination thereof, the sub-layer 60A may also be selected from any one of ITO, inO, IGZO, IZO, IWO or the like, and a combination thereof. When the oxide semiconductor layer 28 is used to form a p-type transistor and includes NiO, cuO, cr ₂ O ₃ 、Co ₃ O ₄ 、Mn ₃ O ₄ Etc., or combinations thereof, sub-layers60A may also be selected from NiO, cuO, cr ₂ O ₃ 、Co ₃ O ₄ 、Mn ₃ O ₄ Etc., and combinations thereof. According to some embodiments, when both oxide semiconductor layer 28 and sub-layer 60A are formed of a material comprising a group of ITO, inO, IGZO, IZO, IWO, or a combination thereof, indium atomic percent IC60A of sub-layer 60A may be higher than indium atomic percent IC28 of oxide semiconductor layer 28. For example, the ratio of IC60A/IC28 may be greater than about 1.2, and may range between about 1.2 and 2.0.

Fig. 19 illustrates a cross-sectional view of some thin film omega transistors 20 (including 20-1, 20-2, 20-3, 20-4, and 20-5) and corresponding underlying finfets 120 according to some embodiments. The thin film omega transistor 20 and FinFET 120 may be interconnected (via metal lines and contact plugs) to form complementary devices, such as inverters. Each of the thin film omega transistors 20-1, 20-2, 20-3, 20-4, and 20-5 may have a structure as discussed in the previous embodiments. The thin film omega transistors 20-1 and 20-2 may be interconnected or disconnected from each other in terms of signal and electrical aspects. According to some embodiments, the oxide semiconductor layer 28 of the thin film omega transistor 20-1 and the oxide semiconductor layer 28 of the thin film omega transistor 20-2 are part of the same continuous oxide semiconductor layer without interruption therebetween, although the thin film omega transistors 20-1 and 20-2 are discrete transistors and may be electrically interconnected or disconnected. For example, although the thin film omega transistors 20-1 and 20-2 both use the same continuous oxide semiconductor layer 28, the gates of the thin film omega transistors 20-1 and 20-2 may be electrically disconnected from each other, their source regions may be electrically disconnected from each other, and their drain regions may be electrically disconnected from each other. It will be appreciated that the use of the same continuous oxide semiconductor layer for both thin film omega transistors 20-1 and 20-2 may result in a slightly higher leakage current, which may be acceptable in some applications.

Fig. 19 also shows thin film omega transistors 20-3 and 20-4 according to an alternative embodiment. In these embodiments, the oxide semiconductor layer 28 of the thin film omega transistor 20-3 and the oxide semiconductor layer 28 of the thin film omega transistor 20-4 are physically separated from each other, wherein there is a break that physically and electrically separates the oxide semiconductor layers 28 from each other. The interruption may be completely or partially filled with the etch stop layer 54 and may or may not be filled with the dielectric layer 56. The interruption may be formed by a patterning process by etching, which may use the underlying gate dielectric 26 as an etch stop layer.

Fig. 20A and 20B illustrate top views of FinFET 120 and thin film omega transistor 20, respectively, according to some embodiments. As shown in fig. 20A, finFET 120 includes source/drain regions 48, with source/drain regions 48 connected to opposite ends of protruding semiconductor fin 40. The gate stack 42 spans the protruding semiconductor fin 40. The source/drain regions 48 are electrically connected to metal lines 70 by source/drain contact plugs 72. The gate stack 42 is electrically connected to a metal line 76 through a gate contact plug 74.

As shown in fig. 20B, the thin film omega transistor 20 includes a gate fin 24, a gate dielectric 26, and an oxide semiconductor layer 28, with source/drain regions 60 intersecting the oxide semiconductor layer 28 above it. The gate fin 24 is electrically connected to the metal line 78 through a gate contact plug 80.

Fig. 21 shows a circuit diagram of an example circuit formed by complementary transistors including an n-type transistor and a p-type transistor. The circuit shown may be an inverter according to an example embodiment. The N-type transistor may be an N-type thin film transistor 20N or an N-type FinFET 120N. The P-type transistor may be a P-type thin film transistor 20P or a P-type FinFET 120P.

Embodiments of the present disclosure have some advantageous features. By forming a thin film omega transistor having an omega-shaped channel region, the chip area occupied by the corresponding transistor is increased while still increasing the saturation current of the transistor. Thin film omega transistors may be formed directly over front-end-of-line transistors such as finfets, so that further chip area is saved.

According to some embodiments of the present disclosure, a method includes forming a first thin film omega transistor, including forming a gate fin over a first dielectric layer; forming a first gate dielectric on sidewalls and a top surface of the gate fin; depositing a first oxide semiconductor layer over the first gate dielectric, wherein the gate fin, the first gate dielectric, and the first oxide semiconductor layer together form a fin structure; forming a source region in contact with a first sidewall and a first top surface of a first portion of the first oxide semiconductor layer; and forming a drain region in contact with the second sidewall and the second top surface of the second portion of the first oxide semiconductor layer.

In one embodiment, the method further includes forming a FinFET on the semiconductor substrate, wherein the first dielectric layer overlies the semiconductor substrate and the FinFET. In an embodiment, the first thin film omega transistor overlaps the FinFET. In an embodiment, the first thin film omega transistor and the FinFET have opposite conductivity types, and the method further comprises electrically interconnecting the first thin film omega transistor and the FinFET to form a complementary device. In an embodiment, each of the source region and the drain region includes an additional oxide semiconductor layer; and a metal layer on the additional oxide semiconductor layer. In an embodiment, forming the source region and the drain region includes forming a second dielectric layer over the fin structure; forming a source opening and a drain opening exposing a first portion and a second portion of the first oxide semiconductor layer, respectively; depositing an additional oxide semiconductor layer extending into the source and drain openings; and depositing a metal layer on the additional oxide semiconductor layer.

In one embodiment, the additional oxide semiconductor layer has a higher conductivity value than the first oxide semiconductor layer. In an embodiment, both the first oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher atomic percentage of indium than the first oxide semiconductor layer. In an embodiment, the method further comprises forming a second thin film omega transistor in close proximity to the first thin film omega transistor, wherein the second thin film omega transistor comprises a second gate dielectric and a second oxide semiconductor layer on the second gate dielectric, wherein the first thin film omega transistor and the second thin film omega transistor are discrete transistors that are electrically disconnected from each other and signal disconnected, and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are part of a continuous oxide semiconductor layer.

In one embodiment, the method further comprises forming a second thin film omega transistor proximate to the first thin film omega transistor, wherein the second thin film omega transistor comprises a second gate dielectric and a second oxide semiconductor layer, wherein the first thin film omega transistor and the second thin film omega transistor are discrete transistors that are electrically disconnected and signal disconnected from each other, and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are separated from each other by an etch stop layer and an additional dielectric layer. In an embodiment, the first gate dielectric and the second gate dielectric are part of a continuous dielectric layer.

According to some embodiments of the present disclosure, a structure includes a first dielectric layer; and a thin film omega transistor comprising a gate fin over the first dielectric layer; a gate dielectric on sidewalls and top surfaces of the gate fin; an oxide semiconductor layer over the gate dielectric; a source region contacting the first sidewall and the first top surface of the first portion of the oxide semiconductor layer; and a drain region contacting the second sidewall and the second top surface of the second portion of the oxide semiconductor layer; an etch stop layer over and contacting the oxide semiconductor layer; and a second dielectric layer over the etch stop layer, wherein the source region and the drain region are in the etch stop layer and the second dielectric layer. In an embodiment, the structure further comprises a FinFET on the semiconductor substrate, wherein the first dielectric layer is over the semiconductor substrate and the FinFET, and wherein the thin film omega transistor overlaps the FinFET.

In one embodiment, the thin film omega transistor and the FinFET have opposite conductivity types, and the structure further includes a metal line and a contact plug electrically interconnecting the thin film omega transistor and the FinFET to form a complementary device. In an embodiment, each of the source region and the drain region includes an additional oxide semiconductor layer having a U-shaped cross-sectional shape; and a metal layer between opposite sidewall portions of the additional oxide semiconductor layer. In an embodiment, the additional oxide semiconductor layer has a higher conductivity value than the oxide semiconductor layer. In an embodiment, both the oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher atomic percentage of indium than the oxide semiconductor layer.

According to some embodiments of the present disclosure, a structure: comprising a first dielectric layer; a thin film omega transistor comprising a conductive fin protruding above a top surface of the first dielectric layer; a gate dielectric on the conductive fin; an oxide semiconductor layer on the gate dielectric, wherein the oxide semiconductor layer has a substantially omega-shaped cross-sectional shape; a source region contacting a first portion of the oxide semiconductor layer; a drain region contacting a second portion of the oxide semiconductor layer; and a dielectric layer over and contacting a third portion of the oxide semiconductor layer, wherein the third portion is located between the first portion and the second portion and interconnects the first portion and the second portion.

In one embodiment, the source region includes an additional oxide semiconductor layer including: a bottom portion over and contacting the oxide semiconductor layer; a sidewall portion above and connected to an opposite end of the bottom portion; and a metal region over the bottom portion and between the sidewall portions. In an embodiment, an oxide semiconductor layer includes: a first sub-layer having a first conductivity value; a second sub-layer over the first sub-layer, wherein the second sub-layer has a second conductivity value that is higher than the first conductivity value.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example

Example 1. A method for forming a semiconductor structure, comprising: forming a first thin film omega transistor comprising: forming a gate fin over the first dielectric layer; forming a first gate dielectric on sidewalls and a top surface of the gate fin; depositing a first oxide semiconductor layer over the first gate dielectric, wherein the gate fin, the first gate dielectric, and the first oxide semiconductor layer together form a fin structure; forming a source region in contact with a first sidewall and a first top surface of a first portion of the first oxide semiconductor layer; and forming a drain region in contact with the second sidewall and the second top surface of the second portion of the first oxide semiconductor layer.

Example 2 the method of example 1, further comprising forming a fin field effect transistor (FinFET) on a semiconductor substrate, wherein the first dielectric layer overlies the semiconductor substrate and the FinFET.

Example 3. The method of example 2, wherein the first thin film omega transistor overlaps the FinFET.

Example 4 the method of example 2, wherein the first thin film omega transistor and the FinFET have opposite conductivity types, and the method further comprises: the first thin film omega transistor and the FinFET are electrically interconnected to form a complementary device.

Example 5 the method of example 1, wherein each of the source region and the drain region comprises: an additional oxide semiconductor layer; and a metal layer on the additional oxide semiconductor layer.

Example 6 the method of example 5, wherein forming the source region and the drain region comprises: forming a second dielectric layer over the fin structure; forming a source opening and a drain opening exposing the first portion and the second portion of the first oxide semiconductor layer, respectively; depositing the additional oxide semiconductor layer extending into the source opening and the drain opening; and depositing the metal layer on the additional oxide semiconductor layer.

Example 7. The method of example 5, wherein the additional oxide semiconductor layer has a higher conductivity value than the first oxide semiconductor layer.

Example 8 the method of example 5, wherein both the first oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher atomic percent of indium than the first oxide semiconductor layer.

Example 9. The method of example 1, further comprising: forming a second thin film omega transistor next to the first thin film omega transistor, wherein the second thin film omega transistor comprises a second gate dielectric and a second oxide semiconductor layer on the second gate dielectric, wherein the first thin film omega transistor and the second thin film omega transistor are discrete transistors electrically and signally disconnected from each other, and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are part of a continuous oxide semiconductor layer.

Example 10. The method of example 1, further comprising: forming a second thin film omega transistor next to the first thin film omega transistor, wherein the second thin film omega transistor comprises a second gate dielectric and a second oxide semiconductor layer, wherein the first thin film omega transistor and the second thin film omega transistor are discrete transistors electrically and signally disconnected from each other, and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are separated from each other by an etch stop layer and an additional dielectric layer.

Example 11 the method of example 10, wherein the first gate dielectric and the second gate dielectric are part of a continuous dielectric layer.

Example 12. A semiconductor structure, comprising: a first dielectric layer; and a thin film omega transistor comprising: a gate fin over the first dielectric layer; a gate dielectric on sidewalls and a top surface of the gate fin; an oxide semiconductor layer over the gate dielectric; a source region contacting the first sidewall and the first top surface of the first portion of the oxide semiconductor layer; and a drain region contacting the second sidewall and the second top surface of the second portion of the oxide semiconductor layer; an etch stop layer over and contacting the oxide semiconductor layer; and a second dielectric layer over the etch stop layer, wherein the source region and the drain region are in the etch stop layer and the second dielectric layer.

Example 13. The structure of example 12, further comprising: a fin field effect transistor (FinFET) on a semiconductor substrate, wherein the first dielectric layer is over the semiconductor substrate and FinFET, and wherein the thin film omega transistor overlaps the FinFET.

Example 14 the structure of example 13, wherein the thin film omega transistor and the FinFET have opposite conductivity types, and the structure further comprises: metal lines and contact plugs electrically interconnect the thin film omega transistors and the finfets to form complementary devices.

Example 15 the structure of example 12, wherein each of the source region and the drain region comprises: an additional oxide semiconductor layer having a U-shaped cross-sectional shape; and a metal layer between opposite sidewall portions of the additional oxide semiconductor layer.

Example 16 the structure of example 15, wherein the additional oxide semiconductor layer has a higher conductivity value than the oxide semiconductor layer.

Example 17 the structure of example 15, wherein both the oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher atomic percent of indium than the oxide semiconductor layer.

Example 18 a semiconductor structure, comprising: a first dielectric layer; a thin film omega transistor comprising: a conductive fin protruding above a top surface of the first dielectric layer; a gate dielectric on the conductive fin; an oxide semiconductor layer on the gate dielectric, wherein the oxide semiconductor layer has a substantially omega-shaped cross-sectional shape; a source region contacting a first portion of the oxide semiconductor layer; and a drain region contacting a second portion of the oxide semiconductor layer; and a dielectric layer over and contacting a third portion of the oxide semiconductor layer, wherein the third portion is between and interconnects the first and second portions.

Example 19 the structure of example 18, wherein the source region comprises: an additional oxide semiconductor layer including: a bottom portion over and contacting the oxide semiconductor layer; and a sidewall portion above and connected to an opposite end of the bottom portion; and a metal region over the bottom portion and between the sidewall portions.

Example 20 the structure of example 18, wherein the oxide semiconductor layer comprises: a first sub-layer having a first conductivity value; and a second sub-layer over the first sub-layer, wherein the second sub-layer has a second conductivity value that is higher than the first conductivity value.

Claims

1. A method for forming a semiconductor structure, comprising:

forming a first thin film omega transistor comprising:

forming a gate fin over the first dielectric layer;

forming a first gate dielectric on sidewalls and a top surface of the gate fin;

depositing a first oxide semiconductor layer over the first gate dielectric, wherein the gate fin, the first gate dielectric, and the first oxide semiconductor layer together form a fin structure;

Forming a source region in contact with a first sidewall and a first top surface of a first portion of the first oxide semiconductor layer; and

a drain region is formed in contact with a second sidewall and a second top surface of the second portion of the first oxide semiconductor layer.

2. The method of claim 1, further comprising forming a fin field effect transistor (FinFET) on a semiconductor substrate, wherein the first dielectric layer overlies the semiconductor substrate and the FinFET.

3. The method of claim 2, wherein the first thin film omega transistor overlaps the FinFET.

4. The method of claim 2, wherein the first thin film omega transistor and the FinFET have opposite conductivity types, and the method further comprises:

the first thin film omega transistor and the FinFET are electrically interconnected to form a complementary device.

5. The method of claim 1, wherein each of the source region and the drain region comprises:

an additional oxide semiconductor layer; and

and a metal layer on the additional oxide semiconductor layer.

6. The method of claim 5, wherein forming the source region and the drain region comprises:

Forming a second dielectric layer over the fin structure;

forming a source opening and a drain opening exposing the first portion and the second portion of the first oxide semiconductor layer, respectively;

depositing the additional oxide semiconductor layer extending into the source opening and the drain opening; and

the metal layer is deposited on the additional oxide semiconductor layer.

7. The method according to claim 5, wherein the additional oxide semiconductor layer has a higher conductivity value than the first oxide semiconductor layer.

8. The method according to claim 5, wherein both the first oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher atomic percentage of indium than the first oxide semiconductor layer.

9. A semiconductor structure, comprising:

a first dielectric layer; and

a thin film omega transistor comprising:

a gate fin over the first dielectric layer;

a gate dielectric on sidewalls and a top surface of the gate fin;

an oxide semiconductor layer over the gate dielectric;

A source region contacting the first sidewall and the first top surface of the first portion of the oxide semiconductor layer; and

a drain region contacting the second sidewall and the second top surface of the second portion of the oxide semiconductor layer;

an etch stop layer over and contacting the oxide semiconductor layer; and

a second dielectric layer over the etch stop layer, wherein the source region and the drain region are in the etch stop layer and the second dielectric layer.

10. A semiconductor structure, comprising:

a first dielectric layer;

a thin film omega transistor comprising:

a conductive fin protruding above a top surface of the first dielectric layer;

a gate dielectric on the conductive fin;

an oxide semiconductor layer on the gate dielectric, wherein the oxide semiconductor layer has a substantially omega-shaped cross-sectional shape;

a source region contacting a first portion of the oxide semiconductor layer; and

a drain region contacting a second portion of the oxide semiconductor layer; and

a dielectric layer over and contacting a third portion of the oxide semiconductor layer, wherein the third portion is between and interconnects the first and second portions.