CN116798465A - Method of operating a memory device and memory device - Google Patents

Abstract

There is provided a method of operating a storage device, comprising: the output node of a cell of a memory device is precharged based on an activation input of the cell. A memory device is provided that includes a precharge circuit configured to precharge an output node of a cell of the memory device based on an activation input for the cell. By using the technical scheme, the power consumption can be reduced.

Description

Method of operating a memory device and memory device

Technical Field

The application relates to the technical field of circuits, in particular to a precharge circuit.

Background

In conventional computing devices, the memory function blocks are separate from the processor function blocks. Data is retrieved from memory to perform operations in the processor functional block.

A computer-in-memory (CIM) device is a device that can perform operations (e.g., operations) in memory. Such an architecture may have the advantage of increased speed or reduced power consumption. One example of an application of a CIM device is to implement a neural network (neural network). Neural networks widely use multiply-accumulate operations (multiply accumulate operation), in which multiple inputs are multiplied by multiple filter weights, and then the multiple products are summed. The CIM device may include hardware for performing multiply and accumulate operations and a memory unit for storing filter weights.

Disclosure of Invention

Some aspects relate to a method of operating a memory device, the method including precharging an output node of a cell of the memory device based on an activation input (activation input) of the cell.

Some aspects relate to a memory device including a precharge circuit configured to precharge an output node of a cell of the memory device based on an activation input of the cell.

The application precharges the output node of the unit based on the activation input of the unit of the storage device, thereby reducing the power consumption.

The foregoing summary is provided by way of example and is not intended to be limiting.

Drawings

The figures are not drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing.

Fig. 1 depicts a high-level block diagram of a CIM device having an array of CIM cells arranged in rows (row) and columns (column).

Fig. 2 is a block diagram showing functional circuit blocks of a CIM unit and functional circuit blocks that provide signals to the CIM unit.

Fig. 3 shows additional details of one example of a CIM unit, wherein the calculation circuitry is configured to perform multiplication of input a with a value W stored in the storage unit.

Fig. 4A-4C illustrate an embodiment for performing a precharge based on an activation input.

Fig. 5A-5C illustrate an embodiment for performing a precharge based on an activation input.

Fig. 6 shows that CIM unit 1 may have a plurality of memory cells storing respective weights W and a demultiplexer 12 providing input a to transistor gates of selected multiplication paths corresponding to selected weights W.

Fig. 7 illustrates an example of precharge logic including a pulse generator configured to generate pulses to initiate precharging in response to a change in any one or more of a plurality of input signals.

Detailed Description

The apparatus and techniques described herein allow for reduced power consumption in a memory array due to precharge operations. The inventors have recognized that the conventional technique of precharging the output node of a cell may result in frequent switching of a precharge device (precharge device) connected to the output node, resulting in high power consumption due to frequent charging and discharging of the gate capacitance of the precharge device. The power consumption can be reduced by switching the precharge device infrequently. In some embodiments, a precharge operation of a memory cell may be triggered by an activation input corresponding to the memory cell. Because the activation signal changes value relatively infrequently, the precharge device can be switched infrequently, and the power consumption caused by precharge can be reduced. Such techniques may be used in CIM devices or other devices having memory arrays.

Fig. 1 depicts a high-level block diagram of a CIM device 10, the device 10 having an array of CIM cells 1 arranged in rows and columns. CIM device 10 may have any number of rows and columns. Each CIM unit 1 has at least one memory cell and associated calculation circuitry, as discussed further below. The output nodes of the computation circuitry need to be precharged before the computation operation is performed.

Fig. 2 is a block diagram illustrating functional circuit blocks of the CIM unit 1 according to some embodiments. The CIM unit 1 includes a memory unit 2, a calculation circuit 3 that performs calculation based on an activation input a and a value W stored in the memory unit, and a precharge device 4 that precharges an output node of the calculation circuit 3. The precharge logic 5 may control the precharge device 4 to precharge the output node 7 of the calculation circuit 3 at a suitable timing (timing). In some embodiments, the precharge device 4 may be turned on (turned on) in response to the activation input a. After the precharge operation, the precharge device 4 is turned off (non-conductive). When the CIM device 10 performs a calculation operation, the calculation circuit 3 is ready to perform the calculation using the input a and the value W stored in the storage unit 2. When the CIM device 10 controls the calculation circuit 3 to perform a calculation operation, the calculation result is supplied to the output node 7. The memory cell 2 may be any suitable type of memory cell, such as a static random access memory (static random access memory, SRAM) cell or a ternary content addressable memory (ternary content addressable memory, TCAM) cell.

Fig. 3 illustrates additional details of one example of a CIM unit according to some embodiments. In this embodiment, the calculation circuit 3a includes a multiplication path including: the first transistor comprises a control end, a first end and a second end, wherein the control end of the first transistor receives a value W, the second end of the first transistor is coupled with the ground, the first end of the first transistor is coupled with the second end of the second transistor, the second transistor comprises a control end, the first end and the second end, the control end of the second transistor receives an activation input A, and the first end of the second transistor is coupled with a node MB. The precharge device 4a may be a PMOS transistor, which includes a control terminal receiving the signal PRCHG, a first terminal coupled to the power rail 8, and a second terminal coupled to the node MB. The input of the inverter 11 is coupled to the node MB, the weak PMOS device comprises a control terminal, a first terminal and a second terminal, the control terminal of the weak PMOS device is coupled to the output of the inverter 11, the first terminal of the weak PMOS device is coupled to the power rail 8, and the second terminal is coupled to the node MB. In this example, the calculation circuit 3a is configured to perform a multiplication of the activation input a with the value W stored in the memory unit 2. Precharge logic 5 provides a signal PRCHG, also shown as node MB, for controlling precharge device 4a to precharge output node 7 a. The precharge device 4a may be a PMOS transistor which is controlled to perform a precharge operation in response to the signal PRCHG having a low logic level. During a precharge operation, the precharge device 4a is turned on (conductive), and the output node 7a is connected to the power supply rail 8. The CIM unit 1 may include an inverter 11, the inverter 11 inverting the signal MB of the node MB to generate the signal M. The signal M may be provided to an adder tree (adder tree) to perform the addition portion of the multiply-accumulate computation. When performing a calculation operation, the input a is multiplied by the value W stored in the storage unit 2. The values a and W may be digital values. If both A and W are logic high, the output node 7a is pulled down to ground (logic low). If either a or W or both are at a logic low level, the output node 7a is not pulled down to ground, but remains at the precharge voltage (in this example, at a logic high level). CIM unit 1 may include circuitry to hold MB at a high logic level when the precharge device is off and either a or W or both have a low logic level: in this example, the weak PMOS device performs this function.

Fig. 4A shows a circuit diagram of an embodiment of a CIM cell, wherein the gate of the precharge device 4A is connected to the activation input a. As shown in the truth table (trunk table) of fig. 4B, when the active input a has a logical value of 0, the precharge device 4a turns on and precharges the node MB to the voltage of the power supply rail 8. Fig. 4C shows the timing of activation input a with a low logic value that results in MB being precharged to a high logic value. When a computing operation is performed and both a and W have high logic values, node MB is pulled down to a low logic value.

Fig. 5A shows a schematic diagram of another embodiment, in which precharge logic 5A generates precharge signal PRCHG in response to activation input a. The precharge logic 5a includes a pulse generator 51 and other logic circuitry. The pulse generator 51 receives the pulse signal CLK and the enable signal EN, and generates a pulse signal PCLK. The other logic circuits comprise an inverter and an AND gate, wherein the inverter receives the pulse signal PCLK and outputs an inverted signal of the pulse signal PCLK, one input end of the AND gate receives the inverted signal of the pulse signal PCLK, the other input end of the AND gate receives the activation input A, and the output end of the AND gate outputs the precharge signal PRCHG. Using the precharge logic 5a, the precharge operation may be initiated by a logic signal a having a low logic level or a pulse signal PCLK generated in response to the enable signal EN. Fig. 5C shows the structure of the pulse generator 51, and those skilled in the art will understand that the pulse generator 51 may have other structures, and is not limited to the structure shown in fig. 5C. Fig. 5B shows a timing chart of the signal shown in fig. 5A, and the signal PEN is an internal signal of the pulse generator 51. In some embodiments, the enable signal EN may transition from a low logic level to a high logic level when a computing operation is enabled in the CIM device 10. In response, the pulse generator 51 may generate a pulse that causes an initial precharge operation to be performed. Specifically, referring to fig. 5B, when EN changes from low to high, the Edge Detector (Edge Detector) generates a high signal PEN. MST LAT is a negative level sensitive latch and SLV LAT is a positive level sensitive latch. When EN changes from low to high and CLK is low, MST LAT is output high. At this time, the SLV LAT is disabled, so it maintains the previous low value, which is inverted by the Inverter (INV). Thus, both inputs to the AND gate are high, and PEN is high. If the D input of the pulse generating circuit (Pulsegen) is high before the rising edge of CLK, it generates a pulse. Thus, if EN changes from low to high, a PCLK pulse is generated. If EN goes from high to low, PEN is low, so PCLK is not generated.

Fig. 6 shows that the CIM unit may have a plurality of memory cells for storing respective weights W and a Demultiplexer (DEMUX) 12 for providing an input a to the transistor gates of a selected multiplication path (multiplexer path) corresponding to a selected weight W. Selection signal FA [ u:0]Is the selection signal of the demultiplexer which decides which filter weight W to select and applies the activation signal a to the gate of the transistor RWL corresponding to the selected weight W. Wherein FA [ u:0]Is the u+1 bit filter address input, W in the figure ⁰ ,W ¹ ，…W ^R-1 ,W ^R Representing weights, r=2 ^(u+1) -1. RWL [ 0] in the figure]，RWL[1]，…RWL[R-1]，RWL[R]Representing a transistor.

In some embodiments, the precharge operation may be triggered in response to a change in the selection signal FA [ u:0]. For this, the enable signal EN of the precharge logic 5a may be the selection signal FA [ u:0]. Alternatively or additionally, the precharge operation may be triggered in response to a change in any of a plurality of signals, such as an enable signal EN that switches to a logic high level when an enable (enable) calculation operation is enabled in CIM device 10, and FA [ u:0]. The precharge logic 5 may activate a precharge operation in response to a change in any such signal. Fig. 7 shows an example of such a precharge logic, such as precharge logic 5b, which includes a pulse generator 71 configured to generate a pulse to initiate a precharge in response to a change in the enable signal EN or the select signal FA [ u:0]. Wherein the pulse generator 71 generates a pulse when any bit of FA u 0 goes from low to high or from high to low.

Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term).

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," or "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

By "coupled" or "connected" is meant the interconnection of circuit elements or signals directly or indirectly through intervening elements.

The terms "about," "substantially," and "approximately" may be used in some embodiments to mean within ±20% of the target value, in some embodiments within ±10% of the target value, in some embodiments within ±5% of the target value, and in some embodiments within ±2% of the target value. The terms "about," "substantially," and "approximately" may include target values.

Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while maintaining the teachings of the present application. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (23)

1. A method of operating a memory device, the method comprising:

the output node of a cell of a memory device is precharged based on an activation input of the cell.

2. The method of claim 1, wherein the precharging is performed when the activation input has a first logic level.

3. The method of claim 1, wherein the precharging is performed by coupling the output node to a power rail using a transistor.

4. A method according to claim 3, wherein the transistor comprises a PMOS transistor.

5. The method of claim 1, wherein the storage device is a memory-integrated CIM device, and the unit includes a storage unit and a computing circuit configured to perform a computation based on the activation input and a value stored in the storage unit.

6. The method of claim 5, wherein the calculating comprises multiplying.

7. The method of claim 1, further comprising precharging the output node in response to an enable signal.

8. The method of claim 7, further comprising generating a pulse in response to a change in the enable signal.

9. The method of claim 1, wherein the unit stores a plurality of filter weights selectable based on a selection signal, and further comprising precharging the output node in response to a change in the selection signal.

10. The method of claim 1, wherein the cells comprise static random access memory, SRAM, cells and/or ternary content addressable memory, TCAM, cells.

11. A memory device, comprising:

the precharge circuit is configured to precharge an output node of a cell of the memory device based on an activation input of the cell.

12. The memory device of claim 11, wherein the precharge circuit precharges the output node when the activation input has a first logic level.

13. The memory device of claim 11, wherein the precharge circuit comprises a transistor configured to couple the output node to a power supply rail.

14. The memory device of claim 13, wherein the transistor comprises a PMOS transistor.

15. The storage device of claim 11, wherein the storage device is a memory-integrated CIM device, and the unit includes a storage unit and a computing circuit configured to perform a calculation based on the activation input and a value stored in the storage unit.

16. The storage device of claim 15, wherein the computation comprises multiplication.

17. The memory device of claim 11, wherein the precharge circuit is configured to precharge the output node in response to an enable signal.

18. The memory device of claim 11, wherein the precharge circuit comprises a pulse generator.

19. The memory device of claim 11, wherein the unit stores a plurality of filter weights selectable based on a selection signal, and the precharge circuit is configured to precharge the output node in response to a change in the selection signal.

20. The memory device of claim 11, wherein the cells comprise static random access memory, SRAM, cells and/or ternary content addressable memory, TCAM, cells.

21. The memory device of claim 11, wherein the memory device comprises a precharge circuit, the precharge circuit comprising:

precharge logic responsive to the activation input having a first logic level or responsive to a pulse signal, generating a control signal for controlling a precharge device to precharge the output node;

and the precharge device is used for receiving a control signal and precharging the output node under the control of the control signal.

22. The memory device of claim 11, wherein the pulse signal is generated in response to an enable signal EN or in response to a change in a selection signal, wherein the selection signal is used to select a filter weight.

23. The storage device of claim 22, further comprising: a demultiplexer for providing the activation input to a multiplication path corresponding to the filter weight selected by the selection signal.