CN116798336B - Sub-pixel unit arrangement structure, display, virtual pixel structure and multiplexing method - Google Patents
Sub-pixel unit arrangement structure, display, virtual pixel structure and multiplexing method Download PDFInfo
- Publication number
- CN116798336B CN116798336B CN202311048100.7A CN202311048100A CN116798336B CN 116798336 B CN116798336 B CN 116798336B CN 202311048100 A CN202311048100 A CN 202311048100A CN 116798336 B CN116798336 B CN 116798336B
- Authority
- CN
- China
- Prior art keywords
- sub
- pixel
- unit
- pixel unit
- units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000012545 processing Methods 0.000 claims description 21
- 239000003086 colorant Substances 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 6
- 238000004364 calculation method Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000000872 buffer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010432 diamond Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 208000003464 asthenopia Diseases 0.000 description 1
- 239000007853 buffer solution Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A sub-pixel unit arrangement structure, a display, a virtual pixel structure and a multiplexing method relate to the pixel unit arrangement structure. In order to solve the color cast problem caused by the two inconvergences of the colors in the horizontal, vertical and right-angle directions in the display process of the uniformly distributed sub-pixel display in the prior art, the invention provides the technical scheme as follows: the sub-pixel unit arrangement structure comprises the following structures: a plurality of non-rectangular parallelograms are tightly paved, each parallelogram is used as a video virtual pixel point, and four vertexes of the parallelogram are respectively a sub-pixel unit; each parallelogram comprises three sub-pixel units; in each parallelogram, the sub-pixel units on the vertexes where two opposite obtuse angles are located are the same sub-pixel units; the adjacent two parallelograms share the sub-pixels on the two vertexes, and the adjacent two parallelograms are different parallelograms. The method is suitable for pixel arrangement of various types of display screens.
Description
Technical Field
The invention relates to the technical field of information display, in particular to subpixel arrangement.
Background
As an important information display device, a display screen plays a vital role in modern society. The display screen provides us with visual immersion and information transfer by presenting images, video and text, whether in a home, business or industrial environment. The evolution of display screens can be traced to early Cathode Ray Tube (CRT) technology, and then new technologies such as Liquid Crystal Display (LCD), organic Light Emitting Diode (OLED), and quantum dot display (QLED) have been developed. These innovative techniques allow the display to have higher resolution, higher brightness, and wider color gamut, thereby achieving more realistic and vivid image display effects.
Among various display screen technologies, a quadrilateral arrangement is one of the most common and widely adopted screen layouts. The feature of this layout is that the screen presents a rectangular shape with four edges so that images and video can be presented completely on the screen.
In addition, the quadrilateral arrangement also helps the user to more intuitively understand the content on the screen and perform interactive operations related to the screen. The design of the arrangement mode also enables the user interface to be more consistent and concise, and improves the use convenience of users.
In the application of exploring quadrilateral arrangement, patent document CN107329279a provides an LED display screen, a display device and a display system, which adopt quadrilateral arrangement to solve the problem of poor display effect of the existing 3D display technology. However, when the LED display screen currently existing adopts quadrilateral arrangement, a challenge is encountered, that is, gaps between the light emitting components of different primary colors are different along with the change of different observation angles, and because the light emitting components of different primary colors are not uniformly arranged, each light emitting component cannot obtain multi-directional color mixing, and color cast occurs in the display process.
This situation may lead to visual fatigue, distraction of the user, and thus reduce visual quality and work efficiency. In order to provide a better user experience, it is desirable to address the problem of biasing the bands.
Summarizing, at present, only the LED display screen with quadrilateral arrangement is easy to generate the color cast problem, thereby influencing the user experience.
Disclosure of Invention
In order to solve the problems that in the prior art, in the LED display screen adopting quadrilateral arrangement, gaps among luminous components of different primary colors are different along with the change of different observation angles, and because the luminous components of different primary colors are not uniformly arranged, each luminous component cannot obtain multi-directional color mixing and color cast occurs in the display process, the invention provides the technical scheme that:
the sub-pixel unit arrangement structure comprises:
a plurality of non-rectangular parallelograms are closely laid,
each parallelogram is used as a video pixel point, and four vertexes of the parallelogram are respectively a sub-pixel unit;
the number of the sub-pixel units is three, namely a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit;
each parallelogram comprises three sub-pixel units;
the parallelogram comprises three types, namely two first sub-pixel units, two second sub-pixel units and two third sub-pixel units;
in each parallelogram, the sub-pixel units on the vertexes where two opposite obtuse angles are located are the same sub-pixel units;
the two parallelograms adjacent by the side share the sub-pixels on the two vertexes, and the two parallelograms adjacent by the side are parallelograms of different types.
Further, there is provided a preferred embodiment wherein the parallelogram is diamond-shaped.
Further, a preferred embodiment is provided, wherein the first subpixel unit is red, the second subpixel unit is green, and the third subpixel unit is blue.
Further, a preferred embodiment is provided, wherein the sub-pixel units are all rectangular.
Further, there is provided a preferred embodiment, in the structure, the sub-pixel units in the horizontal direction are in turn: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
Further, there is provided a preferred embodiment, in the structure, the sub-pixel units in the vertical direction are in sequence: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
Based on the same inventive concept, the invention also provides a display, wherein color units in the display are arranged through the sub-pixel unit arrangement structure.
Based on the same inventive concept, the invention also provides a virtual pixel structure, wherein virtual pixels in the structure are arranged through the sub-pixel unit arrangement structure.
Based on the same inventive concept, the invention also provides a sub-pixel multiplexing method, wherein the method is applied to the control of the virtual pixel structure, and the data processing in the method adopts a sliding window mode.
Further, there is provided a preferred embodiment wherein the arrangement is such that longitudinally adjacent first, third and second sub-pixel units are combined as one pixel output data; the data processing is realized through FIFO for caching data corresponding to three lines of pixels and eight registers for sliding storage.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the sub-pixel unit arrangement structure provided by the invention is a brand-new sub-pixel unit arrangement structure, which is used for solving the technical problems that the color cast phenomenon caused by the proper color mixing effect cannot be obtained and the physical health and the working efficiency of a user are affected, and the sub-pixel unit arrangement structure is used for replacing the position relation among rectangular pixels through diamonds, so that each pixel is adjacent to six other pixels and has the same distance, thereby obtaining better color mixing effect and leading the visual effect of an image formed by the pixels to be more symmetrical.
According to the sub-pixel unit arrangement structure provided by the invention, six other pixels are surrounded around each sub-pixel, and the six other pixels provide a color mixing effect for the sub-pixel. This arrangement can effectively reduce the occurrence of color cast at the high frequency information location because the surrounding six pixels will mix the colors of the sub-pixels, making the color transition smoother and more accurate.
The sub-pixel unit arrangement structure provided by the invention can provide better color balance and accuracy by adding more color mixing contributions of other pixels around the sub-pixels. In this way, the color expression of the high-frequency information positions such as straight lines, edges and the like in the image can be more uniform and natural, and the problem of image artifact or incoherence caused by color deviation is avoided.
According to the sub-pixel unit arrangement structure provided by the invention, six adjacent pixels are added around each sub-pixel, so that more color value selections are provided to realize smooth gradual transition. This reduces the occurrence of jagged edges (also known as aliasing) and makes the boundaries of the image smoother and more natural.
The method is suitable for pixel arrangement of various types of display screens.
Drawings
FIG. 1 is a schematic diagram of a subpixel unit arrangement according to one embodiment;
fig. 2 is a schematic diagram of an arrangement manner and a relation between video source pixels in a sub-pixel unit arrangement structure according to a ninth embodiment, including a multiplexing manner and a data output manner;
fig. 3 is a schematic diagram of signal trend during processing of the first three rows of video source data in the sub-pixel multiplexing method according to the ninth embodiment;
fig. 4 is a schematic diagram of signal trend in a data processing process after the fourth line of video source data in the subpixel multiplexing method according to the ninth embodiment.
Detailed Description
In order to make the advantages and benefits of the technical solution provided by the present invention more apparent, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, in which:
in a first embodiment, referring to fig. 1, the present embodiment provides a subpixel unit arrangement structure, where the structure is:
a plurality of non-rectangular parallelograms are closely laid,
each parallelogram is used as a video pixel point, and four vertexes of the parallelogram are respectively a sub-pixel unit;
the number of the sub-pixel units is three, namely a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit;
each parallelogram comprises three sub-pixel units;
the parallelogram comprises three types, namely two first sub-pixel units, two second sub-pixel units and two third sub-pixel units;
specifically, the parallelogram includes three types, including two first sub-pixel units, one second sub-pixel unit, one third sub-pixel unit, two second sub-pixel units, one first sub-pixel unit, one third sub-pixel unit, two third sub-pixel units, one first sub-pixel unit, and one second sub-pixel unit;
in each parallelogram, the sub-pixel units on the vertexes where two opposite obtuse angles are located are the same sub-pixel units;
the two parallelograms adjacent by the side share the sub-pixels on the two vertexes, and the two parallelograms adjacent by the side are parallelograms of different types.
Specifically, in one of the parallelograms, the subpixel at the upper left corner is the first subpixel unit, and the subpixel at the lower right corner is the second subpixel unit.
The second embodiment and the present embodiment are further defined on the arrangement structure of the sub-pixel unit provided in the first embodiment, where the parallelogram is a rhombus.
In a third embodiment, the arrangement structure of the sub-pixel units provided in the first embodiment is further defined, wherein the first sub-pixel unit is red, the second sub-pixel unit is green, and the third sub-pixel unit is blue.
In the fourth embodiment, the arrangement structure of the sub-pixel units provided in the first embodiment is further limited, and the sub-pixel units are rectangular.
In a fifth embodiment, the present embodiment is further defined on the arrangement structure of the sub-pixel unit provided in the first embodiment, where the sub-pixel units in the horizontal direction are sequentially: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
Specifically, the sub-pixel units in the horizontal direction, in one of the cycle groups, are in turn: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
In a sixth embodiment, the present embodiment is further defined on the arrangement structure of the sub-pixel unit provided in the first embodiment, where the sub-pixel units in the vertical direction are sequentially: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
Specifically, the sub-pixel units in the vertical direction, in one of the cycle groups, are in sequence: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
Embodiment seven, this embodiment provides a display in which the color cells are arranged by the subpixel cell arrangement provided in any one of embodiments one to six.
An eighth embodiment provides a virtual pixel structure in which virtual pixels are arranged by the subpixel unit arrangement structure provided in any one of the first to sixth embodiments.
The ninth embodiment and the present embodiment provide a subpixel multiplexing method, where the method is applied to the control of the virtual pixel structure provided in the eighth embodiment, and the data processing in the method uses a sliding window mode.
Specific:
for the arrangement of the sub-pixel units provided in this embodiment, a multiplexing manner is provided, and other multiplexing manners must exist, where only such multiplexing manner is taken to exemplify the implementation of the control method:
fig. 2 shows a video source pixel point data structure represented by diamond shaped cells. Each diamond represents a video source pixel point, and the numbers in the diamond represent row and column information of video source data. For example, numeral 23 represents pixel data of the second row and the third column of each frame of data of the video source.
The data is output in the form of rounded rectangles. The vertical combination of three sub-pixels of different colors forms a pixel combination as output. For data processing and sliding window operations in the pixel data processing module in the control system, three FIFOs are required to buffer the first three rows of data of the current row and 8 data registers are required to buffer the data of multiple rows and columns.
The data processing module can realize sliding window processing of the video data so as to meet specific processing requirements and algorithm requirements. By using FIFOs and data registers, multiple lines of data can be conveniently cached and accessed to enable computation and processing of sliding window operations
As shown in fig. 3, one data buffer system and one data processing system are required in the pixel multiplication data processing. The processing procedure is as follows:
when the first line of data arrives, the line of pixel data is stored into FIFO1.
When the second line of data arrives, the line of pixel data is stored into FIFO 2.
When the third line data arrives, the pixel data is written into the FIFO3 and the register 8 at the same time in each pixel clock period, and the pixel data of the register 8 is stored into the register 7.
At the same time, the read enable of FIFO1 and FIFO2 is pulled high, and the pixel data of FIFO2 (second line) is read into register 6 while writing FIFO1. In addition, the data in the register 6 is stored in the register 5, the pixel data of the FIFO1 (first line) is stored in the register 4, and the data in the register 4 is stored in the register 3.
At the time when the third data comes, the registers 8, 7, 6, 5, 4, 3 all contain valid pixel data from the second pixel clock period. From this point on, the calculation and assignment operations are performed every clock cycle. The calculation mode adopts a multiplexing method. For example, for a second subpixel point G of a second output subpixel combination, it requires the value of the green subpixel in registers 6, 5, 4, 3. Therefore, the green subpixel values in these registers are fetched, averaged, and the result is assigned to the green subpixel of the output data. The way in which other subpixel output values are calculated is so forth.
The need for pixel multiplication data processing can be achieved by buffering and sliding window operation of the input data, and data storage and multiplexing calculations using registers.
According to fig. 4, when the next data of each line comes, the following operations are performed:
the data is written into FIFO3 and simultaneously assigned to register 8. The pixel data of register 8 is then assigned to register 7.
When the data of FIFO3 and FIFO2 are read, they are assigned to register 6 and register 4, respectively. At the same time, the read data is written into FIFO2 and FIFO1 to realize the sliding window operation of the data.
When data arrives except for the 3 n-th row (n is a positive integer), no calculation operation is performed, no output assignment operation is performed, and only a shift register operation of the data is performed.
Through the operation flow, the sliding window processing of the data can be realized. Every time the 3 n-th line data comes, the calculation operation is performed, and the other line data only performs the shift register processing of the data.
When data output is performed, some sub-pixel combinations are arranged in a mode that the sub-pixel combinations are not arranged according to the standard RGB sequence. Thus, internal sub-pixel data location exchange is required for these out-of-order sub-pixel combinations prior to output.
The calculation operation is performed only on the 3 n-th line, that is, when video source data of other lines arrives, there is no data output although there is data input. Thus, the output data is sparse, and there is only data output every second line. In order to transfer these sparse data to the drive system for display, an off-chip frame buffer operation is required. The SDRAM may be used as an off-chip buffer to store sparse data into the SDRAM. These data are then densely read using VGA standard video timing and sent to the drive system to drive the display operation.
Through the operation flow, sparse data are densely stored, and SDRAM is used as a buffer to realize the storage and reading operation of the sparse data. This may ultimately transmit the data to the drive system for display.
In a tenth embodiment, the present embodiment is further defined by the sub-pixel multiplexing method provided in the ninth embodiment, where in the arrangement structure, the first sub-pixel unit, the third sub-pixel unit, and the second sub-pixel unit that are longitudinally adjacent are combined as one output pixel; the data processing is realized through FIFO for caching data corresponding to three lines of pixels and eight registers for sliding storage.
The technical solution provided by the present invention is described in further detail through several specific embodiments, so as to highlight the advantages and benefits of the technical solution provided by the present invention, however, the above specific embodiments are not intended to be limiting, and any reasonable modification and improvement, combination of embodiments, equivalent substitution, etc. of the present invention based on the spirit and principle of the present invention should be included in the scope of protection of the present invention.
In the description of the present invention, only the preferred embodiments of the present invention are described, and the scope of the claims of the present invention should not be limited thereby; furthermore, the descriptions of the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "N" means at least two, for example, two, three, etc., unless specifically defined otherwise. Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more N executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention. Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or N wires, a portable computer cartridge (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory. It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
Claims (10)
1. The subpixel unit arrangement structure is characterized in that:
a plurality of non-rectangular parallelograms are closely laid,
each parallelogram is used as a video pixel point, and four vertexes of the parallelogram are respectively a sub-pixel unit;
the number of the sub-pixel units is three, namely a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit;
each parallelogram comprises three sub-pixel units;
the parallelogram comprises three types, namely two first sub-pixel units, two second sub-pixel units and two third sub-pixel units;
in each parallelogram, the sub-pixel units on the vertexes where two opposite obtuse angles are located are the same sub-pixel units;
the two parallelograms adjacent by the side share the sub-pixels on the two vertexes, and the two parallelograms adjacent by the side are parallelograms of different types;
in the sub-pixel unit arrangement structure, at least one sub-pixel exists, six sub-pixels surround the periphery of the sub-pixel, and the six sub-pixels are respectively two first sub-pixel units, two second sub-pixel units and two third sub-pixel units.
2. The subpixel unit arrangement according to claim 1, wherein the parallelogram is diamond-shaped.
3. The subpixel unit arrangement of claim 1, wherein the first subpixel unit is red, the second subpixel unit is green, and the third subpixel unit is blue.
4. The subpixel unit arrangement according to claim 1, wherein the subpixel units are each rectangular.
5. The arrangement structure of sub-pixel units according to claim 1, wherein in the structure, the sub-pixel units in the horizontal direction are in turn: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
6. The arrangement structure of sub-pixel units according to claim 1, wherein in the structure, the sub-pixel units in the vertical direction are in sequence: the pixel array comprises a first sub-pixel unit, a third sub-pixel unit and a second sub-pixel unit.
7. A display, characterized in that the color cells in the display are arranged by a subpixel cell arrangement as claimed in any one of claims 1-6.
8. A virtual pixel structure, wherein virtual pixels in the structure are arranged by a subpixel unit arrangement according to any one of claims 1-6.
9. A sub-pixel multiplexing method, wherein the method is applied to the control of the virtual pixel structure as claimed in claim 8, and the data processing in the method adopts a sliding window mode.
10. The sub-pixel multiplexing method according to claim 9, wherein in the arrangement structure, longitudinally adjacent first sub-pixel unit, third sub-pixel unit, and second sub-pixel unit are combined as one pixel output data; the data processing is realized through FIFO for caching data corresponding to three lines of pixels and eight registers for sliding storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311048100.7A CN116798336B (en) | 2023-08-21 | 2023-08-21 | Sub-pixel unit arrangement structure, display, virtual pixel structure and multiplexing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311048100.7A CN116798336B (en) | 2023-08-21 | 2023-08-21 | Sub-pixel unit arrangement structure, display, virtual pixel structure and multiplexing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116798336A CN116798336A (en) | 2023-09-22 |
| CN116798336B true CN116798336B (en) | 2023-11-14 |
Family
ID=88046200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311048100.7A Active CN116798336B (en) | 2023-08-21 | 2023-08-21 | Sub-pixel unit arrangement structure, display, virtual pixel structure and multiplexing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116798336B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117058985B (en) * | 2023-10-12 | 2024-01-05 | 长春希达电子技术有限公司 | Arrangement structure, virtual multiplexing mode, control method and display device |
| CN117133201B (en) * | 2023-10-19 | 2024-02-02 | 长春希达电子技术有限公司 | Arrangement structure, virtual pixel multiplexing mode and control method thereof |
Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978920A (en) * | 2015-07-24 | 2015-10-14 | 京东方科技集团股份有限公司 | Pixel array, display device and display method thereof |
| CN106445247A (en) * | 2016-12-01 | 2017-02-22 | 合肥京东方光电科技有限公司 | Touch panel and display device |
| CN107978616A (en) * | 2016-10-21 | 2018-05-01 | 上海和辉光电有限公司 | A kind of OLED pixel arrangement architecture and display methods |
| CN108493224A (en) * | 2018-04-20 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of pixel arrangement structure and display panel, display device, mask plate |
| CN108762571A (en) * | 2018-05-31 | 2018-11-06 | 上海天马微电子有限公司 | Touch-control display panel and touch control display apparatus |
| CN110620135A (en) * | 2019-09-30 | 2019-12-27 | 武汉天马微电子有限公司 | Display panel and display device |
| CN110767733A (en) * | 2019-10-31 | 2020-02-07 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111292673A (en) * | 2020-04-03 | 2020-06-16 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN112802880A (en) * | 2021-01-19 | 2021-05-14 | 维沃移动通信有限公司 | Display substrate, display panel and electronic device |
| CN113451530A (en) * | 2021-06-29 | 2021-09-28 | 京东方科技集团股份有限公司 | Polarizing structure, preparation method thereof, touch display panel and display device |
| CN113471266A (en) * | 2021-06-30 | 2021-10-01 | 昆山国显光电有限公司 | Pixel arrangement structure, mask assembly and display panel |
| CN113471271A (en) * | 2021-07-01 | 2021-10-01 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113964169A (en) * | 2021-11-22 | 2022-01-21 | 福建华佳彩有限公司 | OLED pixel arrangement structure, mask plate and display thereof |
| CN114512521A (en) * | 2022-02-10 | 2022-05-17 | 合肥维信诺科技有限公司 | Pixel arrangement structure, display panel and display device |
| CN114846536A (en) * | 2020-12-01 | 2022-08-02 | 京东方科技集团股份有限公司 | Data processing method and device and display device |
| CN114937685A (en) * | 2022-06-17 | 2022-08-23 | 合肥维信诺科技有限公司 | Pixel arrangement structure, display substrate and mask set |
| CN115249728A (en) * | 2021-04-28 | 2022-10-28 | 上海和辉光电股份有限公司 | Pixel array, evaporation device and display panel |
| WO2022262343A1 (en) * | 2021-06-17 | 2022-12-22 | 合肥维信诺科技有限公司 | Pixel arrangement structure, mask assembly, and display panel |
| CN219203164U (en) * | 2022-12-30 | 2023-06-16 | 西安诺瓦星云科技股份有限公司 | LED pixel arrangement structure and LED display screen |
| CN219350232U (en) * | 2022-12-30 | 2023-07-14 | 西安诺瓦星云科技股份有限公司 | LED pixel arrangement structure and LED display screen |
| CN116453455A (en) * | 2023-06-14 | 2023-07-18 | 长春希达电子技术有限公司 | Pixel multiplexing method, data transmission system and display screen control system and method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230017360A (en) * | 2020-07-01 | 2023-02-03 | 쿤산 고-비젼녹스 옵토-일렉트로닉스 씨오., 엘티디. | Pixel arrangement structure, display panel, and display device |
-
2023
- 2023-08-21 CN CN202311048100.7A patent/CN116798336B/en active Active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978920A (en) * | 2015-07-24 | 2015-10-14 | 京东方科技集团股份有限公司 | Pixel array, display device and display method thereof |
| CN107978616A (en) * | 2016-10-21 | 2018-05-01 | 上海和辉光电有限公司 | A kind of OLED pixel arrangement architecture and display methods |
| CN106445247A (en) * | 2016-12-01 | 2017-02-22 | 合肥京东方光电科技有限公司 | Touch panel and display device |
| CN108493224A (en) * | 2018-04-20 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of pixel arrangement structure and display panel, display device, mask plate |
| CN108762571A (en) * | 2018-05-31 | 2018-11-06 | 上海天马微电子有限公司 | Touch-control display panel and touch control display apparatus |
| CN110620135A (en) * | 2019-09-30 | 2019-12-27 | 武汉天马微电子有限公司 | Display panel and display device |
| CN110767733A (en) * | 2019-10-31 | 2020-02-07 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111292673A (en) * | 2020-04-03 | 2020-06-16 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN114846536A (en) * | 2020-12-01 | 2022-08-02 | 京东方科技集团股份有限公司 | Data processing method and device and display device |
| CN112802880A (en) * | 2021-01-19 | 2021-05-14 | 维沃移动通信有限公司 | Display substrate, display panel and electronic device |
| CN115249728A (en) * | 2021-04-28 | 2022-10-28 | 上海和辉光电股份有限公司 | Pixel array, evaporation device and display panel |
| WO2022262343A1 (en) * | 2021-06-17 | 2022-12-22 | 合肥维信诺科技有限公司 | Pixel arrangement structure, mask assembly, and display panel |
| CN113451530A (en) * | 2021-06-29 | 2021-09-28 | 京东方科技集团股份有限公司 | Polarizing structure, preparation method thereof, touch display panel and display device |
| CN113471266A (en) * | 2021-06-30 | 2021-10-01 | 昆山国显光电有限公司 | Pixel arrangement structure, mask assembly and display panel |
| CN113471271A (en) * | 2021-07-01 | 2021-10-01 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113964169A (en) * | 2021-11-22 | 2022-01-21 | 福建华佳彩有限公司 | OLED pixel arrangement structure, mask plate and display thereof |
| CN114512521A (en) * | 2022-02-10 | 2022-05-17 | 合肥维信诺科技有限公司 | Pixel arrangement structure, display panel and display device |
| CN114937685A (en) * | 2022-06-17 | 2022-08-23 | 合肥维信诺科技有限公司 | Pixel arrangement structure, display substrate and mask set |
| CN219203164U (en) * | 2022-12-30 | 2023-06-16 | 西安诺瓦星云科技股份有限公司 | LED pixel arrangement structure and LED display screen |
| CN219350232U (en) * | 2022-12-30 | 2023-07-14 | 西安诺瓦星云科技股份有限公司 | LED pixel arrangement structure and LED display screen |
| CN116453455A (en) * | 2023-06-14 | 2023-07-18 | 长春希达电子技术有限公司 | Pixel multiplexing method, data transmission system and display screen control system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116798336A (en) | 2023-09-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116798336B (en) | Sub-pixel unit arrangement structure, display, virtual pixel structure and multiplexing method | |
| KR101095635B1 (en) | System and method for improving sub-pixel rendering of imaging data in non-striped display systems | |
| KR101298921B1 (en) | Pre-subpixel rendered image processing in display systems | |
| TWI425485B (en) | Driving method of a display panel | |
| US10937378B2 (en) | Display panel and display method | |
| CN104952412B (en) | The driving method and driving device of liquid crystal panel | |
| WO2015143860A1 (en) | Display method and display panel | |
| KR101340427B1 (en) | Improved memory structures for image processing | |
| JP6609801B2 (en) | Driving method of liquid crystal panel | |
| CN101471063B (en) | Color signal generating device | |
| CN104751821A (en) | Display panel and driving method thereof | |
| CN104900205A (en) | Liquid-crystal panel and drive method therefor | |
| US20190096360A1 (en) | Display method, image processing device, display device, and storage medium | |
| CN114503187B (en) | Method and system for determining overdrive map dependency in a display panel | |
| CN113795879B (en) | Method and system for determining grey scale mapping correlation in display panel | |
| CN115410525B (en) | Sub-pixel addressing method and device, display control system and display screen | |
| US10559241B2 (en) | Display device and method for displaying image using the same | |
| CN106935213B (en) | Low-delay display system and method | |
| KR102582660B1 (en) | Display apparatus and driving method thereof | |
| KR101624085B1 (en) | LED Display that Improves the Resolution of Six Times by Interpolating the Pixels of the 6 Field Divided Express Way | |
| TW201835881A (en) | Sub-pixel rendering method for delta rgbw panel and delta rgbw panel with sub-pixel rendering function | |
| US10573253B2 (en) | Display apparatus with reduced amount of calculation | |
| JP2001343636A (en) | Matrix type color display device | |
| US11386829B2 (en) | Display panel and drive method thereof, and display device | |
| US20170213492A1 (en) | Color unevenness correction device and color unevenness correction method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |