CN116796697A - CDR clock frequency deviation rectifying method, device and storage medium - Google Patents
CDR clock frequency deviation rectifying method, device and storage medium Download PDFInfo
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Abstract
The application discloses a method, a device and a storage medium for correcting a frequency of a CDR clock, wherein the method comprises the following steps: setting a deviation correction judging line between the edge judging line and the data judging line of the CDR eye diagram; determining different areas in the CDR eye diagram according to the setting positions of the edge judging line, the data judging line and the deviation correcting judging line; in the sampling period, acquiring the positions of clock sampling points in a CDR eye diagram, and judging the position sequence of different areas where the clock sampling points appear according to the distribution of the positions; and correcting the phase detector according to the position sequence to obtain a correction result of the phase detector, and controlling the clock sampling point to move according to the correction result. The application can control the CDR clock to move to the correct direction when the clock frequency and the data frequency have frequency difference, so that the clock frequency and the data frequency are basically consistent, and CDR locking is realized.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a method and apparatus for correcting a CDR clock frequency, and a storage medium.
Background
Serdes is simply called SERializer/deseriaalizer, and has the following specific functions: at the transmitting end (TX) the multiple low-speed parallel signals are converted into high-speed serial signals, which are then converted back into low-speed parallel signals at the receiving end (RX) via a transmission medium (optical cable or copper wire). The CDR (clock data recovery) module is an important structure at the RX end, which has a loop that keeps track of the phase of the incoming data and aligns the sampling instants of the RX local clock with the centre of the incoming data.
For the RX (RX receive) circuit, there may be some frequency difference between the input data and the local clock in addition to phase mismatch. A large frequency difference will rapidly accumulate phase differences, pulling the data and clock off during each cycle. The gain of the phase discriminator is limited, and the extra phase difference accumulation caused by a larger frequency difference cannot be effectively tracked.
The existing CDR clock frequency deviation correcting method generally designs a proportional path and an integral path to track the frequency deviation and the phase difference at the same time in most Serdes RX architectures, so as to realize clock frequency deviation correction, but when the frequency deviation is large, the situation of error judgment of a phase discriminator may occur, which results in poor frequency deviation correcting effect.
Disclosure of Invention
The application provides a method, a device and a storage medium for rectifying CDR clock frequency, which are used for solving the technical problem that the frequency rectifying effect is poor because the situation of error judgment of a phase discriminator possibly occurs when the frequency of the existing CDR clock frequency rectifying method is large.
One embodiment of the present application provides a CDR clock frequency correction method, including:
setting a deviation correction judging line between the edge judging line and the data judging line of the CDR eye diagram;
determining different areas in the CDR eye diagram according to the setting positions of the edge judging line, the data judging line and the deviation correcting judging line;
in a sampling period, acquiring the positions of clock sampling points in the CDR eye diagram, and judging the position sequence of the clock sampling points in different areas according to the distribution of the positions;
and correcting the phase detector according to the position sequence to obtain a correction result of the phase detector, and controlling the clock sampling point to move according to the correction result.
Further, the setting a correction determining line between the edge determining line and the data determining line of the CDR eye pattern includes:
and setting the deviation correction judgment line at 1/2 position between the edge judgment line and the data judgment line.
Further, the determining different regions in the CDR eye diagram according to the setting positions of the edge determining line, the data determining line and the deviation correcting determining line includes:
and taking the area between the deviation rectifying judging line and the edge judging line as a first area, taking the area above the edge judging line as a second area, and taking the area between the data judging line and the deviation rectifying judging line as a third area.
Further, the determining, according to the distribution of the positions, the position sequence of the clock sampling points in the different areas includes:
if the position sequence of the clock sampling points in the different areas is that the first area, the second area, the third area and the first area are circulated, the position sequence is judged to be anticlockwise;
and if the position sequence of the clock sampling points in the different areas is that the first area, the third area, the second area and the first area are circulated, judging that the position sequence is clockwise.
Further, the correcting the result of the phase detector according to the position sequence includes:
when the position sequence is anticlockwise, if the result of the current phase discriminator is 0, correcting the result of the phase discriminator to be 1;
and if the position sequence is clockwise and the result of the phase discriminator is 1, correcting the result of the phase discriminator to be 0.
Further, the controlling the clock sampling point to move according to the correction result includes:
when the correction result of the phase discriminator is 1, controlling the clock sampling point to move rightwards; and when the correction result of the phase detector is 0, controlling the clock sampling point to move leftwards.
One embodiment of the present application provides a CDR clock frequency correction device, including:
the deviation correcting judgment line setting module is used for setting a deviation correcting judgment line between the edge judgment line and the data judgment line of the CDR eye diagram;
the eye pattern region dividing module is used for determining different regions in the CDR eye pattern according to the setting positions of the edge judging line, the data judging line and the deviation correcting judging line;
the position sequence judging module is used for acquiring the positions of the clock sampling points in the CDR eye diagram in a sampling period and judging the position sequence of the clock sampling points in different areas according to the distribution of the positions;
and the sampling point control module is used for correcting the phase detector according to the position sequence to obtain a correction result of the phase detector, and controlling the clock sampling point to move according to the correction result.
Further, the deviation rectifying and judging line setting module is further configured to:
and setting the deviation correction judgment line at 1/2 position between the edge judgment line and the data judgment line.
Further, the eye pattern region dividing module is further configured to: and taking the area between the deviation rectifying judging line and the edge judging line as a first area, taking the area above the edge judging line as a second area, and taking the area between the data judging line and the deviation rectifying judging line as a third area.
An embodiment of the present application provides a computer readable storage medium, where the computer readable storage medium includes a stored computer program, where when the computer program runs, a device where the computer readable storage medium is controlled to execute a CDR clock frequency correction method as described above.
According to the embodiment of the application, the deviation correction judging line is arranged between the edge judging line and the data judging line of the CDR eye diagram, different areas are determined in the CDR eye diagram according to the three judging lines, and the result of the phase discriminator is corrected according to the occurrence sequence of clock sampling points in the different areas so as to control the clock sampling points to move, so that when the frequency difference exists between the clock frequency and the data frequency, the CDR clock is controlled to move in the correct direction, the clock frequency and the data frequency are basically consistent, and the CDR locking is realized.
Furthermore, the embodiment of the application ensures that the clock frequency and the data frequency are basically consistent by controlling the CDR clock to move in the correct direction, can effectively enlarge the frequency locking range, thereby meeting the requirements of various protocols,
drawings
FIG. 1 is a schematic flow chart of a CDR clock frequency correction method according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating different regions of a CDR eye according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing two position sequences of clock sampling points according to an embodiment of the present application
FIG. 4 is a schematic diagram of a flow chart of clock frequency correction based on a position sequence of clock sampling points according to an embodiment of the present application;
FIG. 5 is a schematic diagram of the most time-varying CDR clock frequency provided by an embodiment of the present application;
fig. 6 is a schematic structural diagram of a CDR clock frequency correction device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, an embodiment of the present application provides a CDR clock frequency correction method, which includes:
s1, setting a correction judgment line between an edge judgment line and a data judgment line of a CDR eye diagram;
in the embodiment of the application, the eye diagram is a graph obtained by overlapping each symbol waveform obtained by scanning a data stream.
S2, determining different areas in the CDR eye diagram according to the setting positions of the edge judgment line, the data judgment line and the deviation correction judgment line;
in the embodiment of the application, the area between the deviation rectifying judging line and the edge judging line is taken as a first area, the area above the edge judging line is taken as a second area, and the area between the data judging line and the deviation rectifying judging line is taken as a third area.
S3, acquiring the positions of clock sampling points in the CDR eye diagram in a sampling period, and judging the position sequence of different areas where the clock sampling points appear according to the distribution of the positions;
in the embodiment of the application, the positions of the clock sampling points on the CDR eye diagram are determined, and the position sequence of the clock sampling points is determined according to the sequence of the positions in different areas. The order of the positions may be clockwise or counterclockwise.
When the position sequence is clockwise, the data frequency is slower than the clock frequency, and the phase discriminator output 1 is needed; when the order of positions is counter-clockwise, indicating that the data frequency is faster than the clock frequency, a phase detector output of 0 is required.
S4, correcting the phase detector according to the position sequence to obtain a correction result of the phase detector, and controlling the clock sampling point to move according to the correction result.
According to the embodiment of the application, the deviation correction judging line is arranged between the edge judging line and the data judging line of the CDR eye diagram, different areas are determined in the CDR eye diagram according to the three judging lines, and the result of the phase discriminator is corrected according to the occurrence sequence of clock sampling points in the different areas so as to control the clock sampling points to move, so that when the frequency difference exists between the clock frequency and the data frequency, the CDR clock is controlled to move in the correct direction, the clock frequency and the data frequency are basically consistent, and the CDR locking is realized.
In one embodiment, step S1, setting a correction decision line between the edge decision line and the data decision line of the CDR eye pattern includes:
s11, setting the deviation correction judgment line at 1/2 position between the edge judgment line and the data judgment line.
In the embodiment of the application, the specific positions of the edge judging line and the data judging line in the eye diagram can be determined according to the coordinate values of the edge judging line and the data judging line.
In the embodiment of the application, based on the specific position of the judgment line, the deviation correction judgment line can be arranged at 1/2 position between the edge judgment line and the data judgment line, so that the distance between the deviation correction judgment line and the edge judgment line is consistent with the distance between the deviation correction judgment line and the distance data judgment line, and the distance can avoid the data judgment error caused by the influence of jitter and noise on the distance between the judgment lines.
In one embodiment, step S2, determining different regions in the CDR eye diagram according to the setting positions of the edge determination line, the data determination line, and the correction determination line, further includes:
the area between the deviation correcting judgment line and the edge judgment line is used as a first area, the area above the edge judgment line is used as a second area, and the area between the data judgment line and the deviation correcting judgment line is used as a third area.
Please refer to fig. 2, which is a schematic diagram illustrating different regions of a CDR eye diagram according to an embodiment of the present application.
In one embodiment, step S3, determining, according to the distribution of the positions, the position sequence of the different areas where the clock sampling points appear, includes:
if the position sequence of the clock sampling points in different areas is that the clock sampling points are in circulation from the first area to the second area to the third area to the first area, the position sequence is judged to be anticlockwise;
if the position sequence of the clock sampling points in different areas is that the clock sampling points are in the cycle of the first area, the third area, the second area and the first area, the position sequence is judged to be clockwise.
Referring to fig. 3, two position sequence diagrams are provided in the embodiment of the application.
Referring to fig. 4, a flow chart of performing clock frequency correction based on a position sequence of clock sampling points according to an embodiment of the present application is shown.
In the embodiment of the application, the data [ i ] can be used to represent the value obtained by the data judgment line, wherein 1 is higher than the judgment line, and 0 is lower than the judgment line; using edge [ i ] to represent the value obtained by the data judgment line, wherein 1 is higher than the judgment line, and 0 is lower than the judgment line; and using Scope [ i ] to represent data seen by the deviation correcting judgment line device, wherein 1 is higher than the judgment line, and 0 is lower than the judgment line.
When the edge of the data eye is in the third region, the values of the three determination lines are as follows:
data [ i ] =1, edge [ i ] =0, scope [ i ] =0, at which time the phase detector logic outputs Down (output state represents DN with 1);
when the edge of the data eye is in the first region, the values of the three determination lines are as follows:
data [ i ] =1, edge [ i ] =0, scope [ i ] =1, at which time the phase detector logic outputs Down (output state represents DN with 1);
when the edge of the data eye is in the third region, the values of the three determination lines are as follows:
data [ i ] =1, edge [ i ] =1, scope [ i ] =1, at which point the phase detector logic outputs Up (the output state is represented by 0 for Up).
With continued reference to fig. 4, the previous, up_pre (the previous value of the previous up), dnlock, dnlock_pre (the previous value of the previous Dnlock) may be set as the flag bit, and the phase detector may be instructed to correct the output result when the flag bit is in different states.
In the embodiment of the present application, the first area may be used to reset the values of Upllock and Dnlock and determine one direction of the algorithm, that is, the values of Upllock and Dnlock are reset to 0 each time the clock sampling point passes through the first area. If the data is directly rotated from the third area to the second area or directly rotated from the second area to the third area and does not pass through the first area, 1 is accumulated in Dnlock or upplock, and the next beat passes through the condition of upplock_pre and dnlock_pre (1 accumulated in the previous beat) to determine whether the phase discriminator outputs an error result.
In one embodiment, step S4, correcting the result of the phase detector according to the position sequence includes:
when the position sequence is anticlockwise, if the result of the current phase discriminator is 0, correcting the result of the phase discriminator to be 1;
if the result of the phase detector is 1 in the position order of clockwise, the result of the phase detector is corrected to 0.
Referring to fig. 4, a clock sampling point position sequence according to an embodiment of the present application may be as follows:
the start flag is 0→phase detector= =1 and scope= =0→check the value of the update_pre→update_pre= =0→record dnlock=1→return to the start of the cycle, where the phase detector= =0→scope= =1 (return to the start of the cycle if scope=0) →dnlock_pre= 1 (previously recorded dnlock=1 becomes the previous beat of dnlock_pre at this point→the point where the description position transitions from the third region to the second region and does not pass through the first region. That is, the position sequence of the current clock sampling point is clockwise, and the phase detector is required to output 1 at this time, but in the above process, the current phase detector can be determined to be= 0, which indicates that the output of the current phase detector is wrong.
In one embodiment, controlling clock sampling point movement based on the correction result includes:
when the correction result of the phase discriminator is 1, the clock sampling point is controlled to move rightwards; and when the correction result of the phase detector is 0, the clock sampling point is controlled to move leftwards.
According to the embodiment of the application, the COR clock can be guided to move in the correct direction according to the correction result of the phase discriminator, so that the clock frequency of the CDR is basically consistent with the data frequency.
Please refer to fig. 5, which is a schematic diagram illustrating a CDR clock frequency most time variation according to an embodiment of the present application. In the embodiment of the application, the data frequency is set to be 64 in the CDR model, the initial clock frequency is 63, the frequency difference is 1.56, and after the severe CDR clock frequency deviation correcting method provided by the embodiment of the application is adopted, the clock frequency gradually and slowly increases from 63, finally increases to 64, and keeps consistent with the data frequency, so that the CDR locking can be realized.
The embodiment of the application has the following beneficial effects:
according to the embodiment of the application, the deviation correction judging line is arranged between the edge judging line and the data judging line of the CDR eye diagram, different areas are determined in the CDR eye diagram according to the three judging lines, and the result of the phase discriminator is corrected according to the occurrence sequence of clock sampling points in the different areas so as to control the clock sampling points to move, so that when the frequency difference exists between the clock frequency and the data frequency, the CDR clock is controlled to move in the correct direction, the clock frequency and the data frequency are basically consistent, and the CDR locking is realized.
Furthermore, the embodiment of the application ensures that the clock frequency and the data frequency are basically consistent by controlling the CDR clock to move in the correct direction, and can effectively enlarge the frequency locking range, thereby meeting the requirements of various protocols.
Referring to fig. 6, based on the same inventive concept as the above embodiment, an embodiment of the present application provides a CDR clock frequency correction device, including:
the deviation correcting judging line setting module 10 is used for setting a deviation correcting judging line between the edge judging line and the data judging line of the CDR eye diagram;
the eye pattern region dividing module 20 is configured to determine different regions in the CDR eye pattern according to the setting positions of the edge determination line, the data determination line and the correction determination line;
the position sequence judging module 30 is configured to obtain the positions of the clock sampling points in the CDR eye diagram in the sampling period, and judge the position sequence of the different areas where the clock sampling points appear according to the distribution of the positions;
the sampling point control module 40 is configured to obtain a correction result of the phase detector according to the result of correcting the phase detector according to the position sequence, and control the clock sampling point to move according to the correction result.
In one embodiment, the deviation correcting determination line setting module 10 is further configured to:
the correction judgment line is arranged at 1/2 position between the edge judgment line and the data judgment line.
In one embodiment, the eye region dividing module 20 is further configured to: the area between the deviation correcting judgment line and the edge judgment line is used as a first area, the area above the edge judgment line is used as a second area, and the area between the data judgment line and the deviation correcting judgment line is used as a third area.
In one embodiment, the position order determination module 30 is further configured to:
if the position sequence of the clock sampling points in different areas is that the clock sampling points are in circulation from the first area to the second area to the third area to the first area, the position sequence is judged to be anticlockwise;
if the position sequence of the clock sampling points in different areas is that the clock sampling points are in the cycle of the first area, the third area, the second area and the first area, the position sequence is judged to be clockwise.
In one embodiment, the sample point control module 40 is further configured to:
when the position sequence is anticlockwise, if the result of the current phase discriminator is 0, correcting the result of the phase discriminator to be 1;
if the result of the phase detector is 1 in the position order of clockwise, the result of the phase detector is corrected to 0.
In one embodiment, the sample point control module 40 is further configured to:
when the correction result of the phase discriminator is 1, the clock sampling point is controlled to move rightwards; and when the correction result of the phase detector is 0, the clock sampling point is controlled to move leftwards.
An embodiment of the present application provides a computer readable storage medium, where the computer readable storage medium includes a stored computer program, and when the computer program is executed, controls a device in which the computer readable storage medium is located to execute a CDR clock frequency correction method as described above.
The foregoing is a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (10)
1. A CDR clock frequency correction method, comprising:
setting a deviation correction judging line between the edge judging line and the data judging line of the CDR eye diagram;
determining different areas in the CDR eye diagram according to the setting positions of the edge judging line, the data judging line and the deviation correcting judging line;
in a sampling period, acquiring the positions of clock sampling points in the CDR eye diagram, and judging the position sequence of the clock sampling points in different areas according to the distribution of the positions;
and correcting the phase detector according to the position sequence to obtain a correction result of the phase detector, and controlling the clock sampling point to move according to the correction result.
2. The CDR clock frequency correction method according to claim 1, wherein the setting a correction decision line between the edge decision line and the data decision line of the CDR eye pattern comprises:
and setting the deviation correction judgment line at 1/2 position between the edge judgment line and the data judgment line.
3. The CDR clock frequency correction method according to claim 1, wherein the determining different regions in the CDR eye pattern according to the setting positions of the edge determination line, the data determination line, and the correction determination line comprises:
and taking the area between the deviation rectifying judging line and the edge judging line as a first area, taking the area above the edge judging line as a second area, and taking the area between the data judging line and the deviation rectifying judging line as a third area.
4. The CDR clock frequency correction method according to claim 3, wherein the determining, according to the distribution of the positions, the position order in which the clock sampling points appear in the different areas comprises:
if the position sequence of the clock sampling points in the different areas is that the first area, the second area, the third area and the first area are circulated, the position sequence is judged to be anticlockwise;
and if the position sequence of the clock sampling points in the different areas is that the first area, the third area, the second area and the first area are circulated, judging that the position sequence is clockwise.
5. The CDR clock frequency correction method according to claim 1, wherein the correcting the phase detector result according to the position order comprises:
when the position sequence is anticlockwise, if the result of the current phase discriminator is 0, correcting the result of the phase discriminator to be 1;
and if the position sequence is clockwise and the result of the phase discriminator is 1, correcting the result of the phase discriminator to be 0.
6. The CDR clock frequency correction method according to claim 1, wherein the controlling the clock sampling point to move according to the correction result comprises:
when the correction result of the phase discriminator is 1, controlling the clock sampling point to move rightwards; and when the correction result of the phase detector is 0, controlling the clock sampling point to move leftwards.
7. A CDR clock frequency correction device, comprising:
the deviation correcting judgment line setting module is used for setting a deviation correcting judgment line between the edge judgment line and the data judgment line of the CDR eye diagram;
the eye pattern region dividing module is used for determining different regions in the CDR eye pattern according to the setting positions of the edge judging line, the data judging line and the deviation correcting judging line;
the position sequence judging module is used for acquiring the positions of the clock sampling points in the CDR eye diagram in a sampling period and judging the position sequence of the clock sampling points in different areas according to the distribution of the positions;
and the sampling point control module is used for correcting the phase detector according to the position sequence to obtain a correction result of the phase detector, and controlling the clock sampling point to move according to the correction result.
8. The CDR clock frequency correction device according to claim 7, wherein the correction determination line setting module is further configured to:
and setting the deviation correction judgment line at 1/2 position between the edge judgment line and the data judgment line.
9. The CDR clock frequency correction device of claim 7, wherein the eye region division module is further configured to: and taking the area between the deviation rectifying judging line and the edge judging line as a first area, taking the area above the edge judging line as a second area, and taking the area between the data judging line and the deviation rectifying judging line as a third area.
10. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored computer program, wherein the computer program when run controls a device in which the computer readable storage medium is located to perform the CDR clock frequency correction method according to any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310701499.8A CN116796697A (en) | 2023-06-13 | 2023-06-13 | CDR clock frequency deviation rectifying method, device and storage medium |
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| CN202310701499.8A CN116796697A (en) | 2023-06-13 | 2023-06-13 | CDR clock frequency deviation rectifying method, device and storage medium |
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