CN116795685A - Verilog code defect detection method and system - Google Patents

Abstract

The application relates to a Verilog code defect detection method and system, and belongs to the field of FPGA (field programmable gate array) testing. The method and the system of the application obtain the Verilog code to be detected based on the defect detection requirement and the original Verilog code; the corresponding relation between the description Verilog reserved words, structures and variable names and CST labels/label groups respectively, the corresponding relation between the description Verilog variable names and LLHD variable names, and the corresponding relation between key value pairs in CST expressions and LLHD expressions; converting the Verilog codes to be detected into CST expression and LLHD expression based on the corresponding relations; and respectively writing defect detection functions corresponding to CST expression and/or LLHD expression based on defect detection requirements to detect defects of the Verilog codes, and determining the Verilog code row where the defects are located. The application realizes the detection of semantic level defects in the Verilog code and the customization of defect detection rules by converting the Verilog code into two intermediate representations, namely a grammar tree CST expression and a bottom hardware description LLHD expression.

Description

Verilog code defect detection method and system

Technical Field

The application belongs to the field of FPGA (field programmable gate array) testing, and particularly relates to a Verilog code defect detection method and system.

Background

With the technology of programmable logic devices becoming mature, the programmable logic devices are also becoming widely applied in the fields of military, national defense, aviation, aerospace and the like, and particularly in the aspects of control, data processing and storage, instruments and meters, communication, digital signal processing and the like.

The programmable logic device software has the characteristics of compact and reliable code, strict requirement on real-time performance and the like, and the traditional detection means mainly comprise dynamic test and static test. The dynamic test mainly relies on simulation test means to detect the correctness of designed functions, performances, interfaces and the like and the compliance of requirements, and is difficult to detect code level; the static test is mainly used for detecting the defects of the codes without running code programs, and can comprehensively detect the characteristics of normalization, accuracy, consistency and the like of the software codes, so that the static test becomes an important means for detecting the defects of the software codes of the programmable logic devices.

The use of automated testing methods to develop programmable logic device software code defect detection is a necessary means to improve static test efficiency. Since the hardware description language HDL language is very complex, it is necessary to define the corresponding checking rules on an Intermediate Representation (IR) form for the automatic detection to take place. In Verilog code analysis testing work, many semantic defects containing certain characteristics and rules, such as asynchronous reset signals are not released synchronously, burrs generated by input signals are often detected, and the efficiency of testing work can be greatly improved by automatically finding and positioning the defects. However, verilog, which is a common HDL, cannot be used as an Intermediate Representation (IR) of modern circuit design flows due to its complexity, does not support code defect detection at the semantic level, and cannot achieve customization of defect detection rules.

Disclosure of Invention

In view of the above analysis, the present application aims to provide a Verilog code defect detection method and system, which perform structural conversion on Verilog code, can detect semantic level defects in Verilog code using two types of IR in JSON format, namely, syntax tree (CST expression) and underlying hardware description (LLHD expression), and support customization of defect detection rules.

The application provides a Verilog code defect detection method, which specifically comprises the following steps:

obtaining a to-be-detected Verilog code based on the defect detection requirement and the original Verilog code;

describing a first corresponding relation of a Verilog reserved word, a structure and a variable name and a CST label/label group respectively, describing a second corresponding relation of the Verilog variable name and a LLHD variable name, and describing a third corresponding relation of a key value pair in a CST expression and the LLHD expression;

converting the Verilog code to be detected into CST expression based on the first corresponding relation;

converting the CST expression into LLHD expression based on the first correspondence, the second correspondence, and the third correspondence;

and respectively compiling defect detection functions corresponding to CST expression and/or LLHD expression based on defect detection requirements, and performing defect detection on the CST expression or the LLHD expression based on the defect detection functions of the corresponding expressions to obtain a defect detection result of the Verilog code to be detected.

Further, the CST expression includes a plurality of CST nodes; converting the CST expression into LLHD expression based on the first correspondence, the second correspondence, and the third correspondence, comprising:

determining the Verilog sentence type corresponding to each CST node based on the first corresponding relation;

determining a Verilog variable name corresponding to the CST node based on the Verilog sentence type, a sub-label/sub-label group of the CST node and the first corresponding relation;

determining the LLHD variable name corresponding to the CST node based on the Verilog variable name and the second corresponding relation;

determining LLHD expression and time delay information corresponding to the expression in the CST node based on the expression information in the CST node and the third corresponding relation;

and converting the CST node into an LLHD instruction based on the LLHD variable name, the LLHD expression and the time delay information to obtain the LLHD expression corresponding to the CST node.

Further, the defect detection result comprises the detected defect and the original Verilog code line where the defect is located.

Further, describing a fourth correspondence between a CST node and LLHD instructions when converting the CST expression into the LLHD expression; and obtaining an original Verilog code row where the defect is located based on the fourth corresponding relation.

Further, obtaining an original Verilog code line where the defect is located includes:

for CST expression, determining a Verilog code line to be detected, in which the defect is located, based on the starting and ending positions of the CST node in which the defect is detected;

for LLHD expression, determining a CST node corresponding to the defect based on the detected defect and the fourth corresponding relation, and determining a Verilog code line to be detected, in which the defect is located, based on the starting and ending positions of the corresponding CST node;

and obtaining an original Verilog code line where the defect is located based on the Verilog code line to be detected where the defect is located.

Further, the converting the Verilog code to be detected into the CST expression based on the first correspondence relation includes:

marking reserved words and structures in the Verilog code to be detected by using a CST tag/tag group based on the first corresponding relation;

identifying variables in code blocks in the Verilog code to be detected by using a CST tag/tag group;

converting each sentence in the Verilog code block to be detected into a JSON array expressed by CST; wherein each word in the sentence corresponds to an element of the JSON array.

Further, the obtaining the Verilog code to be detected based on the defect detection requirement and the original Verilog code includes:

based on the defect detection requirement, judging whether the defect to be detected is 'output unregistered across clock domains' and whether the original Verilog code is at the RTL level:

if yes, converting the original Verilog code into a netlist level to obtain a to-be-detected Verilog code;

if not, the original Verilog code is the Verilog code to be detected.

The application also provides a Verilog code defect detection system, which comprises:

the Verilog code preprocessing module is used for obtaining a to-be-detected Verilog code based on the defect detection requirement and the original Verilog code;

the relationship comparison description module is used for describing and storing a first corresponding relationship between a Verilog reserved word, a structure and a variable name and a CST label/label group, a second corresponding relationship between a Verilog variable name and an LLHD variable name, a third corresponding relationship between a key value pair in CST expression and an LLHD expression, and a fourth corresponding relationship between a CST node and an LLHD instruction;

the CST conversion module is used for converting the Verilog codes to be detected into CST expressions based on the first corresponding relation;

the LLHD conversion module is used for converting the CST expression into LLHD expression based on the first corresponding relation, the second corresponding relation and the third corresponding relation;

and the defect detection module is used for carrying out defect detection on the CST expression and/or the LLHD expression based on the defect detection requirement, the fourth corresponding relation and a defect detection function corresponding to the CST expression and/or the LLHD expression to obtain a defect detection result.

Further, the fourth correspondence is obtained by converting the CST expression into LLHD expression.

Further, the defect detection requirement includes a type of defect to be detected and a defect name.

The application can realize at least one of the following beneficial effects:

by converting Verilog into two IR detection defects, namely CST and LLHD, the detection of semantic level defects in the Verilog code is realized; wherein, different defect characteristics correspond to different labels or label groups in CST expression, and corresponding defects can be detected by matching different labels or label groups of JSON nodes in a CST expression file; different defect features correspond to different instructions in LLHD expression, and by extracting different instructions in LLHD expression, the corresponding defects can be detected.

By writing a corresponding defect detection function according to each defect characteristic, inputting CST expression and/or LLHD expression to the defect detection function, and matching the defect characteristics to the CST expression and/or LLHD expression, the defect detection can be realized, thereby realizing customization of defect detection rules.

By describing the correspondence of Verilog codes, CST expressions, and LLHD expressions, after detecting a defect by CST expressions or LLHD expressions, a Verilog code line corresponding to the defect can be located according to the correspondence.

Because LLHD expression separates and expresses control flow and data flow of Verilog design by LLHD instruction mode, and uses LLHD expression to match defect characteristics, it can avoid the scene of matching multi-layer nested label when using CST expression to detect defect characteristics, it is easier to write defect detection function, and improves the efficiency of customizing defect detection rule.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the application, like reference numerals being used to refer to like parts throughout the several views.

FIG. 1 is a flow chart of a method for detecting code defects according to an embodiment of the present application;

FIG. 2 is a diagram showing an example of CST expression in step S02 of the method of the present application;

fig. 3 and 4 are diagrams showing an example of CST expression in step S04 according to an embodiment of the present application.

Detailed Description

The following detailed description of preferred embodiments of the application is made in connection with the accompanying drawings, which form a part hereof, and together with the description of the embodiments of the application, are used to explain the principles of the application and are not intended to limit the scope of the application.

Method embodiment

The application discloses a Verilog code defect detection method, which specifically comprises the following steps:

and S01, obtaining the Verilog code to be detected based on the defect detection requirement and the original Verilog code.

Specifically, the defect detection requirements include the type of defect to be detected and the defect name.

Specifically, the code level of the Verilog code to be detected corresponds to the defect to be detected. .

Specifically, the original Verilog code level includes an RTL level and a netlist level. When a defect is required to be detected and 'output across clock domains is not registered', if the original Verilog code is in RTL level, the original Verilog code is required to be converted into netlist level, and the Verilog code to be detected is obtained; if the original Verilog code is netlist-level, then no conversion is needed, the original Verilog code being the Verilog code to be tested.

Preferably, the method for converting the RLT level Verilog code into the netlist level can be as follows: and integrating a RTL processing front-end tool DFE through a Tool Command Language (TCL) framework, inputting RTL-level Verilog codes to be converted, and deriving a flattened (flat) netlist to obtain netlist-level Verilog codes.

Specifically, when the defect to be detected is other defects, the level of the Verilog code does not need to be converted, and the original Verilog code is the Verilog code to be detected.

Step S02, describing a first corresponding relation between the Verilog reserved word, the structure and the variable names and the CST label/label group, describing a second corresponding relation between the Verilog variable names and the LLHD variable names, and describing a third corresponding relation between key value pairs in the CST expression and the LLHD expression.

It should be noted that, the "first", "second", "third", and the like do not indicate any relative meaning of the corresponding relationships, but are merely used to distinguish between different corresponding relationships.

Specifically, writing a lookup table description of a Verilog reserved word, a structure or a variable name and a CST tag/tag group to describe a first corresponding relationship; wherein, the Verilog variable name refers to a signal name described by Verilog;

specifically, writing a lookup table of Verilog variable names and LLHD variable names to describe a second corresponding relationship; wherein, the LLHD variable name refers to a signal name described by LLHD.

Specifically, the LLHD expression generation function description third correspondence is written. By calling the LLHD expression generating function, key value pairs in CST expression such as numerical expression, conditional expression and signal connection expression can be converted into corresponding LLHD expression. And step S03, converting the Verilog codes to be detected into CST expressions based on the first corresponding relation.

Specifically, based on the first correspondence, using the CST tag/tag group to mark reserved words and structures in the code block; identifying variables in the code block using the CST tag/tag group; and converting each sentence in the Verilog code to be detected into a JSON array expressed by CST, wherein each word in the sentence corresponds to an element of the JSON array.

Illustratively, begin in Verilog, which represents the beginning of a code block, is a reserved word, and the tag "tag:" kBegin "is used in converting to CST expression; the @ start in Verilog represents the list of sensitive signals, i.e., the structure, and the tag @ tag: "kEventControl" @ is used to mark the list for conversion to CST.

Exemplary as in fig. 2, a CST expression after an always code block conversion is shown:

the 644-760 folded lines correspond to a sensitive signal list in a Verilog language software code block, and labels are marked in the figure by using the labels of 'kEventControl'; lines 765-771 describe begin reserved words of the Verilog language (begin is used to indicate the beginning of a Verilog code block), and the JSON element of the corresponding CST uses the tag of line 772 as a whole: "kBegin" tag; "end" and "start" in each JSON node in fig. 2 represent the start and end positions in Verilog code of words in Verilog code corresponding to that node, and are used to subsequently restore CST expression to Verilog code.

Step S04, converting the CST expression into LLHD expression based on the first corresponding relation, the second corresponding relation and the third corresponding relation.

Specifically, step S04 includes the steps of:

s04-1, determining the Verilog sentence type corresponding to each CST node based on the first corresponding relation;

s04-2, determining a Verilog variable name corresponding to a CST node based on the Verilog sentence type, a sub-label/sub-label group of the CST node and a first corresponding relation;

s04-3, determining the LLHD variable name corresponding to the CST node based on the Verilog variable name and the second corresponding relation;

s04-4, determining LLHD expression and time delay information corresponding to the expression in the CST node based on the expression information and the third corresponding relation in the CST node;

s04-5, converting the CST node into an LLHD instruction based on the LLHD variable name, the LLHD expression and the time delay information, namely the LLHD expression corresponding to the CST node;

s04-6 can be further included after S04-5 in order to obtain the original Verilog code line where the defect is located;

s04-6, describing a fourth corresponding relation between the CST node and the LLHD instruction.

Illustratively, converting the CST expression (shown in FIG. 3) corresponding to the non-blocking assignment statement in the Verilog language to a corresponding LLHD expression includes:

s04-1', determining the Verilog sentence type corresponding to each CST node based on the first corresponding relation.

Specifically, labels of CST nodes are: [ Tag: NONBLOCKING_ASSIGNENT_ STATEMENT ], determining that the CST node corresponds to a non-blocking ASSIGNMENT statement in Verilog based on the Tag and the first correspondence.

S04-2' determines the Verilog variable name corresponding to the CST node based on the Verilog statement type, the sub-label/sub-label group of the CST node and the first corresponding relation.

Illustratively, based on the sub-Tag group [ Tag:: LP_value, tag:: REFERENCE_CALL_BASE, tag:: REFERENCE, tag:: LOCAL_ROOT, tag:: UNQUALIFIED_ID, tag:: SYMBOL_IDENTIFIER ], and the first correspondence, determining its corresponding Verilog variable name as rst_reg1, which is the left VALUE of the non-blocking assignment statement in the corresponding Verilog;

s04-3', determining the LLHD variable name corresponding to the CST node based on the Verilog variable name and the second corresponding relation;

illustratively, determining that the LLHD variable name corresponding to the Verilog variable rst_reg1 is described as rst_reg1 based on the Verilog variable name and the second correspondence; note that, in this example, the Verilog variable name and the corresponding LLHD variable name are the same, and for other signal names, the corresponding Verilog variable name and LLHD variable name may be the same or different.

S04-4' determines LLHD expression and time delay information corresponding to the expression in the CST node based on the expression information and the third corresponding relation in the CST node.

Illustratively, based on the key value pair "text: rst_n" (as shown in fig. 4) and the third correspondence in the CST expression in the node, the corresponding LLHD expression is obtained as follows: % rst_n.prb3; specifically, since the Verilog non-blocking assignment statement has no time delay information, and no expression for representing the time delay information is also shown in the corresponding CST node, the time delay information is taken as 0, and the corresponding LLHD time delay information is obtained as% v28.

S04-5', converting the CST node into an LLHD instruction, namely LLHD expression of the corresponding CST node, based on the LLHD variable name, the LLHD expression and the time delay information.

The CST expression comprises a plurality of CST nodes, and LLHD expression corresponding to the CST expression is obtained based on the LLHD expression corresponding to each CST node.

Illustratively, based on the LLHD left value variable name, the right value expression and the time delay information of the non-blocking assignment statement, the LLHD instruction, i.e., the LLHD expression, corresponding to the non-blocking assignment statement is obtained, which is expressed as:

drv％rst_reg1,％rst_n.prb3,％v28；

wherein drv is LLHD instruction type, namely assignment, representing driving a variable; the variable driven is rst_reg1, the value used to drive it is rst_n.prb3, which is derived from the rst_n signal, and%v28 is the delay information, where the delay is 0.

S04-6', describe a fourth correspondence of CST nodes to LLHD instructions.

Illustratively, the corresponding CST node of the non-blocking assignment statement is shown in FIG. 3, and the corresponding LLHD instruction is drv% rst_reg1,% rst_n.prb3,% v28; the two are in one-to-one correspondence.

And step S05, respectively compiling defect detection functions corresponding to CST expression and/or LLHD expression based on defect detection requirements, and carrying out defect detection on the CST expression or the LLHD expression based on the defect detection functions of the corresponding expression to obtain a defect detection result of the Verilog code to be detected.

Step S05 includes the steps of:

s05-1, based on defect detection requirements, writing a defect detection function of corresponding CST expression and/or LLHD expression for each defect to be detected.

In particular, for semantic level defects of Verilog code, their corresponding CST expressions represent these defect features in the form of tags or tag groups; when the defect detection function is written, labels or label groups corresponding to different defects are matched with CST expression, and whether the corresponding defects exist or not can be detected.

Illustratively, a detection function of the defect that a bit operator appears in a conditional expression is written, and the function algorithm includes: determining a label group of CST expression corresponding to a conditional expression in a Verilog code; starting to match the tag group from the root node of the JSON array expressed by the CST; and continuing to match the corresponding label of the bit AND, bit or bit NOT operator in the CST node matched with the label group, and when the corresponding label is matched, indicating that the characteristic of the bit operator appears in the conditional expression conforming to the defect.

Specifically, for semantic level defects of Verilog codes, corresponding LLHD expressions show the defect characteristics through variables and operations of corresponding instructions; when the defect detection function is written, variables and operations of instructions corresponding to different defects are matched to LLHD expression, and whether the corresponding defects exist in the Verilog code can be detected.

Illustratively, a detection function of defect "asynchronous reset not synchronous release" is written:

the detection principle of asynchronous reset and asynchronous release is as follows:

for the rising edge, the falling edge and the level signals in the always statement in each statement block of the Verilog code, all possible reset signals are formed when the signals are converted into LLHD expression;

for each possible reset signal in the LLHD expression, it is necessary to check whether an instruction for a release operation is included; wherein the releasing operation includes reading/driving the net from the net, reading/writing the register from the net, reading the register/driving the net, the corresponding LLHD instruction is (Opcode:: prb, opcode:: drv), (Opcode:: prb, opcode:: st), (Opcode::: drv, opcode:: st); for each possible reset signal in the LLHD expressions, if there is an instruction for at least one release operation, then the possible reset signal is considered to be released; otherwise, the possible reset signal is considered not to be released, i.e. a defect is detected.

Corresponding to the above principle, the algorithm of the defect asynchronous reset asynchronous release detection function comprises: matching all possible reset signals in the LLHD expression; matching the matched possible reset signals with an instruction of the release operation; for the absence of a reset signal released to the instruction, i.e. in accordance with the defect "asynchronous reset not synchronous released" feature.

S05-2, inputting CST expression or LLHD expression into the defect detection function correspondingly expressed to detect the defect, and obtaining the detected defect.

Specifically, the CST expression and/or LLHD expression is input into a defect detection function of the corresponding expression to detect defects, and when the CST label/label group or LLHD instruction accords with the defect characteristics, the corresponding defects are detected.

Illustratively, for the defects in Table one, automatic detection of defects is achieved by detecting CST expression.

TABLE one Defect detected by CST expression

Illustratively, for the defects in Table II, automatic detection of defects is achieved by detecting LLHD expression.

Table II defects detected by LLHD expression

It should be noted that: the CST expression uses a multi-layer nested JOSN format, and automatic detection of the defect is achieved by matching labels or label groups corresponding to different defects by detecting the CST expression, and the method is characterized in that an algorithm for writing a defect detection function is simple, but a scene requiring matching of multi-layer nested labels is possibly met; the LLHD expression is used for separating and expressing the control flow and the data flow of the Verilog design in a LLHD instruction mode, and matching defect characteristics by using the LLHD expression can avoid the scene of matching a plurality of layers of nested labels when the CST expression is used for detecting the defect characteristics, and the detection method is more suitable for detecting defects related to signal operation due to the separation expression of the control flow and the data flow.

Illustratively, as shown in tables one and two, when the defects to be detected included in the detection requirements are listed only in table one, automatic detection of the defects is accomplished by detecting CST expression; when the defects to be detected are listed in table two only, the automatic detection of the defects is completed by detecting LLHD expression; when the defects to be detected are listed in both tables one and two, automatic detection of defects is accomplished by detecting CST expression and detecting LLHD expression.

S05-3, obtaining an original Verilog code row where the defect is located based on the detected defect and the fourth corresponding relation.

Specifically, for the CST expression, the start and end positions of the CST node where the defect is detected are extracted, so as to obtain a Verilog code line containing the defect corresponding to the CST node.

For LLHD expression, based on the LLHD instruction with the detected defect and based on the fourth corresponding relation, a CST node corresponding to the LLHD instruction is obtained, and then the starting position and the ending position of the CST node are extracted, so that a Verilog code line containing the defect can be obtained.

Specifically, for Verilog code lines containing defects: if the Verilog code is converted from the RTL level to the netlist level through the step S01, converting the Verilog code containing the defects into the RTL level by using a prior art tool, and obtaining an original Verilog code row corresponding to the defects; if not converted in step S01, the Verilog code line containing the defect is the original Verilog code line corresponding to the defect.

The embodiment discloses a method for detecting the defects of a Verilog code, which realizes the detection of semantic level defects in the Verilog code by converting the Verilog code into two intermediate expression detection defects of CST and LLHD; customization of defect detection rules is achieved by compiling corresponding defect detection functions according to each defect characteristic; by describing the correspondence between Verilog codes, CST expressions, and LLHD expressions, after detecting a defect, the original Verilog code corresponding to the defect can be located according to the correspondence.

Because LLHD expression separates and expresses control flow and data flow of Verilog design by LLHD instruction mode, and uses LLHD expression to match defect characteristics, it can avoid the scene of matching multi-layer nested label when using CST expression to detect defect characteristics, it is easier to write defect detection function, and improves the efficiency of customizing defect detection rule.

System embodiment

A Verilog code defect detection system comprises a Verilog code preprocessing module, a relation comparison module, a CST expression conversion module, an LLHD expression conversion module and a defect detection module, wherein:

the Verilog code preprocessing module is used for obtaining a to-be-detected Verilog code based on the defect detection requirement and the original Verilog code; the defect detection requirement comprises the type of the defect to be detected and the name of the defect.

The relationship comparison module is used for describing and storing a first corresponding relationship between a Verilog reserved word, a structure and a variable name and a CST label/label group, a second corresponding relationship between the Verilog variable name and an LLHD variable name, a third corresponding relationship between a key value pair in CST expression and an LLHD expression, and a fourth corresponding relationship between a CST node and an LLHD instruction;

the CST conversion module is used for converting the Verilog codes to be detected into CST expressions based on the first corresponding relation;

the LLHD conversion module is used for converting the CST expression into LLHD expression based on the first corresponding relation, the second corresponding relation and the third corresponding relation;

and the defect detection module is used for carrying out defect detection on the CST expression and/or the LLHD expression based on the defect detection requirement, the fourth corresponding relation and a defect detection function corresponding to the CST expression and/or the LLHD expression to obtain a defect detection result.

Wherein the fourth correspondence is obtained by converting the CST expression into LLHD expression.

Compared with the prior art, the beneficial effects of the Verilog code defect detection system provided by the embodiment are basically the same as those of the method embodiment, and are not described in detail herein.

It should be noted that, the above embodiments are based on the same inventive concept, and the description is not repeated, and the description may be referred to each other.

The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application.

Claims (10)

1. A Verilog code defect detection method is characterized by comprising the following steps:

obtaining a to-be-detected Verilog code based on the defect detection requirement and the original Verilog code;

describing a first corresponding relation of a Verilog reserved word, a structure and a variable name and a CST label/label group respectively, describing a second corresponding relation of the Verilog variable name and a LLHD variable name, and describing a third corresponding relation of a key value pair in a CST expression and the LLHD expression;

converting the Verilog code to be detected into CST expression based on the first corresponding relation;

converting the CST expression into LLHD expression based on the first correspondence, the second correspondence, and the third correspondence;

and respectively compiling defect detection functions corresponding to CST expression and/or LLHD expression based on defect detection requirements, and performing defect detection on the CST expression or the LLHD expression based on the defect detection functions of the corresponding expressions to obtain a defect detection result of the Verilog code to be detected.

2. The defect detection method of claim 1, wherein the CST expression comprises a plurality of CST nodes; converting the CST expression into LLHD expression based on the first correspondence, the second correspondence, and the third correspondence, comprising:

determining the Verilog sentence type corresponding to each CST node based on the first corresponding relation;

determining a Verilog variable name corresponding to the CST node based on the Verilog sentence type, a sub-label/sub-label group of the CST node and the first corresponding relation;

determining the LLHD variable name corresponding to the CST node based on the Verilog variable name and the second corresponding relation;

determining LLHD expression and time delay information corresponding to the expression in the CST node based on the expression information in the CST node and the third corresponding relation;

and converting the CST node into an LLHD instruction based on the LLHD variable name, the LLHD expression and the time delay information to obtain the LLHD expression corresponding to the CST node.

3. The defect detection method of claim 2, wherein the defect detection results comprise detected defects and raw Verilog code lines where the defects are located.

4. The defect detection method of claim 3 wherein a fourth correspondence of CST nodes and LLHD instructions is described when converting the CST expression to LLHD expression; and obtaining an original Verilog code row where the defect is located based on the fourth corresponding relation.

5. The defect detection method of claim 4, wherein obtaining the original Verilog code line where the defect is located comprises:

for CST expression, determining a Verilog code line to be detected, in which the defect is located, based on the starting and ending positions of the CST node in which the defect is detected;

for LLHD expression, determining a CST node corresponding to the defect based on the detected defect and the fourth corresponding relation, and determining a Verilog code line to be detected, in which the defect is located, based on the starting and ending positions of the corresponding CST node;

and obtaining an original Verilog code line where the defect is located based on the Verilog code line to be detected where the defect is located.

6. The defect detection method of claim 1, wherein the converting Verilog code to be detected to CST expression based on the first correspondence comprises:

marking reserved words and structures in the Verilog code to be detected by using a CST tag/tag group based on the first corresponding relation;

identifying variables in code blocks in the Verilog code to be detected by using a CST tag/tag group;

converting each sentence in the Verilog code block to be detected into a JSON array expressed by CST; wherein each word in the sentence corresponds to an element of the JSON array.

7. The defect detection method of claim 1, wherein obtaining the Verilog code to be detected based on the defect detection requirements and the original Verilog code comprises:

based on the defect detection requirement, judging whether the defect to be detected is 'output unregistered across clock domains' and whether the original Verilog code is at the RTL level:

if yes, converting the original Verilog code into a netlist level to obtain a to-be-detected Verilog code;

if not, the original Verilog code is the Verilog code to be detected.

8. A Verilog code defect detection system, comprising:

the Verilog code preprocessing module is used for obtaining a to-be-detected Verilog code based on the defect detection requirement and the original Verilog code;

the relationship comparison description module is used for describing and storing a first corresponding relationship between a Verilog reserved word, a structure and a variable name and a CST label/label group, a second corresponding relationship between a Verilog variable name and an LLHD variable name, a third corresponding relationship between a key value pair in CST expression and an LLHD expression, and a fourth corresponding relationship between a CST node and an LLHD instruction;

the CST conversion module is used for converting the Verilog codes to be detected into CST expressions based on the first corresponding relation;

the LLHD conversion module is used for converting the CST expression into LLHD expression based on the first corresponding relation, the second corresponding relation and the third corresponding relation;

and the defect detection module is used for carrying out defect detection on the CST expression and/or the LLHD expression based on the defect detection requirement, the fourth corresponding relation and a defect detection function corresponding to the CST expression and/or the LLHD expression to obtain a defect detection result.

9. The defect detection system of claim 8, wherein the fourth correspondence is obtained by converting the CST expression to LLHD expression.

10. The defect detection system of claim 9, wherein the defect detection requirements include a type of defect to be detected and a defect name.