CN116795605B - Automatic recovery system and method for abnormality of peripheral device interconnection extension equipment - Google Patents
Automatic recovery system and method for abnormality of peripheral device interconnection extension equipment Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
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- G06F11/1402—Saving, restoring, recovering or retrying
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
Abstract
The application provides an abnormal automatic recovery system and method for peripheral device interconnection extension equipment. The system comprises: the data processor is used for storing the state information of at least one PCIE device in real time, wherein the at least one PCIE device is provided with a hardware queue; the processor is used for driving at least one PCIE device through a driver, setting a host queue in a memory of the processor, and mutually matching the hardware queue and the host queue to realize data transmission between the processor and the at least one PCIE device, wherein the memory of the processor records state information of the host queue; the data processor is further configured to, after the exception recovery of the emulator, actively infer state information of a host queue according to the host queue in the memory of the processor, recover a hardware queue according to the state information of the host queue and the host queue, and obtain and recover state information of at least one PCIE device stored before the exception occurs to the emulator.
Description
Technical Field
The application relates to a data processor, in particular to an abnormal automatic recovery system and method for peripheral device interconnection extension equipment.
Background
Peripheral component interconnect (peripheral component interconnect, PCI) is a local parallel bus standard proposed by PCISIG (PCI special interest group). The PCI bus is a tree structure and is independent of the CPU (central processing unit, CPU) bus, and can operate in parallel with the CPU bus. PCI equipment and PCI bridge pieces can be hung on a PCI bus, only one PCI master equipment is allowed on the PCI bus, the other PCI slave equipment is all available, and the read-write operation can only be carried out between the master equipment and the slave equipment, and the data exchange between the slave equipment needs to be transferred through the master equipment. Among them, peripheral Component Interconnect Express (PCIE) is derived from early PCI expansion and is mainly distinguished from compatible PCI by parallel-to-serial switching and faster rates. PCI Express is a layered protocol consisting of a transaction layer, a data link layer, and a physical layer.
However, in the abnormal situation, the PCIE devices may not be all available, and the data service of the CPU may be interrupted, and at the same time, the system of the CPU may be suspended, so that the abnormal situation is handled, and the service on the PCI devices may be recovered only by participation of operation and maintenance personnel.
Disclosure of Invention
The embodiment of the invention provides an automatic recovery system and an automatic recovery method for peripheral device interconnection extension equipment, which can automatically recover the peripheral device interconnection extension equipment when a data processor (Data Processing Unit, DPU) is abnormal.
In a first aspect, a system for automatically recovering abnormality of a peripheral device interconnection extension apparatus is provided, including:
a data processor for providing at least one peripheral device interconnect extension apparatus and hardware logic of a topology relationship of the at least one peripheral device interconnect extension apparatus, the data processor further provided with a simulator for providing at least one peripheral device interconnect extension apparatus and software logic of a topology relationship of the at least one peripheral device interconnect extension apparatus, and negotiating interactions with the hardware logic to enable simulation of the at least one peripheral device interconnect extension apparatus, the data processor storing state information of the at least one peripheral device interconnect extension apparatus in real time, the at least one peripheral device interconnect extension apparatus having a hardware queue;
the processor is used for driving the at least one peripheral device interconnection extension device through a driver, setting a host queue in a memory of the processor, enabling the hardware queue and the host queue to be matched with each other, realizing data transmission between the processor and the at least one peripheral device interconnection extension device, and recording state information of the host queue in the memory of the processor;
The data processor is further configured to, after the simulator is abnormally recovered, actively infer state information of a host queue in a memory of the processor according to the state information of the host queue, recover a hardware queue and state information of the hardware queue according to the state information of the host queue and the state information of the host queue, and obtain and recover the state information of the at least one peripheral device interconnection extension device saved before the simulator is abnormally.
In some possible designs, the data processor is further configured to send an unsupported response to the processor if a request is received from the processor during the simulator exception.
In some possible designs, in a case where the number of peripheral device interconnect extension apparatuses is plural, the plural peripheral device interconnect extension apparatuses include a peripheral device interconnect extension bridge apparatus and a peripheral device interconnect extension end apparatus, the state information of the peripheral device interconnect extension bridge apparatus includes a configuration space state of the peripheral device interconnect extension bridge apparatus, and the state information of the peripheral device interconnect extension end apparatus includes one or more of a configuration space state of the peripheral device interconnect extension end apparatus, attribute information of the peripheral device interconnect extension end apparatus, and a current operation state of the peripheral device interconnect extension end apparatus.
In some possible designs, the configuration space state of the peripheral device interconnect expansion bridge device includes one or more of a peripheral device interconnect expansion configuration space header state and a currently used capability set state; the configuration space state of the peripheral device interconnection extension end equipment comprises one or more of a peripheral device interconnection extension configuration space head state and a currently used capability set state; the attribute information of the peripheral device interconnection extension end equipment comprises one or more of the number of queues of the peripheral device interconnection extension end equipment, the depth of the queues of the peripheral device interconnection extension end equipment, the maximum transmission unit of the peripheral device interconnection extension end equipment and the media access control address of the peripheral device interconnection extension end equipment; the current working state of the peripheral device interconnection extension end equipment comprises one or more of characteristics negotiated with a driver of the processor, virtual local area network information, promiscuous mode information, a queue base address of the hardware queue and an interrupt number used by the hardware queue.
In some possible designs, the at least one peripheral interconnect extension device emulated by the data processor is not available in the event of an exception to the emulator.
In a second aspect, a method for automatically recovering an abnormality of a peripheral device interconnection extension apparatus is provided, and the method is applied to a peripheral device interconnection extension apparatus abnormality automatic recovery system, the peripheral device interconnection extension apparatus abnormality automatic recovery system includes a data processor and a processor, the data processor includes a simulator, the data processor is used for providing at least one peripheral device interconnection extension apparatus and hardware logic of a topology relationship of the at least one peripheral device interconnection extension apparatus, the data processor is further provided with the simulator, the simulator is used for providing at least one peripheral device interconnection extension apparatus and software logic of the topology relationship of the at least one peripheral device interconnection extension apparatus, and negotiating interaction with the hardware logic to simulate the at least one peripheral device interconnection extension apparatus, the data processor stores state information of the at least one peripheral device interconnection extension apparatus in real time, and the at least one peripheral device interconnection extension apparatus has a hardware queue; the processor is used for driving the at least one peripheral device interconnection extension device through a driver, setting a host queue in a memory of the processor, wherein the hardware queue and the host queue are mutually matched to realize data transmission between the processor and the at least one peripheral device interconnection extension device, and the processor is also used for recording state information of the host queue in the memory; after the recovery of the simulator from the anomaly,
The data processor actively infers state information of a host queue in a memory of the processor according to the host queue,
the data processor restores the hardware queue and the state information of the hardware queue based on the state information of the host queue and the state information of the host queue,
and the data processor acquires and restores the state information of the at least one peripheral device interconnection extension device stored before the abnormality of the simulator occurs.
In some possible designs, the method further comprises:
the data processor sends an unsupported response to the processor if a request is received by the processor during the data processor exception.
In some possible designs, in a case where the number of peripheral device interconnect extension apparatuses is plural, the plural peripheral device interconnect extension apparatuses include a peripheral device interconnect extension bridge apparatus and a peripheral device interconnect extension end apparatus, the state information of the peripheral device interconnect extension bridge apparatus includes a configuration space state of the peripheral device interconnect extension bridge apparatus, and the state information of the peripheral device interconnect extension end apparatus includes one or more of a configuration space state of the peripheral device interconnect extension end apparatus, attribute information of the peripheral device interconnect extension end apparatus, and a current operation state of the peripheral device interconnect extension end apparatus.
In some possible designs, the configuration space state of the peripheral device interconnect expansion bridge device includes one or more of a peripheral device interconnect expansion configuration space header state and a currently used capability set state; the configuration space state of the peripheral device interconnection extension end equipment comprises one or more of a peripheral device interconnection extension configuration space head state and a currently used capability set state; the attribute information of the peripheral device interconnection extension end equipment comprises one or more of the number of queues of the peripheral device interconnection extension end equipment, the depth of the queues of the peripheral device interconnection extension end equipment, the maximum transmission unit of the peripheral device interconnection extension end equipment and the media access control address of the peripheral device interconnection extension end equipment; the current working state of the peripheral device interconnection extension end equipment comprises one or more of characteristics negotiated with a driver of the processor, virtual local area network information, promiscuous mode information, a queue base address of the hardware queue and an interrupt number used by the hardware queue.
In some possible designs, the at least one peripheral interconnect extension device of the simulation of the data processor is not available in the event of an exception to the simulator.
In a second aspect, there is provided a data processor comprising: at least one processing core and at least one memory for storing instructions that, when executed by the at least one processing core, enable the method of any one of the second aspects.
In the above scheme, the topology relationship between the peripheral interconnection extension device and the peripheral interconnection extension device can be simulated by the DPU, the state information of the peripheral interconnection extension device in the memory of the data processor is stored in the nonvolatile storage medium in real time, the host queue is set in the memory of the processor, the hardware queue of the peripheral interconnection extension device is set in the data processor, when the DPU is abnormal, the descriptor in the hardware queue will be lost, the state information of the hardware queue will not be lost, the descriptor in the host queue will not be lost, the state information of the host queue will not be lost, after the DPU is abnormal, the DPU can read and recover the state information of the peripheral interconnection extension device from the nonvolatile storage medium, and actively derive the state information of the host queue according to the host queue in the CPU memory, recover the hardware queue and the state information of the hardware queue according to the host queue, and the service between the CPU and the peripheral interconnection extension device can be recovered after the recovery is completed.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
FIG. 1 is a schematic diagram of a system for automatically recovering abnormality of a peripheral device interconnect extension apparatus according to the present application;
FIG. 2 is a schematic diagram of a CPU according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a DPU according to an embodiment of the present application;
fig. 4 is a schematic flow chart of a PCIE device exception automatic recovery method according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an abnormality automatic recovery system for a peripheral device interconnection extension apparatus provided by the present application. As shown in fig. 1, the system for automatically recovering abnormality of a peripheral device interconnection extension apparatus provided by the present application includes: a CPU 11 and a DPU 12.
The CPU 11 is an arithmetic core and a control core, and can handle complex situations. The CPU 11 may be a very large scale integrated circuit. The main operating system and other software programs are installed in the CPU 11, so that the CPU 11 can realize access to the memory and various PCIE devices. The CPU 11 can quickly access the local memory through an on-chip bus. One or more processor cores (cores) may be included in the CPU 11. In one implementation, CPU 11 may be a multi-core chip, i.e., a chip containing multiple processing cores. In another implementation, one or more processor cores (cores) may be included in CPU 11. May be a chip having one processing core.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a CPU according to an embodiment of the present application. As shown in fig. 2, the CPU may include a memory address register 101, a memory data register 102, a program counter 103, an instruction register 104, an instruction decoder 105, a microcode read-only memory 106, an operation controller 107, a calculation unit 108, a general register group 109, an accumulator 110, a program status word register 111, a timing circuit 112, and a processor bus 120. The processor bus 120 may be a data bus, a power bus, a control bus, a status signal bus, or the like.
The CPU is used to process instructions and data stored in the memory 113. In some embodiments, the instructions may include one or more instruction formats. The instruction format may indicate various fields (number of bits, position of bits, etc.) to specify the operation of the data processing to be performed and the operand on which the operation is to be performed. Some instruction formats may be further defined by instruction templates (or sub-formats).
In the CPU, a memory address register 101 is used to hold the address of the memory currently to be accessed by the CPU. The memory data register 102 is used to hold data read from or written to the address by the CPU and instructions to read from or write to make up for differences in operating speed that exist between the processor and the memory.
The timing circuit 112 provides a time reference for each component by a fixed clock, and the processor executes an instruction for one instruction cycle. The program counter 103 is used for storing the address of the next instruction, and when the instructions are executed sequentially, the program counter 103 automatically adds the byte number of one instruction after each instruction is fetched. When a branch instruction is encountered, program counter 103 specifies the address of the next instruction by way of an address code field in the branch instruction. The instruction register 104 is used to hold instructions that are currently executing. The instruction includes two fields, an opcode and an address code, the opcode portion being decoded by the instruction decoder 105 to generate control potentials for the operations required by the instruction. The operation controller 107 may generate various operation control signals according to the control potential signal output from the instruction decoder and the timing signal generated by the timing circuit 112, and control the remaining components of the CPU to complete the operations of fetching and executing instructions.
The micro instruction is the minimum unit for executing instructions by the processor, and one instruction can be a single micro instruction or can be composed of a plurality of micro instructions. The instructions combined by the plurality of microinstructions are referred to as complex instructions, and the decoding of the complex instructions by the instruction decoder 105 may be implemented using a variety of different mechanisms. Specific decoding mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable Logic Arrays (PLAs), microcode read-only memories (ROMs), and the like. In one embodiment, the steps of the microinstruction corresponding to the complex instruction may be stored in the microcode rom 106, and the instruction decoder 105 may query and obtain the operation code and address code of the microinstruction constituting the complex instruction from the microcode rom 106 during the decoding process, and sequentially decode the operation code portion of the microinstruction to generate the control potential for the operation required by the microinstruction.
The operation controller 107 has a plurality of buffers, and can send the decoded instructions to the respective reservation stations for reservation according to the types of the instructions. And the instructions which can be executed in advance are scheduled to the corresponding computing units 108 for execution according to the state of the hardware circuits of the computing units and the specific situation analysis of whether each instruction can be executed in advance. During which the instruction stream is reordered to cause the instruction pipeline to travel and be smoothly scheduled. For example, for an instruction of integer computation, the operation controller 107 may save the instruction using an integer reservation station and assign to the integer computation unit to perform computation; for instructions of floating point number computation, operation controller 107 may save the instructions using a floating point number reservation station and assign to the floating point number computation unit to perform the computation.
The general register set 109 is used for storing data corresponding to an address code according to the address code of an instruction. The calculation unit 108 is configured to receive an operation control signal of the operation controller 107 and perform calculation on data stored in the general register set 109, including arithmetic operations (including basic operations such as addition and subtraction of multipliers and the like and additional operations thereof) and logical operations (including shifting, logical testing, or two-value comparison). The temporary variable generated during calculation is stored in the accumulator 110, and the information of the generated state is stored in the program status word register 111, for example, an operation result advance/borrow flag (C), an operation result overflow flag (O), an operation result zero flag (Z), an operation result negative flag (N), an operation result sign flag (S), and the like. The program status word register is also used to store interrupt and computing device operating status information, so that the CPU can know the machine operating status and program operating status in time.
The computing unit 108 includes a plurality of different circuit modules that can be used to execute different instructions. For example, the integer calculation unit 1081 and the floating point calculation unit 1082 are used for performing arithmetic operation and logical operation on the integer and the floating point, respectively.
It will be appreciated that the above-described CPU is merely a specific embodiment, and may have more or fewer components in actual practice, and will not be described herein.
DPU 12 contains multiple processing cores (cores) that can perform data processing in parallel, and thus DPU 12 tends to have significant computing power. Referring to fig. 3, the dpu includes: a plurality of memories 121, a plurality of processing cores 122, and a communication interface 123, and so on. For example, processing cores 122 may include a first processing core, a second processing core, …, an nth processing core, and memory 121 includes a first memory, a second memory, …, an nth memory. In one possible embodiment, the processing cores 122 in the DPU 12 are less computationally intensive than the processors in the CPU 11, and the memory 121 in the DPU 12 is less storable than the memory in the CPU 11. Thus, CPU 11 is adapted to handle a small number of complex instructions, while DPU 12 is adapted to handle a batch of simple instructions. Memory 121 may be a non-volatile solid state memory. In one possible embodiment, memory 121 includes Read-Only Memory (ROM). The ROM may be mask-programmed ROM, programmable ROM (PROM), erasable PROM (Electrical Programmable ROM, EPROM), electrically erasable PROM (Electrically Erasable Programmable ROM, EEPROM), electrically rewritable ROM (Electrically Alterable ROM, EAROM), or flash memory, or a combination of two or more of these, where appropriate. A slave operating system may be installed on the DPU, the slave operating system being used to manage hardware resources on the DPU. In one possible embodiment, the slave operating system in DPU 12 is less functional than the master operating system in CPU 11. DPU 12 may be configured to simulate the topology of at least one peripheral device interconnect extension device and at least one PCIE device. The hardware resources of the DPU are used to provide at least one PCIE device and hardware logic of the topology relationship of the at least one PCIE device. A simulator may be installed in DPU 12 for providing at least one PCIE device and software logic for the topology of the at least one PCIE device. DPU 12 negotiates interactions between software logic and hardware logic to implement a simulation of at least one PCIE device.
The PCIE devices simulated in the DPU may include PCIE end devices and PCIE bridge devices. The PCIE end device may provide various functions, for example, the PCIE end device may be a network card, provide a function of network data transmission, may be an audio card, and provide processing on an audio source. The PCIE bridge device is used for connecting a plurality of PCIE terminal devices to form different topological relations. The topology of PCIE devices may include one or more of star relationships, tree relationships, ring relationships, bus relationships, and so forth. Taking the topological relation of the PCIE devices in fig. 1 as an example, the first PCIE device is used as a root node of the tree, the second PCIE device, the third PCIE device and the fourth PCIE device are used as leaf nodes of the tree, and are respectively connected to the root node and the first PCIE device.
In the using process of the PCIE device, the state information of the PCIE device may change, however, the conversion of the state information of the PCIE device is relatively slow, so that the state information of the PCIE device may be stored in a nonvolatile storage medium of the DPU, for example, a disk, etc. in real time. The status information of the PCIE device includes a configuration space status of the PCIE bridge device, and so on. The configuration space states of the PCIE bridge device include one or more of PCIE configuration space header states and currently used capability set states. The configuration space state of the PCIE end device includes one or more of a PCIE configuration space header state and a currently used capability set state. The state information of the PCIE end device includes one or more of a configuration space state of the PCIE end device, attribute information of the PCIE end device, and a current working state of the PCIE end device. The attribute information of the PCIE terminal device includes one or more of the number of queues of the PCIE terminal device, the queue depth of the PCIE terminal device, the maximum transmission unit of the PCIE terminal device, and the media access control address of the PCIE terminal device; the current working state of the PCIE end device includes one or more of characteristics negotiated with a driver of the processor, virtual local area network information, promiscuous mode information, a queue base address of the hardware queue, and an interrupt number used by the hardware queue.
In order to realize data transmission between the CPU and the PCIE end device, a host queue of the PCIE device may be set in the CPU, and a hardware queue of the PCIE device may be set in the DPU. The host queue is used for storing the first descriptor, and the hardware queue is used for storing the second descriptor. In a specific embodiment, taking the first descriptor as an example, the first descriptor is used to store metadata, where the metadata includes an address field of 8 bytes, a length field of 4 bytes, a count field of 2 bytes, and a flag field of 2 bytes. The address field is used to store an address of data to be read or written, the length field is used to store a length of data to be read or written, the count field is used to store a count value, the flag field is used to indicate whether the descriptor is available and has been used up, for example, when the flag field is 01, the descriptor is available and has not been used up, and when the flag field is 10, the descriptor is not available and has been used up.
The process of data transmission between the CPU and PCIE end device will be described in a specific embodiment. Assuming that descriptors 1 through 30 are stored in the host queue, the first head pointer of the host queue points to descriptor 10 in the host queue, and the flag fields in descriptors 10-19 in the host queue are all set to 01. The second head pointer of the hardware queue points to the descriptor 10 of the hardware queue. The CPU sends the descriptors 10-19 to the DPU via DMA technology. When the DPU receives the descriptor 10 in the host queue, the descriptor is stored in the descriptor 10 in the hardware queue; when the DPU receives the descriptor 11 in the host queue, the descriptor is stored in the descriptor 11 in the hardware queue; …; until the DPU receives a descriptor 19 in the host queue, the descriptor is stored into the descriptor 19 in the hardware queue. After the DPU receives the descriptors 10-19, data transfer between the CPU and the DPU is achieved by DMA techniques based on the addresses in the address fields and the lengths in the length fields in the descriptors 10-19. After the transfer of data corresponding to descriptors 10-19 between the CPU and the DPU, the first head pointer points to descriptor 20 of the host queue and the second head pointer points to descriptor 20 of the hardware queue, with the flag fields in descriptors 10-19 set to 10. In addition, state information of the host queue may be stored in the memory of the CPU. The state information of the host queue may include the current position of the first head pointer, and so on. The DPU does not store the state information of the hardware queue in the nonvolatile storage medium, because the state information of the hardware queue is constantly changing, and when the state information of the hardware queue is stored in the nonvolatile storage medium, the state information of the hardware queue is always outdated, which has no meaning. However, since the host queue is always stored in the memory of the CPU, the state information of the hardware queue and the hardware queue may be restored by referring to the host queue in the memory of the CPU.
When the simulator in the DPU is abnormal, all the simulated PCIE devices in the DPU are not available, and at this time, the state information of the PCIE devices in the memory of the DPU is lost, and the state information of the hardware queue of the DPU and the hardware queue of the DPU are lost. At this point, traffic between the CPU and the DPU will be interrupted. During a fault in a simulator in the DPU, if the CPU sends a request to the DPU, the DPU sends an unsupported response (Unsupported Request, UR) to the CPU to alert the CPU that the simulator has failed.
In order to actively restore the service between the CPU and the DPU, the need to manually participate in the restoration of the service between the CPU and the DPU is avoided. After the simulator in the DPU is abnormally recovered, the DPU may actively recover the state information of the PCIE device stored in the nonvolatile storage medium in real time. Then, the state information of the host queue is actively inferred according to the host queue in the memory of the CPU, and the hardware queue and the state information of the hardware queue are restored according to the state information of the host queue and the host queue. In a specific embodiment, assume that descriptors 1 through 30 are stored in the host queue, that the first head pointer of the host queue points to descriptor 10 in the host queue, and that the flag fields in descriptors 10-19 in the host queue are all set to 01. The second head pointer of the hardware queue points to the descriptor 10 of the hardware queue. During the transmission of descriptor 13 in the host queue, the simulator of the DPU fails, resulting in the loss of the descriptor in the hardware queue and the loss of state information of the hardware queue. However, the descriptor in the host queue is not lost, and the state information of the host queue is not lost, so that the memory of the host queue can be moved to the memory of the DPU for analysis, and the position of the first pointer of the host queue is resolved, that is, the state information of the host queue is resolved. Because the DPU cannot directly acquire the location information of the host queue, the state information of the host queue can only be deduced from the information of the host queue itself. The DPU may know that the descriptors 10-19 in the host queue need to be transferred to the DPU based on the first head pointer of the host queue pointing to the descriptor 10, with the flag fields in the descriptors 10-19 in the host queue all set to 01. The hardware queues and state information for the hardware queues may then be restored. After the state information of the PCIE device, the state information of the hardware queue, and the hardware queue are restored, normal traffic between the CPU and the DPU may be restored.
Referring to fig. 4, fig. 4 is a flowchart of a PCIE device exception automatic recovery method according to an embodiment of the present application. As shown in fig. 4, the PCIE device anomaly automatic recovery method of the present application is applied to the PCIE device anomaly automatic recovery system, and includes:
s301: the DPU actively infers the state information of the host queue according to the host queue in the memory of the CPU.
In some possible embodiments, a host queue may be provided in the CPU, the host queue for storing the first descriptor. In a specific embodiment, the first descriptor is used to store metadata, the metadata including an 8-byte address field, a 4-byte length field, a 2-byte count field, and a 2-byte flag field. The address field is used to store an address of data to be read or written, the length field is used to store a length of data to be read or written, the count field is used to store a count value, the flag field is used to indicate whether the descriptor is available and has been used up, for example, when the flag field is 01, the descriptor is available and has not been used up, and when the flag field is 10, the descriptor is not available and has been used up.
In some possible embodiments, the state information of the host queue includes: the current position of the first head pointer of the host queue, and so on. The state information of the host queue may be stored in the memory of the CPU. When the simulator in the DPU is abnormal, the state information in the host queue in the memory of the CPU is not lost.
In some possible embodiments, a hardware queue may be provided in the DPU, the hardware queue for storing the second descriptor. In a specific embodiment, the second descriptor is used to store metadata, which includes an 8-byte address field, a 4-byte length field, a 2-byte count field, and a 2-byte flag field. The address field is used to store an address of data to be read or written, the length field is used to store a length of data to be read or written, the count field is used to store a count value, the flag field is used to indicate whether the descriptor is available and has been used up, for example, when the flag field is 01, the descriptor is available and has not been used up, and when the flag field is 10, the descriptor is not available and has been used up. When an exception occurs in the simulator in the DPU, the hardware queues will be lost.
In some possible embodiments, the state information of the hardware queue includes: the current position of the second head pointer of the hardware queue, and so on. The DPU does not store the state information of the hardware queue in the nonvolatile storage medium, because the state information of the hardware queue is constantly changing, and when the state information of the hardware queue is stored in the nonvolatile storage medium, the state information of the hardware queue is always outdated, which has no meaning. When an exception occurs in the simulator in the DPU, state information in the hardware queues will be lost.
In some possible embodiments, a host queue of the PCIE device set in the CPU and a hardware queue of the PCIE device set in the DPU are matched with each other, so that data transmission of the PCIE device in the CPU and the DPU is achieved. In order to ensure that the data transmission of the hardware queue and the host queue can be well matched, the sizes and formats of descriptors of the hardware queue and the host queue can be ensured to be the same. The process of data transmission between the CPU and PCIE end device will be described in a specific embodiment. Assuming that descriptors 1 through 30 are stored in the host queue, the first head pointer of the host queue points to descriptor 10 in the host queue, and the flag fields in descriptors 10-19 in the host queue are all set to 01. The second head pointer of the hardware queue points to the descriptor 10 of the hardware queue. The CPU sends the descriptors 10-19 to the DPU via DMA technology. When the DPU receives the descriptor 10 in the host queue, the descriptor is stored in the descriptor 10 in the hardware queue; when the DPU receives the descriptor 11 in the host queue, the descriptor is stored in the descriptor 11 in the hardware queue; …; until the DPU receives a descriptor 19 in the host queue, the descriptor is stored into the descriptor 19 in the hardware queue. After the DPU receives the descriptors 10-19, data transfer between the CPU and the DPU is achieved by DMA techniques based on the addresses in the address fields and the lengths in the length fields in the descriptors 10-19. After the transfer of data between the CPU and the DPU corresponding to descriptors 10-19, the first head pointer points to the descriptor 20 of the host queue and the second head pointer points to the descriptor 20 of the hardware queue.
In some possible embodiments, the descriptor of the hardware queue of the DPU and the state information of the hardware queue are lost when the simulator of the DPU is abnormal, but the host queue is always stored in the memory of the CPU, so that when the state information of the hardware queue and the hardware queue is recovered, the host queue in the memory of the CPU can be referred to for recovery. Thus, after the exception recovery of the emulator in the DPU, the state information of the host queue is proactively inferred from the host queue in the CPU memory.
S302: the DPU restores the hardware queue and the state information of the hardware queue according to the state information of the host queue and the host queue.
In some possible embodiments, the DPU restores the hardware queue and the state information of the hardware queue based on the state information of the host queue and the host queue. In a specific embodiment, assume that descriptors 1 through 30 are stored in the host queue, that the first head pointer of the host queue points to descriptor 10 in the host queue, and that the flag fields in descriptors 10-19 in the host queue are all set to 01. The second head pointer of the hardware queue points to the descriptor 10 of the hardware queue. During the transmission of descriptor 13 in the host queue, the simulator of the DPU fails, resulting in the loss of the descriptor in the hardware queue and the loss of state information of the hardware queue. However, the descriptor in the host queue is not lost, and the state information of the host queue is not lost, so that the memory of the host queue can be moved to the memory of the DPU for analysis, and the position of the first pointer of the host queue is resolved, that is, the state information of the host queue is resolved. Because the DPU cannot directly acquire the location information of the host queue, the state information of the host queue can only be deduced from the information of the host queue itself. The DPU may know that the descriptors 10-19 in the host queue need to be transferred to the DPU based on the first head pointer of the host queue pointing to the descriptor 10, with the flag fields in the descriptors 10-19 in the host queue all set to 01. The hardware queues and state information for the hardware queues may then be restored.
S303: the DPU acquires and recovers the state information of at least one peripheral device interconnection extension device stored before the abnormality of the simulator occurs.
In some possible embodiments, the PCIE devices include PCIE bridge devices and PCIE end devices. And the PCIE devices are connected through topological relations. The PCIE end device may provide various functions, for example, the PCIE end device may be a network card, provide a function of network data transmission, may be an audio card, and provide processing on an audio source. The PCIE bridge device is used for connecting a plurality of PCIE terminal devices to form different topological relations. The topology of PCIE devices may include one or more of star relationships, tree relationships, ring relationships, bus relationships, and so forth. Taking the topological relation of the PCIE devices in fig. 1 as an example, the first PCIE device is used as a root node of the tree, and the second PCIE device, the third PCIE device, and the fourth PCIE device are used as leaf nodes of the tree and are respectively connected to the root node and the first PCIE device.
In some possible embodiments, the PCIE devices and the topology of the PCIE devices are modeled by the DPU. The hardware resources of the DPU are used to provide at least one PCIE device and hardware logic of the topology relationship of the at least one PCIE device. A simulator may be installed in DPU 12 for providing at least one PCIE device and software logic for the topology of the at least one PCIE device. DPU 12 negotiates interactions between software logic and hardware logic to implement a simulation of at least one PCIE device.
In some possible embodiments, the status information of the PCIE device includes a configuration space status of the PCIE bridge device, and so on. The configuration space states of the PCIE bridge device include one or more of PCIE configuration space header states and currently used capability set states. The configuration space state of the PCIE end device includes one or more of a PCIE configuration space header state and a currently used capability set state. The state information of the PCIE end device includes one or more of a configuration space state of the PCIE end device, attribute information of the PCIE end device, and a current working state of the PCIE end device. The attribute information of the PCIE terminal device includes one or more of the number of queues of the PCIE terminal device, the queue depth of the PCIE terminal device, the maximum transmission unit of the PCIE terminal device, and the media access control address of the PCIE terminal device; the current working state of the PCIE end device includes one or more of characteristics negotiated with a driver of the processor, virtual local area network information, promiscuous mode information, a queue base address of the hardware queue, and an interrupt number used by the hardware queue.
In some possible embodiments, the status information in the register of the PCIE device generally changes slowly during the use of the PCIE device, so that the status information of the PCIE device may be saved to the nonvolatile storage medium of the DPU in real time, and after the abnormal recovery of the DPU, the status information of the PCIE device may be read from the nonvolatile storage medium and recovered.
After the hardware queue, the state information of the hardware queue and the state information of the PCIE device are recovered, normal services can be recovered between the CPU and the DPU.
In the above scheme, the topology relationship between the peripheral interconnection extension device and the peripheral interconnection extension device can be simulated by the DPU, the state information of the peripheral interconnection extension device in the memory of the data processor is stored in the nonvolatile storage medium in real time, the host queue is set in the memory of the processor, the hardware queue of the peripheral interconnection extension device is set in the data processor, when the DPU is abnormal, the descriptor in the hardware queue will be lost, the state information of the hardware queue will not be lost, the descriptor in the host queue will not be lost, the state information of the host queue will not be lost, after the DPU is abnormal, the DPU can read and recover the state information of the peripheral interconnection extension device from the nonvolatile storage medium, and actively derive the state information of the host queue according to the host queue in the CPU memory, recover the hardware queue and the state information of the hardware queue according to the host queue, and the service between the CPU and the peripheral interconnection extension device can be recovered after the recovery is completed.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions which, when loaded and executed on a computer, produce, in whole or in part, a process or function in accordance with embodiments of the present invention. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one network site, computer, server, or data center to another network site, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer and may also be a data storage device, such as a server, data center, etc., that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape, etc.), an optical medium (e.g., DVD, etc.), or a semiconductor medium (e.g., solid state disk), etc.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
Claims (8)
1. An abnormality automatic recovery system for a peripheral device interconnect extension apparatus, comprising:
a data processor for providing at least one peripheral device interconnect extension device and hardware logic of a topology relationship of the at least one peripheral device interconnect extension device, the data processor further provided with a simulator for providing at least one peripheral device interconnect extension device and software logic of a topology relationship of the at least one peripheral device interconnect extension device and negotiating interactions with the hardware logic to enable simulation of the at least one peripheral device interconnect extension device, the data processor storing state information of the at least one peripheral device interconnect extension device in real time in a nonvolatile storage medium, the at least one peripheral device interconnect extension device having a hardware queue;
the processor is used for driving the at least one peripheral device interconnection extension device through a driving program, and setting a host queue in a memory of the processor, wherein the hardware queue and the host queue are mutually matched to realize data transmission of direct memory access between the processor and the at least one peripheral device interconnection extension device, state information of the host queue is recorded in the memory of the processor, the state information of the host queue comprises a current position of a first head pointer, the state information of the hardware queue comprises a current position of a second head pointer, the host queue is used for storing a first descriptor, the hardware queue is used for storing a second descriptor, the first head pointer is used for pointing to one of the first descriptors in the host queue, and the second head pointer is used for pointing to one of the second descriptors in the hardware queue;
The data processor is further configured to actively move the memory of the host queue to the memory of the DPU for analysis after the simulator is abnormally recovered, analyze the position of the first head pointer of the host queue, recover the hardware queue and the second head pointer of the hardware queue according to the position of the first head pointer of the host queue and the host queue, and acquire and recover the state information of the at least one peripheral device interconnection expansion device stored in the nonvolatile storage medium of the DPU before the simulator is abnormally recovered;
in the case that the number of peripheral device interconnection expansion devices is multiple, the multiple peripheral device interconnection expansion devices comprise peripheral device interconnection expansion bridge devices and peripheral device interconnection expansion end devices, the state information of the peripheral device interconnection expansion bridge devices comprises configuration space states of the peripheral device interconnection expansion bridge devices, and the state information of the peripheral device interconnection expansion end devices comprises one or more of configuration space states of the peripheral device interconnection expansion end devices, attribute information of the peripheral device interconnection expansion end devices and current working states of the peripheral device interconnection expansion end devices.
2. The system of claim 1, wherein the data processor is further configured to send a non-support response to the processor if a request is received from the processor during the simulator exception.
3. The system of claim 1, wherein the configuration space state of the peripheral device interconnect expansion bridge device comprises one or more of a peripheral device interconnect expansion configuration space header state and a currently used capability set state; the configuration space state of the peripheral device interconnection extension end equipment comprises one or more of a peripheral device interconnection extension configuration space head state and a currently used capability set state; the attribute information of the peripheral device interconnection extension end equipment comprises one or more of the number of queues of the peripheral device interconnection extension end equipment, the depth of the queues of the peripheral device interconnection extension end equipment, the maximum transmission unit of the peripheral device interconnection extension end equipment and the media access control address of the peripheral device interconnection extension end equipment; the current working state of the peripheral device interconnection extension end equipment comprises one or more of characteristics negotiated with a driver of the processor, virtual local area network information, promiscuous mode information, a queue base address of the hardware queue and an interrupt number used by the hardware queue.
4. The system of claim 1 or 2, wherein the at least one peripheral interconnect extension device emulated by the data processor is not available in the event of an exception to the emulator.
5. The automatic recovery method for the abnormality of the peripheral device interconnection extension equipment is characterized by being applied to an automatic recovery system for the abnormality of the peripheral device interconnection extension equipment, wherein the automatic recovery system for the abnormality of the peripheral device interconnection extension equipment comprises a data processor and a processor which are communicated with each other, the data processor comprises a simulator, the data processor is used for providing at least one peripheral device interconnection extension equipment and hardware logic of the topological relation of the at least one peripheral device interconnection extension equipment, the data processor is also provided with the simulator, the simulator is used for providing at least one peripheral device interconnection extension equipment and software logic of the topological relation of the at least one peripheral device interconnection extension equipment, and negotiating interaction with the hardware logic to simulate the at least one peripheral device interconnection extension equipment, and the data processor stores state information of the at least one peripheral device interconnection extension equipment in real time and has a hardware queue; the processor is used for driving the at least one peripheral device interconnection extension device through a driving program, and setting a host queue in a memory of the processor, wherein the hardware queue and the host queue are mutually matched to realize data transmission of direct memory access between the processor and the at least one peripheral device interconnection extension device, the processor is also used for recording state information of the host queue in the memory, the state information of the host queue comprises a current position of a first head pointer, the state information of the hardware queue comprises a current position of a second head pointer, the host queue is used for storing a first descriptor, the hardware queue is used for storing a second descriptor, the first head pointer is used for pointing to one of the first descriptors in the host queue, and the second head pointer is used for pointing to one of the second descriptors in the hardware queue; after the simulator is recovered abnormally, the data processor actively moves the memory of the host queue to the memory of the DPU for analysis and analyzes the position of the first head pointer of the host queue,
The data processor restores the hardware queue and the second head pointer of the hardware queue based on the location of the first head pointer of the host queue and the host queue,
the data processor acquires and restores the state information of the at least one peripheral device interconnection extension device stored in the nonvolatile storage medium of the DPU before the abnormality of the simulator occurs;
in the case that the number of peripheral device interconnection expansion devices is multiple, the multiple peripheral device interconnection expansion devices comprise peripheral device interconnection expansion bridge devices and peripheral device interconnection expansion end devices, the state information of the peripheral device interconnection expansion bridge devices comprises configuration space states of the peripheral device interconnection expansion bridge devices, and the state information of the peripheral device interconnection expansion end devices comprises one or more of configuration space states of the peripheral device interconnection expansion end devices, attribute information of the peripheral device interconnection expansion end devices and current working states of the peripheral device interconnection expansion end devices.
6. The method of claim 5, wherein the method further comprises:
the data processor sends an unsupported response to the processor if a request is received by the processor during the data processor exception.
7. The method of claim 5, wherein the configuration space state of the peripheral device interconnect expansion bridge device comprises one or more of a peripheral device interconnect expansion configuration space header state and a currently used capability set state; the configuration space state of the peripheral device interconnection extension end equipment comprises one or more of a peripheral device interconnection extension configuration space head state and a currently used capability set state; the attribute information of the peripheral device interconnection extension end equipment comprises one or more of the number of queues of the peripheral device interconnection extension end equipment, the depth of the queues of the peripheral device interconnection extension end equipment, the maximum transmission unit of the peripheral device interconnection extension end equipment and the media access control address of the peripheral device interconnection extension end equipment; the current working state of the peripheral device interconnection extension end equipment comprises one or more of characteristics negotiated with a driver of the processor, virtual local area network information, promiscuous mode information, a queue base address of the hardware queue and an interrupt number used by the hardware queue.
8. A data processor, comprising: at least one processing core and at least one memory for storing instructions that, when executed by the at least one processing core, are capable of implementing the method of any of claims 5 to 7.
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