CN116782662A

CN116782662A - Memory device and method of forming the same

Info

Publication number: CN116782662A
Application number: CN202310602434.8A
Authority: CN
Inventors: 陈逸轩; 陈坤意; 王怡情; 丁裕伟; 涂国基; 黄国钦; 庄学理
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-26
Filing date: 2023-05-26
Publication date: 2023-09-19

Abstract

A method of forming a memory device according to an embodiment of the present application includes: forming a trench in a first substrate of a first wafer; depositing a data storage element in the trench; performing a heat treatment on the first wafer to improve crystallization in the data storage element; forming a first redistribution layer over a first substrate; forming a transistor in a second substrate of a second wafer; forming a second redistribution layer over the second substrate; and bonding the first wafer with the second wafer after performing the heat treatment. The data storage element is electrically coupled to the transistor through the first redistribution layer and the second redistribution layer. Embodiments of the application also relate to memory devices.

Description

Memory device and method of forming the same

Technical Field

Embodiments of the application relate to memory devices and methods of forming the same.

Background

The Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs.

The scaling process has prompted circuit designers to move devices from the front-end-of-line (FEOL) level to the back-end-of-line (BEOL) level where interconnect structures are present. For example, ferroelectric-based memory devices may be formed at BEOL levels. Forming ferroelectric-based memory devices at the BEOL level is not without challenges. For example, when growing ferroelectric films, it may be difficult to achieve the desired crystallization due to insufficient heat treatment, as excessive heat may damage FEOL components. While existing processes and structures of ferroelectric-based memory devices are generally adequate for their intended purposes, they are not satisfactory in all respects.

Disclosure of Invention

Some embodiments of the application provide a method of forming a memory device, comprising: forming a trench in a first substrate of a first wafer; depositing a data storage element in the trench; performing a heat treatment on the first wafer to improve crystallization in the data storage element; forming a first redistribution layer over the first substrate; forming a transistor in a second substrate of a second wafer; forming a second redistribution layer over the second substrate; and bonding the first wafer with the second wafer after performing the thermal treatment such that the data storage elements are electrically coupled to the transistors through the first and second redistribution layers.

Other embodiments of the present application provide a method of forming a memory device, comprising: forming a plurality of Ferroelectric Tunnel Junctions (FTJ) in a first wafer; performing a heat treatment to improve crystallization of a ferroelectric film in the ferroelectric tunnel junction; forming a first redistribution layer on the first wafer, wherein the first redistribution layer includes a plurality of first bond pads associated with the plurality of ferroelectric tunnel junctions; forming a plurality of transistors in a second wafer; forming a second redistribution layer on the second wafer, wherein the second redistribution layer includes a plurality of second bond pads associated with the plurality of transistors; and bonding the first wafer with the second wafer after the heat treatment is performed, such that the plurality of first bonding pads are bonded with the plurality of second bonding pads.

Still further embodiments of the present application provide a memory device comprising: a first substrate including a plurality of transistors; a first distribution layer over the first substrate, the first distribution layer including a plurality of first bond pads electrically coupled to the plurality of transistors; a second distribution layer over the first distribution layer, the second distribution layer comprising a plurality of second bond pads in physical contact with the plurality of first bond pads; and a second substrate over the second distribution layer, the second substrate including a plurality of data storage elements embedded in the second substrate, each of the plurality of data storage elements having a first electrode electrically coupled to one of the plurality of second bond pads.

Drawings

The invention is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a diagram of a memory system in accordance with aspects of the present invention.

Fig. 2, 3A, 3B, 3C, and 3D illustrate cross-sectional views of various embodiments of data storage elements in memory cells in accordance with various aspects of the present invention.

Fig. 4A and 4B are schematic diagrams of some embodiments of memory arrays comprising a plurality of memory cells, according to various aspects of the invention.

Fig. 5 and 6 illustrate an exemplary integrated circuit assembly and a semiconductor device including a bonded integrated circuit assembly, respectively, in accordance with various aspects of the present invention.

Fig. 7, 8 and 9 illustrate exemplary semiconductor wafers including exemplary integrated circuit components according to exemplary embodiments of the invention.

Fig. 10 illustrates a flow chart of a method for forming a memory device in accordance with various aspects of the invention.

Fig. 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 and 26 illustrate cross-sectional views of a memory device during a manufacturing process according to the method of fig. 10 in accordance with one or more aspects of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Furthermore, when values or ranges of values are described using "about," "approximately," etc., as would be understood by one of ordinary skill in the art, the term is intended to include values within a reasonable range that take into account variations inherently present during manufacture. For example, a value or range of values includes a reasonable range of values including the value described, such as within +/-10% of the value described, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may include a size range from 4.5nm to 5.5nm, with a manufacturing tolerance of +/-10% associated with depositing the material layer as known to one of ordinary skill in the art. Still further, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present invention relates generally to manufacturing memory devices and, more particularly, to manufacturing logic devices and memory arrays in separate wafers and bonding the separate wafers together by a wafer-on-wafer (WOW) process.

IC fabrication process flows are generally divided into three categories: front end of line (FEOL) processes, middle of line (MEOL) processes, and back end of line (BEOL) processes. FEOL processes typically include processes related to the fabrication of IC devices, such as transistors. For example, FEOL processes may include forming isolation features, channel features, gate structures, and source and drain features (commonly referred to as source/drain features). MEOL processes typically include processes related to the fabrication of contacts to multi-gate devices, such as fin field effect transistors (finfets) or full-gate-all-around (GAA) transistors (also known as multi-bridge channel (MBC) transistors or Surrounding Gate Transistors (SGTs)). Exemplary MEOL features include contacts to gate structures and/or source/drain features of multi-gate transistors. BEOL processes typically include processes related to the fabrication of multi-layer interconnect (MLI) components that interconnect FEOL IC components, thereby enabling operation of the IC device. To save substrate area at FEOL levels, larger devices of levels that do not require lithographic precision for transistors can be moved to BEOL structures. For example, memory devices such as magnetic-based memory devices (e.g., magnetic Tunnel Junction (MTJ) memory devices) and ferroelectric-based memory devices (e.g., ferroelectric Tunnel Junction (FTJ) memory devices) may be fabricated at the BEOL level.

Ferroelectric-based memory devices (or ferroelectric memory devices) are non-volatile memories (i.e., memories that can store data without a power source). Ferroelectric memory devices, such as ferroelectric field effect transistors (fefets), ferroelectric random access memories (ferams or FRAMs), or Ferroelectric Tunnel Junction (FTJ) memory devices, typically have a ferroelectric film (also referred to as a ferroelectric layer) sandwiched between a bottom electrode and a top electrode. An interface layer, also referred to as a non-polarizing layer, is formed between the ferroelectric film and one of the adjacent electrodes. The formation of the non-polarized layer is important to create remnant polarization, which the ferroelectric memory device relies on to function properly. In FeRAM, a thick ferroelectric film is sandwiched between two electrodes, and the remnant polarization is switched by applying an electric field between the two electrodes. While thick ferroelectric films make it relatively easy to form a non-polarized layer, the read-out current across the thick ferroelectric film tends to be low, which presents challenges for miniaturization or integration into BEOL structures. FTJ memories, on the other hand, include thin ferroelectric films (measured in nanometers) that allow quantum mechanical tunneling. However, when the ferroelectric film becomes thinner (for example, less than 5 nm), formation of the non-polarized layer becomes difficult, and the polarization characteristics of the ferroelectric film start to disappear, which leads to malfunction of the memory device.

It has been observed that adequate heat treatment of ferroelectric films in ferroelectric memory devices is advantageous for achieving crystallization and good ferroelectricity. In some prior art, the heat treatment of the ferroelectric layer is carefully performed, as excessive heat may cause deterioration of FEOL structures, such as gate structures in transistors. The temperature of the heat treatment is often kept below 400 ℃, which may cause insufficient crystallization of the ferroelectric film.

The present invention provides processes and ferroelectric memory devices (e.g., FTJ memory structures) to achieve crystallization of ferroelectric layers without causing undesirable damage to the FEOL structures. The ferroelectric memory device of the present invention uses wafer-on-wafer processing to fabricate logic devices (typically formed in FEOL) and ferroelectric memory devices (including ferroelectric films) (typically formed in MEOL or BEOL) respectively to overcome thermal constraints and prevent high temperatures from affecting elements in the logic device. With wafer-on-wafer technology, there is no thermal limitation in forming the ferroelectric film, as the FEOL structures are located in different wafers and are not subject to the thermal treatment of the wafer in which the ferroelectric film is located. The wafer containing the ferroelectric film may be subjected to a heat treatment having a temperature greater than about 550 ℃, such as between about 550 ℃ and about 1000 ℃, without subjecting the FEOL structure to excessive heat. Accordingly, the crystalline quality of the ferroelectric film is increased and the performance of the ferroelectric memory device is improved with little or no risk of damaging the FEOL structure. Throughout the present invention, embodiments based on FTJ memory devices are presented for illustrative purposes. Of course, the FTJ memory device shown is merely an example and is not intended to be limiting. As discussed above, the ferroelectric film supporting ferroelectric memory applications may be applied to FeFET memory devices, feRAM memory devices, or FTJ memory devices. In addition, many other modern electronic devices including electronic memories may also benefit from wafer-on-wafer processing by processing MEOL/BEOL structures separately from FEOL structures. Examples of next generation electronic memories include Resistive Random Access Memory (RRAM), phase Change Random Access Memory (PCRAM), and Magnetoresistive Random Access Memory (MRAM).

Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Like reference numerals refer to like parts throughout the present invention unless otherwise specifically described.

FIG. 1 is a diagram of a memory system 100 according to some embodiments. Memory system 100 includes a memory controller 105 and a memory array 120. Memory array 120 is a hardware component that stores data. In one aspect, the memory array 120 is embodied as a semiconductor memory device. The memory array 120 includes a plurality of memory circuits or memory cells 125. The memory cells 125 may be arranged in a two-dimensional array or a three-dimensional array. The memory array 120 also includes bit lines BL0, BL 1..blk (each extending in a first direction (e.g., X-direction)) and word lines WL0, wl1..wlj (each extending in a second direction (e.g., Y-direction)). The word line WL and the bit line BL may be conductive metal or conductive tracks. In one aspect, each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and may operate according to a voltage or current through the corresponding word line WL and the corresponding bit line BL. Each memory cell 125 may be coupled to a corresponding word line WL and a corresponding bit line BL. Because the memory cells 125 are arranged at the intersections of the BL and WL, such a memory system 100 is also referred to as a cross-point memory architecture.

In a cross-point memory array, memory cells 125 may include data storage elements. In some embodiments, the resistance of the data storage element varies according to the data state of the data storage element. For example, the data storage element may have a low resistance in a first data state and a high resistance in a second data state. In other embodiments, the capacitance of the data storage element or some other suitable parameter varies depending on the data state of the data storage element. In some embodiments, the data storage element is a metal-insulator-metal (MIM) stack, and the memory cell 125 may be a resistive memory cell. In a further implementation of the embodiment, the data storage element is an FTJ or an MTJ. Other structures for the data storage elements and/or other memory cell types for the memory cells 125 are also possible.

When the FTJ is configured as a data storage element in a memory cell, the cross-point memory array may, for example, include a plurality of one-transistor-FTJ (1T 1F) memory cells arranged at intersections of bit lines and source lines, respectively. The transistors are configured to pass current through the FTJ when biased above a respective threshold voltage. By properly biasing the bit line and the source line, a 1T1F memory cell at the intersection of the bit line and the source line can be selected and the opposite state written. When a 1T1F memory cell is selected, the other bit lines and source lines may be biased at a midpoint voltage to turn off the unselected memory cells. To achieve higher densities, cross-point memory architectures may alternatively implement a 1TNF configuration, where multiple FTJ memory cells may share one transistor without the need for cross-coupled transistors for each memory cell.

The memory controller 105 may write data to the memory array 120 or read data from the memory array 120 according to electrical signals through the word lines WL and the bit lines BL. In other embodiments, memory system 100 includes more, fewer, or different components than those shown in FIG. 1. In some embodiments, memory array 120 includes additional lines (e.g., select lines, reference control lines, power rails, etc.).

Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line controller 112, word line controller 114, and timing controller 110. In one configuration, word line controller 114 is a circuit that provides voltage or current through one or more word lines WL of memory array 120, and bit line controller 112 is a circuit that provides or senses voltage or current through one or more bit lines BL of memory array 120. In one configuration, the timing controller 110 is a circuit that provides a control signal or clock signal to synchronize the operation of the bit line controller 112 and the word line controller 114. The bit line controller 112 may be coupled to bit lines BL of the memory array 120, and the word line controller 114 may be coupled to word lines WL of the memory array 120. In one example, to write data to memory cell 125, word line controller 114 provides a voltage or current to memory cell 125 through a word line WL coupled to memory cell 125, and bit line controller 112 applies a bias voltage to memory cell 125 through a bit line BL coupled to memory cell 125. In one example, to read data from memory cell 125, word line controller 114 provides a voltage or current to memory cell 125 through word line WL coupled to memory cell 125, and bit line controller 112 senses a voltage or current corresponding to data stored by memory cell 125 through bit line BL coupled to memory cell 125. In some embodiments, memory controller 105 includes more, fewer, or different components than those shown in FIG. 1.

FIG. 2 shows data storage elements 128 as in memory cells 125, memory cells 125 being building blocks of memory array 120 as shown in FIG. 1. Data storage element 128 includes FTJ 130 embedded in substrate 132. FTJ 130 includes at least a layer of ferroelectric material, which generally refers to a material that exhibits polarization when an electric field is applied thereto and continues to exhibit polarization when the electric field is removed (or reduced). Thus, ferroelectric materials are also referred to as polarized materials. Typically, ferroelectric materials have an inherent electric dipole that can be switched between polarization states by an electric field, such as switching between a first polarization state and a second polarization state. The first polarization state may correspond to a first data state, such as a logical "1" (e.g., depending on a first resistance or a first capacitance of the ferroelectric memory device). The second polarization state may correspond to a second data state, such as a logic "0" (e.g., depending on a second resistance or a second capacitance of the ferroelectric memory device).

In the illustrated embodiment, FTJ 130 is disposed in a deep trench formed in substrate 132. Deep trenches are typically formed with an aspect ratio (depth to width). Thus, the sidewalls of the various layers (including bottom electrode 134, interface layer 136, discontinuous seed structure 138 (also referred to as ferroelectric facilitating structure), ferroelectric film 140, and top electrode 142) extend further down in substrate 132. The charged area can be increased accordingly, which saves FTJ volume and helps achieve a high density layout. In some embodiments, the aspect ratio of the deep trench in which FTJ 130 is deposited is in the range from about 5 to about 30.

The substrate 132 comprises a semiconductor material, such as silicon. In one embodiment, the substrate 132 may comprise other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In this embodiment, the substrate 132 is a p-type semiconductor substrate (acceptor type) or an n-type semiconductor substrate (donor type). Optionally, the substrate 132 comprises another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. In yet another alternative embodiment, substrate 132 is a semiconductor-on-insulator (SOI). In other alternative embodiments, the substrate 132 may include a doped epitaxial layer, a graded semiconductor layer, and/or a semiconductor layer located on top of a different type of semiconductor layer, such as a silicon layer on a silicon germanium layer. In further implementations of embodiments, the substrate 132 may include a dielectric layer, such as an inter-layer dielectric (ILD) layer on top of a semiconductor layer, such as a silicon layer, and deep trenches are formed in the ILD layer during BEOL processes.

The bottom electrode 134 can be conformally deposited on the sidewalls and bottom of the deep trench. The bottom electrode 134 also covers a portion of the top surface of the substrate 132 that is outside the deep trench. The bottom electrode 134 may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), alloys thereof, and the like. In some embodiments, the bottom electrode 134 may be formed of TiN, ru, W, mo, taN or the like. The bottom electrode 134 may be deposited using any suitable deposition process. For example, suitable deposition processes may include Physical Vapor Deposition (PVD), sputtering, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or combinations thereof. The thickness of the bottom electrode 134 may range from 10nm to 100nm, but smaller and larger thicknesses may also be used.

An interfacial layer 136 may be conformally deposited on the bottom electrode 134. Interface layer 136 comprises a non-polarized material. Interface layer 136 is also referred to as a non-polarizing layer. Interfacial layer 136 may comprise a high-k dielectric material having a dielectric constant greater than 3.9 and may include, but is not limited to, silicon nitride (SiN) _x ) Hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide ((Hf) _0.5 Zr _0.5 O ₂ ) (HZO)), tantalum oxide (Ta ₂ O ₅ ) Alumina (Al) ₂ O ₃ ) Lanthanum aluminate (LaAlO) ₃ ) Hafnium oxide-aluminum oxide (HfO) ₂ -Al ₂ O ₃ ) Zirconium oxide (ZrO) ₂ ) Magnesium oxide (MgO), combinations thereof, and the like. Other suitable dielectric materials are within the scope of the present invention. Interfacial layer 136 may be deposited using any suitable deposition process. For example, suitable deposition processes may include Physical Vapor Deposition (PVD), sputtering, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or combinations thereof. The thickness of interface layer 136 may be less than about 2nm. The thickness is not insignificant. If the thickness of interface layer 136 is greater than about 2nm, the read current flowing through FTJ 130 may become too small to be sensed and/or the difference between the logic states may become too small to be discernable.

The seed structure 138 may be a discontinuous layer of metal particles, which may include discrete metal atoms or discrete metal nanoparticles. The seed structure 138 may be a discontinuous layer such that the seed structure 138 does not form a conductive path on the surface of the interface layer 136. In various embodiments, seed structure 138 does not form a continuous metal layer on interfacial layer 136. The seed structure 138 may have a thickness, and/or the seed metal particles may have a thickness of from about(angstrom) to about->Average particle size within the rangeSuch as from about->To about->Or from about->To about->In some embodiments, the seed structure 138 may be a partial monolayer of seed metal atoms. For example, the seed structure 138 may include from about 1/4 to about 3/4 of the seed metal atoms included in a complete monolayer of seed metal atoms. The seed structure 138 may be formed by depositing a seed metal using any suitable deposition process. For example, the seed structure 138 may be formed using Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. However, other suitable processes for forming the discontinuous seed metal layer may be used.

The ferroelectric film 140 includes a ferroelectric material (polarizing material). The ferroelectric film 140 is also referred to as a polarizing layer. The ferroelectric film 140 may be a single-layer or multi-layer structure such as a first ferroelectric layer disposed over a second ferroelectric layer, wherein the first ferroelectric layer and the second ferroelectric layer have different compositions. The ferroelectric material may be a high-k dielectric material having an orthorhombic crystal structure, such as a dielectric material having a dielectric constant (k) greater than about 28 (e.g., k.gtoreq.28). In some embodiments, the ferroelectric film 140 includes a metal oxide material or a metal oxynitride material. For example, the ferroelectric film 140 may include a hafnium oxide-based material or a zirconium oxide-based material. In further implementations of the examples, the ferroelectric film 140 may include hafnium oxide (e.g., hf _x O _y ) Hafnium zirconium oxide (e.g., hf) _x Zr _z O _y ) (also known as HZO), hafnium aluminum oxide (e.g., hf) _x Al _z O _y ) Hafnium lanthanum oxide (e.g. Hf) _x La _z O _y ) Hafnium cerium oxide (e.g. Hf) _x Ce _z O _y ) Hafnium silicon oxide (Hf) _x SiO _y ) Hafnium gadolinium oxide (e.g. Hf _x Gd _z O _y ) Other suitable Hf-based _x O _y Wherein x, y, z are atomic percentages, or combinations thereof. In another example, ferroelectric film 140 may include Zr-based _j O _k Wherein j, k, z are atomic percent. The ferroelectric film 140 may be formed by depositing a ferroelectric material using any suitable deposition method, such as PVD, spin coating and annealing, sputtering, CVD, ALD, plasma Enhanced Chemical Vapor Deposition (PECVD), spray pyrolysis, pulsed Laser Deposition (PLD), or combinations thereof. During the deposition process, the seed metal may promote the growth of a desired crystalline phase in the ferroelectric film 140. For example, when the ferroelectric film 140 includes a Hf-based ferroelectric material, the primary crystal phase of the ferroelectric film 140 may have an orthorhombic crystal structure. If the ferroelectric film 140 includes a Pb-based material such as PBT or PZT, the primary crystal phase of the ferroelectric film 140 may have a tetragonal crystal structure. In particular, the primary crystalline phase may comprise at least 50% of the ferroelectric film 140, such as from about 60% to about 99.9%, or from about 70% to about 95%. In some embodiments, the thickness of the ferroelectric film 140 is less than about 5nm. The thickness is not insignificant. If the thickness of the ferroelectric film 140 is greater than about 5nm, quantum mechanical tunneling effects may become insignificant and deteriorate FTJ performance. In some embodiments, the ferroelectric film 140 may be thermally annealed to further improve its crystal structure. For example, the ferroelectric film 140 may be annealed using Excimer Laser Annealing (ELA), flash Lamp Annealing (FLA), furnace annealing, or the like.

A top electrode 142 may be deposited on the ferroelectric film 140. The top electrode 142 may include and/or may consist essentially of at least one of a transition metal, a conductive metal nitride, and a conductive metal carbide. Exemplary metallic materials that may be used for the top electrode 142 include, but are not limited to TiN, taN, WN, W, cu, al, ti, ta, ru, co, mo, pt, alloys thereof, and/or combinations thereof. Other suitable materials within the contemplation of the invention may also be used. For example, the top electrode 142 may include and/or may consist essentially of an elemental metal, such as W, cu, ti, ta, ru, co, mo or Pt. The thickness of the top electrode 142 may range from 10nm to 100nm, but smaller and larger thicknesses may also be used.

Still referring to fig. 2, interconnect structure 150 is disposed over FTJ 130. Interconnect structure 150 is typically formed in a BEOL process and is configured to electrically couple FTJ 130 with another layer. In some embodiments, interconnect structure 150 electrically couples FTJ 130 with overlying metal layer 160. Interconnect structure 150 may include conductive vias 152 and 154 and an interlayer dielectric (ILD) 156. Conductive vias 152 and 154 are formed in ILD 156 and are electrically coupled to bottom electrode 134 and top electrode 142 of FTJ 130, respectively. The conductive vias 152 and 154 may be formed of conductive materials such as aluminum, gold, silver, and tungsten. ILD 156 may be formed from a variety of dielectric materials such as oxides (e.g., ge oxide), oxynitrides (e.g., gaP oxynitrides), silicon dioxide (SiO ₂ ) Nitrogen-containing oxides (e.g. nitrogen-containing SiO) ₂ ) Nitrogen doped oxide (e.g. N ₂ Implanted SiO ₂ ) Silicon oxynitride (Si) _x O _y N _z ) Etc.

A metal layer 160 is disposed over the interconnect structure 150. Metal layer 160 is configured to electrically couple FTJ 130 to a redistribution layer for electrical connection with devices or components in another substrate (e.g., another wafer). Metal layer 160 may include metal lines 162 and 164 electrically coupled to conductive vias 152 and 154, respectively. The metal lines 162 and 164 may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu).

Fig. 3A-3D illustrate an alternative embodiment of the data storage element 128 as shown in fig. 2. Referring to fig. 3A, one difference from the embodiment depicted in fig. 2 is that the interface layer 136 is sandwiched between the ferroelectric film 140 and the top electrode 142. Thus, a seed structure 138 is formed on the bottom electrode 134, and a ferroelectric film 140 is formed on the seed structure 138 and positioned below the interfacial layer 136.

Referring to fig. 3B, one difference from the embodiment depicted in fig. 2 is that deep trenches are formed inside doped region 146. Doped region 146 is located on the substrate 132. In some embodiments, doped region 146 is a p-well structure, an n-well structure, or a double-well structure. The doping concentration in doped region 146 is greater than substrate 132. In an embodiment, doped region 146 includes a first dopant type opposite to a second dopant type of substrate 132. For example, substrate 132 is an n-type substrate and doped region 146 is a p-type well. Doped region 146 is configured with substrate 132 to reverse bias the p-n junction to inhibit substrate current leakage. Optionally, FTJ 130 may also include a dielectric layer 133 under bottom electrode 134, with or without doped region 146. Dielectric layer 133 provides electrical insulation between FTJ 130 and substrate 132. In some embodiments, dielectric layer 133 is made of a dielectric material, such as a high-k dielectric material. Examples of high-k dielectric materials include HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. In addition, the thickness of the dielectric layer 133 is designed to be relatively thin. This will save volume in the deep trenches. In some embodiments, the thickness of the dielectric layer 133 is less than the thickness of the ferroelectric film 140.

Still referring to fig. 3B, yet another difference from the embodiment depicted in fig. 2 is that the top surfaces of other layers in FTJ 130 (including dielectric layer 133, interface layer 136, ferroelectric film 140) are covered except that portions of the top surfaces of bottom electrode 134 and top electrode 142 are exposed for bonding conductive vias 152 and 154. This may be controlled during the patterning process after depositing the various layers in FTJ 130. FTJ 130 is better protected from damage during subsequent manufacturing processes by exposing sidewalls of those relatively sensitive layers in FTJ 130 rather than the top surface.

Referring to fig. 3C, one difference from the embodiment depicted in fig. 2 is that the trench surrounded by top electrode 142 is filled with plug 148, plug 148 being different from the dielectric material in ILD 156. The plug 148 has a greater aspect ratio than the deep trench. In some embodiments, the aspect ratio of the plug 148 is in the range from about 30 to about 50. In some embodiments, from a cross-sectional view as depicted in FIG. 3C, plug 148 hasParallel side walls. In some embodiments, plug 148 has tapered sidewalls from its top surface to its bottom surface. That is, the plug 148 may have a width measured from its top surface that is greater than a width measured from any other location away from its top surface. Plug 148 enhances the mechanical strength of high aspect ratio FTJ 130 and may also serve as an extension of top electrode 142 if it is formed of a semiconductor material or a conductive material. In some embodiments, plug 148 includes a dielectric material, such as a high-k dielectric material. Examples of high-k dielectric materials include HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, plug 148 comprises a semiconductor material, such as polysilicon. In some embodiments, the plugs 148 comprise a conductive material, such as copper, aluminum, gold, silver, or tungsten, that is different from the top electrode 142.

Referring to fig. 3D, one difference from the embodiment depicted in fig. 2 is that the conductive material of the top electrode 142 completely fills the remaining volume of the deep trench. The conductive material of the top electrode 142 may first be deposited as a bulk material on the substrate 132 and in the deep trenches, and then thinned by a planarization process, such as by a Chemical Mechanical Polishing (CMP) process. Each of the alternative embodiments of the components discussed above in fig. 3A-3D, such as the location of the bulk conductive material of interfacial layer 136 and ferroelectric film 140 in fig. 3A, doped region 146 in fig. 3B, dielectric layer 133 in fig. 3B, overlying top surface in fig. 3B, plug 148 in fig. 3C, and top electrode 142 in fig. 3D, may be independently applied to each of the embodiments depicted in fig. 2 and 3A-3D.

Referring to fig. 4A, a schematic diagram of some embodiments of a memory array 120 is provided, the memory array 120 including a plurality of memory cells 125 in a plurality of rows and a plurality of columns. Memory cells 125 each include a data storage element 128 electrically coupled in series with a control transistor 180 through a bond pad 170. Bond pad 170 is part of a bonded structure from two redistribution layers of two wafers, one redistribution layer disposed in a top wafer in which data storage elements 128 are formed and the other redistribution layer disposed in a bottom wafer in which control transistors 180 (and other FEOL structures) are formed. For example, the memory units 125 may each be as shown and described with respect to fig. 1-3D. As an example, bit lines (e.g., BL0, BL 1..blk) extend laterally along and are electrically coupled to memory cells in a corresponding column of the memory array, while word lines (e.g., WL0, wl1..wlj) extend laterally along and are electrically coupled to memory cells in a corresponding row of the memory array. The subscript identifies the corresponding row or column and K or J is an integer variable representing the column or row in the memory array 120. By appropriately biasing the bit line BL and the word line WL, the memory cell at the intersection of the bit line BL and the word line WL can be selected for reading or writing through the source line (e.g., SL0, sl1..slk). Each data storage element 128 is electrically coupled to a corresponding control transistor 180 through a bond pad 170.

Fig. 4B shows an alternative embodiment of fig. 4A. Because the bond pads 170 typically have a relatively large area, two or more data storage elements 128 may share one bond pad 170 to reduce the number of bond pads required and to achieve a compact design. In the depicted embodiment, two data storage elements 128 may share one bond pad 170 and one control transistor 180. Correspondingly, the number of bond pads and control transistors required is halved. By properly biasing the bit line BL and the word line WL, and properly biasing the adjacent bit line BL, the memory cell 125 at the intersection of the bit line BL and the word line WL can be properly selected for reading or writing (the number is also halved) through the common source line.

Fig. 5 and 6 collectively illustrate an exemplary bonded integrated circuit assembly according to an exemplary embodiment of the present invention. As shown in fig. 5, an exemplary integrated circuit assembly 200 includes a semiconductor substrate (or substrate) 202 having electronic circuitry formed therein and an interconnect structure 204 disposed on the semiconductor substrate 202. In some embodiments, the integrated circuit assembly 200 includes an active region 200A in which electronic circuitry is formed and a peripheral region 200B surrounding the active region 200A. In a back end of line (BEOL) process, a redistribution layer 206 is fabricated on the interconnect structure 204 of the integrated circuit device 200. The redistribution layer 206 formed on the interconnect structure 204 of the integrated circuit component 200 may serve as a bonding layer when the integrated circuit component 200 is bonded with other components. Thus, the redistribution layer 206 is also referred to as a bonding layer 206. In the exemplary embodiment shown in fig. 5, the electronic circuitry formed in semiconductor substrate 202 includes analog and/or digital circuitry located within a semiconductor stack having one or more conductive layers (also referred to as metal layers) interleaved with one or more non-conductive layers (also referred to as insulating layers). However, one skilled in the relevant art will recognize that the electronic circuitry may include one or more mechanical and/or electromechanical devices without departing from the spirit and scope of the invention.

The semiconductor substrate 202 may be made of silicon or other semiconductor materials. Alternatively, the semiconductor substrate 202 may comprise other elemental semiconductor materials, such as germanium. In some embodiments, the semiconductor substrate 202 is made of a compound semiconductor, such as sapphire, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 202 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 202 includes an epitaxial layer. For example, the semiconductor substrate 202 has an epitaxial layer on top of a bulk semiconductor.

The semiconductor substrate 202 may also include isolation features (not shown), such as Shallow Trench Isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation member may define and isolate the individual semiconductor elements. The semiconductor substrate 202 may also include doped regions (not shown). The doped region may be doped with a P-type dopant (such as boron or BF ₂ ) And/or n-type dopants such As phosphorus (P) or arsenic (As). The doped region may be formed directly on the semiconductor substrate 202 in a P-well structure, an N-well structure, or a double-well structure.

An electronic circuit including the above-described isolation feature and semiconductor elements, such as transistors (e.g., metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other suitable elements, may be formed over the semiconductor substrate 102. Various processes may be performed to form the isolation features and semiconductor elements, such as deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. In some embodiments, the electronic circuit including the isolation features and the semiconductor elements is formed in the semiconductor substrate 202 in a front end of line (FEOL) process.

In some embodiments, interconnect structure 204 includes dielectric layers, conductive vias embedded in the dielectric layers, and conductive wiring formed between the dielectric layers. The different layers of the conductive wiring are electrically connected to each other through conductive vias. In addition, the interconnect structure 204 is electrically connected to electronic circuitry formed in the semiconductor substrate 202. In some embodiments, at least one seal ring and at least one alignment mark are formed in the interconnect structure 204, wherein the seal ring and the alignment mark are formed within the peripheral region 200B of the integrated circuit assembly 200. In some examples, the seal ring surrounds the active region 200A of the integrated circuit assembly 200, and the alignment mark is formed in a region outside the seal ring. In some embodiments, a plurality of alignment marks are formed around corners of the integrated circuit assembly 200. The number of seal rings and alignment marks described above is not limited in the present invention.

In the exemplary embodiment shown in fig. 5, the redistribution layer 206 represents a conductive layer (e.g., a metal layer) from among one or more conductive layers of the semiconductor stack for electrically coupling the electronic circuit to other electrical, mechanical, and/or electromechanical devices. For example, the redistribution layer 206 may be used to electrically couple the electronic circuit to an integrated circuit package, such as a via package, a surface mount package, a pin grid array package, a flat package, a low profile package, a chip scale package, and/or a ball grid array, to provide some examples.

As another example, and as shown in fig. 6, the semiconductor device includes a first integrated circuit component 200.1, a first redistribution layer 206.1, a second integrated circuit component 200.2, and a second redistribution layer 206.2. The first redistribution layer 206.1 and the second redistribution layer 206.2 are located between the first integrated circuit component 200.1 and the second integrated circuit component 200.2. The exemplary first integrated circuit assembly 200.1 includes a first semiconductor substrate 202.1 having first electronic circuitry formed therein and a first interconnect structure 204.1 disposed on the first semiconductor substrate 202.1. The exemplary second integrated circuit assembly 200.2 includes a second semiconductor substrate 202.2 having second electronic circuitry formed therein and a second interconnect structure 204.2 disposed on the semiconductor substrate 202.2. The first redistribution layer 206.1 from within the first semiconductor stack associated with the first electronic circuit may be electrically and/or mechanically coupled to the second redistribution layer 206.2 from within the second semiconductor stack associated with the second electronic circuit to electrically couple the first electronic circuit and the second electronic circuit. In this exemplary embodiment, the first redistribution layer 206.1 is configured and arranged to be electrically and/or mechanically coupled to the second redistribution layer 206.2. In an exemplary embodiment, the first redistribution layer 206.1 is bonded to the second redistribution layer 206.2 using a hybrid bonding technique. In the exemplary embodiment, hybrid bonding techniques utilize a bonding wave to electrically and/or mechanically couple first redistribution layer 206.1 and second redistribution layer 206.2. The term "hybrid bond" derives from the combination of a metal-to-metal bond and an insulator-to-insulator (or dielectric-to-dielectric) bond during the bonding process. In some examples, the redistribution layers 206.1 and 206.2 include conductive components for metal-to-metal bonding and dielectric components for insulator-to-insulator bonding, and the bonding waves connect the dielectric surfaces, which also have metal interconnects to be connected together in the same planar bonding interface. Thus, the redistribution layers 206.1 and 206.2 may also be referred to as the bonding layers 206.1 and 206.2 (or hybrid bonding layers 206.1 and 206.2). As will be described in further detail below, the first and second redistribution layers 206.1 and 206.2 are configured and arranged to facilitate an increase in the balance of the bonding wave propagation paths (e.g., in the X-direction and Y-direction) in symmetrical bonding wave propagation between the first and second redistribution layers 206.1 and 206.2 during bonding, which effectively reduces wafer deformation after bonding. It should be noted that one skilled in the relevant art will recognize that the spirit and scope of the present invention may also be applied to other well known bonding techniques including, but not limited to, direct bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, and transient liquid phase diffusion bonding.

Fig. 7, 8 and 9 illustrate exemplary semiconductor wafers including exemplary integrated circuit components according to exemplary embodiments of the invention. Referring to fig. 7, a plurality of integrated circuit assemblies 200.1 through 200.N are fabricated in a semiconductor wafer 300 using semiconductor device fabrication operations. The semiconductor wafer 300 includes a plurality of integrated circuit components 200.1 through 200.N arranged in an array. In some embodiments, the semiconductor wafer 300 includes a semiconductor substrate 302 having electronic circuitry formed therein and an interconnect structure 304 disposed on the semiconductor substrate 302. In some embodiments, each of the integrated circuit components 200.1 through 200.N included in the semiconductor wafer 300 includes an active region 200A in which electronic circuitry is formed and a peripheral region 200B surrounding the active region 200A. The semiconductor device manufacturing operation uses a predetermined sequence of photographic and chemical processing operations to form a plurality of integrated circuit assemblies 200.1 through 200.N in the first semiconductor wafer 300.

In the exemplary embodiment shown in fig. 7, integrated circuit components 200.1 through 200.N are formed in and/or on semiconductor substrate 302 using a first series of fabrication operations (referred to as front-end-of-line processing) and a second series of fabrication operations (referred to as back-end-of-line processing). The front-end-of-line processing represents a series of photographic and chemical processing operations to form corresponding electronic circuits of the plurality of integrated circuit components 200.1 through 200.N in and/or on the semiconductor substrate 302. The back-end-of-line processing represents another series of photographic and chemical processing operations to form corresponding interconnect structures 204 of the plurality of integrated circuit components 200.1 through 200.N on the semiconductor substrate 302 to form the semiconductor wafer 300. In an exemplary embodiment, the integrated circuit components 200.1 through 200.N included in the semiconductor wafer 300 may be similar and/or different from one another.

As shown in fig. 7, the semiconductor substrate 302 is part of a semiconductor wafer 300. The semiconductor substrate 302 may be made of silicon or other semiconductor materials. In addition, the semiconductor substrate 302 may include the sameIt is an elemental semiconductor material such as germanium. In some embodiments, the semiconductor substrate 302 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 302 is made of an alloy semiconductor, such as sapphire, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 302 includes an epitaxial layer. For example, the semiconductor substrate 302 has an epitaxial layer on top of a bulk semiconductor. The semiconductor substrate 302 may also include isolation features (not shown), such as Shallow Trench Isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation member may define and isolate the individual semiconductor elements. The semiconductor substrate 302 may also include doped regions (not shown). The doped region may be doped with a P-type dopant (such as boron or BF ₂ ) And/or n-type dopants such As phosphorus (P) or arsenic (As). The doped region may be formed directly on the semiconductor substrate 302 in a P-well structure, an N-well structure, or a double-well structure.

In some embodiments, interconnect structure 304 includes a dielectric layer, conductive vias embedded in the dielectric layer, and conductive wiring between the dielectric layer, wherein different layers of the conductive wiring are electrically connected to each other through the conductive vias.

A redistribution layer 306 is formed over the semiconductor wafer 300. In some embodiments, a process for fabricating a redistribution layer 306 over a semiconductor wafer 300 includes: forming a dielectric layer over the semiconductor wafer 300; patterning the dielectric layer to form a plurality of openings in the dielectric layer to expose the conductive pads of the semiconductor wafer 300; depositing a conductive material over the semiconductor wafer 300 such that the dielectric layer and the conductive pads exposed by the openings in the dielectric layer are covered by the conductive material, wherein the conductive material covers not only the dielectric layer and the conductive pads, but also the sidewall surfaces of the openings and completely fills the openings; a polishing process (e.g., a CMP process) is performed to partially remove excess portions of the conductive material until the top surface of the dielectric layer 308 is exposed, thereby forming an array of conductive contacts 310 (e.g., metal vias and/or metal pads) in the dielectric layer 308. The redistribution layer 306, including the dielectric layer 308 and the array of conductive contacts 310, may serve as a bonding layer when performing a wafer level bonding process to bond the semiconductor wafer 300 to another wafer.

As shown in fig. 8, a first semiconductor wafer 300.1 and a second semiconductor wafer 300.2 are provided to be bonded to each other. In some embodiments, two different types of wafers 300.1 and 300.2 are provided. In other words, the integrated circuit components 200.1 to 200.N comprised in the first semiconductor wafer 300.1 and the integrated circuit components 200.1 to 200.N comprised in the second semiconductor wafer 300.2 may have different architectures and perform different functions. For example, the second semiconductor wafer 300.2 is a memory device wafer including a plurality of chips including a memory array (e.g., such as the memory array 120 of fig. 4A or 4B) and other FEOL structures, and the first semiconductor wafer 300.1 is an Application Specific Integrated Circuit (ASIC) wafer including a plurality of transistors and other FEOL structures. The transistors in the first semiconductor wafer 300.1 correspond to memory cells in the memory array in the second semiconductor wafer 300.2 (e.g., as memory cells 125 in fig. 4A or 4B). In a further implementation of the embodiment, the second semiconductor wafer 300.2 is free of transistors, allowing the second semiconductor wafer 300.2 to experience excessive heat to achieve higher crystalline quality for the ferroelectric film in the memory cell.

Before bonding the first and second semiconductor wafers 300.1, 300.2, a first redistribution layer 306.1 and a second redistribution layer 306.2 are formed over the first and second semiconductor wafers 300.1, 300.2, respectively. The process for forming the first redistribution layer 306.1 and the second redistribution layer 306.2 may be similar to the process for forming the redistribution layer 306 shown in fig. 7.

In some embodiments, a process for fabricating a first redistribution layer 306.1 over a first semiconductor wafer 300.1 includes: forming a first dielectric layer over the first semiconductor wafer 300.1; patterning the first dielectric layer to form a plurality of first openings in the first dielectric layer 308.1 to expose the first conductive pads of the first semiconductor wafer 300.1; depositing a first conductive material over the first semiconductor wafer 300.1 such that the first dielectric layer 308.1 and the first conductive pad exposed by the first opening in the first dielectric layer 308.1 are covered by the first conductive material, wherein the first conductive material covers not only the first dielectric layer 308.1 and the first conductive pad but also the sidewall surfaces of the first opening and completely fills the first opening; a first polishing process (e.g., a CMP process) is performed to partially remove the excess portion of the first conductive material until the top surface of the first dielectric layer 308.1 is exposed, thereby forming an array of a plurality of conductive contacts 310.1 (e.g., bond pads BP as in fig. 7) in the first dielectric layer 308.1. In some embodiments, the process for fabricating the second redistribution layer 306.2 over the second semiconductor wafer 300.2 includes: forming a second dielectric layer 308.2 over the second semiconductor wafer 300.2; patterning the second dielectric layer 308.2 to form a plurality of second openings in the second dielectric layer 308.2 to expose the second conductive pads of the second semiconductor wafer 300.2; depositing a second conductive material over the second semiconductor wafer 300.2 such that the second dielectric layer 308.2 and the second conductive pad exposed by the second opening are covered by the second conductive material, wherein the second conductive material covers not only the second dielectric layer 308.2 and the second conductive pad but also the sidewall surfaces of the second opening and completely fills the second opening; a second polishing process (e.g., a CMP process) is performed to partially remove excess portions of the second conductive material until the top surface of the second dielectric layer 308.2 is exposed, thereby forming an array of a plurality of conductive contacts 310.2 (e.g., bond pads BP as in fig. 7) in the second dielectric layer 308.2.

In some embodiments, the array of conductive contacts 310.1 protrudes slightly from the top surface of the first dielectric layer 308.1 and the array of conductive contacts 310.2 protrudes slightly from the top surface of the second dielectric layer 308.2 because during the CMP process, the first dielectric layer 308.1 and the second dielectric layer 308.2 are polished at a relatively high polishing rate while the conductive material is polished at a relatively low polishing rate.

As shown in fig. 8 and 9, after forming the redistribution layer 306.1 and the second redistribution layer 306.2 over the first semiconductor wafer 300.1 and the second semiconductor wafer 300.2, the second semiconductor wafer 300.2 with the second redistribution layer 306.2 formed thereon is flipped over onto the first redistribution layer 306.1 formed on the first semiconductor wafer 300.1 such that the plurality of conductive contact 310.1 arrays of the first redistribution layer 306.1 are substantially aligned with the plurality of conductive contact 310.2 arrays of the second redistribution layer 206.2. The first semiconductor wafer 300.1 is then bonded to the second semiconductor wafer 300.2 through the first redistribution layer 306.1 and the second redistribution layer 306.2 to form semiconductor devices 320. In some embodiments, after the bonding process is performed, the bonding interface between the first redistribution layer 306.1 and the second redistribution layer 306.2 in the bonded structure (e.g., semiconductor device) 320 is substantially free of misalignment. Such bonding may include hybrid bonding, direct bonding, surface-activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding, and/or any other well known bonding technique that will be apparent to those of skill in the relevant art without departing from the spirit and scope of the invention. The bonded structure 320 is then cut into individual chips.

Fig. 10 illustrates a method 400 of semiconductor fabrication including fabrication of a ferroelectric memory device. Method 400 is merely an example and is not intended to limit the present invention beyond what is explicitly recited in the claims. Additional operations may be provided before, during, and after the method 100, and some of the operations described may be replaced, eliminated, or moved around for additional embodiments of the method. Method 100 is described below in connection with fig. 11-26, with fig. 11-26 representing cross-sectional views of embodiments of a memory device according to various stages of method 400 in accordance with some embodiments of the invention.

The method 400 provides (or is provided with) a device structure 500 including a substrate 502, such as shown in fig. 11, in operation 402 (fig. 10). The depicted device structure 500 may be part of a first wafer. The device structure 500 and the device structure 600 (discussed later) will be joined together to form part of an IC chip, a system on a chip (SoC), or part thereof, which may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. In a further implementation of some embodiments, the device structure 500 is part of the upper integrated circuit assembly 200.2 (fig. 6).

Substrate 502 can be substantially similar to substrate 132 (e.g., fig. 2) and/or substrate 202 (e.g., fig. 5) discussed above. Optionally, doped regions (not shown) similar to doped regions 146 (e.g., fig. 3B) may be formed in substrate 502. The doped region has a doping type opposite to the doping type of the substrate 502. The doped region may be formed to have a higher doping concentration than the substrate 502. In some embodiments, the doped regions may be formed by a suitable process, such as POCl ₃ Doping methods or other doping methods.

The method 400 forms a trench 504 in a substrate 502 in operation 404 (fig. 10), such as shown in fig. 12. In some embodiments, the trench 504 has a width W1 and a depth D1, and the aspect ratio of the depth D1 to the width W1 is about from about 5 to about 30. The trench 504 is formed at a position where a trench mask (not shown) is disposed over the substrate 502. The trench mask may be a photoresist mask or a hard mask such as nitride. Then, an etching operation is performed with the trench mask in place. The trench 504 is formed by a suitable etching process, such as a dry etching operation. In some embodiments, the dry etching in the present operation includes Reactive Ion Etching (RIE) using fluorine-containing gas. After forming the trench 504, the trench mask is removed.

The method 400 deposits a bottom electrode layer 506 in operation 406 (fig. 10), such as shown in fig. 13. In some embodiments, a bottom electrode layer 506 is blanket deposited over the device structure 500, including on the sidewalls and bottom surfaces of the trenches 504. The material composition of the bottom electrode layer 506 may be substantially similar to the bottom electrode 134 discussed above (e.g., fig. 2). In some embodiments, the bottom electrode layer 506 may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), alloys thereof, and the like. In some embodiments, the bottom electrode layer 506 may be formed of TiN, ru, W, mo, taN or the like. The bottom electrode layer 506 may be deposited using any suitable deposition process. For example, suitable deposition processes may include Physical Vapor Deposition (PVD), sputtering, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or combinations thereof. The thickness of the bottom electrode layer 506 may range from 10nm to 100nm, although smaller and larger thicknesses may also be used.

The method 400 deposits an interfacial layer 508, such as shown in fig. 14, in operation 408 (fig. 10). In some embodiments, interfacial layer 508 is blanket deposited over device structure 500, including on the sidewalls and bottom surfaces of trench 504. The material composition of interface layer 508 may be substantially similar to interface layer 136 discussed above (e.g., fig. 2). Interfacial layer 508 may comprise a high-k dielectric material having a dielectric constant greater than 3.9 and may include, but is not limited to, silicon nitride (SiN) _x ) Hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide ((Hf) _0.5 Zr _0.5 O ₂ ) (HZO)), tantalum oxide (Ta ₂ O ₅ ) Alumina (Al) ₂ O ₃ ) Lanthanum aluminate (LaAlO) ₃ ) Hafnium oxide-aluminum oxide (HfO) ₂ -Al ₂ O ₃ ) Zirconium oxide (ZrO) ₂ ) Magnesium oxide (MgO), combinations thereof, and the like. Other suitable dielectric materials are also within the scope of the present invention. Interfacial layer 508 can be deposited using any suitable deposition process. For example, suitable deposition processes may include Physical Vapor Deposition (PVD), sputtering, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or combinations thereof. The thickness of interfacial layer 508 can be less than about 2nm.

The method 400 deposits a ferroelectric film 510 in operation 410 (fig. 10), such as shown in fig. 15. A seed structure (not shown) substantially similar to seed structure 138 (e.g., fig. 2) discussed above may optionally be formed on the top surface of interfacial layer 508 prior to depositing ferroelectric film 510. The seed structure may be a discontinuous layer of metal particles Which may comprise discrete metal atoms or discrete metal nanoparticles. The seed structure may be a discontinuous layer such that the seed structure does not form a conductive path on the surface of the interfacial layer 508. The seed structure may have a thickness of from about(angstrom) to about->A thickness in the range, and/or the seed metal particles may have a thickness in the range of from about +.>(angstrom) to about->Average particle size in the range, such as from aboutTo about->Or from about->To about->The seed structure may be formed by depositing a seed metal using any suitable deposition process. For example, the seed structure may be formed using Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like.

In some embodiments, a ferroelectric film 510 is blanket deposited over the device structure 500, including on the sidewalls and bottom surfaces of the trench 504. The material composition of ferroelectric film 510 may be substantially similar to ferroelectric film 140 discussed above (e.g., fig. 2). The ferroelectric film 510 includes a ferroelectric material (polarizing material). The ferroelectric film 510 may be a single-layer or multi-layer structure, such as a first ferroelectric layer disposed over a second ferroelectric layerAnd a ferroelectric layer, wherein the first ferroelectric layer and the second ferroelectric layer have different compositions. The ferroelectric material may be a high-k dielectric material having an orthorhombic crystal structure, such as a dielectric material having a dielectric constant (k) greater than about 28 (e.g., k.gtoreq.28). In some embodiments, the ferroelectric film 510 includes a metal oxide material or a metal oxynitride material. For example, the ferroelectric film 510 may include a hafnium oxide-based material or a zirconium oxide-based material. In further implementations of the examples, the ferroelectric film 510 may include hafnium oxide (e.g., hf _x O _y ) Hafnium zirconium oxide (e.g., hf) _x Zr _z O _y ) (also known as HZO), hafnium aluminum oxide (e.g., hf) _x Al _z O _y ) Hafnium lanthanum oxide (e.g. Hf) _x La _z O _y ) Hafnium cerium oxide (e.g. Hf) _x Ce _z O _y ) Hafnium silicon oxide (Hf) _x SiO _y ) Hafnium gadolinium oxide (e.g. Hf _x Gd _z O _y ) Other suitable Hf-based _x O _y Wherein x, y, z are atomic percentages, or combinations thereof. In another example, ferroelectric film 510 may include Zr-based _j O _k Wherein j, k, z are atomic percent. Ferroelectric film 510 may be formed by depositing a ferroelectric material using any suitable deposition method, such as PVD, spin coating and annealing, sputtering, CVD, ALD, plasma Enhanced Chemical Vapor Deposition (PECVD), spray pyrolysis, pulsed Laser Deposition (PLD), or combinations thereof. During the deposition process, the seed metal may promote the growth of a desired crystalline phase in the ferroelectric film 510. For example, when the ferroelectric film 510 includes a Hf-based ferroelectric material, the primary crystal phase of the ferroelectric film 510 may have an orthorhombic crystal structure. If the ferroelectric film 510 includes a Pb-based material such as PBT or PZT, the primary crystal phase of the ferroelectric film 510 may have a tetragonal crystal structure. In particular, the primary crystalline phase may comprise at least 50% of the ferroelectric film 510, such as from about 60% to about 99.9%, or from about 70% to about 95%. In some embodiments, the thickness of the ferroelectric film 510 is less than about 5nm.

The method 400 deposits a top electrode layer 512 in operation 412 (fig. 10), such as shown in fig. 16. In some embodiments, a top electrode layer 512 is blanket deposited over the device structure 500, including on the sidewalls and bottom surfaces of the trenches 504. The material composition of the top electrode layer 512 may be substantially similar to the top electrode 142 discussed above (e.g., fig. 2). The top electrode layer 512 may include and/or may consist essentially of at least one of a transition metal, a conductive metal nitride, and a conductive metal carbide. Exemplary metallic materials that may be used for the top electrode layer 512 include, but are not limited to TiN, taN, WN, W, cu, al, ti, ta, ru, co, mo, pt, alloys thereof, and/or combinations thereof. Other suitable materials within the contemplation of the invention may also be used. For example, the top electrode layer 512 may include and/or may consist essentially of an elemental metal, such as W, cu, ti, ta, ru, co, mo or Pt. The thickness of the top electrode 512 may range from 10nm to 100nm, although smaller and larger thicknesses may also be used.

The method 400 deposits a plug layer 514 in operation 414 (fig. 10), such as shown in fig. 17. Plug layer 514 plugs the remaining openings in trench 504. The material composition of plug layer 514 may be substantially similar to plug 148 discussed above (e.g., fig. 3C). In some embodiments, plug layer 514 includes a dielectric material, such as a high-k dielectric material. Examples of high-k dielectric materials include HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, plug layer 514 includes a semiconductor material, such as polysilicon. In some embodiments, plug layer 514 includes a different conductive material than top electrode layer 512, such as copper, aluminum, gold, silver, or tungsten. Plug layer 514 may be deposited using any suitable deposition process. For example, suitable deposition processes may include Physical Vapor Deposition (PVD), sputtering, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or combinations thereof. At the end of operation 414, a planarization process (e.g., a CMP process) is performed to remove excess portions of plug layer 514 until the top surface of top electrode layer 512 is exposed, thereby forming a plug embedded in top electrode layer 512. Planarization processThe resulting structure is shown in fig. 18. The plug is shown as plug 516. The plugs 516 enhance the mechanical strength of the high aspect ratio FTJ to be formed and may also serve as extensions of the top electrode layer 512 if formed of a semiconductor material or a conductive material. The top surface of plug 516 may be substantially flush with the top surface of top electrode layer 512. Optionally, the top surface of the plug 516 may have a concave profile and be located below the top surface of the top electrode layer 512 due to a dishing effect during the planarization process. The plug 516 has an aspect ratio of depth D2 to width W2 in the range from about 30 to about 50 that is greater than the aspect ratio of the trench 504.

The method 400 patterns the top electrode layer 512, ferroelectric film 510, interface layer 508, bottom electrode layer 506 to form an FTJ 520 in operation 416 (fig. 10), such as shown in fig. 19. For simplicity, patterned bottom electrode layer 506 and patterned top electrode layer 512 are denoted as bottom electrode 506 and top electrode 512, respectively. In some embodiments, the patterning of the bottom electrode layer 506 includes: depositing a photoresist layer (not shown) over the device structure 500; exposing the photoresist to a pattern; performing a post-exposure baking process; and developing the photoresist to form the masking element. The masking element may then be used to protect the regions of the FTJ 520 and the layers formed thereon, while the etching process removes the layers from the unprotected regions through the openings in the masking element. The etching process may include dry etching, wet etching, RIE, and/or other suitable processes. Patterning of the top electrode layer 512 is performed sequentially by a similar patterning process. Patterning of the top electrode layer 512 exposes the top surface of the bottom electrode 506. In some embodiments, the top surface of the layers stacked between the top electrode and the bottom electrode remain covered by the top electrode 512, while their sidewalls are exposed. In some embodiments, layers 506, 508, 510, and 512 decrease in size sequentially from bottom to top such that each of their layers has an exposed portion of the top surface.

The method 400 performs a thermal treatment 524, such as shown in fig. 20, on the device structure 500 in operation 418 (fig. 10). By forming transistors and other FEOL structures in another wafer, as will be explained in further detail later, excessive thermal temperatures may be applied to the device structure 500 without causing damage to the transistors and other FEOL structures. In some embodiments, the wafer housing the ferroelectric film 510 may be subjected to a thermal treatment having a temperature greater than about 550 ℃, such as between about 550 ℃ and about 1000 ℃, without subjecting the FEOL structure to such excessive heat. Accordingly, the crystalline quality of ferroelectric film 510 is increased and the performance of ferroelectric memory devices is improved with little or no risk of damaging FEOL structures. In some embodiments, the ferroelectric film 510 may be annealed using Excimer Laser Annealing (ELA), flash Lamp Annealing (FLA), furnace annealing, or the like. Operationally, the heat treatment 524 may be performed prior to operation 416, even prior to operation 414, but after operation 412. That is, the crystallization improvement may be performed before the electrode layer, the ferroelectric film, and the interface layer are patterned into the FTJ 520.

The method 400 forms an interconnect structure 530 in operation 420 (fig. 10), the interconnect structure 530 being formed over the device structure 500, such as shown in fig. 21. In some embodiments, interconnect structure 530 may include about two (2) to about five (5) metal layers. Each of the metal layers of the interconnect structure includes a plurality of conductive vias and metal lines embedded in at least one dielectric layer, such as an inter-layer dielectric (ILD) layer and/or an inter-metal dielectric (IMD) layer. The conductive via and the metal line may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu). The dielectric layer may be or include an oxide (such as silicon dioxide), a low-k dielectric material, another suitable dielectric material, or any combination of the preceding. In still further embodiments, the dielectric layer may be or include, for example, silicon dioxide, a low-k dielectric material, silicon nitride, silicon carbide, an extremely low-k (ELK) dielectric material, another suitable dielectric material, or any combination thereof. The conductive vias and metal lines are embedded in or disposed in the dielectric layer. For example, in the depicted embodiment, conductive via 534 is bonded to the exposed top surface of bottom electrode 506 and conductive via 536 is bonded to the top surface of top electrode 512. In the depicted embodiment, the conductive via 536 further electrically couples the top electrode 512 to the top metal line 538.

The method 400 forms a redistribution layer (or hybrid bond layer) 540 overlying the interconnect structure 530 in operation 422 (fig. 10), such as shown in fig. 22. The redistribution layer 540 includes conductive components (e.g., bond pads 542) for metal-to-metal bonds and dielectric components for insulator-to-insulator bonds. Bond pads 542 are electrically connected to FTJ 520 through vias 544 embedded in redistribution layer 540 and metal routing (e.g., top metal lines 538) in interconnect structure 530. In some embodiments, the heat treatment in operation 418 is performed after operation 422 but before operation 426 of the bonding process is performed.

The method 400 forms a device structure 600, such as shown in fig. 23, in operation 424 (fig. 10). The depicted device structure 600 may be part of a second wafer that is different from the first wafer. The device structure 600 is simplified and not all of the components in the device structure 600 are shown or described in detail. The device structure 600 and the device structure 500 discussed above will be bonded together. In further implementations of some embodiments, the device structure 600 is part of the lower integrated circuit assembly 200.1 (fig. 6).

The device structure 600 includes an interconnect structure 604 overlying a substrate 602. In an embodiment, the substrate 602 comprises silicon (Si). Alternatively or additionally, the substrate 602 may include another elemental semiconductor, such as germanium (Ge); compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide; alloy semiconductors such as silicon germanium (SiGe), gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination thereof. Alternatively, the substrate 602 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The substrate 602 may include various doped regions (not shown) depending on the design requirements of the device structure 600. In some implementations, the substrate 602 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant, such as boron (e.g., BF ₂ ) Indium, other p-type dopants, orA combination thereof. In some implementations, the substrate 602 includes an n-type doped region (e.g., an n-type well) doped with an n-type dopant, such As phosphorus (P), arsenic (As), other n-type dopants, or a combination thereof. In some implementations, the substrate 602 includes a doped region formed with a combination of p-type dopants and n-type dopants. The various doped regions may be formed directly on and/or in the substrate 602, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and/or other suitable doping processes may be performed to form the various doped regions.

A plurality of semiconductor devices 608 are disposed within and/or over the substrate 602. In some embodiments, semiconductor device 608 may be configured, for example, as a transistor or as another suitable semiconductor device. In such an embodiment, the semiconductor device 608 may include corresponding source/drain regions 610, corresponding gate structures 612, and corresponding gate cap layers 614. As used herein, a source/drain region or "S/D region" may refer to the source or drain of a device. It may also refer to a region that provides a source and/or drain for multiple devices. In some embodiments, source/drain regions 610 are disposed within the substrate 602. In further embodiments, the gate structure 612 may include a corresponding gate electrode located over a corresponding gate dielectric layer. In various embodiments, the gate electrode may be or comprise, for example, a metal (such as aluminum, tungsten, titanium, any combination of the foregoing materials, etc.), polysilicon, another suitable conductive material, or any combination of the foregoing materials. In further embodiments, the gate dielectric layer may be or comprise, for example, silicon dioxide, a high-k dielectric material, another suitable dielectric material, or any combination of the foregoing. The gate cap 614 is conductive and may be or comprise, for example, tantalum, titanium, silicide, another suitable material, or any combination of the preceding materials. Further, isolation structures 616 are disposed within the substrate 602 and may laterally surround the corresponding semiconductor device 608. In some embodiments, the isolation structure 616 may be configured, for example, as a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, or another suitable isolation structure. In further embodiments, isolation structure 616 may be or comprise, for example, silicon dioxide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the preceding.

Further, the semiconductor device 608 may be a planar transistor or a multi-gate transistor, such as a fin FET (FinFET) or a full-gate-all-around (GAA) transistor. GAA transistors may include channel regions of various shapes, including nanowires, nanorods, or nanoplates, which may be collectively referred to as nanostructures. GAA transistors may also be referred to as multi-bridge channel (MBC) transistors or wrap gate transistors (SGT). Although the semiconductor device 608 is shown in fig. 23 and subsequent figures as a planar device, it should be understood that the semiconductor device 608 may also be a FinFET or GAA transistor.

Interconnect structure 604 includes a lower portion that includes gate contact vias 618 and source/drain contact vias 620 embedded in an interlayer dielectric (ILD) layer. The ILD layer may comprise silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped Silicate Glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused Silicate Glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials. The source/drain contacts may include ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The gate contact via may include tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The interconnect structure 604 includes an upper portion including a plurality of metal layers, such as a first metal layer M1 to an n-th metal layer Mn (not shown), stacked in order. A further metal layer of interconnect structure 604 will be formed over n-th metal layer Mn. In some embodiments, interconnect structure 604 may include about two (2) to about five (5) metal layers. Each of the metal layers of the interconnect structure includes a plurality of vias and metal lines embedded in at least one inter-metal dielectric (IMD) layer. The via and the metal line may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu). The IMD layer may have a composition similar to that of the ILD layer described above. The via and metal line are embedded in or disposed in the IMD layer.

The device structure 600 includes a redistribution layer (or hybrid junction layer) 606 disposed over the interconnect structure 604. The redistribution layer 606 includes conductive components (e.g., bond pads 626) for metal-to-metal bonding and dielectric components for insulator-to-insulator bonding. The bond pads 626 are electrically connected to the control transistors 608 through vias 628 embedded in the redistribution layer 606 and metal routing (e.g., top metal lines 624) in the interconnect structure 604.

The method 400 bonds the device structure 500 with the device structure 600 to form a bonded structure 700 in operation 426 (fig. 10). Fig. 24 shows the bonded structure 700 after the device structures 500 and 600 are bonded together. The top side (or front side) of the bonded structure 700 is the bottom side (or back side) of the device structure 500. The bottom side (or backside) of the bonded structure 700 is the bottom side (or backside) of the device structure 600. In the bonded structure 700, the device structure 500 has a thickness T1, and the device structure 600 has a thickness T2 that is generally greater than T1. In some embodiments, T1 is less than about 10um and T2 is less than about 700um. The pair of bond pads 542 of device structure 500 and bond pad 626 of device structure 600 collectively define hybrid bond pad 702. The electrode of ftj 520 is electrically coupled to one of the source/drain regions 610 of the corresponding control transistor 608 through hybrid bond pad 702.

The method 400 performs further processing in operation 428 (fig. 10) to form various components, such as shown in fig. 25. In the depicted embodiment, front side bond pads 704 are disposed along the front side of bonded structure 700. A Through Substrate Via (TSV) 706 extends from the front side bond pad 704, through the substrate 502, and protrudes into the interconnect structure 530. TSV 706 has a relatively small size (e.g., less than or equal to about 2.5 um), which allows TSV 706 to connect to thin metal lines in interconnect structure 530. The front side bond pads 704 are covered by passivation layers 707 and 708. In various embodiments, passivation layers 707 and 708 may be or include, for example, silicon dioxide, silicon oxynitride, silicon oxycarbide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing. An Under Bump Metal (UBM) layer 710 extends through openings in passivation layers 707 and 708 to contact front side bond pad 704. In some embodiments, UBM layer 710 may also extend along the upper surface of passivation layer 708. Conductive bump 712 is disposed within UBM layer 710 at a location separated from passivation layers 707 and 708 by UBM layer 710. Conductive bumps 712 are configured to provide an electrical connection between the electrodes of FTJ 520 and bit lines BL.

Referring collectively to fig. 4A and 25, in some embodiments, top electrode 512 of FTJ 520 is electrically coupled to source/drain region 610 of control transistor 608 through hybrid bond pad 702, while bottom electrode 506 is coupled to bit line BL through TSV 706. In some alternative embodiments, bottom electrode 506 of FTJ 520 is electrically coupled to the source/drain regions of control transistor 608 through hybrid bond pad 702, while top electrode 512 is coupled to bit line BL through TSV 706.

Referring collectively to fig. 4B and 26, in some alternative embodiments, two or more FTJs may share a hybrid bond pad 702 and control transistor 608 to reduce the number of hybrid bond pads and control transistors required. Because the size of hybrid bond pad 702 is typically much larger than the size of control transistor 608 and FTJ 520, the one-to-one mapping of hybrid bond pads and individual FTJ requires the same number of hybrid bond pads as memory cells in the memory array, which would consume a relatively large device area. As depicted in fig. 26, top electrodes 512 of two or more FTJs 520 may be electrically connected to metal lines by conductive vias 536 and further coupled to a common hybrid bond pad 702, while bottom electrodes 506 are electrically coupled to TSVs 706 in a one-to-one mapping. Alternatively, bottom electrodes 506 of two or more FTJs 520 may be electrically connected to metal lines through conductive vias 536 and further coupled to common hybrid bond pads 702, while top electrodes 512 are electrically coupled to TSVs 706 in a one-to-one mapping. Thus, the number of hybrid bond pads and the number of control transistors required is reduced.

By forming transistors and other FEOL structures in one wafer and data storage elements in memory cells in another wafer, excessive thermal temperatures can be applied to the ferroelectric film to improve crystallization without causing damage to the transistors and other FEOL structures. After heat treatment, the two wafers are bonded together using wafer-on-wafer technology. By forming the data storage elements in the deep trenches, the volume required for the memory cells is reduced and the layout density is increased. By sharing multiple data storage elements with hybrid bond pads and control transistors, the number of hybrid bond pads and control transistors required is also significantly reduced, making a wafer-on-wafer memory structure even more viable.

In one exemplary aspect, the present invention relates to a method of forming a memory device. The method comprises the following steps: forming a trench in a first substrate of a first wafer; depositing a data storage element in the trench; performing a heat treatment on the first wafer to improve crystallization in the data storage element; forming a first redistribution layer over a first substrate; forming a transistor in a second substrate of a second wafer; forming a second redistribution layer over the second substrate; and bonding the first wafer to the second wafer after performing the heat treatment such that the data storage elements are electrically coupled to the transistors through the first and second redistribution layers. In some embodiments, the data storage element includes a Ferroelectric Tunnel Junction (FTJ). In some embodiments, performing the heat treatment occurs before forming the first redistribution layer. In some embodiments, depositing the data storage element includes: depositing a bottom electrode layer in the trench; depositing a ferroelectric film over the bottom electrode layer; depositing a top electrode layer over the ferroelectric film; and patterning the bottom electrode layer, the ferroelectric film, and the top electrode layer to form a data storage element. In some embodiments, performing the heat treatment occurs before patterning the bottom electrode layer, the ferroelectric film, and the top electrode layer. In some embodiments, the heat treatment includes applying a temperature to the first wafer of about 550 ℃ or greater. In some embodiments, after bonding the first wafer to the second wafer, the thickness of the first wafer is less than the thickness of the second wafer. In some embodiments, the first wafer has a thickness of less than about 10um and the second wafer has a thickness of less than about 700um. In some embodiments, the data storage element includes a bottom electrode proximate to a sidewall of the trench and a top electrode distal from the sidewall of the trench, and wherein the bottom electrode is electrically coupled to the transistor. In some embodiments, the data storage element includes a bottom electrode proximate to a sidewall of the trench and a top electrode distal from the sidewall of the trench, and the top electrode is electrically coupled to the transistor.

In another exemplary aspect, the invention relates to a method of forming a memory device. The method comprises the following steps: forming a plurality of Ferroelectric Tunnel Junctions (FTJ) in a first wafer; performing a heat treatment to improve crystallization of the ferroelectric film in the FTJ; forming a first redistribution layer on the first wafer, wherein the first redistribution layer includes a plurality of first bond pads associated with a plurality of FTJ; forming a plurality of transistors in a second wafer; forming a second redistribution layer on the second wafer, wherein the second redistribution layer includes a plurality of second bond pads associated with the plurality of transistors; and bonding the first wafer to the second wafer after performing the heat treatment, thereby bonding the plurality of first bonding pads to the plurality of second bonding pads. In some embodiments, the ferroelectric thin film has a thickness of less than about 5 nm. In some embodiments, forming the plurality of FTJs includes: forming a plurality of trenches in a first wafer; depositing a bottom electrode layer in the plurality of trenches; depositing a ferroelectric film on the bottom electrode layer; depositing a top electrode layer on the ferroelectric film; and patterning the bottom electrode layer, the ferroelectric film, and the top electrode layer to form a plurality of FTJ. In some embodiments, forming the plurality of FTJs further comprises: after depositing the top electrode layer, a plug layer is deposited that fills the trench surrounded by the top electrode layer. In some embodiments, after bonding the first wafer to the second wafer, the bonded first and second bond pad pairs are associated with one and only one of the plurality of FTJ. In some embodiments, after bonding the first wafer to the second wafer, the bonded first and second bond pad pairs are associated with two or more of the plurality of FTJ.

In yet another exemplary aspect, the present invention relates to a memory device. The memory device includes: a first substrate including a plurality of transistors; a first distribution layer over the first substrate, the first distribution layer including a plurality of first bond pads electrically coupled to the plurality of transistors; a second distribution layer over the first distribution layer, the second distribution layer including a plurality of second bond pads in physical contact with the plurality of first bond pads; and a second substrate over the second distribution layer, the second substrate including a plurality of data storage elements embedded in the second substrate, each of the plurality of data storage elements having a first electrode electrically coupled to one of the plurality of second bond pads. In some embodiments, each of the plurality of data storage elements has a second electrode electrically coupled to a Bit Line (BL) of the memory device. In some embodiments, each of the plurality of transistors has a gate structure electrically coupled to a Word Line (WL) of the memory device. In some embodiments, the data storage element includes a Ferroelectric Tunnel Junction (FTJ).

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a memory device, comprising:

forming a trench in a first substrate of a first wafer;

depositing a data storage element in the trench;

performing a heat treatment on the first wafer to improve crystallization in the data storage element;

forming a first redistribution layer over the first substrate;

forming a transistor in a second substrate of a second wafer;

forming a second redistribution layer over the second substrate; and

after the heat treatment is performed, the first wafer is bonded to the second wafer such that the data storage elements are electrically coupled to the transistors through the first and second redistribution layers.

2. The method of claim 1, wherein the data storage element comprises a Ferroelectric Tunnel Junction (FTJ).

3. The method of claim 1, wherein performing the heat treatment is performed prior to forming the first redistribution layer.

4. The method of claim 1, wherein depositing the data storage element comprises:

depositing a bottom electrode layer in the trench;

depositing a ferroelectric film over the bottom electrode layer;

depositing a top electrode layer over the ferroelectric film; and

The bottom electrode layer, the ferroelectric film, and the top electrode layer are patterned to form the data storage element.

5. The method of claim 4, wherein performing the heat treatment occurs prior to patterning the bottom electrode layer, the ferroelectric film, and the top electrode layer.

6. The method of claim 1, wherein the heat treating comprises applying a temperature to the first wafer of about 550 ℃ or greater.

7. The method of claim 1, wherein a thickness of the first wafer is less than a thickness of the second wafer after bonding the first wafer to the second wafer.

8. The method of claim 7, wherein the thickness of the first wafer is less than about 10um and the thickness of the second wafer is less than about 700um.

9. A method of forming a memory device, comprising:

forming a plurality of Ferroelectric Tunnel Junctions (FTJ) in a first wafer;

performing a heat treatment to improve crystallization of a ferroelectric film in the ferroelectric tunnel junction;

forming a first redistribution layer on the first wafer, wherein the first redistribution layer includes a plurality of first bond pads associated with the plurality of ferroelectric tunnel junctions;

Forming a plurality of transistors in a second wafer;

forming a second redistribution layer on the second wafer, wherein the second redistribution layer includes a plurality of second bond pads associated with the plurality of transistors; and

after the heat treatment is performed, the first wafer is bonded to the second wafer such that the plurality of first bond pads are bonded to the plurality of second bond pads.

10. A memory device, comprising:

a first substrate including a plurality of transistors;

a first distribution layer over the first substrate, the first distribution layer including a plurality of first bond pads electrically coupled to the plurality of transistors;

a second distribution layer over the first distribution layer, the second distribution layer comprising a plurality of second bond pads in physical contact with the plurality of first bond pads; and

a second substrate over the second distribution layer, the second substrate comprising a plurality of data storage elements embedded in the second substrate, each of the plurality of data storage elements having a first electrode electrically coupled to one of the plurality of second bond pads.