CN116781203B - Data transmission method and related equipment - Google Patents
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Abstract
The present application relates to the field of communications technologies, and in particular, to a data transmission method and related devices. A method of transmitting data to a data receiving terminal, applied to a data transmitting terminal having N data output ports, a clock line connected between the data transmitting terminal and the data receiving terminal for transmitting a clock signal, the clock signal including a plurality of clock cycles, each clock cycle including a preceding period and a following period, the preceding period including N sub-periods, the method comprising: for each of a plurality of clock cycles: in the 1 st subperiod, the 1 st data output port is caused to generate 1 st bit of data; in the 2 nd subperiod, the 2 nd data output port is caused to generate 2 nd bit data; and so on, in the nth sub-period, the nth data output port is caused to generate the nth bit of data.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data transmission method and related devices.
Background
In the communication technology, a clock signal (simply referred to as a clock signal) is a signal that is continuously transmitted at a certain voltage amplitude and a certain time interval. The time interval between clock pulse signals is referred to as a clock period, and the number of pulses generated in a unit time (e.g., 1 second) is referred to as a clock frequency, each clock period having a rising edge and a falling edge. Fig. 1 shows a set of clock signals, wherein one clock period has a time T and includes at least a rising edge period and a falling edge period.
When data transmission is performed between two communication devices, if synchronous communication is adopted for data transmission, a channel responsible for transmitting data information is arranged on a transmission link, and a clock line is needed to specially transmit clock signals. When transmitting data, the transmitting end transmits the data according to a certain clock frequency, for example, 100HZ, which represents that there are 100 clock pulses within 1 second, a level signal can be transmitted on the data link when each clock pulse is at a rising edge or a falling edge, 100HZ can transmit 100 level signals, and the receiving end of the data also needs to receive the data according to the same clock frequency at the rising edge or the falling edge, so that the transmission of the whole data can be completed.
For example, in the field of display screen inspection, it is generally required to perform screen abnormality inspection on a liquid crystal display screen semi-finished product which is not shipped with a graphic signal generator (Pattern Generator, PG). In a specific operation, the PC side is required to send image data, control instructions and various parameters of the screen side to the PG to complete detection. In order to save cost, an FPGA chip is often used to process high-speed image data, and a single chip microcomputer is used to lower instruction information with a low rate and various parameters of a screen end. Different screens have different transmission protocols which can be supported when in communication, such as IIC, SPI, QSPI, and when the singlechip transmits data, the singlechip needs to transmit the data according to the protocol specified by the screen end.
For example, the QSPI protocol requires four paths of data to be transmitted simultaneously, and therefore, serial-parallel conversion is required when the singlechip is used for working. At present, the singlechip outputs parallel data by adopting fixed delay output data, and the specific method is as follows: the singlechip controls the conversion of 0 and 1 of a single data line to transmit data, so that the singlechip needs to control one data line to transmit data in the data transmission process of a plurality of data lines, and after the data transmission of the line is finished, the singlechip is changed to the next data line to transmit data until the data transmission of all the data lines is finished. Thus, when one data line transmits data, the other data lines wait with a delay until the data line transmits data.
Because some chips, such as a single chip microcomputer, do not support parallel operation by hardware, the data is transmitted in the fixed delay manner, but the data transmission speed is slow, and the transmission efficiency is affected. For example, for a communication system including 4 data lines, a fixed delay transmission mode is adopted, and only 8 bits (bits) of data can be transmitted in total in 8 clock cycles; for a communication device (for example, an FPGA device) with parallel transmission capability, 8 bits of data can be transmitted by each data line in 8 clock cycles, so that a total of 4 bits of data can be transmitted by 4 data in 8 clock cycles, but the FPGA device has a disadvantage of higher hardware cost.
Disclosure of Invention
In view of the above, the present application proposes a data transmission method and related devices.
In a first aspect, the present application provides a method for transmitting data to a data receiving end, applied to a data transmitting end having N data output ports, N is not less than 2, the N data output ports are respectively 1 st to N th data output ports, the N data output ports are respectively connected to the data receiving end through N data lines, a clock line for transmitting a clock signal is connected between the data transmitting end and the data receiving end, the clock signal includes a plurality of clock cycles, each of the clock cycles includes a preceding period and a following period, one of the preceding period and the following period includes a rising edge period of the clock cycle, the other includes a falling edge period of the clock cycle, the preceding period includes N sub-periods, and the N sub-periods are sequentially 1 st to N sub-periods according to a time sequence, the method includes:
for each of the plurality of clock cycles:
during the 1 st sub-period, causing the 1 st data output port to generate 1 st bit of data;
during the 2 nd sub-period, causing the 2 nd data output port to generate 2 nd bit of data;
and so on, in the nth sub-period, enabling the nth data output port to generate data of the nth bit.
In some possible embodiments, the N sub-periods are equally set.
In some possible embodiments, the data transmitting end is a single chip microcomputer or an FPGA chip.
In a second aspect, the present application proposes a method for transmitting data between a data transmitting end and a data receiving end, the data transmitting end having N data output ports, N being not less than 2, the N data output ports being respectively a1 st to an N-th data output port, the N data output ports being respectively connected to the data receiving end through N data lines, and a clock line for transmitting a clock signal being connected between the data transmitting end and the data receiving end, the clock signal including a plurality of clock cycles, each of the clock cycles including a preceding period and a following period, one of the preceding period and the following period including a rising edge period of the clock cycle, the other including a falling edge period of the clock cycle, the preceding period including N sub-periods, the N sub-periods being sequentially a1 st to an N sub-periods in time sequence, the method comprising:
for each of the plurality of clock cycles:
in the 1 st subperiod, the data transmitting end enables the 1 st data output port to generate 1 st bit data;
in the 2 nd subperiod, the data transmitting end enables the 2 nd data output port to generate 2 nd bit data;
and so on, in the nth sub-period, the data transmitting end enables the nth data output port to generate data of an nth bit;
and in the later period, the data receiving end reads the data on each data line.
In some possible embodiments, the N sub-periods are equally set.
In some possible embodiments, the data transmitting end is a single chip microcomputer or an FPGA chip, and the data receiving ends are all FPGA chips.
In a third aspect, the present application proposes a data transmitting terminal, including:
at least two of the data output ports,
the memory device is used for storing the data,
processor and method for controlling the same
Program instructions stored in the memory and executable by the processor;
the program instructions, when executed by the processor, cause the data sender to perform the method according to the first aspect.
In a fourth aspect, the present application provides a chip, comprising:
at least two of the data output ports,
the memory device is used for storing the data,
processor and method for controlling the same
Program instructions stored in the memory and executable by the processor;
the program instructions, when executed by the processor, cause the data sender to perform the method according to the first aspect.
In a fifth aspect, the present application proposes a communication system comprising:
the data transmitting end is provided with N data output ports, N is not less than 2, and comprises a first memory, a first processor and first program instructions which are stored in the first memory and can be executed by the first processor;
the data receiving end comprises a second memory, a second processor and second program instructions which are stored in the second memory and can be executed by the second processor;
n data lines respectively connecting the N data output ports to the data receiving end;
the clock line is connected with the data sending end and the data receiving end;
wherein the first program instructions, when executed by the first processor, and the second program instructions, when executed by the second processor, cause the communication system to perform the method of the second aspect.
In a sixth aspect, the present application proposes a computer readable storage medium storing program instructions which, when run on a communication device, cause the communication device to perform the method according to the first or second aspect.
According to the data transmission method provided by the application, the sending end flexibly distributes the time length duty ratio of a plurality of data channels in the prior period of one clock cycle, and the receiving end reads the data on each channel in the subsequent period of one clock cycle, so that the data transmission efficiency can be ensured, and the hardware cost can be saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present application and are not limiting of the present application.
Fig. 1 is a schematic diagram of a clock signal.
Fig. 2 is a block diagram of a communication system according to an embodiment of the present application.
Fig. 3 is a flowchart of a data transmission method according to an embodiment of the application.
Fig. 4 is a schematic diagram of a data transmission method according to an embodiment of the application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present application fall within the protection scope of the present application. It is to be understood that some of the technical means of the various embodiments described herein may be interchanged or combined without conflict.
In the description of the present application, the terms "first," "second," and the like, if any, are used merely to distinguish between the described objects and do not have any sequential or technical meaning. Thus, an object defining "first," "second," etc. may explicitly or implicitly include one or more such objects. Also, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one, and "a plurality" of "are used to indicate no less than two.
In the description of the present application, reference to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.
The data transmission method provided by the embodiment of the application can be applied to a communication system as depicted in fig. 2, wherein the communication system comprises a data transmitting end, a data receiving end, 4 data lines and a clock line.
The data transmitting end has 4 data output ports, and for convenience of explanation of the present technology, the 4 data output ports are referred to as 1 st to 4 th data output ports, respectively. The hardware of the data transmitting end does not support parallel operation, and 4 data output ports of the data transmitting end cannot be occupied at the same time, namely, the 4 data output ports cannot all perform level change operation at the same time. The data transmitting end can be a singlechip, and the data output port is an I/O port.
The 4 data lines respectively connect the 4 data output ports to the data receiving end. For convenience of explanation of the present technology, the 4 DATA lines are referred to as 1 st DATA line DATA1, 2 nd DATA line DATA2, 3 rd DATA line DATA3, and 4 th DATA line DATA4, respectively.
The clock line CLK connects the data transmitting end and the data receiving end, and is used for transmitting a clock signal generated by the data transmitting end to the data receiving end so that the data receiving end can read data on the data line CLK based on the clock signal. As shown in fig. 1 and 4, the clock signal includes a plurality of clock cycles, each clock cycle includes a preceding period Ta and a following period Tb, the preceding period Ta includes at least a rising edge period of the clock cycle, the following period Tb includes at least a falling edge period of the clock cycle, the preceding period includes 4 sub-periods (i.e. t1=t2=t3=t4) which are equally divided (i.e. t1, t2=t3=t4), and the 4 sub-periods are the 1 st sub-period t1, the 2 nd sub-period t2, the 3 rd sub-period t3, and the 4 th sub-period t4 in sequence. In other embodiments, the 4 sub-periods may not be equal to each other.
The data receiving end is able to read 4 bits of data on 4 data lines simultaneously (i.e., at the same clock cycle of the clock signal). More specifically, the data receiving end may read the data on the respective data lines only in the following period Tb (not in the preceding period Ta) of each clock cycle, as will be described in more detail below. The data receiving end may be an FPGA chip, for example an FPGA chip in a liquid crystal display.
Referring to fig. 3 in combination with fig. 2 and fig. 4, the data transmission method, that is, the method for transmitting data between the data transmitting end and the data receiving end, includes:
for each of the aforementioned plurality of clock cycles:
s301, in a1 st subperiod t1 of the period, a data transmitting end enables a1 st data output port to generate 1 st bit data;
s302, in a2 nd subperiod t2 of the period, the data transmitting end enables a2 nd data output port to generate 2 nd bit data;
s303, in a3 rd subperiod t3 of the period, the data transmitting end enables a3 rd data output port to generate 3 rd bit data;
s304, in a4 th subperiod t4 of the period, the data transmitting end enables a4 th data output port to generate 4 th bit data;
s305, during the following period Tb of the period, the data receiving end reads the data on each data line.
For simplicity, fig. 4 only illustrates the principle of transmitting data from the data transmitting end to the data receiving end at a certain clock period T0 of the clock signal, please refer to fig. 4 in combination with the description of fig. 2 and 3 above:
for the clock period T0, the 1 st sub-period T1 at the front end is occupied by the 1 st data output port of the data transmitting end, and it has been described that since the hardware of the data transmitting end does not support parallel operation, the 4 data output ports cannot be occupied at the same time, and at this time, the 3 data output ports from 2 to 4 are in a non-occupied state—the level change operation cannot be performed. And in the 1 st sub-period t1, 1 st bit of data is generated from the 1 st data output port by the execution of the related instruction by the data transmitting end. In fig. 4, the 1 st bit data is "1", and for example, in the 1 st sub-period t1, the data transmitting end controls the level value of the 1 st data output port to rise from 0 to 3.3V, thereby outputting data "1". The 1 st bit DATA is transmitted to the DATA receiving terminal via the 1 st DATA line DATA 1.
The following 2 nd sub-period t2 is occupied by the 2 nd data output port of the data transmitting end, and the 3 rd data output ports 1, 3 rd and 4 th are in the unoccupied state, so that the 2 nd bit of data is generated from the 2 nd data output port in the 2 nd sub-period t2, and the 2 nd bit of data is also "1" in fig. 4. The DATA of the 2 nd bit is transmitted to the DATA receiving end via the 2 nd DATA line DATA 2. It should be appreciated that during this 2 nd subperiod t2, the 1 st DATA output port is in a non-occupied state where it is unable to change level, so the 1 st DATA output port remains generating a high level signal, for example, a level value of 3.3V, representing DATA "1" flowing to the 1 st DATA line DATA 1. The high level signal output from the 1 st data output port may not be switched to the low level signal until the 1 st sub-period t1 of the next clock cycle, and thus the 1 st data output port is caused to output data "0" in the next clock cycle.
The following 3 rd sub-period t3 is occupied by the 3 rd data output port of the data transmitting end, and the 3 rd data output ports 1, 2 and 4 are in the unoccupied state, so that the 3 rd bit of data is generated from the 3 rd data output port in the 3 rd sub-period t3, and the 3 rd bit of data is also "1" in fig. 4. The DATA of the 3 rd bit is transmitted to the DATA receiving end via the 3 rd DATA line DATA 3. It should be understood that in this 3 rd sub-period t3, the 1 st DATA output port and the 2 nd DATA output port are both in a non-occupied state in which the level cannot be changed, so the 1 st DATA output port and the 2 nd DATA output port remain generating high-level signals representing DATA "1" flowing to the 1 st DATA line DATA1 and the 2 nd DATA line DATA2, respectively. The high level signal output from the 3 rd data output port may not be switched to the low level signal until the 3 rd sub-period t3 of the next clock cycle.
The following 4 th sub-period t4 is occupied by the 4 th data output port of the data transmitting end, at this time, the 3 rd data output ports 1 to 3 rd are in a non-occupied state, and 4 th bit of data is generated from the 4 th data output port in the 4 th sub-period t4, and the 4 th bit of data is also "1" in fig. 4. The DATA of the 4 th bit is transmitted to the DATA receiving end via the 4 th DATA line DATA4. It should be appreciated that during the 4 th subperiod t4, the 1 st to 3 rd data output ports are all in a non-occupied state in which the level cannot be changed, so the 1 st to 3 rd data output ports respectively remain generating high-level signals representing data "1" flowing to the 1 st to 3 rd data lines. The high level signal output from the 4 th data output port may not be switched to the low level signal until the 4 th sub-period t4 of the next clock cycle.
Thereafter, the physical time enters a subsequent period Tb of the clock cycle T0 in fig. 4. As can be seen from the above, in this subsequent period Tb, the 4 DATA output ports each output a high-level signal representing DATA "1" flowing to the 4 DATA lines DATA1 to DATA4. Therefore, as long as the data receiving terminal reads the signals on the respective data lines at the subsequent period Tb of each clock cycle (for example, at the falling edge of the respective clock cycles shown in fig. 4), it is possible to read 4 bits of data in total on 4 data lines at a time per clock cycle. For example, when the clock period T0 signal shown in fig. 4 enters the data receiving terminal, the data receiving terminal may read the aforementioned 1 st, 2 nd, 3 rd and 4 th bits of data from 4 data lines one time at a later period Tb of the clock period T0, such as a falling edge of the clock period T0.
It should be noted that "1 st", "2 nd", "3 rd" and "4 th" of the foregoing 1 st bit data, 2 nd bit data, 3 rd bit data and 4 th bit data do not imply that the four bits of data are subordinate to the same data sequence in the relevant order, and they may be subordinate to four different data sequences, respectively. The embodiment of the present application is not limited thereto.
Obviously, the data transmitting end may also have 2, 3, 5 or more data output ports, and correspondingly, these data output ports are connected to the data receiving end via a corresponding number of data lines, respectively. In connection with the above description of fig. 2 to fig. 4, taking the number of data output ports as N as an example, the previous period Ta of the clock cycle may be divided into N sub-periods according to the time sequence, and the corresponding data output ports output 1 bit of data in each sub-period, and the data receiving end reads N bits of data on each data line in the subsequent period Tb of the clock cycle. It should be understood that the duration of each subinterval should be sufficient to ensure that the data sender is able to complete the data transformation operation in that subinterval (e.g., raising the level value of the port from 0V to 3.3V). In the application, the frequency of the clock signal on the clock line CLK, that is, the duration of the clock period, may be adjusted based on the number of data output ports of the data transmitting end, or the number of data output ports actually participating in communication of the data transmitting end may be selected based on the frequency of the clock signal on the clock line CLK, that is, the duration of the clock period.
In order to improve the data transmission efficiency, the duration of each of the aforementioned 4 sub-periods may be set to the shortest duration required for the data output port (I/O port) switching level. Taking the data transmitting end as a singlechip as an example, the shortest time length can be calculated according to the I/O port frequency of the singlechip, the I/O port frequency can be found in a chip manual, and is generally 72MHz, and the shortest time length can be set to be 0.013ns time length.
Of course, the method is also suitable for the data transmitting end which can work in parallel, such as an FPGA chip, and the data transmission mode has the same data transmission effect as parallel transmission, so that the cost of product development can be reduced in practical application.
In other embodiments, the preceding period Ta includes a falling edge period of a clock cycle, and the following period Tb includes a rising edge period of the clock cycle. In such embodiments, the data receiving end may read the data on the respective data lines at the rising edge of the subsequent period Tb of the clock cycle.
The embodiment of the application also provides a data transmitting terminal, which comprises: at least two data output ports, a memory, a processor, program instructions stored in the memory and executable by the processor; the program instructions, when executed by the processor, cause the data sender to perform the method described above.
The embodiment of the application also provides a communication system, which comprises:
a data transmitting end having N data output ports, N being not less than 2, and including a first memory, a first processor, and first program instructions stored in the first memory and executable by the first processor;
a data receiving end comprising a second memory, a second processor, and second program instructions stored in the second memory and executable by the second processor;
n data lines, which connect N data output ports to the data receiving terminal respectively;
a clock line connected to the data transmitting end and the data receiving end;
wherein the first program instructions, when executed by the first processor, and the second program instructions, when executed by the second processor, cause the communication system to perform the method described above.
The embodiment of the application also provides a computer readable storage medium storing program instructions which, when run on a communication device, cause the communication device to perform the method described above.
Claims (10)
1. A method for transmitting data to a data receiving terminal, wherein the method is applied to a data transmitting terminal having N data output ports, and the data transmitting terminal does not support parallel transmission, N is not less than 2, the N data output ports are respectively 1 st to nth data output ports, the N data output ports are respectively connected to the data receiving terminal through N data lines, a clock line for transmitting a clock signal is connected between the data transmitting terminal and the data receiving terminal, the clock signal includes a plurality of clock cycles, each of the clock cycles includes a preceding period and a following period, one of the preceding period and the following period includes a rising edge period of the clock cycle, the other includes a falling edge period of the clock cycle, the preceding period includes N sub-periods, and the N sub-periods are sequentially 1 st to N sub-periods according to a time sequence, the method includes:
for each of the plurality of clock cycles:
during the 1 st sub-period, causing the 1 st data output port to generate 1 st bit of data;
during the 2 nd sub-period, causing the 2 nd data output port to generate 2 nd bit of data;
and so on, in the nth sub-period, enabling the nth data output port to generate data of the nth bit.
2. The method of claim 1, wherein the N sub-periods are equally set.
3. The method according to claim 1 or 2, wherein the data transmitting end is a single chip microcomputer or an FPGA chip.
4. A method of transmitting data between a data transmitting end and a data receiving end, wherein the data transmitting end has N data output ports, and the data transmitting end does not support parallel transmission, N is not less than 2, the N data output ports are respectively 1 st to nth data output ports, the N data output ports are respectively connected to the data receiving end through N data lines, and a clock line for transmitting a clock signal is connected between the data transmitting end and the data receiving end, the clock signal includes a plurality of clock cycles, each of the clock cycles includes a preceding time period and a following time period, one of the preceding time period and the following time period includes a rising edge time period of the clock cycle, the other includes a falling edge time period of the clock cycle, the preceding time period includes N sub-time periods, the N sub-time periods are sequentially 1 st to N sub-time periods in time sequence, the method comprising:
for each of the plurality of clock cycles:
in the 1 st subperiod, the data transmitting end enables the 1 st data output port to generate 1 st bit data;
in the 2 nd subperiod, the data transmitting end enables the 2 nd data output port to generate 2 nd bit data;
and so on, in the nth sub-period, the data transmitting end enables the nth data output port to generate data of an nth bit;
and in the later period, the data receiving end reads the data on each data line.
5. The method of claim 4, wherein the N sub-periods are equally set.
6. The method according to claim 4 or 5, wherein the data transmitting end is a single chip microcomputer or an FPGA chip, and the data receiving ends are all FPGA chips.
7. A data transmitting terminal, comprising:
at least two of the data output ports,
the memory device is used for storing the data,
processor and method for controlling the same
Program instructions stored in the memory and executable by the processor;
the program instructions, when executed by the processor, cause the data sender to perform the method of any one of claims 1 to 3.
8. A chip, comprising:
at least two of the data output ports,
the memory device is used for storing the data,
processor and method for controlling the same
Program instructions stored in the memory and executable by the processor;
the program instructions, when executed by the processor, cause the data sender to perform the method of any one of claims 1 to 3.
9. A communication system, comprising:
the data transmitting end is provided with N data output ports, N is not less than 2, and comprises a first memory, a first processor and first program instructions which are stored in the first memory and can be executed by the first processor;
the data receiving end comprises a second memory, a second processor and second program instructions which are stored in the second memory and can be executed by the second processor;
n data lines respectively connecting the N data output ports to the data receiving end;
the clock line is connected with the data sending end and the data receiving end;
wherein the first program instructions, when executed by the first processor and the second program instructions, when executed by the second processor, cause the communication system to perform the method of any of claims 1 to 3.
10. A computer readable storage medium having stored thereon program instructions, which when run on a communication device cause the communication device to perform the method of any of claims 1 to 6.
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