CN116781077A - Analog-to-digital conversion circuit calibration method and system - Google Patents
Analog-to-digital conversion circuit calibration method and system Download PDFInfo
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Abstract
The application relates to a calibration method and a calibration system of an analog-to-digital conversion circuit, which are configured by a plurality of cascaded analog-to-digital conversion modules in the analog-to-digital conversion circuit, so that when the input of the analog-to-digital conversion module is a first input value, the amplitude of a signal output by the multiplying digital-to-analog converter is the largest. Under the condition that the input of the analog-to-digital conversion module is a first input value, the output of the sub-analog-to-digital converter is changed, and the weight error of the corresponding nth capacitor to be calibrated is calculated according to the output values of the multiplication digital-to-analog converters under the output of different sub-analog-to-digital converters. And calibrating the output of the analog-to-digital conversion module according to the weight error. Therefore, the capacitor of the pipeline analog-to-digital conversion circuit can be calibrated by setting the sub analog-to-digital converter without inputting a plurality of voltage signals with different amplitudes by an additional signal generator, the circuit structure is simplified, and the calibration efficiency is improved.
Description
Technical Field
The present application relates to the field of analog-to-digital conversion circuits, and in particular, to a method and a system for calibrating an analog-to-digital conversion circuit.
Background
Analog-to-digital converters (ADCs) are used to convert analog signals to digital signals, which are widely used in the fields of wireless communications, high-end test equipment, image-to-voice processing, and the like. With the development of advanced technology and design technology and the expansion of application scenes, the demand for high-speed and high-precision ADCs is increasingly remarkable. And the pipeline ADC can achieve a better compromise between speed and precision. However, mismatch between sampling capacitors and feedback capacitors of the high-precision pipelined ADC may cause DAC errors of sub-digital-to-analog converters (SDACs) and inter-stage gain errors of multiplying digital-to-analog converters (MDACs) in the pipeline, thereby causing actual weights and ideal weights of output symbols of the ADC to be different, resulting in quantization errors, and affecting dynamic and static performances of the ADC.
In the prior art, two capacitance mismatch error calibration algorithms for the pipeline analog-to-digital converter are mainly two types, namely foreground calibration and background calibration. The background calibration has the common problems of dependence of the calibration effect on statistics, slow convergence speed, even misconvergence, high calculation complexity, high cost and the like, and in addition, the background calibration mostly limits the dynamic range of an input signal, and requires an additional pseudo-random code generator and an injection circuit, thereby having additional power consumption. The existing foreground calibration method can only calibrate one of the interstage gain error or the capacitance mismatch error, or requires a complex foreground calibration circuit and a plurality of analog signals for independent test during calibration, and has the disadvantages of complex flow, large calculated amount and low calibration efficiency.
At present, an effective solution has not been proposed for the problem of low capacitance calibration efficiency of a pipeline analog-to-digital converter in the related art.
Disclosure of Invention
Accordingly, it is desirable to provide a calibration method and system for an analog-to-digital conversion circuit capable of improving the capacitance calibration efficiency of a pipeline analog-to-digital converter.
In a first aspect, the present application provides a method for calibrating an analog-to-digital conversion circuit. The method comprises the following steps:
Configuring the sub-digital-to-analog converter and the multiplication digital-to-analog converter so that a transmission curve of the multiplication digital-to-analog converter translates, and when the input of the analog-to-digital conversion module is a first input value, the amplitude of a signal output by the multiplication digital-to-analog converter is close to the maximum amplitude in the transmission curve;
under the condition that the input of the analog-to-digital conversion module is the first input value, changing the output of the sub-analog-to-digital converter, and calculating the weight error of the corresponding nth capacitor to be calibrated according to the output values of the multiplication digital-to-analog converter under different sub-analog-to-digital converter outputs, wherein n is the arrangement sequence number of the selected capacitor to be calibrated in the corresponding sub-analog-to-digital converter;
and calibrating the output of the analog-to-digital conversion module according to the weight error.
In one embodiment, varying the output of the sub-analog-to-digital converter comprises:
setting the sub-analog-digital converter so that the output of the sub-analog-digital converter is a first output value and a second output value respectively, wherein the low n-1 bit of the first output value is a first preset value, and the rest bits are a second preset value; the lower n bits of the second output value are the first preset value, and the rest bits are the second preset value.
In one embodiment, calculating the weight error of the corresponding nth capacitance to be calibrated includes:
and acquiring a first voltage value output by the multiplication digital-to-analog converter corresponding to the first output value and a second voltage value output by the multiplication digital-to-analog converter corresponding to the second output value.
And calculating the weight error of the corresponding nth capacitor to be calibrated according to the first voltage value and the second voltage value.
In one embodiment, calculating the weight error of the corresponding nth capacitance to be calibrated further includes:
and obtaining a difference value between the first voltage value and the second voltage value.
And calculating the actual weight of the nth capacitance to be calibrated according to the difference value.
And calculating the weight error of the nth capacitance to be calibrated according to the actual weight and the ideal weight of the nth capacitance to be calibrated.
In one embodiment, after calculating the weight error of the corresponding nth capacitance to be calibrated, the method further comprises:
setting the sub-analog-digital converter to enable the output of the sub-analog-digital converter to be a third output value, wherein the low n-1 bit and the n+m bit of the third output value are the first preset value, and the rest bits are the second preset value.
And obtaining a third voltage value output by the multiplication digital-to-analog converter corresponding to the third output value.
And calculating the weight error of the corresponding n+m-th capacitance to be calibrated according to the third voltage value and the first voltage value.
In one embodiment, after calculating the weight error of the corresponding nth capacitance to be calibrated, the method further comprises:
setting the sub-analog-digital converter to enable the output of the sub-analog-digital converter to be a fourth output value, wherein the rest bits except the n-th bit in the low n bits of the fourth output value are all the first preset value, and the n-th bit and all the bits except the low n bits are all the second preset value; .
And acquiring a fourth voltage value output by the multiplication digital-to-analog converter corresponding to the fourth output value.
And calculating the weight error of the corresponding n-t capacitors to be calibrated according to the fourth voltage value and the second voltage value.
In one embodiment, calibrating the output of the analog-to-digital conversion circuit according to the weight error includes:
and selecting different weight errors of the capacitors to be calibrated according to the weight errors and the output of the sub-analog-digital converter, updating the output weight of the analog-digital conversion module, and calibrating the output of the analog-digital conversion circuit according to the updated output weight.
In one embodiment, updating the output weight of the analog-to-digital conversion module includes:
an output a of the sub-analog-to-digital converter is obtained.
When the output a of the sub-analog-digital converter is smaller than the half b of the analog-digital conversion circuit, the output weight of the analog-digital conversion module is updated by using the weight errors of the a+1 th to b-a-1 th capacitors to be calibrated.
When the output a of the analog-to-digital converter is larger than the half b of the bit number of the analog-to-digital conversion circuit, updating the output weight of the analog-to-digital conversion module by using the weight errors of the a-th to b-th capacitors to be calibrated.
In a second aspect, the application further provides an analog-to-digital conversion circuit calibration system. The system comprises: the device comprises an analog-to-digital conversion circuit to be calibrated, a short-circuit switch, a setting control circuit and a processing circuit; wherein, the liquid crystal display device comprises a liquid crystal display device,
the analog-to-digital conversion circuit to be calibrated comprises a sub analog-to-digital converter and a multiplication digital-to-analog converter;
the short-circuit switch is used for setting the input of the analog-to-digital conversion circuit to be calibrated as a first input value;
the setting control circuit is used for changing the output of the sub-analog-digital converter;
the processing circuit is used for calculating the weight error of the corresponding nth capacitor to be calibrated according to the output values of the multiplication digital-to-analog converter under the output of different sub-digital-to-analog converters, and calibrating the output of the analog-to-digital conversion circuit to be calibrated according to the weight error.
In one embodiment, the analog-to-digital conversion circuit to be calibrated further includes: calibrating the capacitance; the calibration capacitor is connected with an intermediate node of the multiplying digital-to-analog converter, and is used for configuring the multiplying digital-to-analog converter to have the largest signal amplitude of the output of the multiplying digital-to-analog converter when the input of the analog-to-digital conversion circuit to be calibrated is the first input value.
According to the analog-to-digital conversion circuit calibration method and system, the multiplication digital-to-analog converter of the plurality of cascaded analog-to-digital conversion modules in the analog-to-digital conversion circuit is configured, so that the amplitude of the signal output by the multiplication digital-to-analog converter is maximum when the input of the analog-to-digital conversion module is the first input value. Under the condition that the input of the analog-to-digital conversion module is a first input value, the output of the sub-analog-to-digital converter is changed, and the weight error of the corresponding nth capacitor to be calibrated is calculated according to the output values of the multiplication digital-to-analog converters under the output of different sub-analog-to-digital converters. And calibrating the output of the analog-to-digital conversion module according to the weight error. Therefore, the capacitor of the pipeline analog-to-digital conversion circuit can be calibrated by setting the sub analog-to-digital converter without inputting a plurality of voltage signals with different amplitudes by an additional signal generator, the circuit structure is simplified, and the calibration efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of errors in a pipelined analog-to-digital conversion circuit in one embodiment;
FIG. 2 is a graph of error effects in a pipelined analog-to-digital conversion circuit in one embodiment;
FIG. 3 is a flow chart of a method of calibrating an analog-to-digital conversion circuit according to one embodiment;
FIG. 4 is a schematic diagram of a pipeline analog-to-digital conversion circuit according to an embodiment;
FIG. 5 is a circuit diagram of an analog-to-digital conversion module according to one embodiment;
FIG. 6 is a schematic diagram of a foreground calibration method in the prior art;
FIG. 7 is a schematic diagram of capacitance mismatch error of an analog-to-digital conversion circuit according to one embodiment;
FIG. 8 is a schematic diagram of an inter-stage gain error of an analog-to-digital conversion circuit in one embodiment;
FIG. 9 is a schematic diagram illustrating a left shift of an analog-to-digital conversion circuit transmission curve according to one embodiment;
FIG. 10 is a circuit diagram of a method of calibrating an analog-to-digital conversion circuit according to one embodiment;
FIG. 11 is a flow chart of calibration of various stages of the analog-to-digital conversion circuit in one embodiment;
FIG. 12 is a block diagram of an analog to digital conversion circuit calibration system in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In pipelined analog-to-digital conversion circuits, there may be two errors. Fig. 1 is a schematic diagram of errors in a pipelined analog-to-digital conversion circuit, as shown in fig. 1, mismatch errors result in up-and-down shifting of the transmission curve, while interstage gain errors result in slope changes of the transmission curve. The two act together in an analog to digital conversion circuit, the resulting effect is shown in fig. 2. Wherein the dashed line represents the ideal curve and the solid line represents the curves under the action of both errors.
In one embodiment, as shown in fig. 3, there is provided an analog-to-digital conversion circuit calibration method, the analog-to-digital conversion circuit including a plurality of cascaded analog-to-digital conversion modules, the analog-to-digital conversion modules including an analog-to-digital converter and a multiplying digital-to-analog converter, the method comprising the steps of:
step S302, the sub-analog-digital converter and the multiplication digital-analog converter are configured so that the transmission curve of the multiplication digital-analog converter translates, and when the input of the analog-digital conversion module is the first input value, the amplitude of the signal output by the multiplication digital-analog converter is close to the maximum amplitude in the transmission curve.
Fig. 4 is a schematic diagram of an architecture of a pipeline analog-to-digital conversion circuit, as shown in fig. 4, an input signal Vin is transmitted to a first stage analog-to-digital conversion module STG1 after passing through a sample-and-hold circuit (S/H) (or not) and then sequentially passes through each stage of analog-to-digital conversion modules STG2-STGK and a last stage flash (flash) analog-to-digital conversion module, and when passing through each stage of analog-to-digital conversion module, a quantized result dstagei_h (i=1, 2, … …, k+1, K represents the maximum number of stages of the analog-to-digital conversion modules STG 2-STGK) of the stage of sub-analog-to-digital converter is output to a digital output terminal Dout after weighted addition, so as to obtain a final quantized result. The effective bit of each analog-to-digital conversion module is added to be equal to the resolution (precision) of the analog-to-digital conversion circuit of the pipeline. Each analog-digital conversion module consists of a sub-analog-digital converter, a multiplication digital-analog converter, a gain stage and the like. Taking the analog-digital conversion module STG1 as an example, the sub-analog-digital converter coarsely quantizes the input signals Vin and 1 to obtain quantized results Dstage1_h, and transmits the quantized results Dstage1_h to the digital end, and controls the multiplying digital-analog converter to amplify residual voltage generated by the difference between the input signals and the voltage obtained by the multiplying digital-analog converter through the gain stage Gk, and then transmits the amplified residual voltage to the input Vin and 2 of the next stage.
Fig. 5 is a circuit configuration diagram of an analog-to-digital conversion module, as shown in fig. 5, the effective bit of the analog-to-digital conversion module is 3 bits, the redundant bit is 1bit, the sampling capacitance is Cs0, cs1, … …, cs15, the total capacitance value of the sampling capacitance is cs=cs 0+ Cs1+ … … + Cs15, the feedback capacitance is Cf, the ideal unit sampling capacitance value of the analog-to-digital conversion module is Cu, and in ideal cases, the inter-stage gain gk=cs/Cf, cs 0=cs 1= … … =cs 15=cu, cf=2×cu, gk=cs/cf=16×cu/2×cu=8.
At this time, the analog-to-digital conversion module is calibrated, fig. 6 is a schematic diagram of a foreground calibration method in the prior art, as shown in fig. 6, taking n=16, m=3, k=6, and the last stage of flashADC is 2 bits as an example, where N is the precision of the ADC, M is the precision of the first stage of analog-to-digital conversion module, K is the number of stages of the analog-to-digital conversion module including the multiplying digital-to-analog converter, and since the flashADC of the last stage does not have the multiplying digital-to-analog converter, the flashADC of the last stage is not calibrated in the embodiment of the application. Because of the capacitance mismatch error (as shown in fig. 7) and the inter-stage gain error (as shown in fig. 8) of the analog-to-digital conversion module, calibration is required, and different analog signals need to be input during the calibration. For example, if the capacitor Cs0 corresponding to the a segment in fig. 7 and 8 needs to be calibrated, an analog signal with an amplitude of-15/16×vref needs to be input, and the output d_sadc of SADC (sub-analog-digital converter) is respectively 0 and 1 (corresponding to the thermal codes are 00000000000000000 and 00000000000000001 respectively), so that the obtained output value can be differenced, and the calibration of the capacitor Cs0 to be calibrated can be further completed. This requires an additional signal generator, which is complicated, for example, in fig. 6, and if 16 capacitors of the analog-to-digital conversion block STG1 are to be calibrated, 16 input signals of different magnitudes are required. Therefore, the method has the advantages of higher calibration difficulty and lower calibration efficiency.
The embodiment of the application adopts a method for calibrating the analog-to-digital conversion module when the input is a first input value, wherein the first input value is a direct current signal, the voltage variation fluctuation of the direct current signal is small, and when the input of the analog-to-digital conversion module is the first input value, the amplitude of a signal output by the multiplying digital-to-analog converter is close to the maximum amplitude in a transmission curve, and specifically, the amplitude fluctuation of the signal output is +/-10% of the maximum amplitude, so that the signal can be regarded as being close to the maximum amplitude. In this embodiment, the first input value takes a dc input signal with a voltage of 0. In the actual calibration process, the voltage amplitude of the first input value is not fixed, so long as the voltage is basically free from fluctuation. When the voltage signal is changed, the translation distance of the transmission curve of the multiplication digital-to-analog converter is also changed, and corresponding to the translation distance, each preset output value of the sub analog-to-digital converter is also changed during calibration. As shown in fig. 8, after the transmission curve is shifted to the left by a distance of 1/16 vref, the transmission curve is just near the turning point (segment 6,7H/segment I in fig. 6,7H) of the transmission curve when the input signal amplitude is 0. I.e., the input signal amplitude is 0, the output is the positive maximum voltage amplitude of the H segment and the negative maximum voltage amplitude of the I segment.
Step S304, under the condition that the input of the analog-digital conversion module is the first input value, the output of the sub-analog-digital converter is changed, and the weight error of the corresponding nth capacitor to be calibrated is calculated according to the output values of the multiplication digital-analog converters under the output of different sub-analog-digital converters, wherein n is the arrangement sequence number of the selected capacitor to be calibrated in the corresponding sub-analog-digital converter.
As shown in fig. 5, when the amplitude of the input signal is the first input value, if the analog signal at the input end of the analog-to-digital conversion circuit is input at full scale, the analog-to-digital conversion module STG1 will generate at most 2 (m+1) +1 thermal codes Dstage1_h, which are sequentially 00 … … 00, 00 … … 01, 00 … … 11, … …,01 … … 11, 11 … … 11, and corresponding decimal codes Dstage1_d are sequentially 0,1,2, … …,16. When the quantization result is calculated, the calculation weight of STG1 is set to W1, the later-stage weight is Wi (1<i is less than or equal to K), and the output quantization code of the pipeline analog-digital conversion circuit is as follows:
Dout_ADC＝Dstage1_d*W1+Dstage2_d*W2+…+Dstagei_d*Wi+…+Dstagek_d*Wk+DstageK+1_d。
because of mismatch errors and gain errors, the weight coefficients W1 to Wi are inaccurate and need to be adjusted according to the actual errors. And selecting an nth capacitor to be calibrated, wherein n is the arrangement sequence number of the selected capacitor to be calibrated in the corresponding sub-analog-digital converter, and the value range of n is 1 to the number of capacitors to be calibrated in the sub-analog-digital converter. And calibrating the weight coefficient corresponding to the nth calibration capacitor. Because in the embodiment of the present application, as shown in fig. 9, the transmission curve shifts left, so that when the input is 0, the output is the maximum voltage amplitude. Thus, the input of the analog-to-digital conversion module is set to the first input value, changing the output of the sub-analog-to-digital converter. Because the nth capacitor to be calibrated needs to be calibrated, the corresponding values of the other capacitors except the capacitor to be calibrated in the output of the corresponding multiplication digital-to-analog converter under the output of different sub-analog-to-digital converters need to be ensured to be eliminated by making differences or other methods. In this way, the result including only the capacitance to be calibrated can be obtained.
Step S306, calibrating the output of the analog-to-digital conversion module according to the weight error.
After obtaining an output result only comprising the capacitor to be calibrated, comparing the actual output result with an ideal output result, and updating the comparison result to a weight coefficient output by the analog-to-digital conversion module, thereby completing the calibration of the capacitor to be calibrated.
In this embodiment, the multiplying digital-to-analog converter of several cascaded analog-to-digital conversion modules in the analog-to-digital conversion circuit is configured, so that when the input of the analog-to-digital conversion module is 0, the amplitude of the signal output by the multiplying digital-to-analog converter is the largest. Under the condition that the input of the analog-to-digital conversion module is 0, the output of the sub-analog-to-digital converter is changed, and the weight error of the corresponding nth capacitor to be calibrated is calculated according to the output values of the multiplication digital-to-analog converters under the output of different sub-analog-to-digital converters. And calibrating the output of the analog-to-digital conversion module according to the weight error. Therefore, the capacitor of the pipeline analog-to-digital conversion circuit can be calibrated by setting the sub analog-to-digital converter without inputting a plurality of voltage signals with different amplitudes by an additional signal generator, the circuit structure is simplified, and the calibration efficiency is improved.
In one embodiment, varying the output of the sub-analog-to-digital converter includes: setting the sub analog-to-digital converter to enable the output of the sub analog-to-digital converter to be a first output value and a second output value respectively, wherein the low n-1 bit of the first output value is a first preset value, and the rest bits are a second preset value; the lower n bits of the second output value are the first preset value, and the rest bits are the second preset value.
The method comprises the steps of setting a sub analog-digital converter twice, and obtaining a result only comprising an nth capacitor to be calibrated by a method of setting twice and outputting a result difference. The first preset value and the second preset value can be changed according to an actually adopted calibration method. When the first preset value is 1 and the second preset value is 0, the low n-1 bit of the first output value of the sub-analog-digital converter is made to be the first preset value (namely 1) and the rest bits are made to be the second preset value (namely 0) during the first setting, at this time, under the first output value, the first n-1 capacitors in the output result are output with positive voltages, and the rest are output with negative voltages. And when the second setting is performed, the lower n bits of the second output value of the sub-analog-digital converter are made to be a first preset value (namely 1), the rest bits are made to be a second preset value (namely 0), at the moment, under the second output value, the upper outputs of the first n capacitors in the output result are all positive voltages, and the rest are all negative voltages. When the first preset value is 0 and the second preset value is 1, the low n-1 bit of the first output value of the sub-analog-digital converter is made to be the first preset value (namely 0) and the rest bits are made to be the second preset value (namely 1) during the first setting, at this time, under the first output value, the output on the first n-1 capacitors in the output result is negative voltage, and the rest are positive voltages. And when the second setting is performed, the lower n bits of the second output value of the sub-analog-digital converter are made to be a first preset value (namely 0), the rest bits are made to be a second preset value (namely 1), at the moment, under the second output value, the upper outputs of the first n capacitors in the output result are negative voltages, and the rest are positive voltages. It can be seen that the output result only including the nth capacitor to be calibrated can be obtained by differentiating the calibration method from 0 to 1 or from 1 to 0. Because the analog-to-digital conversion module generally does not have the conditions of high-order 1 and low-order 0 when actually working, the embodiment of the application adopts the method that the first preset value is 1 and the second preset value is 0 for calibration.
In the embodiment, the elimination of the voltage values on the rest capacitors can be realized by setting the sub-analog-digital converter under the condition that no external signal generator is added, so that the actual weight of the capacitor to be calibrated is obtained, the calibration efficiency is improved, and the calibration cost is reduced.
In one embodiment, calculating the weight error for the corresponding nth capacitance to be calibrated includes: and acquiring a first voltage value output by the multiplication digital-to-analog converter corresponding to the first output value and a second voltage value output by the multiplication digital-to-analog converter corresponding to the second output value. And calculating the weight error of the corresponding nth capacitor to be calibrated according to the first voltage value and the second voltage value.
The first voltage value and the second voltage value are differenced, and the first voltage value should be Vref/2 and the second voltage value should be-Vref/2 in ideal cases, wherein Vref is a reference voltage. Therefore, the result obtained after the difference is equal to the reference voltage value, i.e., the weight coefficient in the ideal.
Specifically, fig. 10 is a circuit diagram of a calibration method of an analog-to-digital conversion circuit according to an embodiment of the present application, as shown in fig. 10, taking a calibration capacitor Cs8 as an example, the input amplitude of the input end is made to be 0, the output of the sub-analog-to-digital converter is set to be a first output value 8 (i.e. 0000000011111111), and the output voltage amplitude of the multiplying digital-to-analog converter is:
Ideally, this is equal to Vref/2. The voltage is quantized by a post-stage 13-bit analog-to-digital conversion module and then calculated as D1_code (1).
Next, the output of the sub-adc is set to the second output value 9 (i.e. 0000000111111111), and the output voltage amplitude of the multiplying dac is:
ideally, this is equal to-Vref/2. The voltage is quantized by a post-stage 13-bit analog-to-digital conversion module and then calculated as D1_code (2).
The difference between the two is that the capacitance except Cs8 is eliminated, so that:
and because there is an error between the ideal value and the actual value, the error on Cs8 is:
D1_err8＝4096-D1_res8
thus, the weight error corresponding to Cs8 can be obtained.
In this embodiment, the sub-analog-digital converter is set twice, so that the error of the capacitor on the corresponding bit number can be obtained, and different signals are not required to be input into the additional signal generator respectively, so that the circuit structure is simplified, and the calibration efficiency is improved.
In one embodiment, calculating the weight error of the corresponding nth capacitance to be calibrated further comprises: and obtaining a difference value between the first voltage value and the second voltage value. And calculating the actual weight of the nth capacitance to be calibrated according to the difference value. And calculating the weight error of the nth capacitance to be calibrated according to the actual weight and the ideal weight of the nth capacitance to be calibrated.
Wherein, since the first voltage value and the second voltage value are the same as each other except for one item containing the capacitor to be measured. Therefore, the influence of other capacitors can be eliminated by making a difference, and a voltage result only comprising the capacitor to be tested is obtained. Ideally, the first voltage value should be +Vref/2, the second voltage value should be-Vref/2, and the difference should be Vref. In practice, the actual difference is not equal to the ideal value due to the mismatch error and gain error. Thus, the actual resulting voltage value (i.e., the actual weight) is compared with the ideal weight to obtain a weight error.
Specifically, taking the calibration of Cs8 as an example, after the first voltage value and the second voltage value are obtained, the two values are subtracted, and the capacitances except Cs8 are all eliminated, so:
and because there is an error between the ideal value and the actual value, the error on Cs8 is:
D1_err8＝4096-D1_res8
thus, the weight error corresponding to Cs8 can be obtained.
In this embodiment, the obtained weight error is calculated by the maximum turning point of the n-1 th bit and the minimum turning point of the n-1 th bit, and includes not only the mismatch error for the up-down translation, but also the gain error of the slope table.
In one embodiment, after calculating the weight error of the corresponding nth capacitance to be calibrated, the method further comprises: setting the sub analog-to-digital converter to enable the output of the sub analog-to-digital converter to be a third output value, wherein the low n-1 bit and the n+m bit of the third output value are the first preset value, and the rest bits are the second preset value. And obtaining a third voltage value output by the multiplication digital-to-analog converter corresponding to the third output value. And calculating the weight error of the corresponding n+m-th capacitance to be calibrated according to the third voltage value and the first voltage value.
And the value range of n+m is not more than the highest level of the analog-digital conversion module on the basis of the level n corresponding to the selected capacitance to be calibrated. The previous calibration data may be multiplexed while the remaining capacitances are calibrated. When the n+m capacitor is calibrated, the sub analog-to-digital converter is set once, and calibration can be completed. In the previous calibration process, the first voltage value corresponding to the first output value with the low n-1 bit being the first preset value and the rest being the second preset value has been obtained, so that if the voltage items of the rest capacitors are to be eliminated, only the n+m voltage items of the capacitors to be calibrated are reserved, the sub-analog-digital converter can be set to the third output value, i.e. the low n-1 bit and the n+m bit are the first preset value and the rest are the second preset value. In this way, by making the difference, only the n+m-th capacitance voltage term to be calibrated can be reserved.
Specifically, taking the calibration Cs9 as an example, the output of the sub-adc is set to 0000001011111111, where the third voltage value output by the multiplying dac is:
ideally this is also equal to-Vref/2, and this voltage is calculated as D1_code (2) after quantization by the post 13-bit ADC. Difference is made between D1_code (2) and D1_code (1), and the actual weight is obtained as follows:
comparing the obtained weight error with an ideal weight to obtain a weight error: d1_err9=4096-d1_res9. And updating the weight error into the output weight, thus finishing the calibration of Cs 9.
Taking the calibration Cs10 as an example, the output of the sub-adc is set to 0000010011111111, where the third voltage value output by the multiplying dac is:
ideally this is also equal to-Vref/2, and this voltage is calculated as D1_code (2) after quantization by the post 13-bit ADC. Difference is made between D1_code (2) and D1_code (1), and the actual weight is obtained as follows:
comparing the obtained weight error with an ideal weight to obtain a weight error: d1_err10=4096-d1_res10. And updating the weight error into the output weight, thus finishing the calibration of Cs 9.
And (4) calibrating the Cs11-Cs15 by analogy. When D1_err9-D1_err15 is calculated, the value of D1_code (1) can be multiplexed with the value when D1_err8 is calculated, repeated calculation and storage are not needed, and after D1_err8-D1_err15 is calculated respectively, the storage space of D1_res can be correspondingly emptied, and because the capacitance mismatch error is usually not large, the value of D1_err is smaller, the required storage space is smaller, and compared with a method for directly storing D1_res, the storage space is greatly saved, and the hardware cost is saved.
In this embodiment, when the weight error of the high-order capacitor is calculated, the previous data can be multiplexed, so that the calibration of the capacitor to be calibrated can be completed only by setting the sub-analog-digital converter once to obtain the third voltage value corresponding to the third output value, the reusability of the data and the calibration efficiency are improved, and the calibration cost is reduced.
In one embodiment, after calculating the weight error of the corresponding nth capacitance to be calibrated, the method further comprises: setting the sub analog-to-digital converter to enable the output of the sub analog-to-digital converter to be a fourth output value, wherein the rest bits except the n-th bit in the low n bits of the fourth output value are all first preset values, and the n-th bit and all bits except the low n bits are all second preset values; acquiring a fourth voltage value output by a multiplication digital-to-analog converter corresponding to the fourth output value; and calculating the weight error of the corresponding n-t capacitors to be calibrated according to the fourth voltage value and the second voltage value.
And the value range of n-t is not less than 1 on the basis of the number n of stages corresponding to the selected capacitance to be calibrated, wherein t represents the capacitance to be calibrated in the analog-digital conversion module of the number n-t lower than the number n of the n-th stage t bits. The previous calibration data may be multiplexed while the remaining capacitances are calibrated. When the n-t capacitors are calibrated, the sub analog-to-digital converter is set once, and calibration can be completed. In the previous calibration process, the second voltage value corresponding to the second output value when the lower n bits are the first preset value and the rest bits are the second preset value has been obtained, so if the voltage items of the rest capacitors are to be eliminated, only the voltage items of the n-t capacitors to be calibrated are reserved, the sub-analog-digital converter can be set as the fourth output value, that is, the rest bits except the n-t bits in the lower n bits are the first preset value, and all the n-t bits and all the bits except the lower n bits are the second preset value. In this way, by making the difference, only the n-t-th capacitance voltage term to be calibrated can be reserved.
Specifically, taking the calibration Cs7 as an example, the output of the sub-adc is set to 0000001011111111, and the third voltage value output by the multiplying dac is:
ideally this is equal to Vref/2, which is calculated as D1_code (2) after quantization by the post 13-bit ADC. Difference is made between D1_code (2) and D1_code (1), and the actual weight is obtained as follows:
comparing the obtained weight error with an ideal weight to obtain a weight error: d1_err7=4096-d1_res7. And updating the weight error into the output weight, thus finishing the calibration of Cs 7.
Next, cs6 is calibrated, the output of the sub-adc is set to 000000110111111, and the fourth voltage value output by the multiplying dac is:
ideally this is equal to Vref/2, which is calculated as D1_code (2) after quantization by the post 13-bit ADC. Difference is made between D1_code (2) and D1_code (1), and the actual weight is obtained as follows:
comparing the obtained weight error with an ideal weight to obtain a weight error: d1_err6=4096-d1_res6. And updating the weight error into the output weight, thus finishing the calibration of Cs 6.
Next, cs5-Cs0 can be calibrated by analogy with the procedure described above. When d1_err0-d1_err6 is calculated, the value of d1_code (1) can be multiplexed with the value when d1_err7 is calculated, repeated calculation and storage are not needed, and after d1_err7-d1_err0 is calculated respectively, the storage space of d1_res can be correspondingly emptied.
In this embodiment, when the weight error of the low-order capacitor is calculated, the previous data can be multiplexed, so that the sub-analog-digital converter is set only once to obtain the fourth voltage value corresponding to the fourth output value, the calibration of the capacitor to be calibrated can be completed, the reusability of the data and the calibration efficiency are improved, and the calibration cost is reduced.
In one embodiment, updating the output weight of the analog-to-digital conversion module includes:
obtaining an output a of the sub-analog-digital converter;
when the output a of the sub analog-to-digital converter is smaller than half b of the maximum output value of the analog-to-digital conversion module, updating the output weight of the analog-to-digital conversion module by using the weight error of the a+1th to b-a-1th capacitors to be calibrated;
when the output a of the sub analog-digital converter is larger than the half b of the maximum output value of the analog-digital conversion module, the output weight of the analog-digital conversion module is updated by utilizing the weight errors of the a-th to b-th capacitors to be calibrated.
When the output a of the sub analog-digital converter is smaller than half of the maximum output value b of the analog-digital conversion module, the output of the analog-digital conversion module is the output value of the sub analog-digital conversion module multiplied by the original weight coefficient and added with the weight errors of the (a+1) -th to (b-a-1) -th capacitors to be calibrated. When the output a of the sub analog-digital converter is larger than half of the maximum output value b of the analog-digital conversion module, the output of the analog-digital conversion module is the output value of the sub analog-digital conversion module multiplied by the original weight coefficient and added with the weight errors of the a-th to b-th capacitors to be calibrated. Particularly, when the output a of the sub-analog-digital converter is equal to half of the maximum output b of the analog-digital conversion module, it can be seen that the output of the analog-digital conversion module is the output of the sub-analog-digital conversion module multiplied by the original weight coefficient.
Specifically, taking the first-stage analog-to-digital conversion module as an example, dstage1 is the output of the first-stage analog-to-digital conversion module, dstage1_d is the output value of the sub-analog-to-digital converter, and Dstage 1_erri is the weight error of the capacitor Csi.
When dstag1 _ d=0,
Dstage1＝Dstage1_d*4096+D1_err0+D1_err1+D1_err2+D1_err3+D1_err4+D1_err5+D1_err6+D1_err7
when dstag1 _ d=1,
Dstage1＝Dstage1_d*4096+D1_err1+D1_err2+D1_err3+D1_err4+D1_err5+D1_err6+D1_err7
when dstag1 _ d=2,
Dstage1＝Dstage1_d*4096+D1_err2+D1_err3+D1_err4+D1_err5+D1_err6+D1_err7
when dstag1 _ d=3,
Dstage1＝Dstage1_d*4096+D1_err3+D1_err4+D1_err5+D1_err6+D1_err7
when dstag1 _ d=4,
Dstage1＝Dstage1_d*4096+D1_err4+D1_err5+D1_err6+D1_err7
when dstag1 _ d=5,
Dstage1＝Dstage1_d*4096+D1_err5+D1_err6+D1_err7
when dstag1 _ d=6,
Dstage1＝Dstage1_d*4096+D1_err6+D1_err7
when dstag1 _ d=7,
Dstage1＝Dstage1_d*4096+D1_err7
when dstag1 _ d=8,
Dstage1＝Dstage1_d*4096
when dstag1 _ d=9,
Dstage1＝Dstage1_d*4096-D1_err8
when dstag1 _ d=10,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9
when dstag1 _ d=11,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9-D1_err10
when dstag1 _ d=11,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9-D1_err10-D1_err11
when dstag1 _ d=13,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9-D1_err10-D1_err11-D1_err11
when dstag1 _ d=14,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9-D1_err10-D1_err11-D1_err11-D1_err13
when dstag1 _ d=15,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9-D1_err10-D1_err11-D1_err11-D1_err13-D1_err14
when dstag1 _ d=16,
Dstage1＝Dstage1_d*4096-D1_err8-D1_err9-D1_err10-D1_err11-D1_err11-D1_err13-D1_err14-D1_err15。
in this embodiment, the gain error and the mismatch error can be simultaneously eliminated by updating the output weight of the analog-to-digital conversion module, thereby improving the calibration efficiency.
For different stages of analog-to-digital conversion modules, the calibration process is similar to that of the first stage analog-to-digital conversion module. Specifically, fig. 11 is a flowchart of calibration of each stage of the analog-to-digital conversion circuit according to the embodiment of the present application, as shown in fig. 11, when in calibration, the active bit input short-circuit switch and the calibration enabling switch of the stage are turned on, the calibration capacitor is connected, and the sub-analog-to-digital converter enters the set working mode. The stage is M-bits, i= 2^M, the sub-analog-digital converter of the stage is set as a first output value, and a first voltage value D_code (1) is calculated; setting the sub-analog-digital converter of the stage as a second output value, and calculating a first voltage value D_code (2), wherein the final actual weight is as follows: D_resi=D_code (1) -D_code (2), the weight error is the ideal weight w minus the actual weight D_resi, at this time, the relation between i and 2 (M+1) -1 is judged, when i is smaller than or equal to 2 (M+1) -1, the steps are continuously repeated and the weight error is continuously obtained to the higher position, when i is larger than 2 (M+1) -1, the processing method is similar to the steps, and the positive and negative voltages are opposite, so the final actual weight is D_code (2) -D_code (1), and the weight error is continuously obtained to the lower position. After the weight errors of all the bits are obtained, the short-circuit switch and the calibration enabling switch are turned off, the sub-analog-digital converter performs a normal working mode, and the obtained weight errors of all the bits are updated into the memory.
In addition, the application does not limit the number of stages and the effective bit number of each stage of the analog-digital conversion circuit, and the structure of the analog-digital conversion circuit is not limited, and the analog-digital conversion circuit can be single-ended or differential. The number of stages to calibrate from back to front is not limited, as only the first few stages or some number of stages may be calibrated. The number of bits of the later stage can be increased during calibration, for example, the number of bits of the flash flash_ADC is increased, so that the calibration precision is improved. And the analog-to-digital conversion module for quantizing the output voltage of the stage during calibration can be an analog-to-digital conversion circuit formed by a part of or all analog-to-digital conversion modules at the later stage, and can be any other possible analog-to-digital conversion circuit.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides an analog-to-digital conversion circuit calibration system for realizing the analog-to-digital conversion circuit calibration method. The implementation of the solution provided by the system is similar to that described in the above method, so the specific limitation in the embodiments of the calibration system for an analog-to-digital conversion circuit provided below may be referred to the limitation of the calibration method for an analog-to-digital conversion circuit hereinabove, and will not be repeated here.
In one embodiment, as shown in fig. 12, there is provided an analog-to-digital conversion circuit calibration system, comprising: analog-to-digital conversion circuit 121 to be calibrated, short-circuit switch 122, set control circuit 123 and processing circuit 124; wherein, the liquid crystal display device comprises a liquid crystal display device,
the analog-to-digital conversion circuit 121 to be calibrated comprises a sub-analog-to-digital converter and a multiplication digital-to-analog converter;
a shorting switch 122, configured to set an input of the analog-to-digital conversion circuit 121 to be calibrated to 0;
a set control circuit 123 for changing the output of the sub-analog-to-digital converter;
the processing circuit 124 is configured to calculate a weight error of the corresponding nth capacitance to be calibrated according to the output values of the multiplying digital-to-analog converters under the output of the different sub-digital-to-analog converters, and calibrate the output of the analog-to-digital conversion circuit 121 to be calibrated according to the weight error.
In one embodiment, the analog-to-digital conversion circuit 121 to be calibrated further comprises: calibrating the capacitance; the calibration capacitor is connected to an intermediate node of the multiplying digital-to-analog converter for configuring the multiplying digital-to-analog converter such that the signal amplitude of the output of the multiplying digital-to-analog converter is maximized when the input of the analog-to-digital conversion circuit to be calibrated is 0.
The transfer curve of the embodiment of the present application may be shifted (for example, shifted by 1/16×vref) by adding a calibration capacitor Cd, cd≡cu to the RA input terminal of the multiplying digital-analog converter. If the stage analog-to-digital conversion module in the pipeline analog-to-digital conversion circuit adopts a disturbance (dither) injection technology, the DAC used in the technology can be used as Cd as a whole (when the sum of the capacitance of the dither DAC is close to Cu), and the cost of an additional analog circuit required by calibration is greatly reduced.
In addition, the input amplitude of the embodiment of the application can be any single direct current signal, and if the input amplitude is 0, the input short-circuit switch type is not limited. The calibration capacitance size may vary within an acceptable range. And the distance of translation of the transmission curve may not be limited to 1/16 x vref mentioned above, and may be any possible distance that has no impact on the calibration effect.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (10)
1. An analog-to-digital conversion circuit calibration method, wherein the analog-to-digital conversion circuit comprises a plurality of cascaded analog-to-digital conversion modules, the analog-to-digital conversion modules comprise a sub-analog converter and a multiplication digital-to-analog converter, the method comprising:
configuring the sub-digital-to-analog converter and the multiplication digital-to-analog converter so that a transmission curve of the multiplication digital-to-analog converter translates, and when the input of the analog-to-digital conversion module is a first input value, the amplitude of a signal output by the multiplication digital-to-analog converter is close to the maximum amplitude in the transmission curve;
Under the condition that the input of the analog-to-digital conversion module is the first input value, changing the output of the sub-analog-to-digital converter, and calculating the weight error of the corresponding nth capacitor to be calibrated according to the output values of the multiplication digital-to-analog converter under different sub-analog-to-digital converter outputs, wherein n is the arrangement sequence number of the selected capacitor to be calibrated in the corresponding sub-analog-to-digital converter;
and calibrating the output of the analog-to-digital conversion module according to the weight error.
2. The method of calibrating an analog-to-digital conversion circuit of claim 1, wherein varying the output of the sub-analog-to-digital converter comprises:
setting the sub-analog-digital converter so that the output of the sub-analog-digital converter is a first output value and a second output value respectively, wherein the low n-1 bit of the first output value is a first preset value, and the rest bits are a second preset value; the lower n bits of the second output value are the first preset value, and the rest bits are the second preset value.
3. The method of calibrating an analog-to-digital conversion circuit according to claim 2, wherein calculating a weight error of a corresponding nth capacitance to be calibrated comprises:
Acquiring a first voltage value output by the multiplication digital-to-analog converter corresponding to the first output value and a second voltage value output by the multiplication digital-to-analog converter corresponding to the second output value;
and calculating the weight error of the corresponding nth capacitor to be calibrated according to the first voltage value and the second voltage value.
4. The method of calibrating an analog-to-digital conversion circuit according to claim 3, wherein calculating a weight error of a corresponding nth capacitance to be calibrated further comprises:
obtaining a difference value between the first voltage value and the second voltage value;
calculating the actual weight of the nth capacitance to be calibrated according to the difference value;
and calculating the weight error of the nth capacitance to be calibrated according to the actual weight and the ideal weight of the nth capacitance to be calibrated.
5. A method of calibrating an analog to digital conversion circuit according to claim 3, wherein after calculating the weight error of the corresponding nth capacitance to be calibrated, the method further comprises:
setting the sub-analog-digital converter to enable the output of the sub-analog-digital converter to be a third output value, wherein the low n-1 bit and the n+m bit of the third output value are the first preset value, and the rest bits are the second preset value;
Acquiring a third voltage value output by the multiplication digital-to-analog converter corresponding to the third output value;
and calculating the weight error of the corresponding n+m-th capacitance to be calibrated according to the third voltage value and the first voltage value.
6. A method of calibrating an analog to digital conversion circuit according to claim 3, wherein after calculating the weight error of the corresponding nth capacitance to be calibrated, the method further comprises:
setting the sub-analog-digital converter to enable the output of the sub-analog-digital converter to be a fourth output value, wherein the rest bits except the n-th bit in the low n bits of the fourth output value are all the first preset value, and the n-th bit and all the bits except the low n bits are all the second preset value;
acquiring a fourth voltage value output by the multiplication digital-to-analog converter corresponding to the fourth output value;
and calculating the weight error of the corresponding n-t capacitors to be calibrated according to the fourth voltage value and the second voltage value.
7. The method of calibrating an analog-to-digital conversion circuit according to claim 1, wherein calibrating an output of the analog-to-digital conversion circuit according to the weight error comprises:
and selecting different weight errors of the capacitors to be calibrated according to the weight errors and the output of the sub-analog-digital converter, updating the output weight of the analog-digital conversion module, and calibrating the output of the analog-digital conversion circuit according to the updated output weight.
8. The method of calibrating an analog-to-digital conversion circuit of claim 7, wherein updating the output weight of the analog-to-digital conversion module comprises:
obtaining an output a of the sub-analog-to-digital converter;
when the output a of the sub-analog-digital converter is smaller than half b of the bit number of the analog-digital conversion circuit, updating the output weight of the analog-digital conversion module by using the weight errors of the a+1 th to b-a-1 th capacitors to be calibrated;
when the output a of the analog-to-digital converter is larger than the half b of the bit number of the analog-to-digital conversion circuit, updating the output weight of the analog-to-digital conversion module by using the weight errors of the a-th to b-th capacitors to be calibrated.
9. An analog to digital conversion circuit calibration system, comprising: the device comprises an analog-to-digital conversion circuit to be calibrated, a short-circuit switch, a setting control circuit and a processing circuit; wherein, the liquid crystal display device comprises a liquid crystal display device,
the analog-to-digital conversion circuit to be calibrated comprises a sub analog-to-digital converter and a multiplication digital-to-analog converter;
the short-circuit switch is used for setting the input of the analog-to-digital conversion circuit to be calibrated as a first input value;
the setting control circuit is used for changing the output of the sub-analog-digital converter;
The processing circuit is used for calculating the weight error of the corresponding nth capacitor to be calibrated according to the output values of the multiplication digital-to-analog converter under the output of different sub-digital-to-analog converters, and calibrating the output of the analog-to-digital conversion circuit to be calibrated according to the weight error.
10. The analog-to-digital conversion circuit calibration system of claim 9, wherein the analog-to-digital conversion circuit to be calibrated further comprises: calibrating the capacitance; the calibration capacitor is connected with an intermediate node of the multiplying digital-to-analog converter, and is used for configuring the multiplying digital-to-analog converter to have the largest signal amplitude of the output of the multiplying digital-to-analog converter when the input of the analog-to-digital conversion circuit to be calibrated is the first input value.
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