CN116781056A - Driving circuit and driving chip applied to load switch - Google Patents

Driving circuit and driving chip applied to load switch Download PDF

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Publication number
CN116781056A
CN116781056A CN202310826998.XA CN202310826998A CN116781056A CN 116781056 A CN116781056 A CN 116781056A CN 202310826998 A CN202310826998 A CN 202310826998A CN 116781056 A CN116781056 A CN 116781056A
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China
Prior art keywords
mos tube
load switch
resistor
tube
mos
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CN202310826998.XA
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Chinese (zh)
Inventor
周琦
鲁文先
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Siruipu Microelectronics Technology Shanghai Co ltd
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Siruipu Microelectronics Technology Shanghai Co ltd
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Priority to CN202310826998.XA priority Critical patent/CN116781056A/en
Publication of CN116781056A publication Critical patent/CN116781056A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

Abstract

The application discloses a driving circuit and a driving chip applied to a load switch, wherein the driving circuit comprises: the switch is used for controlling the on-off of the load switch, the first end of the switch is connected with the first potential, and the second end of the switch is connected with the control end of the load switch; the grid electrode of the first MOS tube is connected with the control signal, and the drain electrode of the first MOS tube is connected with the control end of the load switch; the turn-off rate self-adaptive unit comprises a second MOS tube and a first resistor, wherein the grid electrode of the second MOS tube is connected with the first end of the load switch, the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the reference potential, the first end of the first resistor is connected with the source electrode of the first MOS tube, and the second end of the first resistor is connected with the first end of the load switch. The driving circuit provided by the application has a simple structure, is easy to control, and can adaptively consider the current change rate and the overall turn-off time of the load switch when the external load switch is turned off, so that an additional PWM circuit is not needed.

Description

Driving circuit and driving chip applied to load switch
Technical Field
The application belongs to the technical field of load switch control, and particularly relates to a driving circuit and a driving chip applied to a load switch.
Background
The Driver chip (Driver) is used for driving the on and off of an external load switch (FET, field effect transistor), wherein the off rate of the external load switch (i.e. the rate of change of the current flowing through the load switch) has certain requirements. In the prior art, the turn-off rate of the load switch can only be controlled singly, and the change rate of the load switch current and the overall turn-off time cannot be considered.
Therefore, in order to solve the above-mentioned problems, it is necessary to provide a driving circuit and a driving chip for a load switch.
Disclosure of Invention
In view of the above, the present application is directed to a driving circuit and a driving chip for a load switch to adaptively control the turn-off rate of the load switch.
In order to achieve the above object, an embodiment of the present application provides the following technical solution:
a drive circuit for a load switch, the drive circuit comprising:
the switch is used for controlling the on-off of the load switch, the first end of the switch is connected with the first potential, and the second end of the switch is connected with the control end of the load switch;
the grid electrode of the first MOS tube is connected with the control signal, and the drain electrode of the first MOS tube is connected with the control end of the load switch;
the turn-off rate self-adaptive unit comprises a second MOS tube and a first resistor, wherein the grid electrode of the second MOS tube is connected with the first end of the load switch, the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the reference potential, the first end of the first resistor is connected with the source electrode of the first MOS tube, and the second end of the first resistor is connected with the first end of the load switch.
In one embodiment, the load switch is a low-side load switch or a high-side load switch; and/or the number of the groups of groups,
the load switch is an NFET or PFET.
In one embodiment, the load switch is a low-side NFET, the control terminal is a gate, the first terminal is a source, the load switch is connected to the external load RLoad, and the second terminal is a drain, and the load switch is connected to the input voltage VIN;
the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube;
the first potential is a power supply voltage VDD, and the reference potential is a ground potential;
the grid electrode of the first MOS tube is directly connected with a first control signal, and the first control signal is in a high level in the switching-off process of the load switch.
In one embodiment, the load switch is a high-side NFET, the control terminal is a gate, the first terminal is a source, the load switch is connected to the external load RLoad, and the second terminal is a drain, and the load switch is connected to the input voltage VIN;
the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube;
the first potential is VIN+DeltaV, and the reference potential is ground potential;
the grid electrode of the first MOS tube is connected with a first control unit, and the first control unit is used for generating a grid electrode control signal for driving the first MOS tube according to the second control signal.
In an embodiment, the first control unit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a second resistor, and a third resistor, where the third MOS transistor and the fourth MOS transistor are PMOS transistors, and the fifth MOS transistor is an NMOS transistor, and the first control unit includes:
the source electrode of the third MOS tube is connected with the first potential, the grid electrode is in short circuit with the drain electrode, and the drain electrode is connected with the drain electrode of the fifth MOS tube;
the grid electrode of the fifth MOS tube is connected with a second control signal, the source electrode of the fifth MOS tube is connected with the first end of the second resistor, and the second end of the second resistor is connected with the ground potential;
the source electrode of the fourth MOS tube is connected with the first potential, the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube, the drain electrode of the fourth MOS tube is connected with the grid electrode of the first MOS tube, the first end of the third resistor is connected with the grid electrode of the first MOS tube, and the second end of the third resistor is connected with the source electrode of the first MOS tube;
during the turn-off of the load switch, the second control signal is high.
In one embodiment, the load switch is a low-side PFET, the control terminal is a gate, the first terminal is a source connected to the input voltage VIN, and the second terminal is a drain connected to the external load RLoad;
the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube;
the first potential is ground potential, and the reference potential is input voltage VIN;
the grid electrode of the first MOS tube is directly connected with a third control signal, and the first control signal is in a low level in the switching-off process of the load switch.
In one embodiment, the load switch is a high-side PFET, the control terminal is a gate, the first terminal is a source connected to the input voltage VIN, and the second terminal is a drain connected to the external load RLoad;
the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube;
the first potential is VIN-delta V, and the reference potential is the input voltage VIN;
the grid electrode of the first MOS tube is connected with a second control unit, and the second control unit is used for generating a grid electrode control signal for driving the first MOS tube according to a fourth control signal.
In an embodiment, the second control unit includes a sixth MOS transistor, a fourth resistor, and a fifth resistor, where the sixth MOS transistor is an NMOS transistor, and the second control unit includes:
the grid electrode of the sixth MOS tube is connected with a fourth control signal, the source electrode of the sixth MOS tube is connected with the first end of the fifth resistor, and the drain electrode of the sixth MOS tube is connected with the second end of the fourth resistor;
the first end of the fourth resistor is connected with the second end of the first resistor, and the second end of the fifth resistor is connected with the ground potential;
during the turn-off of the load switch, the fourth control signal is high.
In an embodiment, the turn-off rate adaptive unit further includes a sixth resistor, where a first end of the sixth resistor is connected to the gate of the second MOS transistor, and a second end of the sixth resistor is connected to the first end of the load switch.
The technical scheme provided by the other embodiment of the application is as follows:
a driving chip comprises the driving circuit.
The application has the following beneficial effects:
the driving circuit is simple in structure and easy to control, and can adaptively take the current change rate and the overall turn-off time of the load switch into account when the external load switch is turned off, so that an additional PWM (pulse-Width modulation) circuit is not needed;
the application has a faster rate when the voltage difference between the control end and the first end of the load switch is reduced from an initial value to the vicinity of the threshold voltage Vth of the load switch, the current flowing through the load switch is kept unchanged, and has a slower rate when the voltage difference between the control end and the first end of the load switch is reduced from the vicinity of the threshold voltage Vth to 0, and the current flowing through the load switch is gradually reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of a high side NFET driver circuit of comparative example 1 of the present application;
FIG. 2 is a schematic diagram of a high side NFET driver circuit of comparative example 2 of the present application;
FIG. 3 is a schematic diagram of a high side NFET driver circuit of comparative example 3 of the present application;
FIG. 4 is a schematic diagram of a low side NFET driver circuit according to embodiment 1 of the application;
FIG. 5 is a schematic diagram of a high side NFET driver circuit according to embodiment 2 of the application;
FIG. 6 is a schematic diagram of a low-side PFET driving circuit according to embodiment 3 of the application;
FIG. 7 is a schematic diagram of a high-side PFET driving circuit according to embodiment 4 of the application;
FIG. 8 is a schematic diagram of a high side NFET driver circuit according to embodiment 5 of the application;
fig. 9 is a schematic diagram of a high-side PFET drive circuit in embodiment 6 of the application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
The application discloses a driving circuit applied to a load switch, which comprises:
the switch is used for controlling the on-off of the load switch, the first end of the switch is connected with the first potential, and the second end of the switch is connected with the control end of the load switch;
the grid electrode of the first MOS tube is connected with the control signal, and the drain electrode of the first MOS tube is connected with the control end of the load switch;
the turn-off rate self-adaptive unit comprises a second MOS tube and a first resistor, wherein the grid electrode of the second MOS tube is connected with the first end of the load switch, the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the reference potential, the first end of the first resistor is connected with the source electrode of the first MOS tube, and the second end of the first resistor is connected with the first end of the load switch.
The load switch may be a low-side load switch or a high-side load switch, and may be an NFET or a PFET.
In the application, in the turn-off process of a load switch, under a first time sequence, a second MOS tube and a second resistor are both conducted, the pressure difference between a control end and a first end of the load switch is reduced at a first speed, under a second time sequence, the second MOS tube is turned off, the second resistor is conducted, and the pressure difference between the control end and the first end of the load switch is reduced at a second speed, wherein the second speed is smaller than the first speed.
The application is further illustrated below with reference to specific examples and comparative examples.
Comparative example 1:
referring to fig. 1, a circuit diagram of the drive circuit of this comparative example is shown, with the load switch being a high-side NFET.
During the turn-off of the load switch, the gate and source of the NFET are directly shorted. When the control signal turn off is high, current flows through R2, MN, and the voltage difference between the NFET gate G and the source S becomes 0 rapidly, and the current flowing through the NFET becomes 0 rapidly. Subsequently, the G, S point voltage gradually drops to 0. However, the rate at which the external NFET turns from on to off is too fast, which presents a reliability hazard in the event that it would otherwise flow a large current.
Comparative example 2:
referring to fig. 2, a circuit diagram of the drive circuit of this comparative example is shown, with the load switch being a high-side NFET.
During the load switch turn-off, the G, S point is connected via a resistor R3. When MN is conducted, the G point voltage is firstly reduced to the vicinity of the S point voltage plus the threshold voltage of the NFET at a certain speed, and the NFET current is unchanged at the stage; the voltage differential at G, S then begins to decrease at a slower rate and the NFET current begins to decrease gradually, and the final G, S voltage decreases to 0, respectively. A larger resistor R3 allows for a slower rate of change of NFET current, but the time for the voltage differential at G, S to decrease to the threshold voltage of the NFET is also longer, and thus the overall off time is longer.
Comparative example 3:
referring to fig. 3, a circuit diagram of the drive circuit of this comparative example is shown, with the load switch being a high-side NFET.
During the turn-off process of the load switch, the turn-off of the NFET is controlled through PWM, and meanwhile, the change rate of the current of the NFET and the turn-off time are considered.
Specifically, MN1 and MN2 are used to drive the turning off of NFETs together. In one embodiment, R6 has a resistance value that is much less than R4. When driving is started, turn off 1 is high level, turn off 2 is low level, G point voltage is reduced through MN2 and R6, and the NFET current is unchanged at the stage; when the voltage at point G drops to about the voltage at point S plus the NFET threshold voltage, turn off 1 is low and turn off 2 is high, the voltage at point G decreases through MN1 and R4, the NFET current starts to decrease gradually, and finally the voltage at point G, S decreases to 0, respectively.
Since the resistance of R6 is smaller than R4, the comparative example ensures a relatively slow rate of change of the NFET current, while the time for the G, S point differential pressure to decrease to the threshold voltage of the NFET is shorter than in comparative example 2. However, this comparative example requires an additional PWM wave generating circuit, and also requires a double driving circuit overhead, and the duration of turn off 1/2 is difficult to control.
Example 1:
referring to fig. 4, a circuit diagram of a driving circuit in this embodiment is shown, the load switch is a low-side NFET, the source of which is connected to the external load RLoad, and the drain of which is connected to the input voltage VIN.
The driving circuit in this embodiment includes:
the switch S1 is used for controlling the on-off of the load switch NFET, the first end of the switch S1 is connected with the power supply voltage VDD, and the second end of the switch S1 is connected with the grid electrode of the load switch NFET;
the first MOS tube M1 is an NMOS tube, the grid electrode of the first MOS tube is connected with a first control signal Turnoff 1, and the drain electrode of the first MOS tube is connected with the grid electrode of the load switch NFET;
the turn-off rate self-adaptive unit 11 comprises a second MOS tube M2 and a first resistor R1, wherein the second MOS tube M2 is a PMOS tube, a grid electrode is connected with a source electrode of the load switch NFET, the source electrode is connected with a source electrode of the first MOS tube M1, a drain electrode is connected with the ground potential, a first end of the first resistor R1 is connected with the source electrode of the first MOS tube M1, and a second end of the first resistor R1 is connected with a first end of the load switch NFET.
In the process of turning off the load switch NFET, under a first time sequence, the second MOS transistor M2 and the first resistor R1 are both turned on, the voltage difference between the load switch NFET gate G and the source S decreases at a first rate, under a second time sequence, the second MOS transistor M2 is turned off, the first resistor R1 is turned on, and the voltage difference between the load switch NFET gate G and the source S decreases at a second rate, wherein the second rate is smaller than the first rate.
Specifically, the threshold voltage of M2 is comparable to the threshold voltage of the external NFET. When the first control signal Turn off 1 is high, there is a current flowing through R1, M2, both of which are on, the G point voltage begins to drop at a faster rate, and when it drops to the S point voltage plus the threshold voltage of M2, M2 turns off, the process automatically terminates, during which the NFET current remains unchanged. Subsequently, the G-point voltage drops through M1, R1, the differential pressure of G, S begins to decrease at a slower rate, the NFET current begins to gradually decrease, and the final G, S-point voltages respectively decrease to 0.
Example 2:
referring to fig. 5, a circuit diagram of a driving circuit in this embodiment is shown, the load switch is a high-side NFET, the source of which is connected to the external load RLoad, and the drain of which is connected to the input voltage VIN.
The driving circuit in this embodiment includes:
a switch S1 for turning off the load switch NFET, the switch S1 having a first terminal connected to a first potential (VIN+DeltaV) and a second terminal connected to the gate of the load switch NFET;
the first MOS tube M1, wherein the first MOS tube M1 is an NMOS tube, the grid electrode is connected with the first control unit 22, and the drain electrode is connected with the grid electrode of the load switch NFET;
the turn-off rate self-adaptive unit 21 comprises a second MOS tube M2 and a first resistor R1, wherein the second MOS tube M2 is a PMOS tube, a grid electrode is connected with a source electrode of the load switch NFET, the source electrode is connected with a source electrode of the first MOS tube M1, a drain electrode is connected with the ground potential, a first end of the first resistor R1 is connected with the source electrode of the first MOS tube M1, and a second end of the first resistor R1 is connected with a first end of the load switch NFET.
In the process of turning off the load switch NFET, under a first time sequence, the second MOS transistor M2 and the first resistor R1 are both turned on, the voltage difference between the load switch NFET gate G and the source S decreases at a first rate, under a second time sequence, the second MOS transistor M2 is turned off, the first resistor R1 is turned on, and the voltage difference between the load switch NFET gate G and the source S decreases at a second rate, wherein the second rate is smaller than the first rate.
The first control unit 22 in this embodiment is configured to generate a gate control signal for driving the first MOS transistor M1 according to the second control signal turnoff 2.
Illustratively, the first control unit 22 includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a second resistor R2, and a third resistor R3, where the third MOS transistor M3 and the fourth MOS transistor M4 are PMOS transistors, and the fifth MOS transistor M5 is an NMOS transistor, and the following:
the source electrode of the third MOS tube M3 is connected with a first potential (VIN+DeltaV), the grid electrode is in short circuit with the drain electrode, and the drain electrode is connected with the drain electrode of the fifth MOS tube M5;
the grid electrode of the fifth MOS tube M5 is connected with a second control signal Turn off 2, the source electrode is connected with the first end of a second resistor R2, and the second end of the second resistor R2 is connected with the ground potential;
the source electrode of the fourth MOS tube M4 is connected with a first potential (VIN+DeltaV), the grid electrode of the fourth MOS tube M4 is connected with the grid electrode of the third MOS tube M3, the drain electrode of the fourth MOS tube M3 is connected with the grid electrode of the first MOS tube M1, the first end of the third resistor R3 is connected with the grid electrode of the first MOS tube M1, and the second end of the third resistor R3 is connected with the source electrode of the first MOS tube M1;
during the turning off of the load switch NFET, the second control signal turnoff 2 is high.
Specifically, the threshold voltage of M2 is comparable to the threshold voltage of the external NFET. When the second control signal Turn off 2 is high, current flows through R1, R3, M1, M2, all of which are on, the G point voltage begins to drop at a faster rate, and when it drops to the S point voltage plus the threshold voltage of M2, M2 turns off, the process automatically terminates, during which time the NFET current remains unchanged. Subsequently, the G-point voltage drops through M1, R1, the differential pressure of G, S begins to decrease at a slower rate, the NFET current begins to gradually decrease, and the final G, S-point voltages respectively decrease to 0.
Example 3:
referring to fig. 6, a circuit diagram of a driving circuit in this embodiment is shown, the load switch is a low-side PFET, the source is connected to the input voltage VIN, and the drain is connected to the external load RLoad.
The driving circuit in this embodiment includes:
a switch S1 for turning off the load switch PFET, the switch S1 having a first end connected to the ground potential and a second end connected to the gate of the load switch PFET;
the first MOS tube M1 is a PMOS tube, the grid electrode is connected with a third control signal Turnoff_N, and the drain electrode is connected with the grid electrode of the load switch PFET;
the turn-off rate self-adaptive unit 31 comprises a second MOS tube M2 and a first resistor R1, wherein the second MOS tube M2 is an NMOS tube, a grid electrode and a drain electrode are connected with a source electrode of a load switch PFET, the source electrode is connected with a source electrode of the first MOS tube, a first end of the first resistor R1 is connected with the source electrode of the first MOS tube M1, and a second end of the first resistor R1 is connected with the source electrode of the load switch PFET.
During the turn-off process of the load switch PFET, the second MOS transistor M2 and the first resistor R1 are both turned on at a first timing, the voltage difference between the load switch PFET gate G and the source S decreases at a first rate, and the second MOS transistor M2 is turned off at a second timing, the first resistor R1 is turned on, and the voltage difference between the load switch PFET gate G and the source S decreases at a second rate, wherein the second rate is smaller than the first rate.
Specifically, the threshold voltage of M2 is comparable to the threshold voltage of the external PFET. When the third control signal Turn off_N is low, current flows through R1, M2, both are on, the G point voltage begins to rise at a faster rate, and when it rises to the S point voltage minus the threshold voltage of M2, M2 turns off, the process automatically terminates, during which the PFET current remains unchanged. Subsequently, the G-point voltage rises through M1, R1, the differential pressure of G, S begins to decrease at a slower rate, and the PFET current begins to gradually decrease.
Example 4:
referring to fig. 7, a circuit diagram of a driving circuit in this embodiment is shown, the load switch is a high-side PFET, the source is connected to the input voltage VIN, and the drain is connected to the external load RLoad.
The driving circuit in this embodiment includes:
a switch S1 for turning off the load switch PFET, the switch S1 having a first terminal connected to a first potential (VIN- Δv) and a second terminal connected to a gate of the load switch PFET;
the first MOS tube M1 is a PMOS tube, the grid electrode of the first MOS tube M1 is connected with the second control unit 42, and the drain electrode of the first MOS tube M1 is connected with the grid electrode of the load switch PFET;
the turn-off rate self-adaptive unit 41 comprises a second MOS tube M2 and a first resistor R1, wherein the second MOS tube M2 is an NMOS tube, a grid electrode and a drain electrode are connected with a source electrode of a load switch PFET, the source electrode is connected with a source electrode of the first MOS tube M1, a first end of the first resistor R1 is connected with the source electrode of the first MOS tube M1, and a second end of the first resistor R1 is connected with the source electrode of the load switch PFET.
During the turn-off process of the load switch PFET, the second MOS transistor M2 and the first resistor R1 are both turned on at a first timing, the voltage difference between the load switch PFET gate G and the source S decreases at a first rate, and the second MOS transistor M2 is turned off at a second timing, the first resistor R1 is turned on, and the voltage difference between the load switch PFET gate G and the source S decreases at a second rate, wherein the second rate is smaller than the first rate.
The second control unit 42 in this embodiment is configured to generate a gate control signal for driving the first MOS transistor M1 according to the fourth control signal turnoff 4.
The second control unit 42 includes a sixth MOS transistor M6, a fourth resistor R4, and a fifth resistor R5, where the sixth MOS transistor M6 is an NMOS transistor, and the following:
the grid electrode of the sixth MOS tube M6 is connected with a fourth control signal Turn off 4, the source electrode is connected with the first end of the fifth resistor R5, and the drain electrode is connected with the second end of the fourth resistor R4;
the first end of the fourth resistor R4 is connected with the second end of the first resistor R1, and the second end of the fifth resistor R5 is connected with the ground potential;
during the turning off of the load switch PFET, the fourth control signal turnoff 4 is high.
Specifically, the threshold voltage of M2 is comparable to the threshold voltage of the external PFET. When the third control signal turnoff_n is low, current flows through R1, R4, M1, M2, all of which are on, the G-point voltage begins to rise at a faster rate, and when it rises to the S-point voltage minus the threshold voltage of M2, M2 turns off, the process automatically terminates, during which the PFET current remains unchanged. Subsequently, the G-point voltage rises through M1, R1, the differential pressure of G, S begins to decrease at a slower rate, and the PFET current begins to gradually decrease.
Example 5:
referring to fig. 8, a circuit diagram of a driving circuit in this embodiment is shown, the load switch is a high-side NFET, the source of which is connected to the external load RLoad, and the drain of which is connected to the input voltage VIN.
The driving circuit in this embodiment is substantially the same as that in embodiment 2, except that the turn-off rate adaptive unit 21 in this embodiment further includes a sixth resistor R6, where a first end of the sixth resistor R6 is connected to the gate of the second MOS transistor M2 and a second end is connected to the source of the load switch NFET.
In example 2, the G point voltage continues to drop to the S point voltage plus the threshold voltage of M2 during the rapid discharge process, and if the threshold voltage of M2 is less than the threshold voltage of the external NFET, the external NFET will still rapidly change from on to off, and the current change rate may still be too rapid.
By adding a sixth resistor R6 in this embodiment, when the control signal turn off 5 is high, there is a current flowing through R1, R3, R6, M1, M2 all conducting, the G point voltage begins to drop at a faster rate, when it drops to the S point voltage plus V (V equals the voltage drop across the threshold voltage of M2 plus R6, and the greater R6, V is the greater, ensuring that the rapid discharge at G point stops before it drops to the threshold voltage of S point voltage plus NFET), M1 turns off, which process automatically terminates, during which the NFET current remains unchanged. Subsequently, the G-point voltage drops through M1, R6, the differential pressure of G, S begins to decrease at a slower rate and the NFET current begins to decrease gradually.
Example 6:
referring to fig. 9, a circuit diagram of a driving circuit in this embodiment is shown, the load switch is a high-side PFET, the source is connected to the input voltage VIN, and the drain is connected to the external load RLoad.
The driving circuit in this embodiment is substantially the same as that in embodiment 4, except that the off-rate adaptive unit 41 in this embodiment further includes a sixth resistor R6, where a first end of the sixth resistor R6 is connected to the gate of the second MOS transistor M2 and a second end is connected to the source of the load switch NFET.
The function and the working principle of the sixth resistor R6 in this embodiment are similar to those of embodiment 5, and will not be described here again.
In the embodiments 5 and 6, the driving circuits of the high-side NFET and the high-side PFET are described as examples, respectively, and in other embodiments, the sixth resistor R6 may be added to the driving circuits of the low-side NFET and the low-side PFET, which are not further described herein.
As can be seen from the technical scheme, the application has the following advantages:
the driving circuit is simple in structure and easy to control, and can adaptively take the current change rate and the overall turn-off time of the load switch into account when the external load switch is turned off, so that an additional PWM (pulse-Width modulation) circuit is not needed;
the application has a faster rate when the voltage difference between the control end and the first end of the load switch is reduced from an initial value to the vicinity of the threshold voltage Vth of the load switch, the current flowing through the load switch is kept unchanged, and has a slower rate when the voltage difference between the control end and the first end of the load switch is reduced from the vicinity of the threshold voltage Vth to 0, and the current flowing through the load switch is gradually reduced.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims (10)

1. A drive circuit for a load switch, the drive circuit comprising:
the switch is used for controlling the on-off of the load switch, the first end of the switch is connected with the first potential, and the second end of the switch is connected with the control end of the load switch;
the grid electrode of the first MOS tube is connected with the control signal, and the drain electrode of the first MOS tube is connected with the control end of the load switch;
the turn-off rate self-adaptive unit comprises a second MOS tube and a first resistor, wherein the grid electrode of the second MOS tube is connected with the first end of the load switch, the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the reference potential, the first end of the first resistor is connected with the source electrode of the first MOS tube, and the second end of the first resistor is connected with the first end of the load switch.
2. The drive circuit for a load switch according to claim 1, wherein the load switch is a low-side load switch or a high-side load switch; and/or the number of the groups of groups,
the load switch is an NFET or PFET.
3. The driving circuit for a load switch of claim 1, wherein the load switch is a low-side NFET, the control terminal is a gate, the first terminal is a source, the first terminal is connected to an external load RLoad, and the second terminal is a drain, the second terminal is connected to an input voltage VIN;
the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube;
the first potential is a power supply voltage VDD, and the reference potential is a ground potential;
the grid electrode of the first MOS tube is directly connected with a first control signal, and the first control signal is in a high level in the switching-off process of the load switch.
4. The driving circuit for a load switch of claim 1, wherein the load switch is a high-side NFET, the control terminal is a gate, the first terminal is a source, the first terminal is connected to an external load RLoad, and the second terminal is a drain, the second terminal is connected to an input voltage VIN;
the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube;
the first potential is VIN+DeltaV, and the reference potential is ground potential;
the grid electrode of the first MOS tube is connected with a first control unit, and the first control unit is used for generating a grid electrode control signal for driving the first MOS tube according to the second control signal.
5. The driving circuit for a load switch according to claim 4, wherein the first control unit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a second resistor and a third resistor, the third MOS transistor and the fourth MOS transistor are PMOS transistors, and the fifth MOS transistor is an NMOS transistor, wherein:
the source electrode of the third MOS tube is connected with the first potential, the grid electrode is in short circuit with the drain electrode, and the drain electrode is connected with the drain electrode of the fifth MOS tube;
the grid electrode of the fifth MOS tube is connected with a second control signal, the source electrode of the fifth MOS tube is connected with the first end of the second resistor, and the second end of the second resistor is connected with the ground potential;
the source electrode of the fourth MOS tube is connected with the first potential, the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube, the drain electrode of the fourth MOS tube is connected with the grid electrode of the first MOS tube, the first end of the third resistor is connected with the grid electrode of the first MOS tube, and the second end of the third resistor is connected with the source electrode of the first MOS tube;
during the turn-off of the load switch, the second control signal is high.
6. The driving circuit of claim 1, wherein the load switch is a low-side PFET, the control terminal is a gate, the first terminal is a source connected to the input voltage VIN, and the second terminal is a drain connected to the external load RLoad;
the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube;
the first potential is ground potential, and the reference potential is input voltage VIN;
the grid electrode of the first MOS tube is directly connected with a third control signal, and the first control signal is in a low level in the switching-off process of the load switch.
7. The driving circuit of claim 1, wherein the load switch is a high-side PFET, the control terminal is a gate, the first terminal is a source connected to the input voltage VIN, and the second terminal is a drain connected to the external load RLoad;
the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube;
the first potential is VIN-delta V, and the reference potential is the input voltage VIN;
the grid electrode of the first MOS tube is connected with a second control unit, and the second control unit is used for generating a grid electrode control signal for driving the first MOS tube according to a fourth control signal.
8. The driving circuit for a load switch according to claim 7, wherein the second control unit comprises a sixth MOS transistor, a fourth resistor and a fifth resistor, the sixth MOS transistor being an NMOS transistor, wherein:
the grid electrode of the sixth MOS tube is connected with a fourth control signal, the source electrode of the sixth MOS tube is connected with the first end of the fifth resistor, and the drain electrode of the sixth MOS tube is connected with the second end of the fourth resistor;
the first end of the fourth resistor is connected with the second end of the first resistor, and the second end of the fifth resistor is connected with the ground potential;
during the turn-off of the load switch, the fourth control signal is high.
9. The driving circuit for a load switch according to claim 1, wherein the turn-off rate adaptive unit further comprises a sixth resistor, a first end of the sixth resistor is connected to the gate of the second MOS transistor, and a second end of the sixth resistor is connected to the first end of the load switch.
10. A driver chip, characterized in that the driver chip comprises the driver circuit of any one of claims 1-9.
CN202310826998.XA 2023-07-06 2023-07-06 Driving circuit and driving chip applied to load switch Pending CN116781056A (en)

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CN202310826998.XA CN116781056A (en) 2023-07-06 2023-07-06 Driving circuit and driving chip applied to load switch

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117335784A (en) * 2023-09-22 2024-01-02 上海帝迪集成电路设计有限公司 Load switch circuit with controllable output voltage rising and falling rate and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117335784A (en) * 2023-09-22 2024-01-02 上海帝迪集成电路设计有限公司 Load switch circuit with controllable output voltage rising and falling rate and control method thereof

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