CN116779545A

CN116779545A - Epitaxial lower isolation structure

Info

Publication number: CN116779545A
Application number: CN202310049311.6A
Authority: CN
Inventors: 孙志鸿; 林文凯; 张哲豪; 吴振诚; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-11
Filing date: 2023-02-01
Publication date: 2023-09-19

Abstract

Embodiments provide dual-level trench isolation structures under epitaxial regions (e.g., epitaxial source/drain regions) of nanofet transistor devices and methods of forming the same. The first level provides an isolation structure with a low k value. The second level provides isolation structures having a higher k value, a greater material density, and a greater etch resistance than the first level isolation structures.

Description

Epitaxial lower isolation structure

Technical Field

The present application relates to the field of semiconductors.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: insulating or dielectric layers, conductive layers, and semiconductor material layers are sequentially deposited over a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems that should be solved arise.

Disclosure of Invention

A first aspect of the present disclosure provides a method for forming a semiconductor device, comprising: forming a multi-layer stack of alternating layers of a first semiconductor material and a second semiconductor material over a semiconductor substrate; patterning the multi-layer stack into a first fin, the first fin having a first longitudinal direction; forming a dummy gate structure over the first fin, the dummy gate structure having a second longitudinal direction; etching a first recess in the first fin adjacent to the dummy gate structure, the first recess extending into the semiconductor substrate; depositing a first insulating film in the first recess, the first insulating film having a first k value; depositing a second insulating film in the first recess over the first insulating film, the second insulating film having a second k value, the second k value being greater than the first k value; and forming an epitaxial region in the first recess over the second insulating film.

A second aspect of the present disclosure provides a method for forming a semiconductor device, comprising: forming first and second nanostructures over a substrate, each of the first nanostructures alternating with each of the second nanostructures, wherein the substrate, the first nanostructures, and the second nanostructures are stacked to form a first fin; forming a dummy gate structure over the first fin; forming a recess in the first fin adjacent to the dummy gate structure, the recess continuously passing through the first nanostructure, the second nanostructure and exposing the substrate; depositing a first insulating layer in the recess and over the dummy gate structure; etching the first insulating layer to form a first isolation structure at the bottom of the recess; depositing a second insulating layer in the recess over the first isolation structure and over the dummy gate structure; and etching the second insulating layer to form a second isolation structure over the first isolation structure, wherein an etch resistance of the second insulating layer is different from an etch resistance of the first insulating layer.

A third aspect of the present disclosure provides a semiconductor device comprising: a first nanostructure; a second nanostructure located over the first nanostructure; a first spacer interposed between an end of the second nanostructure and a corresponding end of the first nanostructure; a second spacer interposed between a corresponding end of the first nanostructure and a substrate; an epitaxial region adjacent to the first nanostructure and the second nanostructure, the epitaxial region in contact with the first spacer, an end of the second nanostructure, and a corresponding end of the first nanostructure; and a trench isolation structure located under the epitaxial region, the trench isolation structure including a first isolation structure under a second isolation structure, the first isolation structure being in contact with the substrate, the first isolation structure having a k value lower than the second isolation structure.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a nanostructured field effect transistor (nanofet) in a three-dimensional view according to some embodiments.

Fig. 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 15D, 16A, 16B, 16C, 16D, 17A, 17B, 17C, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 22C, 23A, 23B, and 23C are cross-sectional views of intermediate stages of fabricating a nanofet according to some embodiments.

Fig. 24A, 24B, and 24C are cross-sectional views of nano-FETs according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "under," "lower," "over," "upper," and the like) may be used herein to facilitate describing a relationship of one element or feature to another element(s) or feature(s) shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments of a die including a nanofet are described below in particular contexts. However, various embodiments may be applied to dies that include other types of transistors, such as fin field effect transistors (finfets), instead of or in combination with nanofets.

The nanofet transistor includes a plurality of gates all around a channel region vertically stacked and interposed between opposing source/drain regions. Source/drain regions are formed within the semiconductor fin by: a portion of the fin is removed to form a recess and epitaxial material is grown in the recess. However, after the source/drain is formed, current leakage may occur at the bottom of the recess. For example, the source/drain regions may be in contact with the semiconductor material of the semiconductor fin, and current may leak through the contact points. In addition, capacitance through the semiconductor material between the source/drain regions and the adjacent source/drain regions can be observed. Embodiments seek to reduce or eliminate current leakage and capacitance problems by forming a low-k insulating material at the bottom of the recess prior to forming the source/drain regions. In addition, an upper isolation layer is provided over the low-k insulating material to protect the low-k insulating material. The low-k insulating material and the upper isolation layer together form a trench isolation structure.

Fig. 1 illustrates an example of a nano-FET (e.g., nanowire FET, nanoplatelet FET (nano-FET), etc.) in a three-dimensional view according to some embodiments. The nanofet includes nanostructures 55 (e.g., nanoplates, nanowires, etc.) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructures 55 serve as channel regions of the nanofet. The nanostructures 55 may comprise p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions 68 are disposed between adjacent fins 66, and fins 66 may protrude higher than isolation regions 68 from between adjacent isolation regions 68. Although isolation region 68 is depicted/described as being separate from substrate 50, for purposes of this document, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fins 66 are shown as a single continuous material with the substrate 50, the bottom portion of the fins 66 and/or the substrate 50 may comprise a single material or may comprise multiple materials. In this context, fin 66 refers to the portion that extends between adjacent isolation regions 68.

A gate dielectric layer 110 is located over the top surface of fin 66 and along the top, sidewalls, and bottom surfaces of nanostructure 55. A gate electrode 112 is located over the gate dielectric layer 110. Epitaxial source/drain regions 102 are disposed on fin 66 and on opposite sides of gate dielectric layer 110 and gate electrode 112. Source/drain region(s) 102 may be referred to individually or collectively as a source or drain, depending on the context.

Fig. 1 further shows the reference cross section used in the subsequent figures. The cross-section A-A' is along the longitudinal axis of the gate electrode 112 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions 102 of the nanofet. Section B-B 'is perpendicular to section A-A' and parallel to the longitudinal axis of fin 66 of the nanofet and in the direction of current flow, for example, between epitaxial source/drain regions 102 of the nanofet. The section C-C 'is parallel to the section A-A' and extends through the epitaxial source/drain regions of the nanofet. For clarity, the subsequent figures refer to these reference sections.

Some embodiments discussed herein are discussed in the context of a nano-FET formed using a back gate process. In other embodiments, a gate-first process may be used. Further, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs) or fin field effect transistors (finfets).

Fig. 2-24C are cross-sectional views of intermediate stages in the fabrication of a nano-FET according to some embodiments. Fig. 2 to 5, 6A, 17A, 18A, 19A, 20A, 21A, 22A, 23A and 24A show reference sections A-A' shown in fig. 1. Fig. 6B, 7B, 8B, 9B, 10B, 11C, 12B, 13B, 14B, 15C, 15D, 16B, 16D, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B show the reference section B-B' shown in fig. 1. Fig. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16C, 17C, 22C, 23C, and 24C illustrate a reference section C-C' illustrated in fig. 1.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N may be used to form N-type devices, such as NMOS transistors, for example, N-type nanofets, while the P-type region 50P may be used to form P-type devices, such as PMOS transistors, for example, P-type nanofets. The N-type region 50N may be physically separated from the P-type region 50P (as shown by the spacers 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are shown, any number of N-type regions 50N and P-type regions 50P may be provided.

Further, in fig. 2, a multi-layer stack 64 is formed over the substrate 50. The multi-layer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For purposes of illustration and as discussed in more detail below, in the P-type region 50P, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of the nano-FET. In addition, in the N-type region 50N, the first semiconductor layer 51 is removed, and the second semiconductor layer 53 is patterned to form a channel region of the nano FET. However, in some embodiments, in the P-type region 50P, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nano-FET; and in the N-type region 50N, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of the nano FET.

In still other embodiments, in both the N-type region 50N and the P-type region 50P, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nano-FET. In other embodiments, in both the N-type region 50N and the P-type region 50P, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of the nano-FET. In such embodiments, the channel regions in both the N-type region 50N and the P-type region 50P may have the same material composition (e.g., silicon or other semiconductor material) and may be formed simultaneously. Fig. 24A, 24B, and 24C illustrate structures resulting from embodiments in which the channel regions in both the P-type region 50P and the N-type region 50N comprise silicon.

For illustration purposes, the multi-layer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multi-layer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multi-layer stack 64 may be epitaxially grown using a process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (e.g., silicon germanium, etc.) suitable for a p-type nano-FET, and the second semiconductor layer 53 may be formed of a second semiconductor material (e.g., silicon carbon, etc.) suitable for an n-type nano-FET. For illustrative purposes, the multi-layer stack 64 is shown with the bottommost semiconductor layer suitable for a p-type nanofet. In some embodiments, the multi-layer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for an n-type nano-FET.

The first semiconductor material and the second semiconductor material may be materials having a high etching selectivity with respect to each other. As such, in the N-type region 50N, the first semiconductor layer 51 of the first semiconductor material may be removed without substantially removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form a channel region of the N-type nano FET. Similarly, in the P-type region 50P, the second semiconductor layer 53 of the second semiconductor material may be removed without substantially removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form a channel region of the P-type nano-FET.

Referring now to fig. 3, according to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multi-layer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The formation of the nanostructures 55 by etching the multi-layer stack 64 may further define first nanostructures 52A-C (collectively first nanostructures 52) from the first semiconductor layer 51 and second nanostructures 54A-C (collectively second nanostructures 54) from the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 may also be collectively referred to as nanostructures 55.

Fin 66 and nanostructure 55 may be patterned by any suitable method. For example, fin 66 and nanostructure 55 may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine lithography and self-aligned processes, allowing patterns to be created with smaller pitches than would otherwise be possible using a single direct lithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins 66.

Fig. 3 shows fins 66 in N-type region 50N and P-type region 50P, which are substantially equal in width for purposes of illustration. In some embodiments, the width of fin 66 in N-type region 50N may be greater than or less than the width of fin 66 in P-type region 50P. Further, while each of the fins 66 and nanostructures 55 are shown as having a uniform width, in other embodiments, the fins 66 or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and/or nanostructures 55 continuously increases in a direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

In fig. 4, shallow Trench Isolation (STI) regions 68 are formed adjacent to fins 66. STI regions 68 may be formed by depositing an insulating material over substrate 50, fins 66, and nanostructures 55 and between adjacent fins 66. The insulating material may be an oxide (e.g., silicon oxide), a nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not separately shown) may first be formed along the surfaces of substrate 50, fins 66, and nanostructures 55. Thereafter, a filler material as described above may be formed over the liner.

A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 55. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like, may be used. The planarization process exposes the nanostructures 55 such that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is completed.

The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that upper portions of fins 66 in N-type region 50N and P-type region 50P protrude from between adjacent STI regions 68. Further, the top surface of STI region 68 may have a flat surface, convex, concave (e.g., dished), or a combination thereof as shown. The top surface of STI regions 68 may be formed flat, convex, and/or concave by a suitable etch. STI regions 68 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of fin 66 and nanostructure 55). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) may be used.

The process described above with respect to fig. 2-4 is merely one example of how fin 66 and nanostructure 55 may be formed. In some embodiments, the fins 66 and/or nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form fin 66 and/or nanostructure 55. The epitaxial structure may comprise alternating semiconductor materials as described above, for example a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid previous and/or subsequent implants, but in situ doping and implant doping may be used together.

Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and thus the nanostructure 52) and the second semiconductor layer 53 (and thus the nanostructure 54) are shown and discussed herein as comprising the same material in the P-type region 50P and the N-type region 50N. However, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be a different material or formed in a different order in the P-type region 50P and the N-type region 50N.

Furthermore, in fig. 4, suitable wells (not separately shown) may be formed in fin 66, nanostructure 55, and/or STI region 68. In embodiments with different well types, a photoresist or other mask (not shownShown separately) different implantation steps for the N-type region 50N and the P-type region 50P are implemented. For example, a photoresist may be formed over fin 66 and STI region 68 in N-type region 50N and P-type region 50P. The photoresist is patterned to expose the P-type region 50P. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, an N-type impurity implantation is performed in the P-type region 50P, and the photoresist may act as a mask to substantially prevent N-type impurities from being implanted into the N-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc. implanted into the region at a concentration of from about 10 ¹³ Atoms/cm ³ To about 10 ¹⁴ Atoms/cm ³ Within a range of (2). After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

After or before implantation of P-type region 50P, a photoresist or other mask (not separately shown) is formed over fins 66, nanostructures 55, and STI regions 68 in P-type region 50P and N-type region 50N. The photoresist is patterned to expose the N-type region 50N. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, P-type impurity implantation may be performed in the N-type region 50N, and the photoresist may act as a mask to substantially prevent P-type impurities from being implanted into the P-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc. implanted into the region at a concentration of from about 10 ¹³ Atoms/cm ³ To about 10 ¹⁴ Atoms/cm ³ Within a range of (2). After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

After implantation of the N-type region 50N and the P-type region 50P, an anneal may be performed to repair the implant damage and activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in situ during growth, which may avoid implantation, but in situ doping and implantation doping may be used together.

In fig. 5, a dummy dielectric layer 70 is formed on fin 66 and/or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. A dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized by CMP or the like. A mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polysilicon (polysilicon), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other technique for depositing the selected material. The dummy gate layer 72 may be made of other materials having a high etch selectivity to the etch of the isolation regions. Mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the N-type region 50N and the P-type region 50P. It is noted that the dummy dielectric layer 70 is shown to cover only the fins 66 and the nanostructures 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

Fig. 6A-23C illustrate various additional steps in the fabrication of the device of the embodiments. Fig. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16C, 17A, 17C, 18A, 19A, 22C, and 23C illustrate features in the region 50N or the region 50P. In fig. 6A and 6B, mask layer 74 (see fig. 5) may be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 may then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. Dummy gate 76 covers the corresponding channel region of fin 66. The pattern of the mask 78 may be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 66.

In fig. 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed over the structures shown in fig. 6A and 6B, respectively. The first spacer layer 80 and the second spacer layer 82 are then patterned to act as spacers for forming self-aligned source/drain regions. In fig. 7A and 7B, a first spacer layer 80 is formed on the top surface of STI region 68; formed on top surfaces and sidewalls of fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using a technique such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material having a different etching rate from that of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

After forming the first spacer layer 80 and before forming the second spacer layer 82, implantation for lightly doped source/drain (LDD) regions (not separately shown) may be performed. In embodiments with different device types, similar to the implantation discussed above in fig. 4, a mask (e.g., photoresist) may be formed over N-type region 50N while exposing P-type region 50P, and appropriate type (e.g., P-type) impurities may be implanted into exposed fin 66 and nanostructure 55 in P-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the P-type region 50P while exposing the N-type region 50N, and appropriate type (e.g., N-type) impurities may be implanted into the exposed fin 66 and nanostructure 55 in the N-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have an impurity concentration of from about 1 x 10 ¹⁵ Atoms/cm ³ Up to about 1X 10 ¹⁹ Atoms/cm ³ Within a range of (2). Annealing may be used to repair implant damage and activate implant dopantsQuality is high.

In fig. 8A and 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacers 81 and 83 serve to self-align subsequently formed source drain regions, as well as to protect the sidewalls of the fins 66 and/or nanostructures 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), and the like. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 may act as an etch stop layer when the second spacer layer 82 is patterned, and such that the second spacer layer 82 may act as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms the second spacers 83, as shown in fig. 8A. Thereafter, the second spacers 83 serve as a mask while etching the exposed portions of the first spacer layer 80, thereby forming the first spacers 81, as shown in fig. 8A.

As shown in fig. 8A, first and second spacers 81 and 83 are disposed on sidewalls of fin 66 and/or nanostructure 55. As shown in fig. 8B, in some embodiments, the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, a different sequence of steps may be used (e.g., first spacers 81 may be patterned before depositing second spacer layer 82), additional spacers may be formed and removed, etc. In addition, n-type and p-type devices may be formed using different structures and steps.

In fig. 9A and 9B, a first recess 86 is formed in fin 66, nanostructure 55, and substrate 50, according to some embodiments. Epitaxial source/drain regions are then formed in the first recesses 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. As shown in fig. 9A, fin 66 may be etched such that the bottom surface of first recess 86 is disposed lower than the top surface of STI region 68. In various embodiments, a top surface of STI region 68 may be flush with a bottom surface of first recess 86; etc. The first recess 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). The first spacers 81, the second spacers 83, and the mask 78 mask portions of the fins 66, the nanostructures 55, and the substrate 50 during the etching process used to form the first recesses 86. Each layer of nanostructures 55 and/or fins 66 may be etched using a single etching process or multiple etching processes. The timed etch process may be used to stop etching of the first recess 86 after the first recess 86 reaches a desired depth.

In fig. 10A and 10B, the portion of the sidewalls of the layers of the multi-layer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 86 is etched to form sidewall recess 88 in the N-type region 50N, and the portion of the sidewalls of the layers of the multi-layer stack formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the first recess 86 is etched to form sidewall recess 88 in the P-type region 50P. Although the sidewalls of the first nanostructures 52 and the second nanostructures 54 in the sidewall recess 88 are shown as being straight in fig. 10B, the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process (e.g., wet etching, etc.). A mask (not shown) may be used to protect the P-type region 50P while etching the first nanostructures 52 using an etchant selective to the first semiconductor material such that the second nanostructures 54 and the substrate 50 are in contact with the first of the N-type region 50NThe nanostructures 52 remain relatively unetched as compared to the other. Similarly, a mask (not shown) may be used to protect the N-type region 50N while etching the second nanostructures 54 using an etchant selective to the second semiconductor material such that the first nanostructures 52 and the substrate 50 remain relatively unetched compared to the second nanostructures 54 in the P-type region 50P. In embodiments where the first nanostructures 52 comprise, for example, siGe and the second nanostructures 54 comprise, for example, si or SiC, a material having tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH may be used ₄ OH), etc., and the sidewalls of the second nanostructures 54 in the P-type region 50P may be etched using a wet etching process or a dry etching process with hydrogen fluoride, another fluorine-based etchant, etc.

In fig. 11A, 11B, and 11C, a first inner spacer 90 is formed in the sidewall recess 88. The first inner spacer 90 may be formed by depositing an inner spacer layer (not separately shown) over the structure shown in fig. 10A and 10B. The first internal spacers 90 act as isolation features between subsequently formed source/drain regions and the gate structure. As will be discussed in more detail below, source/drain regions will be formed in the recess 86, while the first nanostructures 52 in the N-type region 50N and the second nanostructures 54 in the P-type region 50P will be replaced by corresponding gate structures.

The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, etc. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low dielectric constant (low-k) material having a k value less than about 3.5. The inner spacer layer may then be anisotropically etched to form first inner spacers 90. Although the outer sidewall of the first inner spacer 90 is shown as being flush with the sidewall of the second nanostructure 54 in the N-type region 50N and flush with the sidewall of the first nanostructure 52 in the P-type region 50P, the outer sidewall of the first inner spacer 90 may extend beyond the sidewall of the second nanostructure 54 and/or the first nanostructure 52 or be recessed relative to the sidewall of the second nanostructure 54 and/or the first nanostructure 52, respectively.

Furthermore, although the outer sidewall of the first inner spacer 90 is shown as straight in fig. 11B, the outer sidewall of the first inner spacer 90 may be concave or convex. As one example, fig. 11C illustrates an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed relative to the sidewalls of the second nanostructures 54 in the N-type region 50N. Also shown is an embodiment in which the sidewalls of the second nanostructures 54 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed relative to the sidewalls of the first nanostructures 52 in the P-type region 50P. The inner spacer layer may be etched by an anisotropic etching process (e.g., RIE, NBE, etc.). The first internal spacers 90 may be used to prevent damage to subsequently formed source/drain regions (e.g., epitaxial source/drain region 102, discussed below with reference to fig. 16A-16D) by a subsequent etching process (e.g., an etching process used to form a gate structure).

In fig. 12A and 12B, a first insulating film 92 is deposited over the structure shown in fig. 11A and 11B and in the recess 86, including along the trench bottoms of the recess 86. The first insulating film 92 may be formed using any suitable process and any suitable material. In some embodiments, the first insulating film 92 is deposited using a flowable CVD process at a process temperature of between about 30 ℃ and about 100 ℃ (e.g., between about 40 ℃ and 85 ℃) and at a process pressure of between about 0.1Torr and 50Torr (e.g., between about 2Torr and 10 Torr). The material of the first insulating film 92 may be any acceptable combination of materials having a low k value (k value less than 6). The low k value of the first insulating film 92 may be achieved by increasing the porosity through process conditions and/or by increasing the relative percentage of oxygen with respect to other materials of the first insulating film 92. In some embodiments, the material of the first insulating film 92 is silicon oxynitride (SiON) (where Si is between 40% and 60%, O is between 40% and 50%, and N is between 10% and 20%, in atomic percent), with a k value between 4 and 5.5. In other embodiments, the material of the first insulating film 92 is silicon oxynitride (SiOCN) (where Si is between 20% and 40%, O is between 50% and 60%, C is between 20% and 30%, and N is between 5% and 10%, in atomic percent), and k is between 3 and 5. The first insulating film 92 may be deposited to have a sidewall thickness along the gate structure of about 3nm to about 5nm (e.g., having an interface with the gate spacer 83 or the gate spacer 81) and a thickness in the recess 86 of between about 18nm to about 22 nm.

In fig. 13A and 13B, the first insulating film 92 is etched using an acceptable etching process to remove a sidewall portion of the first insulating film and form a lower isolation structure 93. In the illustrated embodiment, portions of the dummy gate structure above the mask 78 are also removed, however, in some embodiments, some portions of the first insulating film 92 above the mask 78 may remain (and be removed in subsequent processes). The removal may be performed by any suitable etching process at a process temperature of between about 50 ℃ and about 200 ℃, such as by a dry etching process using a suitable etchant (e.g., a fluorine-containing etchant). The remaining portions of the first insulating film 92 in the bottom of the recess 86 form the lower isolation structures 93, but the thickness of these portions may be reduced from the first insulating film 92 to the lower isolation structures 93. For example, the thickness of the lower isolation structure 93 may be about 25% to 35% or about 27% to 33% of the thickness of the corresponding bottom portion of the first insulating film 92. In some embodiments, the thickness of the lower isolation structure 93 may be between about 12nm and 16nm at its thickest point.

As shown in fig. 13A and 13B, the lower isolation structure 93 may extend upward along a sidewall of a lower portion of the recess 86 (corresponding to the fin 66). In some embodiments, the exposed portions of fins 66 may be entirely covered by lower isolation structures 93, while in other embodiments a portion of fins 66 may still be exposed from lower isolation structures 93. Examples of each of these components are provided and discussed below with respect to fig. 15C and 15D.

In fig. 14A and 14B, a second insulating film 94 is deposited over the structure shown in fig. 13A and 13B and in the recess 86, including along the lower isolation structure 93. The second insulating film 94 may be formed using any suitable process and material. In some embodiments, the second insulating film 94 is deposited using a flowable CVD process at a process temperature of between about 100 ℃ and about 150 ℃ (e.g., between about 110 ℃ and 140 ℃) and at a process pressure of between about 0.1Torr and 50Torr (e.g., between about 2Torr and 10 Torr). In other embodiments, the second insulating film 94 is deposited using an ALD process at a process temperature of between about 200 ℃ and about 500 ℃ (e.g., between about 300 ℃ and 400 ℃) and at a process pressure of between about 1Torr and 20Torr (e.g., between about 3Torr and 10 Torr).

The material of the second insulating film 94 is formed using a higher temperature process than the first insulating film 92. Therefore, the second insulating film 94 will be formed denser than the first insulating film 92 and have higher etching resistance than the first insulating film 92 or have etching selectivity to the first insulating film 92. For example, the second insulating film 94 may have an etch selectivity to the first insulating film 92 of greater than about 5, such as between about 5 and 8.

The second insulating film 94 may be any acceptable combination of materials. In some embodiments, the material of the second insulating film 94 is silicon oxynitride (SiON) (where Si is between 40% and 60%, O is between 30% and 50%, and N is between 10% and 30%, in atomic percent), with a k value between 4 and 5.5. In other embodiments, the material of the second insulating film 94 is silicon oxynitride (SiOCN) (where Si is between 20% and 40%, O is between 40% and 60%, C is between 20% and 30%, and N is between 10% and 20%, in atomic percent), and k has a value between 3 and 5. In still other embodiments, the material of the second insulating film 94 is silicon nitride (SiN) (where Si is between 40% and 60% and N is between 40% and 50% in atomic percent), with a k value between 5 and 6. The second insulating film 94 may be deposited to have a sidewall thickness along the gate structure of about 2nm to about 4nm (e.g., having an interface with the gate spacer 83 or the gate spacer 81) and a bottom thickness in the recess 86 (over the lower isolation structure 93) of between about 12nm and about 14 nm.

In an embodiment in which the material of the lower isolation structure 93 (i.e., from the first insulating film 92) is the same as the material of the second insulating film 94, the second insulating film 94 has a lower percentage of oxygen than the lower isolation structure 92. Further, the material of the second insulating film 94 has more N and/or more C (if applicable) than the lower isolation structure 93, which provides higher etching resistance.

In fig. 15A and 15B, the second insulating film 94 is etched using an acceptable etching process to remove a sidewall portion of the second insulating layer 94 and form an upper isolation structure 95. The structure formed by the lower isolation structure 93 and the upper isolation structure 95 together may be referred to as a trench isolation structure 97. In the illustrated embodiment, the portion of the second insulating film 94 that is above the mask 78 of the dummy gate structure is also removed, however, in some embodiments, a portion of the second insulating film 94 that is above the mask 78 may remain (and be removed in subsequent processes). The removal may be performed by any suitable etching process at a process temperature of between about 50 ℃ and about 200 ℃, such as by a dry etching process using a suitable etchant (e.g., a fluorine-containing etchant). The remaining portions of the second insulating film 94 located in the bottom of the recess 86 form the upper isolation structures 95, but the thickness of these portions may be reduced from the second insulating film 94 to the upper isolation structures 95. For example, the thickness of the upper isolation structure 95 may be about 40% to 80% of the thickness of the corresponding bottom of the second insulating film 94. In some embodiments, the thickness of the upper isolation structure 95 may be between about 4nm and 5nm at its thickest point.

Fig. 15C illustrates an enlarged portion of the 15CDN and 15CDP of fig. 15B in accordance with some embodiments. In some embodiments, lower isolation structure 93 extends partially up recess 86 and covers a portion of fin 66, while a portion of fin 66 remains clear of (uncovered by) lower isolation structure 93. Then, a subsequently formed upper isolation structure 95 is formed over the lower isolation structure 93, and the upper isolation structure extends partially upward along the recess 86 and covers the remaining portion of the fin 66 exposed from the lower isolation structure 93. In this way, all exposed portions of fin 66 are covered by the combination of lower isolation structure 93 and upper isolation structure 95 when recess 86 is formed. The ratio of the thickness t1 of the lower isolation structure 93 to the thickness t2 of the upper isolation structure 95 is between about 2:1 and about 1:1.

The upper isolation structure 95 may have an interface with the inner spacer 90, such as in the N-type region 50N, or with a portion of the first nanostructure 52A, such as in the P-type region 50P. In some embodiments, the P-type region 50P may be formed using the same nanostructures 54 as the n-type region (see fig. 24A, 24B, and 24C), in which case the upper isolation structure 95 may have an interface with the inner spacers 90 alongside the first nanostructures 52A in the P-type region 50. Since the lower isolation structure 93 does not completely cover the fin 66, leaving a portion of the fin exposed, which is then covered by the upper isolation structure 95, the lower isolation structure 93 does not contact either the inner spacer 90 or the first nanostructure 52A.

Fig. 15D illustrates an enlarged portion of the 15CDN and 15CDP of fig. 15B in accordance with other embodiments. In some embodiments, the lower isolation structure 93 extends partially up the recess 86 and covers all of the exposed fins 66. Then, subsequently formed upper isolation structures 95 are formed over the lower isolation structures 93, and the upper isolation structures 95 extend partially upward along the recesses 86. In this way, all exposed portions of fin 66 are covered only by lower isolation structure 93 when recess 86 is formed, and upper isolation structure 95 does not contact any portion of fin 66 or have an interface with any portion of fin 66. The ratio of the thickness t1 of the lower isolation structure 93 to the thickness t2 of the upper isolation structure 95 is between about 2:1 and about 1:1.

The upper isolation structure 95 may have an interface (i.e., physical contact) with the inner spacer 90, such as in the N-type region 50N, or an interface with a portion of the first nanostructure 52A, such as in the P-type region 50P. In some embodiments, the P-type region 50P may be formed using the same nanostructures 54 as the N-type region 50N (see fig. 24A, 24B, and 24C), in which case the upper isolation structure 95 may have an interface of the inner spacer 90 alongside the first nanostructure 52A in the P-type region 50. Likewise, the lower isolation structure 93 may also have an interface (i.e., physical contact) with the inner spacer 90 or a portion of the first nanostructure 52A.

Providing trench isolation structure 97 (including lower isolation structure 93 and upper isolation structure 95) reduces parasitic capacitance issues and reduces current leakage through fin 66 and/or substrate 50. The use of the upper isolation structure 95 over the lower isolation structure 93 provides a denser isolation structure with improved etch resistance that helps protect the lower isolation structure 93 from subsequent cleaning processes and the growth of epitaxial regions in the remaining recess 86. The use of the lower isolation structure 93 provides a low-k isolation feature, for example, providing better isolation than a high-k material, but may also be more susceptible to damage. Thus, using the combination of the upper isolation structure 95 and the lower isolation feature 93 for the trench isolation structure 97 provides good isolation and robustness.

In fig. 16A, 16B, 16C, and 16D, epitaxial source/drain regions 102 are formed in the first recesses 86 over the upper isolation structures 95 of the trench isolation structures 97. In some embodiments, the source/drain regions 102 may stress the second nanostructures 54 in the N-type region 50N and the first nanostructures 52 in the P-type region 50P, thereby improving performance. As shown in fig. 16B, epitaxial source/drain regions 102 are formed in the first recess 86 such that each dummy gate 76 is disposed between a respective adjacent pair of epitaxial source/drain regions 102. In some embodiments, first spacers 81 are used to separate the epitaxial source/drain regions 102 from the dummy gate 76, and first internal spacers 90 are used to separate the epitaxial source/drain regions 102 from the nanostructures 55 by an appropriate lateral distance so that the epitaxial source/drain regions 102 are not shorted to the subsequently formed gates of the resulting nanofet.

Epitaxial source/drain regions 102 in N-type region 50N (e.g., NMOS region) may be formed by masking P-type region 50P (e.g., PMOS region). Epitaxial source/drain regions 102 are then epitaxially grown in the first recesses 86 of the N-type regions 50N. The epitaxial source/drain regions 102 may comprise any acceptable material suitable for an n-type nanofet. For example, if the second nanostructure 54 is silicon, the epitaxial source/drain regions 102 may comprise a material that imparts a tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions 102 may have a surface that protrudes from a corresponding upper surface of the nanostructure 55, and may have facets.

Epitaxial source/drain regions 102 in P-type region 50P (e.g., PMOS region) may be formed by masking N-type region 50N (e.g., NMOS region). Epitaxial source/drain regions 102 are then epitaxially grown in the first recesses 86 in the P-type region 50P. The epitaxial source/drain regions 102 may comprise any acceptable material suitable for a p-type nanofet. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source/drain regions 102 may comprise a material that imparts a compressive strain on the first nanostructure 52, such as silicon germanium, boron doped silicon germanium, germanium tin, and the like. The epitaxial source/drain regions 102 may also have surfaces that are raised from the corresponding surfaces of the multi-layer stack, and may have facets.

The epitaxial source/drain regions 102, the first nanostructures 52, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly doped source/drain regions, followed by annealing. The impurity concentration of the source/drain regions may be about 1×10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Between them. The n-type and/or p-type impurities of the source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 102 may be doped in-situ during growth.

Due to the epitaxial process used to form the epitaxial source/drain regions 102 in the N-type region 50N and the P-type region 50P, the upper surface of the epitaxial source/drain electrical regions 102 has facets that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source/drain regions 102 of the same nanofet to merge, as shown in fig. 16A. In other embodiments, as shown in fig. 16C, adjacent epitaxial source/drain regions 102 remain separated after the epitaxial process is completed. In the embodiment shown in fig. 16A and 16C, a first spacer 81 may be formed on the top surface of the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the first spacers 81 may cover portions of the sidewalls of the nanostructures 55, thereby further preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown regions to extend to the surface of the STI regions 68.

The epitaxial source/drain regions 102 may include one or more layers of semiconductor material. For example, the epitaxial source/drain regions 102 may include a first semiconductor material layer 102A, a second semiconductor material layer 102B, and a third semiconductor material layer 102C. Any number of layers of semiconductor material may be used for epitaxial source/drain regions 102. Each of the first, second, and third semiconductor material layers 102A, 102B, and 102C may be formed of different semiconductor materials, and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 102A may have a dopant concentration that is less than the second semiconductor material layer 102B and greater than the third semiconductor material layer 102C. In embodiments where the epitaxial source/drain regions 102 comprise three layers of semiconductor material, a first layer of semiconductor material 102A may be deposited, a second layer of semiconductor material 102B may be deposited over the first layer of semiconductor material 102A, and a third layer of semiconductor material 102C may be deposited over the second layer of semiconductor material 102B. In some embodiments, a first semiconductor material layer 102A may be formed at the bottom of the recess 86 over the upper isolation structure 95 (see fig. 15A and 15B) and have a curved/bowl-shaped outer surface (the outer surface being opposite to the surface on which the first semiconductor material layer 102A is deposited). Further, the first semiconductor material layer 102A may be formed along the sidewall spacer 90 and have an outward curved/button shape. Accordingly, the first semiconductor material layer 102A formed on the sidewall spacers 90 may have an outer surface shape opposite to the first semiconductor material layer 102A formed at the bottom of the recess 86. In other words, the first semiconductor material layer 102A disposed on the bottom of the recess 86 is concave, while the first semiconductor material layer 102A disposed on the sidewall spacer 90 is convex. This may be the case even if the sidewall spacer 90 has a curved surface, as shown in fig. 16D. In some embodiments, the first semiconductor material layer 102A at the bottom of the recess 86 may be merged with the first semiconductor layer 102A on the sidewall spacer 90.

Due to the upper isolation structure 95 of the trench isolation structure 97, the lower isolation structure 93 of the trench isolation structure 97 is protected from damage during the growth process when forming the epitaxial source/drain regions 102 (e.g., comprising the first semiconductor material layer 102A), because the upper isolation structure 95 is more robust than the lower isolation structure 93. Furthermore, trench isolation structure 97 provides good isolation of epitaxial source/drain regions 102 from fin 66, particularly due to the low-k insulating material of lower isolation structure 93.

In some embodiments, a cleaning process may be used to remove etch residues that may remain after etching the sidewall spacer layer, the first insulating layer 92, and/or the second insulating layer 94 prior to growing the epitaxial source/drain regions 102. The cleaning process may use, for example, dilute hydrofluoric acid (dHF), deionized water, or other suitable cleaning agents to remove these residues. Although the lower isolation structure 93 has a lower k value than the upper isolation structure 95, the upper isolation structure 95 has a higher etching resistance than the lower isolation structure 93, thereby protecting the lower isolation structure 93 from damage that may be caused by the cleaning process.

Fig. 16D illustrates an embodiment in which the sidewalls of the first nanostructures 52 in the N-type region 50N and the sidewalls of the second nanostructures 54 in the P-type region 50P are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are concave with respect to the sidewalls of the second nanostructures 54 and the first nanostructures 52, respectively. As shown in fig. 16D, the epitaxial source/drain regions 102 may be formed in contact with the first internal spacers 90 and may extend past the sidewalls of the second nanostructures 54 in the N-type region 50N and past the sidewalls of the first nanostructures 52 in the P-type region 50P.

In fig. 17A, 17B, and 17C, a first interlayer dielectric (ILD) 106 is deposited over the structures shown in fig. 16A, 16B, and 16A, respectively (the process associated with fig. 7A-16D does not alter the cross-section shown in fig. 6A). The first ILD 106 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma Enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass, undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a Contact Etch Stop Layer (CESL) 104 is disposed between the first ILD 106 and the epitaxial source/drain regions 102, mask 78, and first spacers 81. The CESL 104 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., that has an etch rate different from the material of the first ILD 106 above.

In fig. 18A, 18B, a planarization process (e.g., CMP) may be performed to level the top surface of the first ILD 106 with the top surface of the dummy gate 76 or mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and portions of the first spacers 81 along the sidewalls of the mask 78. In embodiments where portions of first insulating layer 92 and/or second insulating layer 94 remain over mask 78, the planarization process will also remove these remaining portions of first insulating layer 92 and/or first insulating layer 94. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 106 are level over process variations. Thus, the top surface of the dummy gate 72 is exposed through the first ILD 106. In some embodiments, the mask 78 may remain, in which case the planarization process flushes the top surface of the first ILD 106 with the top surfaces of the mask 78 and the first spacers 81.

In fig. 19A and 19B, the dummy gate 76 and mask 78 (if present) are removed in one or more etching steps, thereby forming a second recess 105. The portion of the dummy gate dielectric 71 in the second recess 105 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using a reactive gas(s) that selectively etches the dummy gate 76 at a faster rate than the first ILD 106 or the first spacer 81. Each second recess 105 exposes and/or overlies portions of the nanostructure 55 that serve as channel regions in subsequently completed nanofets. The portion of the nanostructure 55 that acts as a channel region is disposed between an adjacent pair of epitaxial source/drain regions 102. During the removal, the dummy gate dielectric 71 may act as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric 71 may then be removed after the dummy gate 76 is removed.

In fig. 20A and 20B, the first nanostructures 52 in the N-type region 50N and the second nanostructures 54 in the P-type region 50P are removed, thereby extending the second recesses 105. First nanostructure 52 may be removed by forming a mask (not shown) over P-type region 50P and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant selective to the material of first nanostructure 52, while STI region 68 remains relatively unetched compared to first nanostructure 52. In embodiments where the first nanostructures 52 comprise, for example, siGe and the second nanostructures 54A-54C comprise, for example, si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) may be used ₄ OH), etc., to remove the first nanostructures 52 in the N-type region 50N.

The second nanostructures 54 in the P-type region 50P may be removed by forming a mask (not shown) over the N-type region 50N and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant selective to the material of the second nanostructures 54, while the STI regions 68 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 comprise SiGe, for example, and the first nanostructures 52 comprise Si or SiC, for example, hydrogen fluoride, another fluorine-based etchant, or the like, may be used to remove the second nanostructures 54 in the P-type region 50P.

In other embodiments, the channel regions in the N-type region 50N and the P-type region 50P may be formed simultaneously, for example, by removing the first nanostructures 52 in both the N-type region 50N and the P-type region 50P, or by removing the second nanostructures 54 in both the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions of the n-type nanofet and the p-type nanofet may have the same material composition, e.g., silicon germanium, etc. Fig. 24A, 24B and 24C illustrate structures resulting from embodiments in which the channel regions in both the P-type region 50P and the N-type region 50N are provided by the second nanostructures 54 and comprise, for example, silicon.

In fig. 21A and 21B, a gate dielectric layer 110 and a gate electrode 112 for a replacement gate are formed. A gate dielectric layer 110 is conformally deposited in the second recess 105. In the N-type region 50N, a gate dielectric layer 110 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the P-type region 50P, the gate dielectric layer 110 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. A gate dielectric layer 110 may also be deposited on top surfaces of the first ILD 106, CESL 104, first spacers 81, and STI regions 68.

According to some embodiments, gate dielectric layer 110 includes one or more dielectric layers, such as an oxide, a metal oxide, or the like, or a combination thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layer 110 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 110 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 110 may be the same or different in the N-type region 50N and the P-type region 50P. The formation method of the gate dielectric layer 110 may include Molecular Beam Deposition (MBD), ALD, PECVD, etc.

Gate electrodes 112 are deposited over the gate dielectric layers 110, respectively, and fill the remaining portions of the second recesses 105. The gate electrode 112 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although a single layer gate electrode 112 is shown in fig. 21A and 21B, the gate electrode 112 may include any number of liner layers, any number of work function tuning layers, and a filler material. Any combination of layers comprising gate electrode 112 may be deposited in N-type region 50N between each adjacent second nanostructure 54 and between second nanostructure 54A and substrate 50; and may be deposited in the P-type region 50P between the first nanostructures 52.

The formation of the gate dielectric layer 110 in the N-type region 50N and the P-type region 50P may occur simultaneously such that the gate dielectric layer 110 in each region is formed of the same material, and the formation of the gate electrode 112 may occur simultaneously such that the gate electrode 112 in each region is formed of the same material. In some embodiments, the gate dielectric layer 110 in each region may be formed by a different process, such that the gate dielectric layer 110 may be a different material and/or have a different number of layers; and/or the gate electrode 112 in each region may be formed by a different process such that the gate electrode 112 may be a different material and/or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

After filling the second recesses 105, a planarization process (e.g., CMP) may be performed to remove excess portions of the material of the gate dielectric layer 110 and the gate electrode 112, which are located over the top surface of the first ILD 106. The remaining portions of the material of gate electrode 112 and gate dielectric layer 110 thereby form a replacement gate structure for the resulting nano-FET. The gate electrode 112 and the gate dielectric layer 110 may be collectively referred to as a "gate structure"

In fig. 22A, 22B and 22C, the gate structure (including the gate dielectric layer 110 and the corresponding upper gate electrode 112) is recessed, thereby forming a recess directly above the gate structure and between opposing portions of the first spacers 81. A gate mask 114 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recesses, which are then subjected to a planarization process to remove excess portions of the dielectric material extending over the first ILD 106. A subsequently formed gate contact (e.g., gate contact 124, discussed below with respect to fig. 23A and 23B) penetrates gate mask 114 to contact the top surface of recessed gate electrode 112.

As further shown in fig. 22A-22C, a second ILD 116 is deposited over the first ILD 106 and the gate mask 114. In some embodiments, the second ILD 116 is a flowable film formed by FCVD. In some embodiments, the second ILD 116 is formed of a dielectric material, e.g., PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, e.g., CVD, PECVD, etc.

In fig. 23A, 23B, and 23C, the second ILD 116, the first ILD 106, the CESL104, and the gate mask 114 are etched to form a third recess exposing a surface of the epitaxial source/drain regions 102 and/or the gate structure. The third recess may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, a first etch process may be used to etch a third recess through the second ILD 116 and the first ILD 106; the third recess may be etched through the gate mask 114 using a second etching process; a third etch process may then be used to etch a third recess through CESL 104. A mask (e.g., photoresist) may be formed over the second ILD 116 and patterned to mask portions of the second ILD 116 for the first etch process and the second etch process. In some embodiments, the etching process may overetch, and thus, the third recess extends into the epitaxial source/drain region 102 and/or the gate structure, and the bottom of the third recess may be flush with (e.g., at the same level as, or at the same distance from, the substrate) or lower than (e.g., closer to the substrate) the epitaxial source/drain region 102 and/or the gate structure. Although fig. 23B shows contacts 122 and 124 formed in a third recess in the same cross-section, in various embodiments, the epitaxial source/drain regions 102 and gate structure may be exposed by the third recess in a different cross-section, thereby reducing the risk of shorting of subsequently formed contacts. After forming the third recess, silicide regions 120 are formed over the epitaxial source/drain regions 102. In some embodiments, silicide regions 120 are formed by: a metal (not shown) (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the underlying semiconductor material (e.g., silicon germanium, germanium) of epitaxial source/drain region 102 is first deposited to form a silicide or germanide region over the exposed portions of epitaxial source/drain region 102, and then a thermal annealing process is performed to form silicide region 120. Unreacted portions of the deposited metal are then removed by an etching process. Although silicide region 120 is referred to as a silicide region, silicide region 120 may also be a germanide region or a silicon germanide region (e.g., a region that includes silicide and germanide). In one embodiment, silicide region 120 comprises TiSi and has a thickness in a range between about 2nm and about 10 nm.

Next, contacts 122 and 124 (may also be referred to as contact plugs) are formed in the third recess. Contacts 122 and 124 may each include one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, contacts 122 and 124 each include a barrier layer and a conductive material and are electrically coupled to underlying conductive features (e.g., gate electrode 112 and/or silicide region 120 in the illustrated embodiment). Contacts 124 are electrically coupled to gate electrode 112 and may be referred to as gate contacts, and contacts 122 are electrically coupled to silicide regions 120 and may be referred to as source/drain contacts. The barrier layer may include titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (e.g., CMP) may be performed to remove excess material from the surface of the second ILD 116.

Fig. 23B provides four insert boxes (a), (B), (C), and (D) that illustrate variations on how trench isolation structures 97 interact with sidewall spacers 90 and channel region 54A. An illustration frame variant is provided for N-type region 50N, but it should be understood that illustration frames (B) and (D) are applicable to P-type region 50P if channel region 52A is substituted for sidewall spacer 90. The insert boxes (a) and (C) are not applicable to the P-type region 50P in these embodiments because the channel region 52A (in the case where the channel region 52A replaces the sidewall spacers 90, the gate dielectric layer 110 and the gate electrode 112) would be covered by the trench isolation structure 97. It should be noted that these variations may be combined with the above description in fig. 15C and 15D, wherein the interaction of trench isolation structure 97 with fin 66 is described. Further, with respect to the picture-inserting frames (a), (B), (C), and (D) discussed below, each of these aspects of the upper isolation structure 95 and the lower isolation structure 93 may be appropriately combined.

Regarding the lower isolation structure 93, in the illustration frame (a), the lower isolation structure 93 is shown not to contact the inner spacer 90. Instead, the lower isolation structure 93 covers only a portion of the fins 66, and a portion of the fins 66 remain out of contact with the lower isolation structure 93. In the illustration frame (B), the lower isolation structure 93 covers all of the fins 66 and meets the bottom of the sidewall spacer 90. In the illustration frame (C), the lower isolation structure 93 covers all of the fins 66 and also all of the sidewall spacers 90. In the illustration frame (D), the lower isolation structure 93 covers all of the fins 66 and has an interface with the sidewall spacer 90 that stops at a position between the upper surface of the sidewall spacer 90 and the lower surface of the sidewall spacer 90.

Regarding the upper isolation structure 95, in the illustration frame (a), the upper isolation structure 95 is shown covering all of the inner spacers 90. Further, the upper isolation structure 95 may contact a portion of the second nanostructure 54A. The upper isolation structure 95 may also contact a portion of the fin 66. In the picture frame (B), the upper isolation structure 95 has an interface with the sidewall spacer 90, which stops at a position interposed between the upper surface of the sidewall spacer 90 and the lower surface of the sidewall spacer 90. In the illustration frame (C), the upper isolation structure 95 has an interface with the second nanostructure 54A. In the illustration frame (D), the upper isolation structure 95 has an interface with the sidewall spacer 90 starting from a position between the upper surface of the sidewall spacer 90 and the lower surface of the sidewall spacer 90 and stopping at a position between the upper surface of the sidewall spacer 90 and the lower surface of the sidewall spacer 90, wherein the starting position is lower than the stopping position.

Fig. 24A, 24B, and 24C illustrate cross-sectional views of devices according to some alternative embodiments. Fig. 24A shows a reference section A-A' shown in fig. 1. Fig. 24B shows a reference section B-B' shown in fig. 1. Fig. 24C shows a reference section C-C' shown in fig. 1. In fig. 24A to 24C, the same reference numerals denote the same elements formed by the same processes as those of the structures of fig. 23A to 23C. However, in fig. 24A-24C, the channel regions in N-type region 50N and P-type region 50P comprise the same material. For example, the second nanostructure 54 comprising silicon provides a channel region for a P-type nanofet in the P-type region 50P and an N-type nanofet in the N-type region 50N. The structure of fig. 24A-24C may be formed, for example, by: first nanostructure 52 is removed from both P-type region 50P and N-type region 50N simultaneously; depositing a gate dielectric layer 110 and a gate electrode 112P (e.g., a gate electrode suitable for a P-type nanofet) around the second nanostructure 54 in the P-type region 50P; and depositing a gate dielectric layer 110 and a gate electrode 112N (e.g., a gate electrode suitable for an N-type nanofet) around the second nanostructure 54 in the N-type region 50N. In such an embodiment, the material of the epitaxial source/drain regions 102 may be different in the N-type region 50N compared to the P-type region 50P, as described above.

Fig. 24B shows the same situation of the insert boxes (a), (B), (C), and (D) discussed above with respect to fig. 23B. Since the embodiment shown in fig. 24A-24C utilizes the second nanostructure 54 as a channel region for both an N-type nanofet and a P-type nanofet, the description above regarding each of the insert boxes (a), (B), (C), and (D) applies to both the N-type region 50N and the P-type region 50P shown in fig. 24A-C.

Embodiments may realize advantages. For example, embodiments provide trench isolation structures (e.g., trench isolation structure 97 (including lower isolation structure 93 and upper isolation structure 95)) below epitaxial region 102, which reduces parasitic capacitance and reduces current leakage through fin 66 and/or substrate 50. The lower isolation structure 93 provides a low-k insulating material, which provides better isolation (e.g., relative to a higher-k insulating material) to reduce parasitic capacitance and current leakage, but may also be more susceptible to damage. The upper isolation structure 95 is a denser material composition with higher etch resistance than the lower isolation structure 93, which serves to protect the lower isolation structure 93 from damage caused by subsequent cleaning processes and/or by epitaxial region growth in the remaining recess 86. Thus, using the combination of the upper isolation structure 95 and the lower isolation feature 93 for the trench isolation structure 97 provides good isolation and structural robustness with respect to the epitaxial source/drain regions.

One embodiment is a method comprising forming a multi-layer stack of alternating layers of a first semiconductor material and a second semiconductor material over a semiconductor substrate. The method also includes patterning the multi-layer stack into a first fin, the first fin having a first longitudinal direction. The method also includes forming a dummy gate structure over the first fin, the dummy gate structure having a second longitudinal direction. The method also includes etching a first recess in the first fin adjacent to the dummy gate structure, the first recess extending into the semiconductor substrate. The method further includes depositing a first insulating film in the first recess, the first insulating film having a first k value. A second insulating film is deposited in the first recess over the first insulating film, the second insulating film having a second k value, the second k value being greater than the first k value. The method further includes forming an epitaxial region in the first recess over the second insulating film. In one embodiment, the method comprises: etching the first insulating film to remove a portion of the first insulating film along sidewalls of the dummy gate structure after depositing the first insulating film; and etching the second insulating film to remove a portion of the second insulating film along sidewalls of the dummy gate structure after depositing the second insulating film. In one embodiment, after etching the second insulating film, a portion of the first insulating film or the second insulating film remains over the dummy gate structure. In one embodiment, forming the epitaxial region may include: a first epitaxial layer is formed on the sidewall spacer and a second epitaxial layer is formed over the first epitaxial layer, a surface of the first epitaxial layer having a curved surface opposite the sidewall of the sidewall spacer. In one embodiment, the second insulating film has an interface with the sidewall spacer after the epitaxial region is formed. In one embodiment, the first fin may include a fin portion of the multi-layer stack over a fin portion of the semiconductor substrate, wherein the first recess exposes the fin portion of the semiconductor substrate; after the epitaxial region is formed, the first insulating film completely covers the fin portion of the semiconductor substrate. In one embodiment, the process temperature at which the deposition of the first insulating film is performed is lower than the process temperature for the deposition of the second insulating film. In one embodiment, the second insulating film is denser than the first insulating film.

Another embodiment is a method comprising: first and second nanostructures are formed over a substrate, each of the first nanostructures alternating with each of the second nanostructures, the substrate, the first nanostructures, and the second nanostructures being stacked to form a first fin. The method also includes forming a dummy gate structure over the first fin. The method also includes forming a recess in the first fin adjacent to the dummy gate structure, the recess continuously passing through the first nanostructure, the second nanostructure, and exposing the substrate. The method further includes depositing a first insulating layer in the recess and over the dummy gate structure. The method further includes etching the first insulating layer to form a first isolation structure at a bottom of the recess. The method further includes depositing a second insulating layer in the recess over the first isolation structure and over the dummy gate structure. The method further includes etching the second insulating layer to form a second isolation structure over the first isolation structure, wherein an etch resistance of the second insulating layer is different than an etch resistance of the first insulating layer. In one embodiment, the second insulating layer is deposited to have an oxygen content less than the first insulating layer. In one embodiment, a portion of the substrate in the recess does not contact the first isolation structure, wherein the second isolation structure is in contact with the substrate in the recess, wherein a portion of the second isolation structure contacts the sidewall spacer after the second isolation structure is formed. In one embodiment, the method comprises: depositing a first portion of a first layer of an epitaxial region on the sidewall spacer and depositing a second portion of the first layer of the epitaxial region on the second isolation structure, wherein the first portion has a curved surface opposite the sidewall of the sidewall spacer and the second portion has a curved surface opposite the interface with the second isolation structure, wherein the first portion merges with the second portion; and the method includes depositing a second layer of the epitaxial region over the first layer of the epitaxial region, the second layer filling the recess.

Another embodiment is a device comprising a first nanostructure; and a second nanostructure located over the first nanostructure. The device further includes a first spacer interposed between an end of the second nanostructure and a corresponding end of the first nanostructure. The device further includes a second spacer interposed between a corresponding end of the first nanostructure and the substrate. The device further includes an epitaxial region adjacent to the first nanostructure and the second nanostructure, the epitaxial region being in contact with the first spacer, an end of the second nanostructure, and a corresponding end of the first nanostructure. The device further includes a trench isolation structure located under the epitaxial region, the trench isolation structure including a first isolation structure under a second isolation structure, the first isolation structure being in contact with the substrate, the first isolation structure having a k value lower than the second isolation structure. In one embodiment, the oxygen content of the first isolation structure is greater than the oxygen content of the second isolation structure. In one embodiment, the first isolation structure and the second isolation structure may comprise the same material having different material atomic percentages. In one embodiment, the epitaxial region may include a first layer in contact with the second isolation structure, the first spacer, and the second spacer, the first layer having a curvilinear surface opposite respective interfaces with the second isolation structure, the first spacer, and the second spacer. In one embodiment, the ratio of the thickness of the second isolation structure to the first isolation structure is between 0.5:1 and 1:1. In one embodiment, a portion of the substrate does not contact the first isolation structure, wherein the second isolation structure contacts the substrate adjacent to the first isolation structure. In one embodiment, the second isolation structure is in contact with a sidewall of the second spacer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. A method for forming a semiconductor device, comprising:

forming a multi-layer stack of alternating layers of a first semiconductor material and a second semiconductor material over a semiconductor substrate;

patterning the multi-layer stack into a first fin, the first fin having a first longitudinal direction;

forming a dummy gate structure over the first fin, the dummy gate structure having a second longitudinal direction;

etching a first recess in the first fin adjacent to the dummy gate structure, the first recess extending into the semiconductor substrate;

Depositing a first insulating film in the first recess, the first insulating film having a first k value;

depositing a second insulating film in the first recess over the first insulating film, the second insulating film having a second k value, the second k value being greater than the first k value; and

an epitaxial region is formed in the first recess over the second insulating film.

Example 2. The method of example 1, further comprising:

etching the first insulating film to remove a portion of the first insulating film along sidewalls of the dummy gate structure after depositing the first insulating film; and

after depositing the second insulating film, the second insulating film is etched to remove a portion of the second insulating film along sidewalls of the dummy gate structure.

Example 3. The method of example 2, wherein a portion of the first insulating film or a portion of the second insulating film remains over the dummy gate structure after etching the second insulating film.

Example 4. The method of example 1, further comprising:

and forming a sidewall spacer in the first recess along a sidewall of the first layer of the first fin, wherein forming the epitaxial region includes forming a first epitaxial layer on the sidewall spacer and forming a second epitaxial layer over the first epitaxial layer, a surface of the first epitaxial layer having a curved surface opposite the sidewall of the sidewall spacer.

Example 5. The method of example 4, wherein the second insulating film has an interface with the sidewall spacer after forming the epitaxial region.

Example 6 the method of example 1, wherein the first fin comprises a fin portion of the multi-layer stack over a fin portion of the semiconductor substrate, wherein the first recess exposes the fin portion of the semiconductor substrate; after the epitaxial region is formed, the first insulating film completely covers the fin portion of the semiconductor substrate.

Example 7. The method of example 1, wherein the process temperature to deposit the first insulating film is performed is lower than the process temperature to deposit the second insulating film.

Example 8. The method of example 1, wherein the second insulating film is denser than the first insulating film.

Example 9. A method for forming a semiconductor device, comprising:

forming first and second nanostructures over a substrate, each of the first nanostructures alternating with each of the second nanostructures, wherein the substrate, the first nanostructures, and the second nanostructures are stacked to form a first fin;

Forming a dummy gate structure over the first fin;

forming a recess in the first fin adjacent to the dummy gate structure, the recess continuously passing through the first nanostructure, the second nanostructure and exposing the substrate;

depositing a first insulating layer in the recess and over the dummy gate structure;

etching the first insulating layer to form a first isolation structure at the bottom of the recess;

depositing a second insulating layer in the recess over the first isolation structure and over the dummy gate structure; and

the second insulating layer is etched to form a second isolation structure over the first isolation structure, wherein an etch resistance of the second insulating layer is different from an etch resistance of the first insulating layer.

Example 10 the method of example 9, wherein the second insulating layer is deposited to have an oxygen content less than the first insulating layer.

Example 11 the method of example 9, wherein a portion of the substrate in the recess does not contact the first isolation structure, wherein the second isolation structure contacts the substrate in the recess.

Example 12. The method of example 9, further comprising:

A sidewall spacer is formed on a sidewall of the base nanostructure of the first nanostructure, wherein a portion of the second isolation structure contacts the sidewall spacer after forming the second isolation structure.

Example 13. The method of example 12, further comprising:

depositing a first portion of a first layer of an epitaxial region on the sidewall spacer and depositing a second portion of the first layer of the epitaxial region on the second isolation structure, the first portion having a curved surface opposite the sidewall of the sidewall spacer, the second portion having a curved surface opposite the interface with the second isolation structure, wherein the first portion is merged with the second portion; and

a second layer of the epitaxial region is deposited over the first layer of the epitaxial region, the second layer filling the recess.

Example 14. A semiconductor device, comprising:

a first nanostructure;

a second nanostructure located over the first nanostructure;

a first spacer interposed between an end of the second nanostructure and a corresponding end of the first nanostructure;

a second spacer interposed between a corresponding end of the first nanostructure and a substrate;

An epitaxial region adjacent to the first nanostructure and the second nanostructure, the epitaxial region in contact with the first spacer, an end of the second nanostructure, and a corresponding end of the first nanostructure; and

and the channel isolation structure is positioned below the epitaxial region and comprises a first isolation structure below a second isolation structure, the first isolation structure is in contact with the substrate, and the k value of the first isolation structure is lower than that of the second isolation structure.

Example 15 the device of example 14, wherein the first isolation structure has an oxygen content that is greater than an oxygen content of the second isolation structure.

Example 16 the device of example 14, wherein the first isolation structure and the second isolation structure comprise the same material having different material atomic percentages.

Example 17 the device of example 14, wherein the epitaxial region comprises a first layer in contact with the second isolation structure, the first spacer, and the second spacer, the first layer having a curvilinear surface opposite respective interfaces with the second isolation structure, the first spacer, and the second spacer.

Example 18 the device of example 14, wherein a ratio of a thickness of the second isolation structure to the first isolation structure is between 0.5:1 and 1:1.

Example 19 the device of example 14, wherein a portion of the substrate does not contact the first isolation structure, wherein the second isolation structure contacts the substrate adjacent to the first isolation structure.

Example 20 the device of example 14, wherein the second isolation structure is in contact with a sidewall of the second spacer.

Claims

1. A method for forming a semiconductor device, comprising:

2. The method of claim 1, further comprising:

3. The method of claim 2, wherein a portion of the first insulating film or a portion of the second insulating film remains over the dummy gate structure after etching the second insulating film.

4. The method of claim 1, further comprising:

5. The method of claim 4, wherein the second insulating film has an interface with the sidewall spacer after forming the epitaxial region.

6. The method of claim 1, wherein the first fin comprises a fin portion of the multi-layer stack over a fin portion of the semiconductor substrate, wherein the first recess exposes the fin portion of the semiconductor substrate. After the epitaxial region is formed, the first insulating film completely covers the fin portion of the semiconductor substrate.

7. The method according to claim 1, wherein a process temperature at which depositing the first insulating film is performed is lower than a process temperature for depositing the second insulating film.

8. The method of claim 1, wherein the second insulating film is denser than the first insulating film.

9. A method for forming a semiconductor device, comprising:

Forming a dummy gate structure over the first fin;

10. A semiconductor device, comprising:

a first nanostructure;

a second nanostructure located over the first nanostructure;