CN116779542A - Method for integrating germanium-silicon heterojunction transistor in silicon-based self-aligned bipolar process and semiconductor device - Google Patents

Abstract

The invention provides a method for integrating a germanium-silicon heterojunction transistor in a silicon-based self-aligned bipolar process and a semiconductor device, wherein the invention is based on ingenious design of process steps, the process steps of the germanium-silicon heterojunction transistor are integrated in the silicon-based self-aligned bipolar process, the vertical bipolar transistor and the germanium-silicon heterojunction bipolar transistor are simultaneously integrated and prepared by utilizing a single manufacturing process under the condition of not remarkably increasing the process complexity, the process efficiency is improved, the process cost is reduced, the transistors are further divided into NPN type and PNP type, the correspondingly prepared semiconductor device can cover various transistor structure combinations, is suitable for application scenes with different functional requirements, and can correspondingly improve the electrical performance of the corresponding semiconductor device or chip.

Description

Method for integrating germanium-silicon heterojunction transistor in silicon-based self-aligned bipolar process and semiconductor device

Technical Field

The invention belongs to the technical field of semiconductor device processes, and particularly relates to a method for integrating a germanium-silicon heterojunction transistor in a silicon-based self-aligned bipolar process and a semiconductor device.

Background

In the semiconductor integrated circuit manufacturing process, bipolar transistors (BJTs) generally have two structures, a vertical type (VerticalBipolar Transistor, VBT) and a lateral type (LateralBipolarTransistor, LBT). VBT of vertical structure has significant performance advantages over LBT of lateral structure, such as higher characteristic frequency f _T Current gain beta, early voltage V _A Lower noise characteristics NF, etc., but the manufacturing process is more complicated. Whereas conventional bipolar processes typically include only vertical NPN transistors (VNPN), their integrated PNP transistors are typically lateral structures (LPNP). The complementary bipolar (ComplementaryBipolar, CB) fabrication process of the NPN and PNP integrated vertical structures is not simple, and adding vertical structure PNP (VPNP) adds significant technical complexity and process manufacturing costs.

To further enhance the rf performance of bipolar transistors, an important technical approach is to replace the Si-based region with germanium-silicon (Si _1-X Ge _X ) Material, forming heterojunction bipolar transistors (sige hbts). Because the SiGeHBT process requires additional lithography pattern area definition, siGe heterojunction epitaxy, polysilicon outer base connection and strict control of thermal budget, so the introduction of SiGe process further increases the technical difficulty and complexity of the process. In particular, the technology for integrating the SiGeHBT with the symmetrical and complementary silicon vertical VNPN and VPNP transistors is not reported in the open literature at present.

Vertical bipolar transistor technology is the main technology of high-speed/high-precision analog and radio frequency chips. Among other things, silicon germanium heterojunction bipolar transistors (sige hbts) and silicon vertical bipolar transistors (sibbt) have respective advantages and disadvantages: sige hbts have excellent radio frequency performance but higher crystal defects due to lattice matching between silicon and germanium, with higher leakage currents; siVBT can withstand a wider range of operating voltages, higher operating currents, and lower leakage currents, but device cut-off frequencies are typically limited to within 50 GHz.

Thus, there is a need for a SiGe-Si complementary bipolar process that can integrate both germanium-silicon heterojunction transistors (SiGe hbts) and silicon vertical bipolar transistors (sibbt) in a single manufacturing process, and in particular, can integrate vertical VNPN and PNP transistors together, without increasing the complexity of the process.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a process scheme for integrating a germanium-silicon heterojunction transistor in a silicon-based self-aligned bipolar process, which can integrate a germanium-silicon heterojunction transistor and a vertical-structured silicon bipolar transistor simultaneously in a single manufacturing process without significantly increasing the process complexity.

In order to achieve the above object and other related objects, the present invention provides the following technical solutions.

A method of integrating a silicon germanium heterojunction transistor in a silicon-based self-aligned bipolar process, comprising:

providing a silicon substrate, wherein N collector regions and a plurality of field oxide isolation regions are formed in the silicon substrate, the N collector regions comprise M first collector regions and N-M second collector regions, and the collector regions are mutually isolated through the plurality of field oxide isolation regions;

forming a first dielectric layer on the silicon substrate, wherein the first dielectric layer contacts and covers each collector region and each field oxide isolation region, and etching the first dielectric layer to expose M first collector regions;

forming a first doped polysilicon layer, wherein the first doped polysilicon layer covers the residual first dielectric layer and the exposed first collector region, a second dielectric layer is formed on the first doped polysilicon layer, the second dielectric layer and the first doped polysilicon layer are etched to form N emitter windows which are in one-to-one correspondence with N collector regions, the N emitter windows comprise M first emitter windows and N-M second emitter windows, the M first emitter windows are in one-to-one correspondence with the M first collector regions, and the N-M second emitter windows are in one-to-one correspondence with the M first dielectric layers on the N-M second collector regions;

Performing ion implantation and annealing along the M first emitter windows, forming a first collector injection layer, an inner base region and an inner base region connecting layer in the first collector region, wherein the inner base region and the inner base region connecting layer are positioned at the top of the first collector region, and the inner base region is connected with the residual first doped polysilicon layer through the inner base region connecting layer and the inner base region connecting layer;

forming a third dielectric layer, wherein the third dielectric layer covers the second dielectric layers and the first doped polysilicon layers at the side walls of the N emitter windows, the third dielectric layer covers the inner base regions and the inner and outer base region connecting layers at the bottoms of the M first emitter windows, and the third dielectric layer also covers the first dielectric layers at the bottoms of the N-M second emitter windows;

etching along the N-M second emitter windows, removing the third dielectric layer and the first dielectric layer at the bottom of the second emitter windows, performing ion implantation along the N-M second emitter windows, and forming a second collector implantation layer in the second collector region;

performing epitaxial growth along the N-M second emitter windows, forming germanium-silicon heterojunction inner base regions on the second collector regions, etching along the M first emitter windows, and removing the third dielectric layers at the bottoms of the first emitter windows to expose the inner base regions and the inner and outer base region connecting layers in the first collector regions;

Wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

Optionally, the first collector region includes an N-type doped collector region or a P-type doped collector region, the second collector region includes an N-type doped collector region or a P-type doped collector region, and the step of providing a silicon substrate includes:

providing an initial silicon substrate, wherein the initial silicon substrate comprises N device areas;

forming N heavily doped buried layers on the N device regions of the initial silicon substrate in a one-to-one correspondence manner, wherein the heavily doped buried layers comprise N-type heavily doped buried layers and P-type heavily doped buried layers;

forming N collector regions on N device regions of the initial silicon substrate in a one-to-one correspondence manner, wherein the collector regions comprise N-type doped collector regions and P-type doped collector regions, the N-type doped collector regions are positioned above the N-type heavily doped buried layer, and the P-type doped collector regions are positioned above the P-type heavily doped buried layer;

and forming a plurality of field oxide isolation regions to isolate N device regions, wherein in a first plane, the field oxide isolation regions are arranged around the N-type doped collector region and the N-type heavily doped buried layer, or the field oxide isolation regions are arranged around the P-type doped collector region and the P-type heavily doped buried layer.

Optionally, the step of forming a first dielectric layer on the silicon substrate, where the first dielectric layer contacts and covers each collector region and each field oxide isolation region, and etching the first dielectric layer to expose M first collector regions includes:

forming a first dielectric layer on the silicon substrate by adopting a deposition process, wherein the first dielectric layer contacts and covers each collector region and each field oxide isolation region;

and removing part of the first dielectric layer by adopting a photoetching process and an etching process so as to expose M first collector regions.

Optionally, the step of forming a first doped polysilicon layer, where the first doped polysilicon layer covers the remaining first dielectric layer and the exposed first collector region, forming a second dielectric layer on the first doped polysilicon layer, and etching the second dielectric layer and the first doped polysilicon layer to form N emitter windows corresponding to N collector regions one-to-one, where the N emitter windows include M first emitter windows and N-M second emitter windows, where the M first emitter windows expose M first collector regions one-to-one, and the N-M second emitter windows expose the first dielectric layer on the N-M second collector regions one-to-one, includes:

Forming a first polysilicon layer by adopting a deposition process, wherein the first polysilicon layer covers the residual first dielectric layer and the exposed first collector region;

doping the first polysilicon layer by adopting an ion implantation process, carrying out P+ type implantation doping on the region of the first polysilicon layer on the N-type doped collector region, and carrying out N+ type implantation doping on the region of the first polysilicon layer on the P-type doped collector region to form the first doped polysilicon layer;

forming the second dielectric layer on the first doped polysilicon layer by adopting a deposition process;

and etching the second dielectric layer and the first doped polysilicon layer by adopting a photoetching process and an etching process to form M first emitter windows and N-M second emitter windows, wherein the M first emitter windows are in one-to-one correspondence to expose M first collector regions, and the N-M second emitter windows are in one-to-one correspondence to expose the first dielectric layers on the N-M second collector regions.

Optionally, the step of performing ion implantation and annealing along M first emitter windows to form a first collector implantation layer, an inner base region, and an inner base region connecting layer in the first collector region, where the inner base region and the inner base region connecting layer are located on top of the first collector region, and the inner base region is connected with the remaining first doped polysilicon layer through the inner base region connecting layer, includes:

Forming a photoresist mask layer by adopting a photoetching process, wherein the photoresist mask layer covers the residual second dielectric layer, the residual first doped polysilicon layer and N-M second emitter windows, and exposes M first emitter windows;

performing first ion implantation along the M first emitter windows, and forming first collector implantation layers in the M first collector regions respectively;

performing second ion implantation along the M first emitter windows, performing P-type implantation doping on the N-type doped collector region, performing N-type implantation doping on the P-type doped collector region, and forming an inner base region in each of the M first collector regions, wherein the inner base region is positioned at the top of the first collector region and above the first collector implantation layer;

and activating the impurities after ion implantation by adopting an annealing process, so that the impurities doped in the residual first doped polysilicon layer are diffused into the first collector region to form an inner and outer base region connecting layer, and the residual first doped polysilicon layer is connected with the inner base region through the inner and outer base region connecting layer.

Optionally, an oxidation process or a deposition process is used to form the third dielectric layer.

Optionally, the step of etching along the N-M second emitter windows to remove the third dielectric layer and the first dielectric layer at the bottom of the second emitter windows, and then performing ion implantation and annealing along the N-M second emitter windows to form a second collector implantation layer in the second collector region includes:

performing dry etching along the N-M second emitter windows by adopting a photoetching process and a dry etching process to remove the third dielectric layer and part of the first dielectric layer at the bottom of each second emitter window;

wet etching is carried out along the N-M second emitter windows by adopting a wet etching process, and the first dielectric layer at the bottom of each second emitter window and part of the first dielectric layer below the residual first doped polysilicon layer are removed so as to expose the second collector region and the residual first doped polysilicon layer;

and then carrying out ion implantation along the N-M second emitter windows, and forming a second collector implantation layer in the second collector region.

Optionally, the step of epitaxially growing along the N-M second emitter windows, forming an sige heterojunction intrinsic base region on the second collector region, etching along the M first emitter windows, and removing the third dielectric layer at the bottom of the first emitter windows to expose the intrinsic base region and the intrinsic base region connecting layer in the first collector region includes:

Adopting an epitaxial growth process to carry out epitaxial growth along the N-M second emitter windows, and forming a germanium-silicon heterojunction inner base region on the second collector region, wherein the germanium-silicon heterojunction inner base region is respectively connected with the second collector region and the residual first doped polysilicon layer;

and etching along the M first emitter windows by adopting a photoetching process and an etching process, and removing the third dielectric layer at the bottom of the first emitter windows to expose the inner base region and the inner and outer base region connecting layer in the first collector region.

Optionally, the method for integrating a germanium-silicon heterojunction transistor in a silicon-based self-aligned bipolar process further comprises:

forming a fourth dielectric layer, wherein the fourth dielectric layer covers the residual second dielectric layer, the residual first doped polysilicon layer, the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window;

etching the fourth dielectric layer to expose the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window, and forming an emitter-base side wall blocking structure;

Forming a second doped polysilicon layer, wherein the second doped polysilicon layer covers the residual second dielectric layer, the residual first doped polysilicon layer, the residual fourth dielectric layer, the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window;

etching the second doped polysilicon layer and rapidly annealing to form a polysilicon emitter region, and diffusing doped impurities in the polysilicon emitter region into the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window to form an emitter-base junction;

and forming an emitter contact electrode, a base contact electrode and a collector contact electrode, wherein the emitter contact electrode is in ohmic contact with the polycrystalline silicon emitter region, the base contact electrode is in ohmic contact with the residual first doped polycrystalline silicon layer, and the collector contact electrode is in ohmic contact with the collector region.

A semiconductor device manufactured by the method for integrating a germanium-silicon heterojunction bipolar transistor in a silicon-based self-aligned bipolar process according to any one of the above, wherein a silicon vertical bipolar transistor and a germanium-silicon heterojunction bipolar transistor are integrated on the semiconductor device, the silicon vertical bipolar transistor comprises a PNP type silicon vertical bipolar transistor or an NPN type silicon vertical bipolar transistor, and the germanium-silicon heterojunction bipolar transistor comprises a PNP type germanium-silicon heterojunction bipolar transistor or an NPN type germanium-silicon heterojunction bipolar transistor.

As described above, the method for integrating the germanium-silicon heterojunction transistor in the silicon-based self-aligned bipolar process and the semiconductor device provided by the invention have at least the following beneficial effects:

forming a first collector region and a second collector region on a silicon substrate at the same time, forming a first dielectric layer on the silicon substrate and etching, wherein the etched first dielectric layer exposes the first collector region and covers the second collector region, and then forming a first doped polysilicon layer and a second dielectric layer and etching to form a first emitter window and a second emitter window, wherein the first emitter window exposes the first collector region, and the second emitter window exposes the first dielectric layer on the second collector region; taking the etched first dielectric layer as a barrier layer, performing ion implantation along a first emitter window, and annealing to form a conventional silicon inner base region structure in a first collector region; and forming a third dielectric layer and etching, wherein the etched third dielectric layer is used as a blocking layer, ion implantation and epitaxial growth are carried out along a second emitter window exposed after etching, a germanium-silicon heterojunction inner base region structure is formed on a second collector region, a polycrystalline silicon emitter region, an emitter contact electrode, a base contact electrode and a collector contact electrode are formed synchronously, so that the process of integrating the germanium-silicon heterojunction transistor in the silicon-based self-aligned bipolar process is carried out, the silicon vertical bipolar transistor and the germanium-silicon heterojunction bipolar transistor are simultaneously integrated and prepared by utilizing a single manufacturing process under the condition of not remarkably increasing the process complexity, the process efficiency is improved, the process cost is reduced, the transistor is further divided into NPN type and PNP type, the correspondingly prepared semiconductor device can cover various transistor structure combinations, is applicable to application scenes with different functional requirements, and can be used for improving the electrical performance of the corresponding semiconductor device according to the situation.

Drawings

Fig. 1 is a schematic diagram illustrating the steps of a method for integrating a sige heterojunction transistor in a silicon-based self-aligned bipolar process according to the present invention.

Fig. 2-20 are process flow diagrams illustrating a method of integrating a sige heterojunction transistor in a silicon-based self-aligned bipolar process in accordance with an alternative embodiment of the present invention.

Description of the reference numerals

00-field oxide isolation region, 01-first collector region, 02-second collector region, 03-heavily doped buried layer, 100-initial silicon substrate, 1-silicon substrate, 2-first dielectric layer, 3-first doped polysilicon layer, 4-second dielectric layer, 51-first collector injection layer, 52-inner base region, 53-inner and outer base region connection layer, 54-second collector injection layer, 55-germanium-silicon heterojunction inner base region, 6-third dielectric layer, 7-fourth dielectric layer, 8-emitter-base sidewall blocking structure, 9-second doped polysilicon layer, 10-polysilicon emitter region, PV-photoresist mask layer, T1-first emitter window, T2-second emitter window.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 20. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure for the purpose of understanding and reading by those skilled in the art, and are not intended to limit the scope of the invention, so that any structural modifications, proportional changes, or dimensional adjustments should not be construed as essential to the invention, but should still fall within the scope of the invention as defined by the appended claims without affecting the efficacy or achievement of the invention.

As described in the foregoing background, the inventors have studied to find: the bipolar transistor with the vertical structure is a main technology of high-speed/high-precision simulation and radio frequency chips, and the silicon germanium heterojunction bipolar transistor and the silicon bipolar transistor with the vertical structure have the advantages and the disadvantages: the silicon-germanium heterojunction bipolar transistor with the vertical structure has excellent radio frequency performance, but has higher crystal defects due to lattice matching between silicon and germanium and higher leakage current; silicon bipolar transistors of vertical structure can withstand a wider operating voltage, higher operating current, and lower leakage current, but device cut-off frequencies are typically limited to within 50 GHz.

Based on this, the present invention proposes a SiGe-Si complementary bipolar process integrating bipolar transistors of vertical structure together: the process of integrating the germanium-silicon heterojunction transistor in the silicon-based self-aligned bipolar process simultaneously utilizes the silicon vertical bipolar transistor and the germanium-silicon heterojunction bipolar transistor to be prepared by integrating in a single manufacturing process simultaneously under the condition of not remarkably increasing the process complexity so as to improve the process efficiency and reduce the process cost, and the transistor is further divided into NPN type and PNP type, and the correspondingly prepared semiconductor device covers various transistor structure combinations and can be suitable for application scenes with various different functional requirements, and the electrical performance of the corresponding semiconductor device can be improved according to local conditions.

As shown in fig. 1, the present invention provides a method for integrating a germanium-silicon heterojunction transistor in a silicon-based self-aligned bipolar process, comprising the steps of:

s1, providing a silicon substrate 1, wherein N collector regions and a plurality of field oxide isolation regions 00 are formed in the silicon substrate 1, the N collector regions further comprise M first collector regions 01 and N-M second collector regions 02, and the collector regions are isolated from each other through the plurality of field oxide isolation regions 00;

s2, forming a first dielectric layer 2 on the silicon substrate 1, wherein the first dielectric layer 2 contacts and covers each collector region and each field oxide isolation region 00, and etching the first dielectric layer 2 to expose M first collector regions 01;

S3, forming a first doped polysilicon layer 3, wherein the first doped polysilicon layer 3 covers the residual first dielectric layer 2 and the exposed first collector region 01, forming a second dielectric layer 4 on the first doped polysilicon layer 3, etching the second dielectric layer 4 and the first doped polysilicon layer 3 to form N emitter windows which are in one-to-one correspondence with N collector regions, wherein the N emitter windows comprise M first emitter windows T1 and N-M second emitter windows T2, the M first emitter windows T1 are in one-to-one correspondence with the M first collector regions 01, and the N-M second emitter windows T2 are in one-to-one correspondence with the M first dielectric layers 2 on the N-M second collector regions 02;

s4, performing ion implantation along M first emitter windows T1, and annealing to form a first collector injection layer 51, an inner base region 52 and an inner base region connecting layer 53 in the first collector region 01, wherein the inner base region 52 and the inner base region connecting layer 53 are positioned on the top of the first collector region 01, and the inner base region 52 is connected with the residual first doped polysilicon layer 3 through the inner base region connecting layer 53;

s5, forming a third dielectric layer 6, wherein the third dielectric layer 6 covers the second dielectric layers 4 and the first doped polysilicon layers 3 at the side walls of the N emitter windows, the third dielectric layer 6 covers the inner base regions 52 and the inner and outer base region connecting layers 53 at the bottoms of the M first emitter windows, and the third dielectric layer 6 also covers the first dielectric layers 2 at the bottoms of the N-M second emitter windows;

S6, etching is carried out along the N-M second emitter windows T2, the third dielectric layer 6 and the first dielectric layer 2 at the bottom of the second emitter windows T2 are removed, ion implantation is carried out along the N-M second emitter windows T2, and a second collector implantation layer 54 is formed in the second collector region 02;

s7, performing epitaxial growth along the N-M second emitter windows T2, forming germanium-silicon heterojunction inner base regions 55 on the second collector region 02, etching along the M first emitter windows T1, and removing the third dielectric layer 6 at the bottom of the first emitter windows T1 to expose the inner base regions 52 and the inner and outer base region connecting layers 53 in the first collector region 01;

wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

In detail, in step S1, as shown in fig. 2, N collector regions (where M is 1, N is 2, and the values of M and N are not limited thereto and can be flexibly adjusted according to actual requirements) are provided in the silicon substrate 1, where the first collector region 01 may be an N-type doped collector region, or may be a P-type doped collector region, and the second collector region 02 is the same as the first collector region 01 based on the different requirements of the bipolar transistor types to be formed subsequently; the collector region may be formed by epitaxy of a doping material, or may be prepared by an ion implantation doping process (ion implantation+annealing), which is not limited herein; meanwhile, a heavily doped buried layer 03 and a field oxide isolation region 00 are also formed in the silicon substrate 1.

In detail, in an alternative embodiment of the present invention, as shown in fig. 2, the step S1 of providing the silicon substrate 01 further includes:

s101, providing an initial silicon substrate 100, wherein the initial silicon substrate 100 comprises N device regions (each region separated by a dashed line in fig. 2);

s102, forming N heavily doped buried layers 03 on N device regions of an initial silicon substrate 100 in a one-to-one correspondence manner, wherein the heavily doped buried layers 03 further comprise N-type heavily doped buried layers and P-type heavily doped buried layers;

s103, N collector regions are formed on the N device regions of the initial silicon substrate 100 in a one-to-one correspondence manner, each collector region comprises an N-type doped collector region and a P-type doped collector region, the N-type doped collector region is located above the N-type heavily doped buried layer, and the P-type doped collector region is located above the P-type heavily doped buried layer along the Z-axis direction;

s104, forming a plurality of field oxide isolation regions 00 to isolate N device regions, wherein the field oxide isolation regions 00 are arranged around the N-type doped collector region and the N-type heavily doped buried layer or the field oxide isolation regions 00 are arranged around the P-type doped collector region and the P-type heavily doped buried layer in a first plane (namely an XY plane).

In more detail, in step S101, the initial silicon substrate 100 is not limited to the support layer of the entire semiconductor device, but may be a single crystal silicon material, or may be another substrate material such as Silicon On Insulator (SOI).

In more detail, in step S102, the heavily doped buried layer 03 may be formed using an ion implantation process + an annealing process or an epitaxy process, and the Rc resistance of the transistor finally formed by the heavily doped buried layer 03. In order to further reduce Rc resistance of the finally formed transistor, N collector penetrating layers (not shown in the figure) may be formed on N device regions of the initial silicon substrate 100 in a one-to-one correspondence manner, and details may be referred to in the prior art, which are not described herein.

In more detail, in step S103, an ion implantation process + an annealing process or an epitaxial process may be used to form N collector regions on the N device regions of the initial silicon substrate 100 in one-to-one correspondence, the N collector regions further including M first collector regions 01 and N-M second collector regions 02, the first collector regions 01 being used to form silicon vertical bipolar transistors and the second collector regions 02 being used to form silicon germanium heterojunction bipolar transistors. The first collector region 01 includes an N-type doped collector region or a P-type doped collector region, and the second collector region 02 includes an N-type doped collector region or a P-type doped collector region. On each device region, the doping type of the collector region is the same as the doping type of the corresponding heavily doped buried layer 03.

In more detail, in step S104, a photolithography process, an etching process, a deposition process, a photolithography process and an etching process may be sequentially used to form a trench refill, a plurality of field oxide isolation regions 00 may be formed on the initial silicon substrate 100 based on a deep trench isolation technique, or a plurality of field oxide isolation regions 00 may be formed on the initial silicon substrate 100 based on a local field oxide technique, each device region is isolated by the field oxide isolation regions 00, and the field oxide isolation regions 00 are disposed around one device region in a first plane (i.e., XY plane), so that the N-type doped collector region and the N-type heavily doped buried layer in the device region are isolated from other structures, or the P-type doped collector region and the P-type heavily doped buried layer in the device region are isolated from other structures.

In detail, in an alternative embodiment of the present invention, as shown in fig. 3, a first dielectric layer 2 is formed on a silicon substrate 1, the first dielectric layer 2 contacts and covers each collector region and each field oxide isolation region 02, and the first dielectric layer 2 is etched to expose M first collector regions 01, which further includes:

s201, a first dielectric layer 2 is formed on a silicon substrate 1 by adopting a deposition process, and the first dielectric layer 2 contacts and covers each collector region and each field oxide isolation region 00;

S202, removing part of the first dielectric layer 2 by adopting a photoetching process and an etching process to expose M first collector regions 01.

In more detail, in step S201, a Chemical Vapor Deposition (CVD) process or a thermal oxidation process is used to form a first dielectric layer 2 on the silicon substrate 1, and the first dielectric layer 2 may be a silicon oxide material or a silicon nitride material. The thickness of the first dielectric layer 2 depends on the thickness of the SiGe epitaxial layer in the subsequent process steps (most applications are between 20nm and 200nm depending on the device characteristic frequency and withstand voltage requirements of the particular application).

In more detail, in step S202, the first dielectric layer 2 on the first collector region 01 is removed by photolithography and etching in sequence, so as to facilitate the subsequent process of the intrinsic base region of the silicon vertical bipolar transistor.

In detail, in an alternative embodiment of the present invention, as shown in fig. 4-6, a first doped polysilicon layer 3 is formed, the first doped polysilicon layer 3 covers the remaining first dielectric layer 2 and the exposed first collector region 01, a second dielectric layer 4 is formed on the first doped polysilicon layer 3, and the second dielectric layer 4 and the first doped polysilicon layer 3 are etched to form N emitter windows corresponding to N collector regions one by one, wherein the N emitter windows include M first emitter windows T1 and N-M second emitter windows T2, the M first emitter windows T1 expose the M first collector regions 01 one by one, and the N-M second emitter windows T2 expose the first dielectric layer 2 on the N-M second collector regions 02 one by one, which further includes:

S301, as shown in FIG. 4, a deposition process is adopted to form a first polysilicon layer, wherein the first polysilicon layer covers the residual first dielectric layer 2 and the exposed first collector region 01;

s302, as shown in FIG. 4, an ion implantation process (not shown) is adopted to dope the first polysilicon layer, P+ type implantation doping is carried out on the region of the first polysilicon layer on the N type doped collector region, N+ type implantation doping is carried out on the region of the first polysilicon layer on the P type doped collector region, and a first doped polysilicon layer 3 is formed;

s303, as shown in FIG. 5, a deposition process is adopted to form a second dielectric layer 4 on the first doped polysilicon layer 3;

s304, as shown in FIG. 6, the second dielectric layer 4 and the first doped polysilicon layer 3 are etched by using a photolithography process (not shown) and an etching process, so as to form M first emitter windows T1 and N-M second emitter windows T2, wherein the M first emitter windows T1 are in one-to-one correspondence to expose the M first collector regions 01, and the N-M second emitter windows T2 are in one-to-one correspondence to expose the first dielectric layer 2 on the N-M second collector regions 02.

In more detail, in steps S301 to S302, as shown in fig. 4, the first doped polysilicon layer 3 is formed using a deposition process+an ion implantation process. It will be appreciated that the first doped polysilicon layer 3 may also be formed by a doped polysilicon deposition process, and is not limited herein.

In more detail, in step S303, as shown in fig. 5, the second dielectric layer 4 may be a single layer of silicon nitride or a single layer of silicon oxide, or may be a multi-layer composite layer of silicon nitride and silicon oxide, and when the second dielectric layer 4 is a multi-layer composite layer of silicon nitride and silicon oxide, the top layer is silicon nitride.

In more detail, in step S304, as shown in fig. 6, a photoresist mask layer is formed by photolithography, and then etching is performed using the photoresist mask layer as a mask, so as to form M first emitter windows T1 and N-M second emitter windows T2, wherein the etching of the first emitter windows T1 is stopped on the first collector region 01, the first emitter windows T1 expose the first collector region 01, the etching of the second emitter windows T2 is stopped on the first dielectric layer 2, and the second emitter windows T2 expose the first dielectric layer 2 on the second collector region 02; simultaneously, etching to form a device isolation trench, and cutting off the first doped polysilicon layer 3 and the second dielectric layer 4 in each device region to form independent blocks.

In detail, in an alternative embodiment of the present invention, as shown in fig. 7 to 10, the step S4 of performing ion implantation along the M first emitter windows T1 and annealing to form a first collector implant layer 51, an intrinsic base region 52 and an intrinsic base region connection layer 53 in the first collector region 01, the intrinsic base region 52 and the intrinsic base region connection layer 53 being located on top of the first collector region 01, and the intrinsic base region 52 being connected to the remaining first doped polysilicon layer 3 through the intrinsic base region connection layer 53, includes:

S401, as shown in FIG. 7, a photoresist mask layer PV is formed by adopting a photoetching process, wherein the photoresist mask layer PV covers the residual second dielectric layer 4, the residual first doped polysilicon layer 3 and N-M second emitter windows T2, and M first emitter windows T1 are exposed;

s402, as shown in fig. 8, performing a first ion implantation along the M first emitter windows T1, and forming first collector implantation layers 51 in the M first collector regions 01, respectively;

s403, as shown in FIG. 9, performing a second ion implantation along the M first emitter windows T2, performing a P-type implantation doping on the N-type doped collector region, performing an N-type implantation doping on the P-type doped collector region, and forming an inner base region 52 in each of the M first collector regions 01, wherein the inner base region 52 is located on top of the first collector region 01 and above the first collector implantation layer 51;

s404, as shown in fig. 10, the photoresist mask layer PV is removed, and the impurity after ion implantation is activated by an annealing process, so that the impurity doped in the residual first doped polysilicon layer 3 diffuses into the first collector region 01, forming an inner and outer base region connecting layer 53, and the residual first doped polysilicon layer 3 is connected with the inner base region 52 through the inner and outer base region connecting layer 53.

In more detail, in step S401, the photoresist after lithography is used as an etching mask, and other passivation layers after etching may be used as etching masks, which will not be described herein.

In more detail, in step S402, first ion implantation is performed along the M first emitter windows T1, and the first collector implant layers 51 are formed in the M first collector regions 01, respectively. Step S402 is an optional step, and may be optional and optionally flexibly determined.

In more detail, in steps S403 to S404, after the second ion implantation, the photoresist mask layer PV is removed and annealed, impurity activation diffusion is performed, the inner and outer base region connecting layer 53 is formed, and the connection between the remaining first doped polysilicon layer 3 and the inner base region 52 is achieved through the inner and outer base region connecting layer 53.

In detail, in step S5, as shown in fig. 11, the third dielectric layer 6 covering the whole surface is formed by an oxidation process or a deposition process, for example, the third dielectric layer 6 made of silicon oxide is formed by an oxidation process, the third dielectric layer 6 made of silicon oxide is formed by a deposition process, the third dielectric layer 6 made of silicon oxide and silicon nitride is formed by a deposition process, or the third dielectric layer 6 made of silicon oxide and silicon nitride is formed by an oxidation process, and then a silicon nitride is formed by a deposition process, so as to obtain the third dielectric layer 6 with a composite structure.

In detail, in an alternative embodiment of the present invention, as shown in fig. 12-14, etching is performed along N-M second emitter windows T2 to remove the third dielectric layer 6 and the first dielectric layer 2 at the bottom of the second emitter windows T2, and then ion implantation is performed along N-M second emitter windows T2 to form a second collector implant layer 54 in the second collector region 02, which further includes:

s601, as shown in FIG. 12, performing dry etching along the N-M second emitter windows T2 by adopting a photoetching process and a dry etching process, and removing the third dielectric layer 6 and part of the first dielectric layer 2 at the bottom of each second emitter window T2;

s602, as shown in FIG. 13, performing wet etching along the N-M second emitter windows T2 by adopting a wet etching process, and removing the first dielectric layer 2 at the bottom of each second emitter window T2 and a part of the first dielectric layer 2 below the residual first doped polysilicon layer 3 to expose the second collector region 02 and the residual first doped polysilicon layer 3;

s603, as shown in fig. 14, ion implantation is performed along the N-M second emitter windows T2, and a second collector implant layer 53 is formed in the second collector region 02.

In more detail, in steps S601 to S602, as shown in fig. 12 to 13, the third dielectric layer 6 and the first dielectric layer 2 at the bottom of the second emitter window T2 are removed in combination with anisotropic dry etching and isotropic wet etching, and a "overhang layer" of lateral etching is formed under the first doped polysilicon layer 3 at the bottom of the second emitter window T2. Meanwhile, the side wall and the bottom of the first emitter window T1 are blocked by the residual third dielectric layer 6; the sidewalls of the second emitter window T2 are still blocked by the remaining third dielectric layer 6, the bottom of the second emitter window T2 exposing the second collector region 02.

In more detail, in step S603, as shown in fig. 14, ion implantation is performed along the N-M second emitter windows T2, forming a second collector implant layer 53 in the second collector region 02. Likewise, step S603 is an optional step, and the selective ion implantation doping of the second collector implant layer 53 is flexibly selectable according to the specific application requirements.

In detail, in an alternative embodiment of the present invention, as shown in fig. 15 to 16, an epitaxial growth is performed along N-M second emitter windows T2, a sige heterojunction inter-base region 55 is formed on the second collector region 02, etching is performed along M first emitter windows T1, and the third dielectric layer 6 at the bottom of the first emitter windows T1 is removed to expose the inter-base region 52 and the inter-and-outer-base region connection layer 53 in the first collector region 01, which further includes the step S7 of:

s701, as shown in FIG. 15, performing epitaxial growth along the N-M second emitter windows T2 by adopting an epitaxial growth process, forming a germanium-silicon heterojunction inner base region 55 on the second collector region 02, wherein the germanium-silicon heterojunction inner base region 55 is respectively connected with the second collector region 02 and the residual first doped polysilicon layer 3;

s702, as shown in fig. 16, a photolithography process and an etching process are used to etch along the M first emitter windows T1, so as to remove the third dielectric layer 6 at the bottom of the first emitter window T1, and expose the inner base region 52 and the inner and outer base region connecting layer 53 in the first collector region 01.

In more detail, in step S701, as shown in fig. 15, a SiGe or SiGe-C material SiGe heterojunction intrinsic base region 55 is grown on the second collector region 02 by a selective epitaxial growth process, and the formed SiGe heterojunction intrinsic base region 55 is connected to the second collector region 02 and the remaining first doped polysilicon layer 3, respectively.

In more detail, in step S702, as shown in fig. 16, the third dielectric layer 6 at the bottom of the first emitter window T1 is removed by photolithography and etching to expose the inner base region 52 and the inner and outer base region connecting layer 53 in the first collector region 01, so as to expose the silicon inner base region structure in the first emitter window T1 and the germanium inner base region structure in the second emitter window T2, respectively.

In detail, as shown in fig. 17-20, the method for integrating a germanium-silicon heterojunction transistor in a silicon-based self-aligned bipolar process further comprises the steps of:

s8, as shown in FIG. 17, a fourth dielectric layer 7 is formed, and the fourth dielectric layer 7 covers the residual second dielectric layer 4, the residual first doped polysilicon layer 3, the inner base region 52 at the bottom of the first emitter window T1 and the germanium-silicon heterojunction inner base region 55 at the bottom of the second emitter window T2;

s9, as shown in FIG. 18, etching the fourth dielectric layer 7 to expose the inner base region 52 at the bottom of the first emitter window T1 and the germanium-silicon heterojunction inner base region 55 at the bottom of the second emitter window T2, and forming an emitter-base side wall blocking structure 8;

S10, as shown in FIG. 19, a second doped polysilicon layer 9 is formed, and the second doped polysilicon layer 9 covers the residual second dielectric layer 4, the residual first doped polysilicon layer 3, the residual fourth dielectric layer 7, the inner base region 52 at the bottom of the first emitter window T1 and the germanium-silicon heterojunction inner base region 55 at the bottom of the second emitter window T2;

s11, as shown in FIG. 20, etching the second doped polysilicon layer 9 and rapidly annealing to form a polysilicon emitter region 10, and diffusing impurities doped in the polysilicon emitter region 10 into an inner base region 52 at the bottom of the first emitter window T1 and a germanium-silicon heterojunction inner base region 55 at the bottom of the second emitter window T2 to form an emitter-base junction;

and S12, forming an emitter contact electrode, a base contact electrode and a collector contact electrode, wherein the emitter contact electrode is in ohmic contact with the polycrystalline silicon emitter region 10, the base contact electrode is in ohmic contact with the residual first doped polycrystalline silicon layer 3, and the collector contact electrode is in ohmic contact with the collector region.

In more detail, in steps S8 to S9, as shown in fig. 17 to fig. 18, a deposition process is first used to form a fourth dielectric layer 7 on the entire surface, the fourth dielectric layer 7 generally adopts a composite layer structure, and then the emitter-base sidewall barrier structure 8 with a conventional morphology or an "L" morphology is formed by combining the conventional "Spacer" manufacturing processes in the industry.

In more detail, in step S10, as shown in fig. 19, a deposition process is first used to form a second polysilicon layer on the entire surface, and then a heavily doped ion implantation is performed on the second polysilicon layer, for example, n+ type ion implantation is phosphorus or arsenic, p+ type ion implantation is boron or boron difluoride, so as to form a second doped polysilicon layer 9.

In more detail, in step S11, as shown in fig. 20, the second doped polysilicon layer 9 is etched and rapidly annealed (RTA) to form a polysilicon emitter 10, and impurities doped in the polysilicon emitter 10 are diffused into the inner base region 52 at the bottom of the first emitter window T1 and the germanium-silicon heterojunction inner base region 55 at the bottom of the second emitter window T2 to form an emitter-base junction; meanwhile, most of the remaining fourth dielectric layer 7, third dielectric layer 6 and second dielectric layer 4 are etched away to expose the remaining first polysilicon layer 3, which is used as an outer base region structure, so as to facilitate the subsequent manufacture of the base contact electrode. At this time, the main structures of the silicon vertical bipolar transistor and the germanium-silicon heterojunction bipolar transistor are completed.

In more detail, in step S12, a metal is deposited and etched to form an emitter contact electrode, a base contact electrode, and a collector contact electrode to electrically draw out the electrodes of the respective bipolar transistors. In addition, according to the specific application requirements, the following processes of silicide (Salicide), ILD medium, hole/via, multilayer metal wiring, surface passivation, etc. may be involved, and these processes are all common practices in the semiconductor industry, and are not emphasized by the present invention, which is not described in detail herein.

Finally, based on the method for integrating the germanium-silicon heterojunction transistor in the silicon-based self-aligned bipolar process, a semiconductor device is manufactured, wherein a silicon vertical bipolar transistor and a germanium-silicon heterojunction bipolar transistor are integrated on the semiconductor device, the silicon vertical bipolar transistor comprises a PNP type silicon vertical bipolar transistor or an NPN type silicon vertical bipolar transistor, and the germanium-silicon heterojunction bipolar transistor comprises a PNP type germanium-silicon heterojunction bipolar transistor or an NPN type germanium-silicon heterojunction bipolar transistor.

The process shown in fig. 2-20 is to prepare 2 silicon vertical bipolar transistors and 1 germanium-silicon heterojunction bipolar transistor correspondingly, and the specific type of each bipolar transistor can be flexibly selected. It should be noted that, the semiconductor device is provided with a silicon vertical bipolar transistor and a germanium-silicon heterojunction bipolar transistor in a synchronous integrated manner, and the number and types of the two bipolar transistors can be arbitrarily combined and configured, which is not limited herein.

In an alternative embodiment of the present invention, an NPN silicon vertical bipolar transistor and an NPN silicon germanium heterojunction bipolar transistor are integrated on the semiconductor device, where the NPN silicon germanium heterojunction bipolar transistor is used to achieve a radio frequency or low noise performance with higher performance, and the NPN silicon vertical bipolar transistor is used to expand a high voltage function, build a low leakage module, or improve ESD (electrostatic discharge) capability of the whole circuit.

In an alternative embodiment of the present invention, a PNP type silicon vertical bipolar transistor and an NPN type silicon germanium heterojunction bipolar transistor are integrally disposed on the semiconductor device, where the PNP type silicon vertical bipolar transistor is used to make up for a short plate with insufficient LPNP tube performance in a conventional SiGe process, and a complementary push-pull structure is constructed.

In another alternative embodiment of the present invention, the semiconductor device is provided with an NPN silicon vertical bipolar transistor, a PNP silicon vertical bipolar transistor and an NPN germanium silicon heterojunction bipolar transistor in an integrated manner, and the integrated circuit can realize the function of integrating the radio frequency module and the high-speed high-voltage swing-rate operational amplifier and the logarithmic detection amplifier with unique complementary push-pull structures and exponential/logarithmic volt-ampere characteristics on the same chip because the NPN germanium silicon heterojunction bipolar transistor with radio frequency performance and the NPN silicon vertical bipolar transistor and the PNP silicon vertical bipolar transistor with longitudinal symmetry complementary can be simultaneously provided.

The current main SiGe bipolar process solutions in the industry are of two main types: the first type is a conventional SiGe bipolar process integrating an NPN silicon-germanium heterojunction bipolar transistor and a lateral PNP silicon bipolar transistor of vertical structure; the second type is a complementary SiGe bipolar process that integrates an NPN-type SiGe heterojunction bipolar transistor of vertical structure and a PNP-type SiGe heterojunction bipolar transistor of vertical structure simultaneously. Compared with the first scheme, the invention can integrate the silicon vertical bipolar transistor with a vertical structure to make up for the short plate with insufficient LPNP tube performance in the conventional SiGe process, such as being used for constructing a complementary push-pull structure, and the structure has very wide application scenes in the fields of high-speed, high-precision and broadband operational amplifiers and logarithmic amplifier products; compared with the second scheme, the invention has obvious cost advantages (the process is simpler, an N-type SiGe epitaxial furnace is not required to be additionally arranged, and the like), and in addition, the high voltage function can be expanded, the low leakage module can be constructed or the ESD capacity of the whole circuit can be improved by utilizing the high voltage resistance and low leakage characteristic of the silicon vertical bipolar transistor relative to the germanium-silicon bipolar transistor.

Based on the analysis, the process scheme of integrating the germanium-silicon heterojunction transistor in the silicon-based self-aligned bipolar process provided by the invention is that a first collector region and a second collector region are simultaneously formed on a silicon substrate, a first dielectric layer is formed on the silicon substrate and etched, the etched first dielectric layer exposes the first collector region and covers the second collector region, and then a first doped polysilicon layer and a second dielectric layer are formed and etched to form a first emitter window and a second emitter window, wherein the first emitter window exposes the first collector region, and the second emitter window exposes the first dielectric layer on the second collector region; taking the etched first dielectric layer as a barrier layer, performing ion implantation along a first emitter window, and annealing to form a conventional silicon inner base region structure in a first collector region; the method comprises the steps of forming a third dielectric layer, etching, taking the etched third dielectric layer as a barrier layer, carrying out ion implantation and epitaxial growth along a second emitter window exposed after etching, forming a germanium-silicon heterojunction inner base region structure on a second collector region, and then synchronously forming a polycrystalline silicon emitter region, an emitter contact electrode, a base contact electrode and a collector contact electrode.

It should be noted that, in the steps of the above embodiments, simple procedures and conditions of well-known and obvious general-purpose cleaning in industry are omitted, which are well known to those skilled in the art, and will not be described in detail here.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method of integrating a silicon germanium heterojunction transistor in a silicon-based self-aligned bipolar process, comprising:

providing a silicon substrate, wherein N collector regions and a plurality of field oxide isolation regions are formed in the silicon substrate, the N collector regions comprise M first collector regions and N-M second collector regions, and the collector regions are mutually isolated through the plurality of field oxide isolation regions;

forming a first dielectric layer on the silicon substrate, wherein the first dielectric layer contacts and covers each collector region and each field oxide isolation region, and etching the first dielectric layer to expose M first collector regions;

Forming a first doped polysilicon layer, wherein the first doped polysilicon layer covers the residual first dielectric layer and the exposed first collector region, a second dielectric layer is formed on the first doped polysilicon layer, the second dielectric layer and the first doped polysilicon layer are etched to form N emitter windows which are in one-to-one correspondence with N collector regions, the N emitter windows comprise M first emitter windows and N-M second emitter windows, the M first emitter windows are in one-to-one correspondence with the M first collector regions, and the N-M second emitter windows are in one-to-one correspondence with the M first dielectric layers on the N-M second collector regions;

performing ion implantation and annealing along the M first emitter windows, forming a first collector injection layer, an inner base region and an inner base region connecting layer in the first collector region, wherein the inner base region and the inner base region connecting layer are positioned at the top of the first collector region, and the inner base region is connected with the residual first doped polysilicon layer through the inner base region connecting layer and the inner base region connecting layer;

forming a third dielectric layer, wherein the third dielectric layer covers the second dielectric layers and the first doped polysilicon layers at the side walls of the N emitter windows, the third dielectric layer covers the inner base regions and the inner and outer base region connecting layers at the bottoms of the M first emitter windows, and the third dielectric layer also covers the first dielectric layers at the bottoms of the N-M second emitter windows;

Etching along the N-M second emitter windows, removing the third dielectric layer and the first dielectric layer at the bottom of the second emitter windows, performing ion implantation along the N-M second emitter windows, and forming a second collector implantation layer in the second collector region;

performing epitaxial growth along the N-M second emitter windows, forming germanium-silicon heterojunction inner base regions on the second collector regions, etching along the M first emitter windows, and removing the third dielectric layers at the bottoms of the first emitter windows to expose the inner base regions and the inner and outer base region connecting layers in the first collector regions;

wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

2. The method of integrating a silicon germanium heterojunction transistor in a silicon-based self-aligned bipolar process of claim 1, wherein the first collector region comprises an N-type doped collector region or a P-type doped collector region, the second collector region comprises an N-type doped collector region or a P-type doped collector region, the step of providing a silicon substrate comprising:

providing an initial silicon substrate, wherein the initial silicon substrate comprises N device areas;

Forming N heavily doped buried layers on the N device regions of the initial silicon substrate in a one-to-one correspondence manner, wherein the heavily doped buried layers comprise N-type heavily doped buried layers and P-type heavily doped buried layers;

forming N collector regions on N device regions of the initial silicon substrate in a one-to-one correspondence manner, wherein the collector regions comprise N-type doped collector regions and P-type doped collector regions, the N-type doped collector regions are positioned above the N-type heavily doped buried layer, and the P-type doped collector regions are positioned above the P-type heavily doped buried layer;

and forming a plurality of field oxide isolation regions to isolate N device regions, wherein in a first plane, the field oxide isolation regions are arranged around the N-type doped collector region and the N-type heavily doped buried layer, or the field oxide isolation regions are arranged around the P-type doped collector region and the P-type heavily doped buried layer.

3. The method of claim 2, wherein forming a first dielectric layer on the silicon substrate, the first dielectric layer contacting and covering each of the collector regions and each of the field oxide isolation regions, and etching the first dielectric layer to expose M of the first collector regions, comprises:

Forming a first dielectric layer on the silicon substrate by adopting a deposition process, wherein the first dielectric layer contacts and covers each collector region and each field oxide isolation region;

and removing part of the first dielectric layer by adopting a photoetching process and an etching process so as to expose M first collector regions.

4. The method of claim 3, wherein the forming a first doped polysilicon layer covering the remaining first dielectric layer and the exposed first collector region, forming a second dielectric layer on the first doped polysilicon layer, and etching the second dielectric layer and the first doped polysilicon layer to form N emitter windows in one-to-one correspondence with N collector regions, the N emitter windows including M first emitter windows and N-M second emitter windows, the M first emitter windows exposing M first collector regions in one-to-one correspondence with N-M first dielectric layers on the second collector regions, comprises:

Forming a first polysilicon layer by adopting a deposition process, wherein the first polysilicon layer covers the residual first dielectric layer and the exposed first collector region;

doping the first polysilicon layer by adopting an ion implantation process, carrying out P+ type implantation doping on the region of the first polysilicon layer on the N-type doped collector region, and carrying out N+ type implantation doping on the region of the first polysilicon layer on the P-type doped collector region to form the first doped polysilicon layer;

forming the second dielectric layer on the first doped polysilicon layer by adopting a deposition process;

and etching the second dielectric layer and the first doped polysilicon layer by adopting a photoetching process and an etching process to form M first emitter windows and N-M second emitter windows, wherein the M first emitter windows are in one-to-one correspondence to expose M first collector regions, and the N-M second emitter windows are in one-to-one correspondence to expose the first dielectric layers on the N-M second collector regions.

5. The method of integrating a sige heterojunction transistor in a silicon-based self-aligned bipolar process of claim 4, wherein said step of performing ion implantation along M of said first emitter windows and annealing forms a first collector implant layer, an intrinsic base region and an intrinsic base region connecting layer in said first collector region, said intrinsic base region and said intrinsic base region connecting layer being located on top of said first collector region and said intrinsic base region connecting with the remaining first doped polysilicon layer through said intrinsic base region connecting layer comprises:

Forming a photoresist mask layer by adopting a photoetching process, wherein the photoresist mask layer covers the residual second dielectric layer, the residual first doped polysilicon layer and N-M second emitter windows, and exposes M first emitter windows;

performing first ion implantation along the M first emitter windows, and forming first collector implantation layers in the M first collector regions respectively;

performing second ion implantation along the M first emitter windows, performing P-type implantation doping on the N-type doped collector region, performing N-type implantation doping on the P-type doped collector region, and forming an inner base region in each of the M first collector regions, wherein the inner base region is positioned at the top of the first collector region and above the first collector implantation layer;

and activating the impurities after ion implantation by adopting an annealing process, so that the impurities doped in the residual first doped polysilicon layer are diffused into the first collector region to form an inner and outer base region connecting layer, and the residual first doped polysilicon layer is connected with the inner base region through the inner and outer base region connecting layer.

6. The method of integrating a silicon germanium heterojunction transistor in a silicon-based self-aligned bipolar process as claimed in claim 1 or 5, wherein said third dielectric layer is formed by employing an oxidation process or a deposition process.

7. The method of claim 1, wherein the etching along the N-M second emitter windows, removing the third dielectric layer and the first dielectric layer at the bottom of the second emitter windows, and performing ion implantation along the N-M second emitter windows, forming a second collector implant layer in the second collector region, comprises:

performing dry etching along the N-M second emitter windows by adopting a photoetching process and a dry etching process to remove the third dielectric layer and part of the first dielectric layer at the bottom of each second emitter window;

wet etching is carried out along the N-M second emitter windows by adopting a wet etching process, and the first dielectric layer at the bottom of each second emitter window and part of the first dielectric layer below the residual first doped polysilicon layer are removed so as to expose the second collector region and the residual first doped polysilicon layer;

and then carrying out ion implantation and annealing along the N-M second emitter windows, and forming a second collector implantation layer in the second collector region.

8. The method of claim 1, wherein the step of epitaxially growing along N-M second emitter windows, forming an sige heterojunction intrinsic base region on the second collector region, etching along M first emitter windows, and removing the third dielectric layer at the bottom of the first emitter windows to expose the intrinsic base region and the intrinsic-extrinsic base connection layer in the first collector region comprises:

adopting an epitaxial growth process to carry out epitaxial growth along the N-M second emitter windows, and forming a germanium-silicon heterojunction inner base region on the second collector region, wherein the germanium-silicon heterojunction inner base region is respectively connected with the second collector region and the residual first doped polysilicon layer;

and etching along the M first emitter windows by adopting a photoetching process and an etching process, and removing the third dielectric layer at the bottom of the first emitter windows to expose the inner base region and the inner and outer base region connecting layer in the first collector region.

9. The method of integrating a silicon germanium heterojunction transistor in a silicon-based self-aligned bipolar process of claim 1, further comprising:

Forming a fourth dielectric layer, wherein the fourth dielectric layer covers the residual second dielectric layer, the residual first doped polysilicon layer, the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window;

etching the fourth dielectric layer to expose the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window, and forming an emitter-base side wall blocking structure;

forming a second doped polysilicon layer, wherein the second doped polysilicon layer covers the residual second dielectric layer, the residual first doped polysilicon layer, the residual fourth dielectric layer, the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window;

etching the second doped polysilicon layer and rapidly annealing to form a polysilicon emitter region, and diffusing doped impurities in the polysilicon emitter region into the inner base region at the bottom of the first emitter window and the germanium-silicon heterojunction inner base region at the bottom of the second emitter window to form an emitter-base junction;

And forming an emitter contact electrode, a base contact electrode and a collector contact electrode, wherein the emitter contact electrode is in ohmic contact with the polycrystalline silicon emitter region, the base contact electrode is in ohmic contact with the residual first doped polycrystalline silicon layer, and the collector contact electrode is in ohmic contact with the collector region.

10. A semiconductor device, characterized in that the semiconductor device is manufactured by the method for integrating a germanium-silicon heterojunction bipolar transistor in a silicon-based self-aligned bipolar process according to any one of claims 1-9, and a silicon vertical bipolar transistor and a germanium-silicon heterojunction bipolar transistor are integrated on the semiconductor device, wherein the silicon vertical bipolar transistor comprises a PNP type silicon vertical bipolar transistor or an NPN type silicon vertical bipolar transistor, and the germanium-silicon heterojunction bipolar transistor comprises a PNP type germanium-silicon heterojunction bipolar transistor or an NPN type germanium-silicon heterojunction bipolar transistor.