CN116778839A - Display signal detection circuit of micro display panel - Google Patents
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Abstract
The invention discloses a display signal detection circuit of a micro display panel, which comprises: the signal detection units are provided with the same circuit structure, and each signal detection unit comprises a signal rising edge and falling edge separation unit, a rising edge detection unit, a falling edge detection unit and a signal synthesis and detection result output unit; the micro display panel display signal detection circuit further comprises an I2C bus register; the signal rising edge and falling edge separation unit is used for separating the rising edge and the falling edge of the signal in the field synchronous signal VS, the line synchronous signal HS or the effective display data strobe signal DE, and forming a rising edge trigger signal and a falling edge trigger signal respectively so as to realize the detection of the rising edge and the falling edge respectively; the false rising edge signal or falling edge signal generated by the system reset signal is avoided, so that the accuracy of display signal detection is improved.
Description
Technical Field
The invention relates to the technical field of image display, in particular to a display signal detection circuit of a micro display panel.
Background
Micro-display technology based on Micro-LEDs or Micro-OLEDs refers to display technology in which self-luminous Micro-scale LEDs or OLEDs are used as luminous pixel units, and the luminous pixel units are assembled on a driving panel to form a high-density LED array. The micro display chip has the advantages of small size, high integration level, self-luminescence and the like, and has the advantages of display brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like. Based on the above advantages, the micro display chip-based display device can be manufactured as a miniature and portable product, which allows the micro display chip-based display device to be applied to an AV or VR display device.
Because AV or VR display device's characteristics lie in miniaturized portable, therefore the encapsulation of micro display panel and other parts of device can be inseparabler, when micro display panel appears unusual needs to detect, and be inconvenient for using oscilloscope connection micro display panel's each pin to detect micro display panel's video data signal state, and then be inconvenient for carrying out the location to micro display panel reason of unusual demonstration.
Accordingly, there is a need in the art for a method and circuit that facilitates detection of display signals on a microdisplay panel in a tightly packaged state.
Disclosure of Invention
The technical purpose to be achieved by the invention is to provide a micro display panel display signal detection circuit, which comprises a plurality of signal detection units 1, wherein the signal detection units 1 have the same circuit structure, and each signal detection unit 1 comprises a signal rising edge and falling edge separation unit 2, a rising edge detection unit 3, a falling edge detection unit 4 and a signal synthesis and detection result output unit 5; the micro display panel display signal detection circuit further comprises an I2C bus register 6;
the field synchronizing signal VS, the line synchronizing signal HS and the effective display data strobe signal DE in the display signals are respectively and correspondingly input to a signal detection unit 1;
the signal rising edge and falling edge separating unit 2 is configured to separate a rising edge and a falling edge of the field synchronization signal VS, the line synchronization signal HS, or the valid display data strobe signal DE, and form a rising edge trigger signal and a falling edge trigger signal, so as to implement detection of the rising edge and the falling edge respectively;
the rising edge detection unit 3 generates a rising edge detection result signal of the signal to be detected according to the rising edge trigger signal transmitted by the signal rising edge and falling edge separation unit 2 and continuously outputs the rising edge detection result signal; the falling edge detection unit 4 generates a falling edge detection result signal of the signal to be detected according to the falling edge trigger signal transmitted by the signal rising edge and falling edge separation unit 2 and continuously outputs the falling edge detection result signal;
the signal synthesis and detection result output unit 5 combines the rising edge detection result signal output by the rising edge detection unit 3 and the falling edge detection result signal output by the falling edge detection unit 4 to generate a field synchronization signal VS, a line synchronization signal HS or a detection result of whether the valid display data strobe signal DE is valid or not, and outputs the detection result to the I2C bus register 6, wherein the I2C bus register 6 stores the detection result of whether the display signal contains the field synchronization signal VS, the line synchronization signal HS or the valid display data strobe signal DE or not, and the I2C bus register 6 can be accessed by other devices on the I2C bus.
In one embodiment, the signal rising edge and falling edge separation unit 2 includes a first D flip-flop 21, a first not gate 22, a first and gate 23, a second not gate 24, and a second and gate 25; the signal input end D of the first D trigger 21 is connected with a field synchronous signal VS, a line synchronous signal HS or an effective display data strobe signal DE; the first output end Q of the first D flip-flop 21 is connected to the input end of the first not gate 22, the output end of the first not gate 22 is connected to the first input end of the first and gate 23, and the second input end of the first and gate 23 is connected to the signal input end D of the first D flip-flop 21; the input end of the first AND gate 23 outputs rising edge information of the detected signal; the input end of the second not gate 24 is connected to the signal input end D of the first D flip-flop 21, the output end of the second not gate 24 is connected to the first input end of the second and gate 25, and the second input end of the second and gate 25 is connected to the first output end Q of the first D flip-flop 21. The input terminal of the first and gate 23 outputs the falling edge information of the detected signal.
In one embodiment, the output terminal of the first and gate 23 is connected to the rising edge detection unit 3, the rising edge detection unit 3 includes a first data selector 31 and a second D flip-flop 32, the signal switching control terminal and the first signal input terminal of the first data selector 31 are both connected to the output terminal of the first and gate 23, the output terminal of the first data selector 31 is connected to the input terminal D of the second D flip-flop 32, and the second input terminal of the first data selector 31 is connected to the output terminal Q of the second D flip-flop 32; the first data selector 31 selects and outputs the signal of the first input terminal of the first data selector 31 when the signal switching control terminal is at a high level, and selects and outputs the signal of the second input terminal of the first data selector 31 when the signal switching control terminal is at a low level.
In one embodiment, the output terminal of the second and gate 25 is connected to the falling edge detection unit 4, the falling edge detection unit 4 includes a second data selector 41 and a third D flip-flop 42, the signal switching control terminal and the first signal input terminal of the second data selector 41 are both connected to the output terminal of the second and gate 25, the output terminal of the second data selector 41 is connected to the input terminal D of the third D flip-flop 42, and the second input terminal of the second data selector 41 is connected to the output terminal Q of the third D flip-flop 42; the second data selector 41 selects and outputs the signal of the first input terminal of the second data selector 41 when the signal switching control terminal is at a high level, and selects and outputs the signal of the second input terminal of the second data selector 41 when the signal switching control terminal is at a low level.
In one embodiment, the signal synthesis and detection result output unit 5 is formed by a third and gate 51, and when the output result of the rising edge detection unit 3 and the output result of the falling edge detection unit 4 are both output at a high level, the field sync signal VS, the line sync signal HS, and the valid display data strobe signal DE to be detected may be determined as valid signals.
In one embodiment, the output result of the third and gate 51 is stored into the I2C bus register 6, and the I2C bus register 6 may be set to a 3bit memory space, corresponding to the detection result of the field sync signal VS, the line sync signal HS, or the valid display data strobe signal DE signal, respectively.
In one embodiment, the clock signal inputs of the first D flip-flop 21, the second D flip-flop 32, and the third D flip-flop 42 each employ a pixel clock of the display signal.
In one embodiment, the reset signal inputs of the first D flip-flop 21, the second D flip-flop 32, and the third D flip-flop 42 use the same system reset signal.
One or more embodiments of the present invention may have the following advantages over the prior art:
the display signal detection circuit of the micro display panel can greatly simplify detection of the display signal input of the packaged micro display panel, and avoids pseudo rising edge signals or falling edge signals generated by a system reset signal by setting a separation detection mode of rising edges and falling edges, thereby improving the accuracy of display signal detection.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of a display signal detection circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a display signal detection circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram showing the operation timing of the signal detection circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an I2C register structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Examples
As shown in fig. 1, the micro display panel display signal detection circuit of the present invention includes a plurality of signal detection units 1, the plurality of signal detection units 1 having the same circuit structure, each signal detection unit 1 including a signal rising edge and falling edge separation unit 2, a rising edge detection unit 3, a falling edge detection unit 4, and a signal synthesis and detection result output unit 5; the micro display panel display signal detection circuit further comprises an I2C bus register 6.
The present invention determines whether the display signal is in a normal state by using states of the field sync signal VS, the line sync signal HS, and the valid display data strobe signal DE in the display signal. When the signal is detected to have both a rising edge and a falling edge for any one of the field sync signal VS, the line sync signal HS, and the valid display data strobe signal DE, the signal is proved valid. However, due to the reset condition in the display driving circuit, when the register in the display driving circuit is reset, the field sync signal VS, the row sync signal HS, and the valid display data strobe signal DE may be caused to be reset to 0 or 1, thereby causing the signal detecting circuit to detect a false rising edge or falling edge, that is, the false rising edge or falling edge is not generated by the field sync signal VS, the row sync signal HS, and the valid display data strobe signal DE by itself but is forced to be generated by the reset signal. Therefore, the influence on the validity detection of the field sync signal VS, the row sync signal HS and the valid display data strobe signal DE generated by the reset signal needs to be considered excluded in the present invention.
The multiple signal detection units 1 of the present invention are used for respectively detecting the signal validity of the field synchronization signal VS, the line synchronization signal HS and the valid display data strobe signal DE, i.e. the field synchronization signal VS, the line synchronization signal HS and the valid display data strobe signal DE are respectively input into one signal detection unit 1.
The signal rising edge and falling edge separating unit 2 is used for separating the rising edge and the falling edge of the signal in the field synchronous signal VS, the line synchronous signal HS or the effective display data strobe signal DE so as to realize the detection of the rising edge and the falling edge respectively. As shown in fig. 2, the signal rising edge and falling edge separating unit 2 of the present invention includes a first D flip-flop 21, a first not gate 22, a first and gate 23, a second not gate 24, and a second and gate 25. Wherein the signal input D of the first D flip-flop 21 is connected to the VS/HS/DE signal. Subsequently, the first output Q of the first D flip-flop 21 is connected to the input of the first not gate 22, the output of the first not gate 22 is connected to the first input of the first and gate 23, and the second input of the first and gate 23 is connected to the signal input D of the first D flip-flop 21. The input terminal of the first and gate 23 outputs rising edge information of the detected signal.
Meanwhile, the input end of the second not gate 24 is connected to the signal input end D of the first D flip-flop 21, the output end of the second not gate 24 is connected to the first input end of the second and gate 25, and the second input end of the second and gate 25 is connected to the first output end Q of the first D flip-flop 21. The input terminal of the first and gate 23 outputs the falling edge information of the detected signal.
As shown in the timing chart of fig. 3, when a rising edge jump occurs in the field sync signal VS, the row sync signal HS or the valid display data strobe signal DE, the rising edge jump is shown as a channel; the second input end of the first AND gate 23 is consistent with the a-channel signal; on the arrival of the rising edge of the next clock after this rising edge, the first output Q of the first D flip-flop 21 is shown to change, which signal is shown as channel b in fig. 3 after passing through the first not gate 22. Through the operation of the first and gate 23, the output of the first and gate 23 is indicated by a channel c, that is, when a rising edge transition occurs in the field sync signal VS, the line sync signal HS, or the valid display data strobe signal DE, the first and gate 23 outputs a high level, and the high level is maintained only until the first output terminal Q of the first D flip-flop 21 transitions due to the rising edge occurrence, which is referred to as a rising edge trigger signal in this embodiment.
Likewise, when a falling edge transition occurs in the field sync signal VS, the line sync signal HS, or the valid display data strobe signal DE, the first output terminal Q of the first D flip-flop 21 changes when the rising edge of the next clock after the falling edge arrives, the signal of which is shown as a channel a in fig. 3. When the field sync signal VS, the row sync signal HS, or the valid display data strobe signal DE is input to the second input terminal of the second and gate 25 through the second not gate 24, the signal is shown as channel B in fig. 3. Through the operation of the second and gate 25, the output of the second and gate 25 is shown as a channel C, that is, when a falling edge transition occurs in the field sync signal VS, the row sync signal HS, or the valid display data strobe signal DE, the second and gate 23 outputs a high level, and the high level is maintained only until the first output terminal Q of the first D flip-flop 21 transitions due to the falling edge occurrence, which is referred to as a falling edge trigger signal in this embodiment.
As shown in fig. 2, the output end of the first and gate 23 is connected to the rising edge detection unit 3, the rising edge detection unit 3 includes a first data selector 31 and a second D flip-flop 32, the signal switching control end and the first signal input end of the first data selector 31 are both connected to the output end of the first and gate 23, the output end of the first data selector 31 is connected to the input end D of the second D flip-flop 32, and the second input end of the first data selector 31 is connected to the output end Q of the second D flip-flop 32. Meanwhile, the first data selector 31 of the present invention selectively outputs the signal of the first input terminal of the first data selector 31 when the signal switching control terminal is at the high level, and selectively outputs the signal of the second input terminal of the first data selector 31 when the signal switching control terminal is at the low level.
Meanwhile, the output end of the second and gate 25 is connected to the falling edge detection unit 4, the falling edge detection unit 4 includes a second data selector 41 and a third D flip-flop 42, the signal switching control end and the first signal input end of the second data selector 41 are both connected to the output end of the second and gate 25, the output end of the second data selector 41 is connected to the input end D of the third D flip-flop 42, and the second input end of the second data selector 41 is connected to the output end Q of the third D flip-flop 42. Meanwhile, the second data selector 41 of the present invention selectively outputs the signal of the first input terminal of the second data selector 41 when the signal switching control terminal is at the high level, and selectively outputs the signal of the second input terminal of the second data selector 41 when the signal switching control terminal is at the low level.
As shown in the timing chart of fig. 3, when the first and gate 23 outputs the rising edge signal shown in the c channel, the first data selector 31 transmits the rising edge detection signal to the input terminal D of the second D flip-flop 32, and when the rising edge of the next clock after the rising edge detection signal arrives, the output terminal Q of the second D flip-flop 32 transitions to the high level, and after the rising edge detection signal transitions to the low level, the first data selector 31 selects to input the second input terminal signal to the input terminal D of the second D flip-flop 32, i.e., to maintain the high level output of the output terminal Q of the second D flip-flop 32, as shown in the channel D.
Similarly, when the second and gate 25 outputs a falling edge signal as shown in the C channel, the second data selector 41 transmits the falling edge detection signal to the input terminal D of the third D flip-flop 42, and when the rising edge of the next clock after the falling edge detection signal arrives, the output terminal Q of the third D flip-flop 42 transitions to a high level, and after the falling edge detection signal transitions to a low level, the second data selector 41 will select to input the second input terminal signal to the input terminal D of the third D flip-flop 42, i.e. maintain the high level output of the output terminal Q of the third D flip-flop 42 as shown in the channel D.
As shown in fig. 2, the output result of the rising edge detection unit 3 and the output result of the falling edge detection unit 4 are both input to the signal synthesizing and detection result output unit 5 in the present invention. In the present invention, the signal synthesizing and detecting result output unit 5 is formed by a third and gate 51, and when the output result of the rising edge detecting unit 3 and the output result of the falling edge detecting unit 4 are both output at high level, it can be determined that the field sync signal VS, the line sync signal HS and the valid display data strobe signal DE to be detected are valid signals, and otherwise, it is determined that the valid field sync signal VS, the line sync signal HS or the valid display data strobe signal DE is not detected. The output result of the third and gate 51 is stored into the I2C bus register 6, and the I2C bus register 6 may be set to a 3bit memory space, corresponding to the detection result of the field sync signal VS, the line sync signal HS, or the valid display data strobe signal DE signal, respectively. The I2C bus register 6 may be accessed by other devices on the I2C bus by having obtained the signal state of the field sync signal VS, the row sync signal HS or the valid display data strobe signal DE signal.
In this embodiment, the clock signal input terminals of the first D flip-flop 21, the second D flip-flop 32, and the third D flip-flop 42 all use the pixel clock of the display signal, and the reset signal input terminals of the first D flip-flop 21, the second D flip-flop 32, and the third D flip-flop 42 use the same system reset signal. In this embodiment, when the system reset signal is input to the display signal detection circuit, the output result of the rising edge detection unit 3 and the output result of the falling edge detection unit 4 are both reset to low level, and the display signal detection circuit needs to re-detect the rising edge and the falling edge of the signal to be detected. Thus avoiding a case where a false rising edge or falling edge due to a system reset is taken as a detection result.
The above description is only a specific embodiment of the present invention, and the scope of the present invention is not limited thereto, and any person skilled in the art should modify or replace the present invention within the technical specification described in the present invention.
Claims (9)
1. A micro display panel display signal detection circuit, characterized in that the micro display panel display signal detection circuit comprises: the signal detection units are provided with the same circuit structure, and each signal detection unit comprises a signal rising edge and falling edge separation unit, a rising edge detection unit, a falling edge detection unit and a signal synthesis and detection result output unit; the micro display panel display signal detection circuit further comprises an I2C bus register;
the field synchronizing signal VS, the line synchronizing signal HS and the effective display data strobe signal DE in the display signals are respectively and correspondingly input to a signal detection unit;
the signal rising edge and falling edge separation unit is used for separating the rising edge and the falling edge of the signal in the field synchronous signal VS, the line synchronous signal HS or the effective display data strobe signal DE, and forming a rising edge trigger signal and a falling edge trigger signal respectively so as to realize the detection of the rising edge and the falling edge respectively;
the rising edge detection unit generates a rising edge detection result signal of the signal to be detected according to the rising edge trigger signal transmitted by the signal rising edge and falling edge separation unit and continuously outputs the rising edge detection result signal; the falling edge detection unit generates a falling edge detection result signal of the signal to be detected according to the falling edge trigger signal transmitted by the signal rising edge and falling edge separation unit and continuously outputs the falling edge detection result signal;
the signal synthesis and detection result output unit combines the rising edge detection result signal output by the rising edge detection unit and the falling edge detection result signal output by the falling edge detection unit to generate a detection result of whether the field synchronization signal VS, the line synchronization signal HS or the effective display data strobe signal DE to be detected is effective and outputs the detection result to the I2C bus register, wherein the I2C bus register stores the detection result of whether the display signal contains the field synchronization signal VS, the line synchronization signal HS or the effective display data strobe signal DE, and the I2C bus register can be accessed by other devices on the I2C bus.
2. The micro-display panel display signal detection circuit according to claim 1, wherein the signal rising edge and falling edge separation unit comprises a first D flip-flop, a first not gate, a first and gate, a second not gate, and a second and gate; the signal input end D of the first D trigger is connected with a field synchronizing signal VS, a line synchronizing signal HS or an effective display data strobe signal DE; the first output end Q of the first D trigger is connected with the input end of a first NOT gate, the output end of the first NOT gate is connected with the first input end of a first AND gate, and the second input end of the first AND gate is connected with the signal input end D of the first D trigger; the input end of the first AND gate outputs rising edge information of the detected signal; the input end of the second NOT gate is connected with the signal input end D of the first D trigger, the output end of the second NOT gate is connected with the first input end of the second AND gate, and the second input end of the second AND gate is connected with the first output end Q of the first D trigger; and the output end of the first AND gate outputs the falling edge information of the detected signal.
3. The micro display panel display signal detection circuit according to claim 2, wherein the output end of the first and gate is connected to a rising edge detection unit, the rising edge detection unit includes a first data selector and a second D flip-flop, the signal switching control end and the first signal input end of the first data selector are both connected to the output end of the first and gate, the output end of the first data selector is connected to the input end D of the second D flip-flop, and the second input end of the first data selector is connected to the output end Q of the second D flip-flop; the first data selector selects and outputs the signal of the first input end of the first data selector when the signal switching control end is in a high level, and selects and outputs the signal of the second input end of the first data selector when the signal switching control end is in a low level.
4. A micro display panel display signal detection circuit according to claim 3, wherein the output terminal of the second and gate is connected to a falling edge detection unit, the falling edge detection unit comprises a second data selector and a third D flip-flop, the signal switching control terminal and the first signal input terminal of the second data selector are both connected to the output terminal of the second and gate, the output terminal of the second data selector is connected to the input terminal D of the third D flip-flop, and the second input terminal of the second data selector is connected to the output terminal Q of the third D flip-flop; the second data selector selects and outputs the signal of the first input end of the second data selector when the signal switching control end is at a high level, and selects and outputs the signal of the second input end of the second data selector when the signal switching control end is at a low level.
5. The micro-display panel display signal detection circuit according to claim 4, wherein the signal synthesis and detection result output unit is composed of a third and gate, and when the output result of the rising edge detection unit and the output result of the falling edge detection unit are both output at a high level, the field sync signal VS, the line sync signal HS, and the valid display data strobe signal DE to be detected can be determined as valid signals.
6. The micro-display panel display signal detection circuit according to claim 5, wherein the output result of the third and gate is stored into an I2C bus register, and the I2C bus register is a 3bit memory space, and corresponds to the detection result of the field sync signal VS, the line sync signal HS, or the valid display data strobe signal DE signal, respectively.
7. The micro-display panel display signal detection circuit according to claim 6, wherein the clock signal input terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop each use a pixel clock of the display signal.
8. The micro-display panel display signal detection circuit according to claim 4, wherein the reset signal input terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop use the same system reset signal.
9. A display device, wherein the display device comprises a Micro display panel based on Micro-LED or Micro-OLED light emitting elements, and the Micro display panel comprises the Micro display panel display signal detection circuit according to any one of claims 1 to 8.
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| CN106841870A (en) * | 2017-02-14 | 2017-06-13 | 济南浪潮高新科技投资发展有限公司 | A kind of abnormal signal auxiliary positioning circuit and method |
| CN108964638A (en) * | 2018-05-29 | 2018-12-07 | 苏州大学 | A kind of novel signal rising edge edge sense circuit |
| CN111477149A (en) * | 2020-04-22 | 2020-07-31 | 京东方科技集团股份有限公司 | Data output circuit, data output method and display device |
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