CN116776791A - Static time sequence analysis algorithm for eliminating pessimistic degree of public path - Google Patents
Static time sequence analysis algorithm for eliminating pessimistic degree of public path Download PDFInfo
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- 238000012300 Sequence Analysis Methods 0.000 title claims abstract description 10
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F2111/00—Details relating to CAD techniques
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- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
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Abstract
The invention discloses a static time sequence analysis algorithm for eliminating pessimistic degree of a public path, which comprises the following steps: global routing result and relevant time sequence constraint input, credit value table establishment, signal pin array construction, multi-pin unit output pin array combination and critical path search. The invention belongs to the technical field of pessimistic degree elimination algorithms, and particularly provides a key path searching algorithm without repeated path searching based on graph traversal; storing candidates of all critical paths with ordered numbers and no duplicate paths; establishing a credit value table in a parallel mode of independently establishing a table for each thread and finally combining the tables into a multi-thread unlocked type table; using the credit value difference as a filtering condition of the key path candidate to complete the combination of arrival time combinations of the output pins of the multi-input pin unit; a static timing analysis algorithm for removing pessimistic common paths for critical path lookups is accomplished with each slot value corresponding to one of the group of slot values in the preamble pin.
Description
Technical Field
The invention belongs to the technical field of pessimistic degree elimination algorithms, and particularly relates to a static time sequence analysis algorithm for eliminating pessimistic degree of a public path.
Background
In advanced algorithms for static timing analysis common path pessimistic cancellation, performing critical path lookups for each pair of flip-flops (flip-flop) individually is a popular method of optimizing both timing analysis efficiency and accuracy, but this approach results in repeated path traversals over paired flip-flops that have a common unit of logical path. Graph-based algorithms are an effective way to eliminate such redundant computation, so designing an efficient graph-based common path pessimistic elimination algorithm is critical to static timing analysis. The static time sequence analysis plays a key role in reaching the standard of the design frequency of the whole circuit.
The existing common path pessimistic degree elimination method is poor in efficiency and accuracy of finding a large number of critical paths. In particular, existing path-based common path pessimistic cancellation algorithms are either path-based or block-based algorithms. Although the path-based method can find all critical paths, the speed of searching a large number of critical paths in millions of gate circuits and circuits above is seriously reduced; the block-based common path pessimistic cancellation algorithm prunes the same layers and paths as the circuit is traversed to reduce the computation of critical paths, but on millions of gates and beyond, the accuracy of finding critical paths is severely degraded. Under the condition of ensuring the precision, the searching efficiency of the key paths is improved, so that the circuit paths are traversed and the key paths are pruned according to the traversal of the graph, and under the condition of ensuring the precision, the searching efficiency of a large number of key paths is improved.
Disclosure of Invention
In order to solve the existing problems, the invention provides a key path searching algorithm without repeated path searching based on graph traversal; storing candidates of all critical paths using ordered sets and no duplicate paths; establishing a credit value table by using a parallel mode of independently establishing a table for each thread and finally combining the tables into a multi-thread unlocked type table; using the credit value difference as a filtering condition of the critical path candidate to complete the combination of arrival time combinations of the output pins of the multi-input pin unit; a static timing analysis algorithm for removing pessimistic common paths of a critical path full path lookup is accomplished using a pattern that each slot value corresponds to a group of slot values in a preamble pin.
The technical scheme adopted by the invention is as follows: the invention discloses a static time sequence analysis algorithm for eliminating pessimistic degree of a public path, which comprises the following steps:
step S1: the input of the global wiring result and the related time sequence constraint can update the arrival time of all pin signals according to the global wiring result and the related time sequence constraint;
step S2: establishing a credit value table, calculating credit values for all paired triggers through a clock tree, establishing the credit value table, and obtaining the difference value of the credit value boundary values through the credit value table;
step S3: signal pin array construction, storing signal arrival times at each pin using an ordered array (simultaneously storing ascending and descending arrays, wherein ascending corresponds to a hold time check and descending corresponds to a setup time check), and at the output pins of the multiple input pin unit;
step S4: the output pin arrays of the multi-pin unit are combined, and the input arrays are filtered by using the credit difference and are combined into an array (ascending order and descending order);
step S5: searching critical paths, namely sorting all arrays by using a heap at an end point trigger, and finding the required number of critical paths through pointers;
step S5: outputting the critical path.
Preferably, in step S2, the credit value table is built by mapping the common path delay calculation to the clock tree structure, converting the pairing trigger credit value calculation to the lowest common parent node (LCA) calculation of the clock tree, and using the calculation result to build the credit table, so as to obtain the boundary value difference value of the credit table, wherein the credit table is built by using multithread without locking, and an independent table is built for each thread independently, and finally, the two tables are combined into a table.
Preferably, in step S3, the signal pin array is constructed, and when the signal arrival time is calculated, all possible critical path results are stored by using the array, so that the accuracy is guaranteed to be completely accurate.
Preferably, in step S4, the multiple pin unit output pin arrays are combined, when updating each pin array, no operation is adopted for the single input unit output pin, the array is directly transferred to a lower unit, and at the multiple pin unit output pin, the combination is performed, so that the critical path searching range is greatly reduced, and any possible value is not missed.
Preferably, in step S5, the critical paths are searched, and at the end point trigger and the main output, the values in all the arrays and the corresponding credit values are calculated by searching the credit value table to obtain the final slack values, then the stack ordering mode is used to obtain the required number of slack values, and finally the required number of critical paths are obtained through the previous stage pins stored at each pin, so that the algorithm is simple, low in complexity and capable of achieving all correct results.
Preferably, the combination combining process: combining the multiple arrays into an array with the size of k (k is the number of critical paths to be searched), adding and summing the credit value difference value and the last value in the array, and inserting the value less than or equal to the sum in all the arrays.
The beneficial effects obtained by the invention by adopting the structure are as follows: the static time sequence analysis algorithm for eliminating the pessimistic degree of the public path provided by the scheme remarkably improves the efficiency of searching the key path after eliminating the pessimistic degree of the public path in the static time sequence analysis, and shows extremely strong stable searching time when searching the key path of ten thousand orders of magnitude or more on the scale of millions of gates and more. Static timing analysis is an important component of the whole computer chip aided design software (EDA) and can improve the quality of the computer chip aided design software, so that the performance of a chip designed by the computer chip aided design software can be improved.
Drawings
FIG. 1 is a flow chart of a static timing analysis algorithm for eliminating pessimistic degree of a common path according to the present scheme;
FIG. 2 is a clock tree established by the credit value table of the scheme, wherein FF is a trigger, r is a clock source, n is a circuit unit, and the value is a unit delay boundary value;
FIG. 3 is a schematic diagram of an array memory critical path of the static timing analysis algorithm for eliminating pessimistic degree of a common path according to the present embodiment;
fig. 4 is a combined schematic diagram of the static timing analysis algorithm for eliminating pessimistic degree of the common path according to the present embodiment.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The static time sequence analysis algorithm for eliminating the pessimistic degree of the public path, which is provided by the scheme, comprises the following steps:
step S1: the input of the global wiring result and the related time sequence constraint can update the arrival time of all pin signals according to the global wiring result and the related time sequence constraint;
step S2: establishing a credit value table, calculating credit values for all paired triggers through a clock tree, establishing the credit value table, and obtaining the difference value of the credit value boundary values through the credit value table;
step S3: signal pin array construction, storing signal arrival times at each pin using an ordered array (simultaneously storing ascending and descending arrays, wherein ascending corresponds to a hold time check and descending corresponds to a setup time check), and at the output pins of the multiple input pin unit;
step S4: the output pin arrays of the multi-pin unit are combined, and the input arrays are filtered by using the credit difference and are combined into an array (ascending order and descending order);
step S5: searching critical paths, namely sorting all arrays by using a heap at an end point trigger, and finding the required number of critical paths through pointers;
step S5: outputting the critical path.
The credit value table is built in step S2, by mapping the common path delay calculation into the clock tree structure, converting the pairing trigger credit value calculation into the clock tree lowest common parent node (LCA) calculation, and using the calculation result to build the credit table, calculating to obtain the boundary value difference value of the credit table, wherein the credit table is built by using multithread without locking, and an independent table is built for each thread independently, and finally, the two tables are combined into a table.
In step S3, an array of signal pins is constructed, and the array is used to store all possible critical path results during the calculation of the signal arrival time.
In step S4, the multiple pin unit output pin combinations are combined, when updating each pin array, no operation is adopted for the single input unit output pin, the array is directly transferred to a lower unit, and at the multiple pin unit output pin, the combination is performed, and the combination process is performed: combining the multiple arrays into an array with the size of k (k is the number of critical paths to be searched), adding and summing the credit value difference value and the last value in the array, and inserting the value less than or equal to the sum in all the arrays.
In step S5, the critical paths are searched, and at the end point trigger and the main output, the values in all the arrays and the corresponding credit values are calculated by searching the credit value table to obtain the final slack values, then the stack ordering mode is used to obtain the required number of slack values, and finally the required number of critical paths are obtained through the previous stage pins stored at each pin.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The static time sequence analysis algorithm for eliminating the pessimistic degree of the public path is characterized in that: the method comprises the following steps:
step S1: the input of the global wiring result and the related time sequence constraint can update the arrival time of all pin signals according to the global wiring result and the related time sequence constraint;
step S2: establishing a credit value table, calculating credit values for all paired triggers through a clock tree, establishing the credit value table, and obtaining the difference value of the credit value boundary values through the credit value table;
step S3: constructing a signal pin array, storing signal arrival time at each pin in an ordered array mode, and simultaneously storing an ascending order and a descending order array, wherein the ascending order corresponds to a hold time check, the descending order corresponds to a setup time check, and the descending order corresponds to an output pin of the multi-input pin unit;
step S4: the output pin arrays of the multi-pin unit are combined, and the input multiple arrays are filtered by using the credit difference value and are combined into one array;
step S5: searching critical paths, namely sorting all arrays by using a heap at an end point trigger, and finding the required number of critical paths through pointers;
step S5: outputting the critical path.
2. The static timing analysis algorithm for eliminating common path pessimism of claim 1, wherein: in step S2, the credit value table is built, the common path delay calculation is mapped into the clock tree structure, the pairing trigger credit value calculation is converted into the calculation of the lowest common father node of the clock tree, the credit table is built by using the calculation result, the boundary value difference value of the credit table is obtained by calculation, the multi-thread is used for unlocking when the credit table is built, an independent table is built for each thread independently, and finally the independent tables are combined into one table.
3. The static timing analysis algorithm for eliminating common path pessimism of claim 1, wherein: in step S3, an array of signal pins is constructed, and the array is used to store all possible critical path results during the calculation of the signal arrival time.
4. The static timing analysis algorithm for eliminating common path pessimism of claim 1, wherein: in step S4, the multiple pin unit output pin combinations are combined, and when updating each pin array, the single input unit output pin is not operated at all, the array is directly transferred to a lower unit, and the multiple pin unit output pins are combined.
5. The static timing analysis algorithm for eliminating common path pessimism of claim 1, wherein: in step S5, the critical paths are searched, and at the end point trigger and the main output, the values in all the arrays and the corresponding credit values are calculated by searching the credit value table to obtain the final slots, then the stack ordering mode is used to obtain the required number of slots, and finally the required number of critical paths are obtained through the previous stage pins stored at each pin.
6. The static timing analysis algorithm for eliminating common path pessimism of claim 4, wherein: the combination and combination process is as follows: combining the multiple arrays into an array with the size of k, wherein k is the number of critical paths to be searched, adding and summing the credit value difference value and the last value in the array, and inserting the value less than or equal to the sum in all the arrays.
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